Service Manual LG 43UF640

Internal Use Only
North/Latin America http://aic.lgservice.com

Europe/Africa http://eic.lgservice.com
Asia/Oceania http://biz.lgservice.com
LED TV
SERVICE MANUAL
CHASSIS : LD59R / LD5ZR
MODEL : 43/49UF640* 43/49UF640*-ZA
CAUTION
BEFORE SERVICING THE CHASSIS,
READ THE SAFETY PRECAUTIONS IN THIS MANUAL.
P/NO : MFL69305903 (1506-REV00) Printed in Korea

CONTENTS
CONTENTS ............................................................................................... 2
SAFETY PRECAUTIONS ......................................................................... 3
SERVICING PRECAUTIONS..................................................................... 4
SPECIFICATION........................................................................................ 6
ADJUSTMENT INSTRUCTION............................................................... 15
BLOCK DIAGRAM................................................................................... 21
EXPLODED VIEW ................................................................................... 30
SCHEMATIC CIRCUIT DIAGRAM ............................................ APPENDIX
TROUBLE SHOOTING GUIDE ................................................. APPENDIX
Copyright © LG Electronics. Inc. All rights reserved. -2- LGE Internal Use Only
Only for training and service purposes
SAFETY PRECAUTIONS
IMPORTANT SAFETY NOTICE

Many electrical and mechanical parts in this chassis have special safety-related characteristics. These parts are identified by in the
Schematic Diagram and Exploded View.
It is essential that these special safety parts should be replaced with the same components as recommended in this manual to prevent
Shock, Fire, or other Hazards.
Do not modify the original design without permission of manufacturer.
General Guidance Leakage Current Hot Check (See below Figure)

Plug the AC cord directly into the AC outlet.
An isolation Transformer should always be used during the
servicing of a receiver whose chassis is not isolated from the AC Do not use a line Isolation Transformer during this check.
power line. Use a transformer of adequate power rating as this Connect 1.5 K / 10 watt resistor in parallel with a 0.15 uF capacitor
protects the technician from accidents resulting in personal injury between a known good earth ground (Water Pipe, Conduit, etc.)
from electrical shocks. and the exposed metallic parts.
Measure the AC voltage across the resistor using AC voltmeter
It will also protect the receiver and it's components from being with 1000 ohms/volt or more sensitivity.
damaged by accidental shorts of the circuitry that may be Reverse plug the AC cord into the AC outlet and repeat AC voltage
inadvertently introduced during the service operation. measurements for each exposed metallic part. Any voltage
measured must not exceed 0.75 volt RMS which is corresponds to
If any fuse (or Fusible Resistor) in this TV receiver is blown, 0.5 mA.
replace it with the specified. In case any measurement is out of the limits specified, there is
possibility of shock hazard and the set must be checked and
When replacing a high wattage resistor (Oxide Metal Film Resistor, repaired before it is returned to the customer.
over 1 W), keep the resistor 10 mm away from PCB.
Leakage Current Hot Check circuit
Keep wires away from high voltage or high temperature parts.
Before returning the receiver to the customer,
always perform an AC leakage current check on the exposed

metallic parts of the cabinet, such as antennas, terminals, etc., to
be sure the set is safe to operate without damage of electrical
shock.
Leakage Current Cold Check(Antenna Cold Check)

With the instrument AC plug removed from AC source, connect an
electrical jumper across the two AC plug prongs. Place the AC
switch in the on position, connect one lead of ohm-meter to the AC
plug prongs tied together and touch other ohm-meter lead in turn to
each exposed metallic parts such as antenna terminals, phone
jacks, etc.
If the exposed metallic part has a return path to the chassis, the
measured resistance should be between 1 MΩ and 5.2 MΩ.
When the exposed metal has no return path to the chassis the
reading must be infinite.
An other abnormality exists that must be corrected before the
receiver is returned to the customer.
SERVICING PRECAUTIONS
CAUTION: Before servicing receivers covered by this service 2. After removing an electrical assembly equipped with ES
manual and its supplements and addenda, read and follow the devices, place the assembly on a conductive surface such as
SAFETY PRECAUTIONS on page 3 of this publication. aluminum foil, to prevent electrostatic charge buildup or expo-
NOTE: If unforeseen circumstances create conflict between the sure of the assembly.
following servicing precautions and any of the safety precautions 3. Use only a grounded-tip soldering iron to solder or unsolder
on page 3 of this publication, always follow the safety precau- ES devices.
tions. Remember: Safety First. 4. Use only an anti-static type solder removal device. Some sol-
der removal devices not classified as “anti-static” can generate
General Servicing Precautions electrical charges sufficient to damage ES devices.
1. Always unplug the receiver AC power cord from the AC power 5. Do not use freon-propelled chemicals. These can generate
source before; electrical charges sufficient to damage ES devices.
a. Removing or reinstalling any component, circuit board 6. Do not remove a replacement ES device from its protective
module or any other receiver assembly. package until immediately before you are ready to install it.
b. Disconnecting or reconnecting any receiver electrical plug (Most replacement ES devices are packaged with leads elec-
or other electrical connection. trically shorted together by conductive foam, aluminum foil or
c. Connecting a test substitute in parallel with an electrolytic comparable conductive material).
capacitor in the receiver. 7. Immediately before removing the protective material from the
CAUTION: A wrong part substitution or incorrect polarity leads of a replacement ES device, touch the protective mate-
installation of electrolytic capacitors may result in an explo- rial to the chassis or circuit assembly into which the device will
sion hazard. be installed.
2. Test high voltage only by measuring it with an appropriate CAUTION: Be sure no power is applied to the chassis or cir-
high voltage meter or other voltage measuring device (DVM, cuit, and observe all other safety precautions.
FETVOM, etc) equipped with a suitable high voltage probe. 8. Minimize bodily motions when handling unpackaged replace-
Do not test high voltage by "drawing an arc". ment ES devices. (Otherwise harmless motion such as the
3. Do not spray chemicals on or near this receiver or any of its brushing together of your clothes fabric or the lifting of your
assemblies. foot from a carpeted floor can generate static electricity suf-
4. Unless specified otherwise in this service manual, clean ficient to damage an ES device.)
electrical contacts only by applying the following mixture to the
contacts with a pipe cleaner, cotton-tipped stick or comparable General Soldering Guidelines
non-abrasive applicator; 10 % (by volume) Acetone and 90 % 1. Use a grounded-tip, low-wattage soldering iron and appropri-
(by volume) isopropyl alcohol (90 % - 99 % strength) ate tip size and shape that will maintain tip temperature within
CAUTION: This is a flammable mixture. the range or 500 °F to 600 °F.
Unless specified otherwise in this service manual, lubrication 2. Use an appropriate gauge of RMA resin-core solder composed
of contacts in not required. of 60 parts tin/40 parts lead.
5. Do not defeat any plug/socket B+ voltage interlocks with which 3. Keep the soldering iron tip clean and well tinned.
receivers covered by this service manual might be equipped. 4. Thoroughly clean the surfaces to be soldered. Use a mall wire-
6. Do not apply AC power to this instrument and/or any of its bristle (0.5 inch, or 1.25 cm) brush with a metal handle.
electrical assemblies unless all solid-state device heat sinks Do not use freon-propelled spray-on cleaners.
are correctly installed. 5. Use the following unsoldering technique
7. Always connect the test receiver ground lead to the receiver a. Allow the soldering iron tip to reach normal temperature.
chassis ground before connecting the test receiver positive (500 °F to 600 °F)
lead. b. Heat the component lead until the solder melts.
Always remove the test receiver ground lead last. c. Quickly draw the melted solder with an anti-static, suction-
8. Use with this receiver only the test fixtures specified in this type solder removal device or with solder braid.
service manual. CAUTION: Work quickly to avoid overheating the circuit
CAUTION: Do not connect the test fixture ground strap to any board printed foil.
heat sink in this receiver. 6. Use the following soldering technique.
a. Allow the soldering iron tip to reach a normal temperature
Electrostatically Sensitive (ES) Devices (500 °F to 600 °F)
Some semiconductor (solid-state) devices can be damaged eas- b. First, hold the soldering iron tip and solder the strand
ily by static electricity. Such components commonly are called against the component lead until the solder melts.
Electrostatically Sensitive (ES) Devices. Examples of typical ES c. Quickly move the soldering iron tip to the junction of the
devices are integrated circuits and some field-effect transistors component lead and the printed circuit foil, and hold it there
and semiconductor “chip” components. The following techniques only until the solder flows onto and around both the compo-
should be used to help reduce the incidence of component dam- nent lead and the foil.
age caused by static by static electricity. CAUTION: Work quickly to avoid overheating the circuit
1. Immediately before handling any semiconductor component or board printed foil.
semiconductor-equipped assembly, drain off any electrostatic d. Closely inspect the solder area and remove any excess or
charge on your body by touching a known earth ground. Alter- splashed solder with a small wire-bristle brush.
natively, obtain and wear a commercially available discharg-
ing wrist strap device, which should be removed to prevent
potential shock reasons prior to applying power to the unit
under test.
IC Remove/Replacement 3. Solder the connections.
Some chassis circuit boards have slotted holes (oblong) through CAUTION: Maintain original spacing between the replaced
which the IC leads are inserted and then bent flat against the cir- component and adjacent components and the circuit board to
cuit foil. When holes are the slotted type, the following technique prevent excessive component temperatures.
should be used to remove and replace the IC. When working with
boards using the familiar round hole, use the standard technique Circuit Board Foil Repair
as outlined in paragraphs 5 and 6 above. Excessive heat applied to the copper foil of any printed circuit
board will weaken the adhesive that bonds the foil to the circuit
Removal board causing the foil to separate from or "lift-off" the board. The
1. Desolder and straighten each IC lead in one operation by following guidelines and procedures should be followed when-
gently prying up on the lead with the soldering iron tip as the ever this condition is encountered.
solder melts.
2. Draw away the melted solder with an anti-static suction-type At IC Connections
solder removal device (or with solder braid) before removing To repair a defective copper pattern at IC connections use the
the IC. following procedure to install a jumper wire on the copper pattern
Replacement side of the circuit board. (Use this technique only on IC connec-
1. Carefully insert the replacement IC in the circuit board. tions).
2. Carefully bend each IC lead against the circuit foil pad and
solder it. 1. Carefully remove the damaged copper pattern with a sharp
3. Clean the soldered areas with a small wire-bristle brush. knife. (Remove only as much copper as absolutely necessary).
(It is not necessary to reapply acrylic coating to the areas). 2. carefully scratch away the solder resist and acrylic coating (if
used) from the end of the remaining copper pattern.
"Small-Signal" Discrete Transistor 3. Bend a small "U" in one end of a small gauge jumper wire and
Removal/Replacement carefully crimp it around the IC pin. Solder the IC connection.
1. Remove the defective transistor by clipping its leads as close 4. Route the jumper wire along the path of the out-away copper
as possible to the component body. pattern and let it overlap the previously scraped end of the
2. Bend into a "U" shape the end of each of three leads remain- good copper pattern. Solder the overlapped area and clip off
ing on the circuit board. any excess jumper wire.
3. Bend into a "U" shape the replacement transistor leads.
4. Connect the replacement transistor leads to the corresponding At Other Connections
leads extending from the circuit board and crimp the "U" with Use the following technique to repair the defective copper pattern
long nose pliers to insure metal to metal contact then solder at connections other than IC Pins. This technique involves the
each connection. installation of a jumper wire on the component side of the circuit
board.
Power Output, Transistor Device
Removal/Replacement 1. Remove the defective copper pattern with a sharp knife.
1. Heat and remove all solder from around the transistor leads. Remove at least 1/4 inch of copper, to ensure that a hazardous
2. Remove the heat sink mounting screw (if so equipped). condition will not exist if the jumper wire opens.
3. Carefully remove the transistor from the heat sink of the circuit 2. Trace along the copper pattern from both sides of the pattern
board. break and locate the nearest component that is directly con-
4. Insert new transistor in the circuit board. nected to the affected copper pattern.
5. Solder each transistor lead, and clip off excess lead. 3. Connect insulated 20-gauge jumper wire from the lead of the
6. Replace heat sink. nearest component on one side of the pattern break to the
lead of the nearest component on the other side.
Diode Removal/Replacement Carefully crimp and solder the connections.
1. Remove defective diode by clipping its leads as close as pos- CAUTION: Be sure the insulated jumper wire is dressed so the
sible to diode body. it does not touch components or sharp edges.
2. Bend the two remaining leads perpendicular y to the circuit
board.
3. Observing diode polarity, wrap each lead of the new diode
around the corresponding lead on the circuit board.
4. Securely crimp each connection and solder it.
5. Inspect (on the circuit board copper side) the solder joints of
the two "original" leads. If they are not shiny, reheat them and
if necessary, apply additional solder.
Fuse and Conventional Resistor

Removal/Replacement
1. Clip each fuse or resistor lead at top of the circuit board hollow
stake.
2. Securely crimp the leads of replacement component around
notch at stake top.
SPECIFICATION
NOTE : Specifications and others are subject to change without notice for improvement.
1. Application range 3. Test method

This specification is applied to the LED TV used LD59R / 1) Performance: LGE TV test method followed
LD5ZR chassis. 2) Demanded other specification
- Safety : CE, IEC specification
- EMC : CE, IEC specification
2. Requirement for Test
Each part is tested as below without special appointment.
1) Temperature: 25 °C ± 5 °C(77 °F ± 9 °F), CST: 40 °C ± 5 °C

2) Relative Humidity: 65 % ± 10 %
3) Power Voltage
: Standard input voltage (AC 100-240 V~, 50/60 Hz)
* Standard Voltage of each products is marked by models.
4) Specification and performance of each parts are followed
each drawing and specification by part number in
accordance with BOM.
5) The receiver must be operated for about 20 minutes prior to
the adjustment.
4. Model General Specification

No. Item Specification Remarks
DTV & Analog (Total 37 countries)
DTV (MPEG2/4, DVB-T) : 26 countrie

Germany, Netherland, Switzerland, Hungary, Austria, Slovenia, Bulgaria,
France, Spain, Belgium, Luxemburg, Greece, Czech, Turkey, Morocco,
Ireland, Latvia, Estonia, Lithuania, Poland, Portugal, Romania, Albania,
Bosnia, Slovakia, Belarus
DTV (MPEG2/4, DVB-T2) :11 countries

UK(Ireland), Sweden, Denmark, Finland, Norway, Ukraine, Kazakhstan,
Russia, Italy, Croatia, Serbia
DTV (MPEG2/4, DVB-C) : 37 countries

France, Spain, Italy, Belgium, Russia, Luxemburg, Greece, Czech, Cro-
atia, Turkey, Morocco, Ireland, Latvia, Estonia, Lithuania, Poland, Portu-
gal, Romania, Albania, Bosnia, Serbia, Slovakia, Belarus, UK, Sweden,
Denmark, Finland, Norway, Ukraine, Kazakhstan
1 Market EU/CIS(PAL Market-37Countries)
DTV (MPEG2/4,DVB-S) : 37 countries
France, Spain,Belgium, Luxemburg, Greece, Czech, Turkey, Morocco,
Ireland, Latvia, Estonia, Lithuania, Poland, Portugal, Romania, Albania,
Bosnia, Slovakia, Belarus, UK(Ireland), Sweden, Denmark, Finland,
Norway, Ukraine, Kazakhstan,Russia, Italy, Croatia, Serbia
Supported satellite : 35 satellites

ABS1 75.0E, AMOS 4.0W, ASIASAT3S 105.5E, ASTRA 19.2E, ASTRA
23.5E, ASTRA 28.2E, ASTRA 4.8E, ATLANTIC BIRD2 8.0W, ATLANTIC
BIRD3 5.0W, BADR 26.0E, DIRECTV-1R 56.0E, EUROBIRD 9A 9.0E,
EUROBIRD3 33.0E, EUTELSAT 36 A/B 36.0E,EUTELSAT W2A 10.0E,
EUTELSAT W3A 7.0E, EUTELSAT7WA 7.3WEUTELSAT 16.0E, EX-
PRESS AM1 40.0E, EXPRESS AM3 140.0E, EXPRESS AM33 96.5E,
HELLASSAT 39.0E, HISPASAT 1CDE 30.0WHOTBIRD 13.0E, INTEL-
SAT10&7 68.5E, INTELSAT15 85.2E, INTELSAT1R 50.0W, INTEL-
SAT903 33.5W, INTELSAT904 60.0E, NILESAT 7.0W, NSS12 57.0E,
THOR 0.8W, TURKSAT 42.0E,YAMAL201 90.0E, OTHER
No. Item Specification Remarks
(1) PAL/SECAM B/G/I/D/K, SECAM L/L’
2 Broadcasting system
(2) DVB-T/T2, C, S/S2
(1) Digital TV
- VHF, UHF
- C-Band, Ku-Band
(2) Analogue TV
3 Program coverage
-VHF : E2 to E12
-UHF : E21 to E69
-CATV : S1 to S20
-HYPER : S21 to S47
► DVB-T
- Guard Interval(Bitrate_Mbit/s)
1/4, 1/8, 1/16, 1/32
- Modulation : Code Rate
QPSK : 1/2, 2/3, 3/4, 5/6, 7/8
16-QAM : 1/2, 2/3, 3/4, 5/6, 7/8
64-QAM : 1/2, 2/3, 3/4, 5/6, 7/8
► DVB-T2
- Guard Interval(Bitrate_Mbit/s)
1/4, 1/8, 1/16, 1/32, 1/128, 19/128, 19/256,
- Modulation : Code Rate
QPSK : 1/2, 2/5, 2/3, 3/4, 5/6
Analog : Upper Heterodyne
16-QAM : 1/2, 2/5, 2/3, 3/4, 5/6
4 Receiving system Digital : COFDM, QAM
64-QAM : 1/2, 2/5, 2/3, 3/4, 5/6
256-QAM : 1/2, 2/5, 2/3, 3/4, 5/6
► DVB-C
- Symbolrate : 4.0 Msymbols/s to 7.2 Msymbols/s
- Modulation : 16QAM, 64-QAM, 128-QAM and 256-QAM
► DVB-S/S2
- symbolrate :
DVB-S2 (8PSK / QPSK) : 2 ~ 45 Msymbol/s
DVB-S (QPSK) : 2 ~ 45 Msymbol/s
- viterbi
DVB-S mode : 1/2, 2/3, 3/4, 5/6, 7/8
DVB-S2 mode : 1/2, 2/3, 3/4, 3/5, 4/5, 5/6, 8/9, 9/10
5 Input Voltage AC 100 ~ 240V 50/60Hz
5. External Input Format
5.1. Standard Level For Input Signal (Video, Audio, Y/C, Component)
No. Item Min Typ Max Unit
1. Video Input Level 0.9 1 1.1 Vpp
2. S Video Input Level(Y) 0.85 1 1.15 Vpp
3. S Video Input Level(C-Burst) 0.143 0.286 Vpp
4. Audio Input Level 0.4 0.5 0.6 Vrms PAL,SECAM, AV1(SCART), AV2, Component
Component Video Input Level
5. 0.6 0.7 0.8 Vpp
(Y, CB/PB, CR/PR)
5.2. 2D Mode
(1) Component (Y, CB/PB, CR/PR)
No. Resolution H-freq(kHz) V-freq(Hz) Pixel clock(MHz) Proposed
1 720*480 15.73 60 13.5135 SDTV ,DVD 480I
2 720*480 15.73 59.94 13.5 SDTV ,DVD 480I
3 720*480 31.50 60 27.027 SDTV 480P
4 720*480 31.47 59.94 27.0 SDTV 480P
5 1280*720 45.00 60.00 74.25 HDTV 720P
6 1280*720 44.96 59.94 74.176 HDTV 720P
7 1920*1080 33.75 60.00 74.25 HDTV 1080I
8 1920*1080 33.72 59.94 74.176 HDTV 1080I
9 1920*1080 67.500 60 148.50 HDTV 1080P
10 1920*1080 67.432 59.94 148.352 HDTV 1080P
11 1920*1080 27.000 24.000 74.25 HDTV 1080P
12 1920*1080 26.97 23.976 74.176 HDTV 1080P
13 1920*1080 33.75 30.000 74.25 HDTV 1080P
14 1920*1080 33.71 29.97 74.176 HDTV 1080P
(2) HDMI Input(DTV)
No. Resolution H-freq(kHz) V-freq.(kHz) Pixel clock(MHz) Proposed Remarks

1 640*480 31.46 59.94 25.13 SDTV 480P
2 640*480 31.50 60.00 25.13 SDTV 480P
3 720*480 15.73 59.94 13.50 SDTV, DVD 480I(525I)
4 720*480 15.75 60.00 13.51 SDTV, DVD 480I(525I) Spec. out but display
5 720*576 15.62 50.00 13.50 SDTV, DVD 576I(625I) 50Hz
6 720*480 31.47 59.94 27.00 SDTV 480P
7 720*480 31.50 60.00 27.03 SDTV 480P
8 720*576 31.25 50.00 27.00 SDTV 576P
9 1280*720 44.96 59.94 74.18 HDTV 720P
10 1280*720 45.00 60.00 74.25 HDTV 720P
11 1280*720 37.50 50.00 74.25 HDTV 720P
12 1920*1080 28.12 50.00 74.25 HDTV 1080I
13 1920*1080 33.72 59.94 74.18 HDTV 1080I
14 1920*1080 33.75 60.00 74.25 HDTV 1080I
15 1920*1080 26.97 23.97 63.30 HDTV 1080P
16 1920*1080 27.00 24.00 63.36 HDTV 1080P
17 1920*1080 33.71 29.97 79.12 HDTV 1080P
18 1920*1080 33.75 30.00 79.20 HDTV 1080P
19 1920*1080 56.25 50.00 148.50 HDTV 1080P
20 1920*1080 67.43 59.94 148.35 HDTV 1080P
21 1920*1080 67.50 60.00 148.50 HDTV 1080P
22 3840*2160 53.95 23.98 297.00 UDTV 2160P UHD only
23 3840*2160 54.00 24.00 297.00 UDTV 2160P UHD only
24 3840*2160 56.25 25.00 297.00 UDTV 2160P UHD only
25 3840*2160 61.43 29.97 297.00 UDTV 2160P UHD only
26 3840*2160 67.50 30.00 297.00 UDTV 2160P UHD only
27 3840*2160 112.50 50.00 594.00 UDTV 2160P(DVB) UHD only(Port1)
28 3840*2160 135.00 59.94 593.41 UDTV 2160P UHD only(Port1)
30 4096*2160 53.95 23.98 297.00 UDTV 2160P UHD only
31 4096*2160 54.00 24.00 297.00 UDTV 2160P UHD only
32 4096*2160 56.25 25.00 297.00 UDTV 2160P UHD only
33 4096*2160 61.43 29.97 297.00 UDTV 2160P UHD only
34 4096*2160 67.50 30.00 297.00 UDTV 2160P UHD only
35 4096*2160 112.50 50.00 594.00 UDTV 2160P(DVB) UHD only(Port1)
(3) HDMI Input (PC)
No. Resolution H-freq(kHz) V-freq.(kHz) Pixel clock(MHz) Proposed Remarks
1 640*350 31.46 70.09 25.17 EGA
2 720*400 31.46 70.08 28.32 DOS
3 640*480 31.46 59.94 25.17 VESA(VGA)
4 800*600 37.87 60.32 40.00 VESA(SVGA)
5 1024*768 48.36 60.00 65.00 VESA(XGA)
6 1152*864 54.34 60.05 80.00 VESA
7 1280*1024 63.98 60.02 109.00 VESA(SXGA) FHD only
8 1360*768 47.71 60.01 85.00 VESA(WXGA)
9 1920*1080 67.50 60.00 158.40 WUXGA(CEA 861D) FHD only
10 3840*2160 67.50 30.00 297.00 UDTV 2160P UHD only
11 3840*2160 56.25 25.00 297.00 UDTV 2160P UHD only
12 3840*2160 54.00 24.00 297.00 UDTV 2160P UHD only
13 4096*2160 53.95 23.97 296.703 UDTV 2160P UHD only
14 4096*2160 54.00 24.00 297.00 UDTV 2160P UHD only
Copyright © LG Electronics. Inc. All rights reserved. - 10 - LGE Internal Use Only
ADJUSTMENT INSTRUCTION
1. Application Range 3.2. LAN Inspection
This specification sheet is applied to all of the LED TV with 3.2.1. Equipment & Condition
LD59R / LD5ZR chassis. ▪ Each other connection to LAN Port of IP Hub and Jig
2. Designation
(1) Because this is not a hot chassis, it is not necessary to
use an isolation transformer. However, the use of isolation
transformer will help protect test instrument.
(2) Adjustment must be done in the correct order.
(3) The adjustment must be performed in the circumstance of
25 °C ± 5 °C of temperature and 65 % ± 10 % of relative
3.2.2. LAN inspection solution
▪ LAN Port connection with PCB
humidity if there is no specific designation.
▪ Network setting at MENU Mode of TV
(4) The input voltage of the receiver must keep AC 100-240
▪ setting automatic IP
V~, 50/60 Hz.
▪ Setting state confirmation
(5) The receiver must be operated for about 5 minutes prior to
- If automatic setting is finished, you confirm IP and MAC
the adjustment when module is in the circumstance of over
Address.
15 °C.
In case of keeping module is in the circumstance of 0 °C, it

should be placed in the circumstance of above 15 °C for 2
hours.
In case of keeping module is in the circumstance of below

-20 °C, it should be placed in the circumstance of above 15
°C for 3 hours.
[Caution]
When still image is displayed for a period of 20 minutes or
longer (Especially where W/B scale is strong. Digital pattern
13ch and/or Cross hatch pattern 09ch), there can some 3.2.3. WIDEVINE key Inspection
afterimage in the black level area. - Confirm key input data at the "IN START" MENU Mode.
3. Automatic Adjustment
3.1. MAC address D/L, CI+ key D/L, Widevine
key D/L, ESN D/L, HDCP2.0 D/L
Connect: USB port
Communication Prot connection
▪ Com 1,2,3,4 and 115200(Baudrate)
Mode check: Online Only
▪ C heck the test process: DETECT → MAC → ESN →
Widevine → CI → HDCP20
▪ Play: Press Enter key
▪ Result: Ready, Test, OK or NG
▪ Printer Out (MAC Address Label)
3.3. LAN PORT INSPECTION(PING TEST) 3.5. CI+ Key checking method
Connect SET → LAN port == PC → LAN Port (Check the Section 3.1)
Check whether the key was downloaded or not at ‘In Start’
SET PC menu. (Refer to below).
3.3.1. Equipment setting

(1) Play the LAN Port Test PROGRAM.
(2) Input IP set up for an inspection to Test Program. => Check the Download to CI+ Key value in LGset.
*IP Number : 12.12.2.2 3.5.1. Check the method of CI+ Key value
(1) Check the method on Instart menu
3.3.2. LAN PORT inspection(PING TEST) (2) Check the method of RS232C Command
(1) Play the LAN Port Test Program. 1) Into the main ass’y mode(RS232: aa 00 00)
(2) Connect each other LAN Port Jack. CMD 1 CMD 2 Data 0
(3) Play Test (F9) button and confirm OK Message. A A 0 0
(4) Remove LAN cable.
2) Check the key download for transmitted command
(RS232: ci 00 10)
CMD 1 CMD 2 Data 0
C I 1 0
3) Result value
- Normally status for download : OKx
- Abnormally status for download : NGx
3.5.2. Check the method of CI+ key value(RS232)

1) Into the main ass’y mode(RS232: aa 00 00)
CMD 1 CMD 2 Data 0
3.4. Model name & Serial number Download A A 0 0
3.4.1. Model name & Serial number D/L 2) Check the mothed of CI+ key by command
▪ Press "P-ONLY" key of service remote control. (RS232: ci 00 20)
(Baud rate : 115200 bps)
▪ Connect RS-232C Signal to USB Cable to USB.
CMD 1 CMD 2 Data 0
▪ Write Serial number by use USB port. C I 2 0
▪ Must check the serial number at Instart menu.
3) Result value
i 01 OK 1d1852d21c1ed5dcx
3.4.2. Method & notice
CI+ Key Value
(1) Serial number D/L is using of scan equipment.
(2) Setting of scan equipment operated by Manufacturing
Technology Group.
(3) Serial number D/L must be conformed when it is produced 3.6. WIFI MAC ADDRESS CHECK
in production line, because serial number D/L is mandatory (1) Using RS232 Command
by D-book 4.0. H-freq(kHz) V-freq.(Hz)
Transmission [A][I][][Set ID][][20][Cr] [O][K][X] or [NG]
* Manual Download (Model Name and Serial Number)
If the TV set is downloaded by OTA or service man, sometimes
model name or serial number is initialized.(Not always) (2) Check the menu on in-start
It is impossible to download by bar code scan, so It need
Manual download.
1) Press the "Instart" key of Adjustment remote control.
2) Go to the menu "7.Model Number D/L" like below photo.
3) Input the Factory model name(ex 47LB650V-ZA) or Serial
number like photo.
4) Check the model name Instart menu. → Factory name

displayed. (ex 47LB650V-ZA)
5) C heck the Diagnostics.(DTV country only) → Buyer
model displayed. (ex 47LB650V-ZA)
4. Manual Adjustment (1) EDID for 2D Model(UF68)
1) DTS
* ADC adjustment is not needed because of OTP(Auto ADC
adjustment) # HDMI 1(C/S : A0 C7) - HDMI UHD Deep On Case
EDID Block 0, Bytes 0-127 [00H-7FH]
0 1 2 3 4 5 6 7 8 9 A B C D E F
4.1. EDID(The
Extended Display Identification 0 00 FF FF FF FF FF FF 00 1E 6D 01 00 01 01 01 01
Data)/DDC(Display Data Channel) download 10 01 19 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26
20 0F 50 54 A1 08 00 31 40 45 40 61 40 71 40 81 80
4.1.1. Overview 30 01 01 01 01 01 01 08 E8 00 30 F2 70 5A 80 B0 58
It is a VESA regulation. A PC or a MNT will display an optimal 40 8A 00 40 84 63 00 00 1E 02 3A 80 18 71 38 2D 40
resolution through information sharing without any necessity 50 58 2C 45 00 40 84 63 00 00 1E 00 00 00 FD 00 3A
of user input. It is a realization of "Plug and Play". 60 3E 1E 88 3C 00 0A 20 20 20 20 20 20 00 00 00 FC
70 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 01 A0
4.1.2. Equipment EDID Block 1, Bytes 128-255 [80H-FFH]
- Since embedded EDID data is used, EDID download JIG,
0 1 2 3 4 5 6 7 8 9 A B C D E F
HDMI cable and D-sub cable are not need. 80 02 03 47 F1 58 10 9F 04 13 05 14 03 02 12 20 21
- Adjustment remote control 90 22 15 01 60 61 5D 5E 5F 65 66 62 63 64 29 3D 06
A0 C0 15 07 50 09 57 07 6E 03 0C 00 10 00 B8 3C 20
4.1.3. Download method B0 00 80 01 02 03 04 67 D8 5D C4 01 78 80 03 E3 05
(1) Press "ADJ" key on the Adjustment remote control, then C0 C0 00 E4 0F 00 C0 18 66 21 50 B0 51 00 1B 30 40
select "12.EDID D/L", By pressing "Enter" key, enter EDID D0 70 36 00 40 84 63 00 00 1E 01 1D 00 72 51 D0 1E
E0 20 6E 28 55 00 40 84 63 00 00 1E 00 00 00 00 00
D/L menu.
F0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 C7
For HDMI EDID
DVI-D to HDMI or HDMI to HDMI # HDMI 1(C/S : E6 1D) - HDMI UHD Deep Off Case
EDID Block 0, Bytes 0-127 [00H-7FH]
0 1 2 3 4 5 6 7 8 9 A B C D E F
0 00 FF FF FF FF FF FF 00 1E 6D 01 00 01 01 01 01
10 01 19 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26
20 0F 50 54 A1 08 00 31 40 45 40 61 40 71 40 81 80
30 01 01 01 01 01 01 02 3A 80 18 71 38 2D 40 58 2C
(2) S elect "Start" button by pressing "Enter" key, HDMI1/ 40 45 00 40 84 63 00 00 1E 66 21 50 B0 51 00 1B 30
HDMI2/ HDMI3/ HDMI4 are writing and display OK or NG. 50 40 70 36 00 40 84 63 00 00 1E 00 00 00 FD 00 3A
60 3E 1E 53 10 00 0A 20 20 20 20 20 20 00 00 00 FC
70 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 01 E6
4.1.4. EDID DATA
▪ Reference EDID Block 1, Bytes 128-255 [80H-FFH]
- HDMI1 ~ HDMI3 0 1 2 3 4 5 6 7 8 9 A B C D E F
- In the data of EDID, bellows may be different by Input mode. 80 02 03 38 F1 54 10 9F 04 13 05 14 03 02 12 20 21
0 1 2 3 4 5 6 7 8 9 A B C D E F 90 22 15 01 5D 5E 5F 62 63 64 29 3D 06 C0 15 07 50
0x00 00 FF FF FF FF FF FF 00 1E 6D ⓐ ⓑ A0 09 57 07 6E 03 0C 00 10 00 B8 3C 20 00 80 01 02
0x01 ⓒ 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26 B0 03 04 E5 0E 60 61 65 66 01 1D 80 18 71 1C 16 20
0x02 0F 50 54 A1 8 00 31 40 45 40 61 40 71 40 81 80 C0 58 2C 25 00 40 84 63 00 00 9E 01 1D 00 72 51 D0
0x03 01 01 01 01 01 01 02 3A 80 18 71 38 2D 40 58 2C D0 1E 20 6E 28 55 00 40 84 63 00 00 1E 00 00 00 00
0x04 45 00 40 84 63 00 00 1E 66 21 50 B0 51 00 1B 30
E0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x05 40 70 36 00 40 84 63 00 00 1E 00 00 00 FD 00 3A
F0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 1D
0x06 3E 1E 53 10 00 0A 20 20 20 20 20 20 ⓓ
0x07 ⓓ 01 ⓔ1
# HDMI 2(C/S : A0 B7) - HDMI UHD Deep On Case
0x00 02 03 3A F1 4E 10 9F 04 13 05 14 03 02 12 20 21
0x01 22 15 01 29 3D 06 C0 15 07 50 ⓕ EDID Block 0, Bytes 0-127 [00H-7FH]
0x02 ⓕ 0 1 2 3 4 5 6 7 8 9 A B C D E F
0x03 ⓕ 10 28 10 E3 05 03 01 02 3A 80 18 71 38 0 00 FF FF FF FF FF FF 00 1E 6D 01 00 01 01 01 01
0x04 2D 40 58 2C 45 00 40 84 63 00 00 1E 01 1D 80 18 10 01 19 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26
0x05 71 1C 16 20 58 2C 25 00 40 84 63 00 00 9E 01 1D 20 0F 50 54 A1 08 00 31 40 45 40 61 40 71 40 81 80
0x06 00 72 51 D0 1E 20 6E 28 55 00 40 84 63 00 00 1E
30 01 01 01 01 01 01 08 E8 00 30 F2 70 5A 80 B0 58
0x07 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ⓔ2
40 8A 00 40 84 63 00 00 1E 02 3A 80 18 71 38 2D 40
50 58 2C 45 00 40 84 63 00 00 1E 00 00 00 FD 00 3A
ⓐ Product ID
60 3E 1E 88 3C 00 0A 20 20 20 20 20 20 00 00 00 FC
ⓑ Serial No: Controlled on production line.
70 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 01 A0
ⓒ Month, Year: Controlled on production line:
ex) Monthly : ‘01’ → ‘01’, Year : ‘2015’ → ‘19’ EDID Block 1, Bytes 128-255 [80H-FFH]
ⓓ Model Name(Hex): LGTV 0 1 2 3 4 5 6 7 8 9 A B C D E F
ⓔ Checksum(LG TV): Changeable by total EDID data. 80 02 03 47 F1 58 10 9F 04 13 05 14 03 02 12 20 21
ⓕ Vendor Specific(HDMI) 90 22 15 01 60 61 5D 5E 5F 65 66 62 63 64 29 3D 06
A0 C0 15 07 50 09 57 07 6E 03 0C 00 20 00 B8 3C 20
B0 00 80 01 02 03 04 67 D8 5D C4 01 78 80 03 E3 05
C0 C0 00 E4 0F 00 C0 18 66 21 50 B0 51 00 1B 30 40
D0 70 36 00 40 84 63 00 00 1E 01 1D 00 72 51 D0 1E
E0 20 6E 28 55 00 40 84 63 00 00 1E 00 00 00 00 00
70 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 B7
# HDMI 2(C/S : E6 0D) - HDMI UHD Deep Off Case EDID Block 1, Bytes 128-255 [80H-FFH]
EDID Block 0, Bytes 0-127 [00H-7FH] 0 1 2 3 4 5 6 7 8 9 A B C D E F
0 1 2 3 4 5 6 7 8 9 A B C D E F 80 02 03 35 F1 54 10 9F 04 13 05 14 03 02 12 20 21
0 00 FF FF FF FF FF FF 00 1E 6D 01 00 01 01 01 01 90 22 15 01 5D 5E 5F 62 63 64 26 15 07 50 09 57 07
10 01 19 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26 A0 6E 03 0C 00 10 00 B8 3C 20 00 80 01 02 03 04 E5
20 0F 50 54 A1 08 00 31 40 45 40 61 40 71 40 81 80 B0 0E 60 61 65 66 01 1D 80 18 71 1C 16 20 58 2C 25
30 01 01 01 01 01 01 02 3A 80 18 71 38 2D 40 58 2C C0 00 40 84 63 00 00 9E 01 1D 00 72 51 D0 1E 20 6E
40 45 00 40 84 63 00 00 1E 66 21 50 B0 51 00 1B 30 D0 28 55 00 40 84 63 00 00 1E 00 00 00 00 00 00 00
50 40 70 36 00 40 84 63 00 00 1E 00 00 00 FD 00 3A E0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60 3E 1E 53 10 00 0A 20 20 20 20 20 20 00 00 00 FC F0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 26
70 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 01 E6
# HDMI 2(C/S : A0 C0) - HDMI UHD Deep On Case
EDID Block 1, Bytes 128-255 [80H-FFH] EDID Block 0, Bytes 0-127 [00H-7FH]
0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 4 5 6 7 8 9 A B C D E F
80 02 03 38 F1 54 10 9F 04 13 05 14 03 02 12 20 21 0 00 FF FF FF FF FF FF 00 1E 6D 01 00 01 01 01 01
90 22 15 01 5D 5E 5F 62 63 64 29 3D 06 C0 15 07 50 10 01 19 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26
A0 09 57 07 6E 03 0C 00 20 00 B8 3C 20 00 80 01 02 20 0F 50 54 A1 08 00 31 40 45 40 61 40 71 40 81 80
B0 03 04 E5 0E 60 61 65 66 01 1D 80 18 71 1C 16 20 30 01 01 01 01 01 01 08 E8 00 30 F2 70 5A 80 B0 58
C0 58 2C 25 00 40 84 63 00 00 9E 01 1D 00 72 51 D0 40 8A 00 40 84 63 00 00 1E 02 3A 80 18 71 38 2D 40
D0 1E 20 6E 28 55 00 40 84 63 00 00 1E 00 00 00 00 50 58 2C 45 00 40 84 63 00 00 1E 00 00 00 FD 00 3A
E0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60 3E 1E 88 3C 00 0A 20 20 20 20 20 20 00 00 00 FC
F0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0D 70 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 01 A0
* Checksum(HDMI 1/2) EDID Block 1, Bytes 128-255 [80H-FFH]

HDMI Deep Color On HDMI Deep Color Off 0 1 2 3 4 5 6 7 8 9 A B C D E F
Input
FFh (Checksum) FFh (Checksum) 80 02 03 44 F1 58 10 9F 04 13 05 14 03 02 12 20 21
HDMI1 A0 C7 E6 1D 90 22 15 01 60 61 5D 5E 5F 65 66 62 63 64 26 15 07
HDMI2 A0 B7 E6 0D A0 50 09 57 07 6E 03 0C 00 20 00 B8 3C 20 00 80 01
B0 02 03 04 67 D8 5D C4 01 78 80 03 E3 05 C0 00 E4
C0 0F 00 C0 18 66 21 50 B0 51 00 1B 30 40 70 36 00
2) AC3
D0 40 84 63 00 00 1E 01 1D 00 72 51 D0 1E 20 6E 28
# HDMI 1(C/S : A0 D0) - HDMI UHD Deep On Case E0 55 00 40 84 63 00 00 1E 00 00 00 00 00 00 00 00
EDID Block 0, Bytes 0-127 [00H-7FH] F0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 C0
0 1 2 3 4 5 6 7 8 9 A B C D E F
0 00 FF FF FF FF FF FF 00 1E 6D 01 00 01 01 01 01 # HDMI 2(C/S : E6 16) - HDMI UHD Deep off Case
10 01 19 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26 EDID Block 0, Bytes 0-127 [00H-7FH]
20 0F 50 54 A1 08 00 31 40 45 40 61 40 71 40 81 80 0 1 2 3 4 5 6 7 8 9 A B C D E F
30 01 01 01 01 01 01 08 E8 00 30 F2 70 5A 80 B0 58 0 00 FF FF FF FF FF FF 00 1E 6D 01 00 01 01 01 01
40 8A 00 40 84 63 00 00 1E 02 3A 80 18 71 38 2D 40 10 01 19 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26
50 58 2C 45 00 40 84 63 00 00 1E 00 00 00 FD 00 3A 20 0F 50 54 A1 08 00 31 40 45 40 61 40 71 40 81 80
60 3E 1E 88 3C 00 0A 20 20 20 20 20 20 00 00 00 FC 30 01 01 01 01 01 01 02 3A 80 18 71 38 2D 40 58 2C
70 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 01 A0 40 45 00 40 84 63 00 00 1E 66 21 50 B0 51 00 1B 30
50 40 70 36 00 40 84 63 00 00 1E 00 00 00 FD 00 3A
EDID Block 1, Bytes 128-255 [80H-FFH] 60 3E 1E 53 10 00 0A 20 20 20 20 20 20 00 00 00 FC
0 1 2 3 4 5 6 7 8 9 A B C D E F 70 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 01 E6
80 02 03 44 F1 58 10 9F 04 13 05 14 03 02 12 20 21
90 22 15 01 60 61 5D 5E 5F 65 66 62 63 64 26 15 07 EDID Block 1, Bytes 128-255 [80H-FFH]
A0 50 09 57 07 6E 03 0C 00 10 00 B8 3C 20 00 80 01 0 1 2 3 4 5 6 7 8 9 A B C D E F
B0 02 03 04 67 D8 5D C4 01 78 80 03 E3 05 C0 00 E4 80 02 03 35 F1 54 10 9F 04 13 05 14 03 02 12 20 21
C0 0F 00 C0 18 66 21 50 B0 51 00 1B 30 40 70 36 00 90 22 15 01 5D 5E 5F 62 63 64 26 15 07 50 09 57 07
D0 40 84 63 00 00 1E 01 1D 00 72 51 D0 1E 20 6E 28 A0 6E 03 0C 00 20 00 B8 3C 20 00 80 01 02 03 04 E5
E0 55 00 40 84 63 00 00 1E 00 00 00 00 00 00 00 00 B0 0E 60 61 65 66 01 1D 80 18 71 1C 16 20 58 2C 25
F0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 D0 C0 00 40 84 63 00 00 9E 01 1D 00 72 51 D0 1E 20 6E
D0 28 55 00 40 84 63 00 00 1E 00 00 00 00 00 00 00
# HDMI 1(C/S : E6 26) - HDMI UHD Deep Off Case E0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
EDID Block 0, Bytes 0-127 [00H-7FH] F0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 16
0 1 2 3 4 5 6 7 8 9 A B C D E F
0 00 FF FF FF FF FF FF 00 1E 6D 01 00 01 01 01 01 * Checksum(HDMI 1/2)
10 01 19 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26 HDMI Deep Color On HDMI Deep Color Off
Input
20 0F 50 54 A1 08 00 31 40 45 40 61 40 71 40 81 80 FFh (Checksum) FFh (Checksum)
30 01 01 01 01 01 01 02 3A 80 18 71 38 2D 40 58 2C HDMI1 A0 D0 E6 26
40 45 00 40 84 63 00 00 1E 66 21 50 B0 51 00 1B 30 HDMI2 A0 C0 E6 16
50 40 70 36 00 40 84 63 00 00 1E 00 00 00 FD 00 3A
60 3E 1E 53 10 00 0A 20 20 20 20 20 20 00 00 00 FC
70 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 01 E6
3) PCM # HDMI 2(C/S : E6 88) - HDMI UHD Deep off case
# HDMI 1(C/S : A0 42) - HDMI UHD Deep On Case EDID Block 0, Bytes 0-127 [00H-7FH]
EDID Block 0, Bytes 0-127 [00H-7FH] 0 1 2 3 4 5 6 7 8 9 A B C D E F
0 1 2 3 4 5 6 7 8 9 A B C D E F 00 00 FF FF FF FF FF FF 00 1E 6D 01 00 01 01 01 01
0 00 FF FF FF FF FF FF 00 1E 6D 01 00 01 01 01 01 01 01 19 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26
10 01 19 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26 0F 0F 50 54 A1 08 00 31 40 45 40 61 40 71 40 81 80
20 0F 50 54 A1 08 00 31 40 45 40 61 40 71 40 81 80 01 01 01 01 01 01 01 02 3A 80 18 71 38 2D 40 58 2C
30 01 01 01 01 01 01 08 E8 00 30 F2 70 5A 80 B0 58 45 45 00 40 84 63 00 00 1E 66 21 50 B0 51 00 1B 30
40 8A 00 40 84 63 00 00 1E 02 3A 80 18 71 38 2D 40 40 40 70 36 00 40 84 63 00 00 1E 00 00 00 FD 00 3A
50 58 2C 45 00 40 84 63 00 00 1E 00 00 00 FD 00 3A 3E 3E 1E 53 10 00 0A 20 20 20 20 20 20 00 00 00 FC
60 3E 1E 88 3C 00 0A 20 20 20 20 20 20 00 00 00 FC 00 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 01 E6
70 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 01 A0
EDID Block 1, Bytes 128-255 [80H-FFH]
EDID Block 1, Bytes 128-255 [80H-FFH] 0 1 2 3 4 5 6 7 8 9 A B C D E F
0 1 2 3 4 5 6 7 8 9 A B C D E F 80 02 03 32 F1 54 10 9F 04 13 05 14 03 02 12 20 21
80 02 03 41 F1 58 10 9F 04 13 05 14 03 02 12 20 21 90 22 15 01 5D 5E 5F 62 63 64 23 09 57 07 6E 03 0C
90 22 15 01 60 61 5D 5E 5F 65 66 62 63 64 23 09 57 A0 00 20 00 B8 3C 20 00 80 01 02 03 04 E5 0E 60 61
A0 07 6E 03 0C 00 10 00 B8 3C 20 00 80 01 02 03 04 B0 65 66 01 1D 80 18 71 1C 16 20 58 2C 25 00 40 84
B0 67 D8 5D C4 01 78 80 03 E3 05 C0 00 E4 0F 00 C0 C0 63 00 00 9E 01 1D 00 72 51 D0 1E 20 6E 28 55 00
C0 18 66 21 50 B0 51 00 1B 30 40 70 36 00 40 84 63 D0 40 84 63 00 00 1E 00 00 00 00 00 00 00 00 00 00
D0 00 00 1E 01 1D 00 72 51 D0 1E 20 6E 28 55 00 40 E0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
E0 84 63 00 00 1E 00 00 00 00 00 00 00 00 00 00 00 F0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 88
F0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 42
* Checksum(HDMI 1/2)
# HDMI 1(C/S : E6 98) - HDMI UHD Deep off case Input
HDMI Deep Color On HDMI Deep Color Off
EDID Block 0, Bytes 0-127 [00H-7FH] FFh (Checksum) FFh (Checksum)
HDMI1 A0 42 E6 98
0 1 2 3 4 5 6 7 8 9 A B C D E F
HDMI2 A0 32 E6 88
0 00 FF FF FF FF FF FF 00 1E 6D 01 00 01 01 01 01
10 01 19 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26
20 0F 50 54 A1 08 00 31 40 45 40 61 40 71 40 81 80
4.1.5. Green Eye inspection guide(Depending on model)
30 01 01 01 01 01 01 02 3A 80 18 71 38 2D 40 58 2C
Step 1) Turn on the TV set.
40 45 00 40 84 63 00 00 1E 66 21 50 B0 51 00 1B 30
50 40 70 36 00 40 84 63 00 00 1E 00 00 00 FD 00 3A
Step 2). Press “EYE” button on the Adjustment remote control.
60 3E 1E 53 10 00 0A 20 20 20 20 20 20 00 00 00 FC
70 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 01 E6

0 1 2 3 4 5 6 7 8 9 A B C D E F
80 02 03 32 F1 54 10 9F 04 13 05 14 03 02 12 20 21
90 22 15 01 5D 5E 5F 62 63 64 23 09 57 07 6E 03 0C
A0 00 10 00 B8 3C 20 00 80 01 02 03 04 E5 0E 60 61
B0 65 66 01 1D 80 18 71 1C 16 20 58 2C 25 00 40 84
C0 63 00 00 9E 01 1D 00 72 51 D0 1E 20 6E 28 55 00
D0 40 84 63 00 00 1E 00 00 00 00 00 00 00 00 00 00
E0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Step 3) Block the Intelligent Sensor module on the front C/A
F0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 98 about 6 seconds. When the “Sensor Data” is lower
than 20, you can see the “OK” message
# HDMI 2(C/S : A0 32) - HDMI UHD Deep On Case → If it doesn’t show “OK” message, the Sensor
EDID Block 0, Bytes 0-127 [00H-7FH] Module is defected one.
0 1 2 3 4 5 6 7 8 9 A B C D E F You have to replace that with a good one.
0 00 FF FF FF FF FF FF 00 1E 6D 01 00 01 01 01 01
10 01 19 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26
20 0F 50 54 A1 08 00 31 40 45 40 61 40 71 40 81 80
30 01 01 01 01 01 01 08 E8 00 30 F2 70 5A 80 B0 58
40 8A 00 40 84 63 00 00 1E 02 3A 80 18 71 38 2D 40
50 58 2C 45 00 40 84 63 00 00 1E 00 00 00 FD 00 3A
60 3E 1E 88 3C 00 0A 20 20 20 20 20 20 00 00 00 FC
70 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 01 A0

0 1 2 3 4 5 6 7 8 9 A B C D E F
80 02 03 41 F1 58 10 9F 04 13 05 14 03 02 12 20 21 Step 4) After check the “OK” message come out, take out
90 22 15 01 60 61 5D 5E 5F 65 66 62 63 64 23 09 57
your hand from the Sensor module.
A0 07 6E 03 0C 00 20 00 B8 3C 20 00 80 01 02 03 04
B0 67 D8 5D C4 01 78 80 03 E3 05 C0 00 E4 0F 00 C0
→ Check “Backlight” value change from “0” to “100” or
C0 18 66 21 50 B0 51 00 1B 30 40 70 36 00 40 84 63
not. If it doesn’t change the value, the sensor is also
D0 00 00 1E 01 1D 00 72 51 D0 1E 20 6E 28 55 00 40 defected one.
E0 84 63 00 00 1E 00 00 00 00 00 00 00 00 00 00 00 You have to replace it.
F0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 32
4.2. V-COM Adjust (ONLY FOR EPI model) ▪ V-com Adj. must begin as start command “va 00 00” , and
finish as end command “wb 00 ff”
4.2.1 Overview
▪ V-com adjust data
▪ V-COM adj. Objective & How-it-works
V-com Data
- O bjective: To reduce each Panel’s V-COM voltage 43 inch
deviation hex dec
- How-it-works: When V-COM gain in the adjust-OSD of Max B4 180
each SET is at default value, each SET can have flicker by Default 96 150
each Panel’s V-COM voltage deviation. In order to prevent Min 78 120
flicker of each SET, find the desired each Panel’s V-COM
V-com Data
voltage value. 49 inch
hex dec
- Adj. condition: normal temperature
1) Surrounding Temperature: 25 °C ± 5 °C Max 8B 139
2) Warm-up time: About 5 Min Default 6D 109
3) Surrounding Humidity: 20% ~ 80% Min 4F 79
V-com Data
4.2.2 Equipment 55 inch
hex dec
(1) Color Analyzer: CA-310(LED Module : CH 14) or CM-H505
Max 85 133
(2) A dj. Computer(During auto adj., RS-232C protocol is
Default 68 104
needed)
(3) Adjust Remote control Min 49 73
(4) Signal : internal flicker Pattern in SET V-com Data
▪ Color Analyzer Matrix should be calibrated using CS-100 65 inch
hex dec
Max AB 171
4.2.3 Equipment connection MAP Default 8D 141
Flicker Analyzer Min 6F 111
Probe RS-232C
Computer
USB to RS-232C
4.3. White Balance Adjustment
* If you want to use Signal Source,
you use TV internal Flicker pattern
4.3.1. Overview
▪ W/B adj. Objective & How-it-works
(1) Objective: To reduce each Panel's W/B deviation
4.2.4 Adj. Command (Protocol) (2) How-it-works : When R/G/B gain in the OSD is at 192, it
<Command Format> means the panel is at its Full Dynamic Range. In order to
CMD ID DATA CR RF prevent saturation of Full Dynamic range and data, one
of R/G/B is fixed at 192, and the other two is lowered to
-. CMD: Command find the desired value.
-. ID : Command (3) Adjustment condition : normal temperature
-. Data : Command 1) Surrounding Temperature : 25 °C ± 5 °C
Ex) [Send: va 00 00\r\n] 2) Warm-up time: About 5 Min
3) Surrounding Humidity : 20 % ~ 80 %
▪ RS-232C Command used during auto-adj.
RS-232C COMMAND 4.3.2. Equipment
Explanation (1) Color Analyzer: CA-210 (LED Module : CH 14)
[CMD ID DATA]
va 00 00 V-com pattern (2) Adjustment Computer(During auto adj., RS-232C protocol
vb 00 00 ~ FE V-com adj.(internal Flicker pattern) is needed)
wb 00 FF V-com adj. completed
(3) Adjustment Remote control
(4) Video Signal Generator MSPG-925F 720p/216-Gray
(Model: 204, Pattern: 49)
4.2.5 Adj. method → Only when internal pattern is not available
• Color Analyzer Matrix should be calibrated using CS-100.
(1) Auto adj. method
1) Set TV in POWER-ONLY mode using POWER ONLY key.
2) Zero calibrate probe then place it on the center of the
Display.
3) Connect Cable(RS-232C to USB).
4) Select Model in “V-com adj. Program” and begin “V-com
adj.”.
5) When V-com adj. is complete(OK).
6) Remove probe and RS-232C to USB cable to complete
adjustment.
4.3.3. Equipment connection MAP 4.3.5. Adj. method
(1) Auto adj. method
Co lo r Analyzer
Probe RS -232C
1) Set TV in adj. mode using POWER ON key.
Co m p ut er 2) Zero calibrate probe then place it on the center of the
RS -232C
RS -232C Display.
Pat t ern Generat o r 3) Connect Cable.(RS-232C to USB)
Signal Source
4) Select mode in adj. Program and begin adj.
5) When adj. is complete (OK Sign), check adj. status pre
* If TV internal pattern is used, not needed
mode. (Warm, Medium, Cool)

4.3.4. Adj. Command (Protocol) 6) Remove probe and RS-232C cable to complete adj.
<Command Format>
START 6E A 50 A LEN A 03 A CMD A 00 A VAL A CS STOP ▪ W/B Adj. must begin as start command “wb 00 00”, and
- LEN: Number of Data Byte to be sent finish as end command “wb 00 ff”, and Adj. offset if need.
- CMD: Command
- VAL: FOS Data value (2) Manual adjustment. method
- CS: Checksum of sent data 1) Set TV in Adj. mode using POWER ON.
- A: Acknowledge 2) Zero Calibrate the probe of Color Analyzer, then place it
Ex) [Send: JA_00_DD] / [Ack: A_00_okDDX] on the center of LCD module within 10 cm of the surface.
3) Press ADJ key → EZ adjust using adj. R/C → 7. White-
▪ RS-232C Command used during auto-adjustment. Balance then press the cursor to the right(key ►).
RS-232C COMMAND (When right key(►) is pressed 216 Gray internal pattern
Explanation will be displayed)
[CMD ID DATA]
wb 00 00 Begin White Balance adjustment 4) One of R Gain / G Gain / B Gain should be fixed at 192,
wb 00 10 Gain adjustment(internal white pattern) and the rest will be lowered to meet the desired value.
wb 00 1f Gain adjustment completed
5) Adjustment is performed in COOL, MEDIUM, WARM 3
modes of color temperature.
wb 00 20 Offset adjustment(internal white pattern)
wb 00 2f Offset adjustment completed
** G-fix adjustment
End White Balance adjustment Adjust modes (Cool), Fix the G gain to 172 (default data)
wb 00 ff
(internal pattern disappears )
and change the others (G/B Gain).
Ex) wb 00 00 → Begin white balance auto-adj. Adjust two modes(Medium / Warm), Fix the one of R/G/B
wb 00 10 → Gain adj. gain to 192 (default data) and decrease the others.
ja 00 ff → Adj. data If internal pattern is not available, use RF input. In EZ Adj.
jb 00 c0 menu 7.White Balance, you can select one of 2 Test-
... pattern: ON, OFF. Default is inner(ON). By selecting OFF,
... you can adjust using RF signal in 216 Gray pattern.
wb 00 1f → Gain adj. completed
*(wb 00 20(Start), wb 00 2f(end)) → Off-set adj. ▪ Adjustment condition and cautionary items
wb 00 ff → End white balance auto-adj. 1) Lighting condition in surrounding area
Surrounding lighting should be lower 10 lux. Try to
▪ Adj. Map isolate adj. area into dark surrounding.
Command Data Range 2) Probe location
(lower case ASCII) (Hex.) Default : Color Analyzer(CA-210) probe should be within 10 cm
Adj. item
(Decimal)
CMD1 CMD2 MIN MAX and perpendicular of the module surface (80° ~ 100°)
R Gain j g 00 C0 3) Aging time
G Gain j h 00 C0 - After Aging Start, Keep the Power ON status during 5
B Gain j i 00 C0 Minutes.
Cool - In case of LCD, Back-light on should be checked using
R Cut
G Cut
no signal or Full-white pattern.
B Cut
R Gain j a 00 C0
G Gain j b 00 C0
B Gain j c 00 C0
Medium
R Cut
G Cut
B Cut
R Gain j d 00 C0
G Gain j e 00 C0
Warm B Gain j f 00 C0
R Cut
G Cut
4.3.6.
R eference (White balance adjusmtment 4.5. Magic Motion Remote control test
coordinate and color temperature) - E quipment : RF Remote control for test, IR-KEY-Code
▪ Luminance : 206 Gray Remote control for test
▪ Standard color coordinate and temperature using CS-1000 - You must confirm the battery power of RF-Remote control
(over 26 inch) before test(recommend that change the battery per every lot)
Coordinate - Sequence (test)
Mode Temp ∆uv 1) If you select the ‘start key(OK)’ on the Adjustment remote
x y
control, you can pairing with the TV SET.
Cool 0.271 0.270 13000 K 0.0000 2) You can check the cursor on the TV Screen, when select
Medium 0.286 0.289 9300 K 0.0000 the "OK" key on the Adjustment remote control.
Warm 0.313 0.329 6500 K 0.0000 3) You must remove the pairing with the TV Set by select
‘Mute + OK Key’ on the Adjustment remote control.
▪ Standard color coordinate and temperature using CA-210(CH 14)
Mode
Coordinate
Temp ∆uv
4.6. 3D function test
x y (Pattern Generator MSHG-600, MSPG-6100[Support HDMI1.4])
Cool 0.271 ± 0.002 0.270 ± 0.002 13000 K 0.0000 * HDMI mode NO. 872 , pattern No.83
(1) Please input 3D test pattern like below.
Medium 0.286 ± 0.003 0.289 ± 0.003 9300 K 0.0000
Warm 0.313 ± 0.002 0.329 ± 0.002 6500 K 0.0000
4.3.7. EDGE & IOL LED White balance table

▪ Edge & ALEF LED module change color coordinate because
of aging time.
▪ Apply under the color coordinate table, for compensated
aging time. (2) When 3D OSD appear automatically, then select green key.
▪ (Normal line) Edge & ALEF LED White balance table
- gumi(Mar.~Dec.) & Global
Model : (normal line)LGD, CMI
Aging Cool Medium Warm
time x y x y x y
(Min) 271 270 286 289 313 329
1 0-2 282 289 297 308 324 348
2 3-5 281 287 296 306 323 346
3 6-9 279 284 294 303 321 343
4 10-19 277 280 292 299 319 339
5 20-35 275 277 290 296 317 336
6 36-49 274 274 289 293 316 333 (3) Don't wear a 3D Glasses, Check the picture like below.
7 50-79 273 272 288 291 315 331
8 80-119 272 271 287 290 314 330
9 Over 120 271 270 286 289 313 329
4.4. Local Dimming Function Check

(1) Turn on TV.
(2) A t the Local Dimming mode, module Edge Backlight
moving right to left Back light of IOP module moving.
(3) Confirm the Local Dimming mode.
(4) Press “exit” Key.
4.7. Option selection per country 5. GND and Internal Pressure check
4.7.1. Overview 5.1. Method
- Option selection is only done for models in AJ/JA/IL (1) GND & Internal Pressure auto-check preparation
- Check that Power Cord is fully inserted to the SET. (If
4.7.2.Method loose, re-insert)
(1) Press "ADJ" key on the Adjustment remote control, then (2) Perform GND & Internal Pressure auto-check
select Country Group Menu. - Unit fully inserted Power cord, Antenna cable and A/V
(2) Depending on destination, select Country Group Code or arrive to the auto-check process.
Country Group then on the lower Country option, select - Connect D-terminal to AV JACK TESTER
US, CA, MX. Selection is done using +, - or ►◄ KEY. - Auto CONTROLLER(GWS103-4) ON
- Perform GND TEST
4.8. HDMI ARC Function Inspection - If NG, Buzzer will sound to inform the operator.
(1) Test equipment - If OK, changeover to I/P check automatically.
- Optic Receiver Speaker (Remove CORD, A/V form AV JACK BOX.)
- MSHG-600 (SW: 1220 ↑) - Perform I/P test
- HDMI Cable (for 1.4 version) - If NG, Buzzer will sound to inform the operator.
- If OK, Good lamp will lit up and the stopper will allow the
(2) Test method pallet to move on to next process.
1) Insert the HDMI Cable to the HDMI ARC port from the
master equipment. (HDMI2) 5.2. Checkpoint
▪ TEST voltage
- GND: 1.5 KV / min at 100 mA
- SIGNAL: 3 KV / min at 100 mA
▪ TEST time: 1 second
▪ TEST POINT
- GND TEST = POWER CORD GND & SIGNAL CABLE
METAL GND
- Internal Pressure TEST = POWER CORD GND & LIVE &
NEUTRAL
▪ LEAKAGE CURRENT: At 0.5 mArms
2) Check the sound from the TV Set. 6. Audio

No. Item Min Typ Max Unit
Audio practical max 10 12 W EQ Off
1 Output, L/R(Distortion AVL Off
= 10 % max Output) 8.10 10.8 Vrms Clear Voice Off
EQ On
Speaker
2 10 12 W AVL On
(8 Ω Impedance)
Clear Voice On
3) Check the Sound from the Speaker or using AV & Optic Measurement condition:
TEST program (It’s connected to MSHG-600) (1) RF input: Mono, 1 KHz sine wave signal, 100 % Modulation
(2) CVBS, Component: 1 KHz sine wave signal 0.5 Vrms
4.9. Tool Option selection
- Method : Press "ADJ" key on the Adjustment remote control,
then select Tool option.
4.10. Ship-out mode check (In-stop)

- After final inspection, press In-Stop key of the Adjustment
remote control and check that the unit goes to Stand-by
mode.
7. USB S/W Download(Service only)
(1) Put the USB Stick to the USB socket.
(2) Go to General menu then enter to About This TV.
- If your downloaded program version in USB Stick is
Lower, it didn’t work.
B ut your downloaded version is Newer, USB data is
automatically detecting. (Download Version High & Power
only mode, Set is automatically Download)
(3) Show the message “Copying files from memory”.
(4) Updating is starting.

(5) Updating completed, the TV will restart automatically
(6) If your TV is turned on, check your updated version and
Tool option. (explain the Tool option, next stage)
* If downloading version is more new than your TV have,
TV can lost all channel data. In this case, you have to
channel recover. if all channel data is cleared, you didn’t
have a DTV/ATV test on production line.
* After downloading, have to adjust Tool Option again.

(1) Push "IN-START" key in service remote control.
(2) Select "Tool Option 1" and push "OK" key.
(3) Punch in the number. (Each model has their number)
Copyright ©
X_TAL
24MHz
CI Slot DDR3 1866 X 32
T2/C/S2 W/O AD (512MB X 2EA)
P_TS
P_TS
1. LM14A(+URSA11)
Air/ A B

Cable TUNER DDR3 1866 X 32
R IF (+/-) (256MB X 2EA)
E (T2/C/A)
A P_TS
R DVB-S EEPROM(NVRAM)
TUNER DEMOD I2C 1
(S2) CVBS (256Kb)
(S2)
LG Electronics. Inc. All rights reserved.

LNB eMMC
(4GB)
Vx1
Mstar URSA11
51P
- 21 -
OCP LM14A
USB1 (2.0) USB
With URSA model
HDMI1 (4K@60Hz/DVI)
HDMI
HDMI2(ARC)
I2S Out MAIN Audio AMP
BLOCK DIAGRAM
I2C 4 (NTP7515)
USB_WIFI WIFI
SUB
AV/COMP CVBS/YPbPr ASSY
SCART
CVBS/RGB IR / KEY
(IN/OUT)
OPTIC SPDIF OUT

I2C 3 Sub Micom X_TAL
LAN ETHERNET (HW Port) (RENESAS 32.768KHz
R5F100GEAFB)
LGE Internal Use Only

2. Internal
3. I2C
Copyright ©
+3.3V_NORMAL
MSTAR
LM14A
1.8KΩ
+3.3V_TU
I2C SCL/SDA4(SW)
GPIO19 / [LED0] / GPIO74

IC5800 100Ω
NTP7515(Main AMP) GPIO20 / [LED1] / GPIO75
1.8KΩ
I2C_SCL/SDA2(HW)
33pF +3.3V_NORMAL
GPIO30 / SCK4
33Ω TU6702
GPIO31 / SDA4 TUNER

1.8KΩ +3.3V_NORMAL
I2C SCL/SDA3(HW)
IC3000 GPIO28 / SCK0 / GPIO83
RENESAS 33Ω
GPIO29 / SDA0 /GPIO84 1.8KΩ
MICOM
- 23 -
I2C SCL/SDA1(HW)
DDCR_CK/ SCK3 / GPIO54
+3.3V_NORMAL 33Ω IC101
DDCR_DA / SDA3 / GPIO53 NVRAM
+3.3V_LNA_TU
1.8KΩ
I2C_SCL/SDA6(SW)
DIM2 / TX4 / GPIO112
IC7700
33Ω 1.8KΩ
SW5094A (PMIC) DIM3 / RX4 / GPIO113
I2C SCL/SDA5(HW)
GPIO32 / SCK5 / GPIO87 TU6702
33Ω
GPIO33 / SDA5 / GPIO88 TUNER

Copyright ©
4. URSA11

Power +13.5V
I2C_SDA6
I2C_SCL6
I2C_SCL7 V x1
URSA11 PQ
HTPDn_IN
LOCKn_IN
PANEL_VCC
(+12V)
URSA I2C_SDA7 8 lane

DC- DC Converter +1.5V_U_DDR UART2_RX DEBUG
Data_Format_0
Data_Format_1
UART I2CS_SCL
(BD9D320EFJ _3A) Switch
(URSA DDR) UART2_TX
I2CS_SDA 51P
URSA11 SYS
DC- DC Converter +1.15V
IRE SCL2_+3.3V_DB
(MP8762HGLE-Z_10A) I2C_S Port
UART

(URSA) 4 Pin
UART1_TX SDA2_+3.3V_DB
Jig Download
X-Tal
(24Mhz)
- 24 -
XO_URSA
XIN_URSA
LOCKn
HTPDn
Data_Format_1
Vx1 VIDEO 8Lane
Data_Format_2
3D_EN
Vx1 OSD 4Lane L_DIM_EN
SPI_DI SPI FLASH
LM14A LOCKAn_OSD / LOCKAN_Video URSA11 SPI_DO/CK/CS (4MB)
IRE
UART1_TX
UART2_RX
UART2_TX
URSA9_CONNECT I2CS_SCL
I2CS_SDA

Copyright ©
5. Tuner/CI
TDJM-G301D +3.3V_NORMAL
+2.5V_NORMAL
[+3.3V_LNA_TU] 1
[+3.3V_TUNER] 11
[3.3V_Demod_TU] 26
[+2.5V_DEMOD] 38 +3.3V_NORMAL
+1.1V_Demod_Core
[1,1V_D_Demod_Core] 28 1.8KΩ CI Slot

LNB_TX 10 [TONECTRL]
[LNB_TX] 29 LNB PCM_5V_CTL CI 5V +5V_CI_ON
LNB_OUT 2 [LNB] VCC
[LNB_OUT] 31 IC6900 Power detect
I2C_SCL2 7 [SCL]
[I2C_SCL2_TU] 27 A8303SESTR-TB
33Ω 8 [SDA]
[I2C_SDA2_TU] 30 I2C_SDA2
+5V_CI_ON
F5[SCK2]
LM14A
33 Ω
F6 [SDA2] AE3[GPIO_PM4] CAM_CD1_N 10K Ω
/CI_CD1 CI_CD1

[I2C_SCL5_TU] 4 I2C_SCL5 OR
33 Ω F10[SCK5] AR17[PCMCD] /CI_CD2
[I2C_SDA5_TU] 5 I2C_SDA5 G10[SDA5] GATE CI_CD2
AP13[TS2CLK] CI_MISTRT
FE_DEMOD1_TS_ERROR AP12[TS2VALID] CI_MIVA_ERR
[FE_DEMOD1_TS_ERROR_TU] 12
AM13[TS2SYNC] /PCM_CE1 CI_MCLKI
FE_DEMOD1_TS_CLK AM13[PCMCEN]
[FE_DEMOD1_1_TS_CLK] 14 PCM_CE1
FE_DEMOD1_TS_SYNC AN11[TS0CLK]
[FE_DEMOD1_TS_SYNC] 15 AP9(TS0SYNC]
FE_DEMOD1_TS_VAL EB_BE_NO
[FE_DEMOD1_TS_VAL] 16 AN9[TS0VALID] AT15[PCMIOWR] CI_IOWR
EB_BE_N1
AR15PCMIORD] CI_IORD
- 25 -
FE_DEMOD1_TS_DATA[0] 17
FE_DEMOD1_TS_DATA[2] 19 EB_ADDR[0-14] CI_ADDR[0-14]
FE_DEMOD1_TS_DATA[3] 20 AU10-AR19 CI_ADDR[0-14]
FE_DEMOD1_TS_DATA [0-7] AP10~AM9
FE_DEMOD1_TS_DATA[4] 21 [TS0DATA[0-7] EB_DATA[0-7] CI_DATA[0-7]
FE_DEMOD1_TS_DATA[5] 22 AT13-AT18 EB_DATA[0-7]
FE_DEMOD1_TS_DATA[7] 24 AU11[PCMRST]
PCM_RESET
PCM_RESET
AT10[PCMWAIT] CAM_WAIT_N CAM_WAIT_N
CAM_REG_N
REG
AR14[PCMREG]
CAM_IREQ_N CAM_IREQ_N
AU20[PCMIRQA]
/EB_OE_N
AT21[PCMOEN] CI_OE
RF_SWITCH_CTL /EB_WE_N
A15 [GPIO159] AR11[[PCMWEN] CI_WE
[RF_SWITCH_CTL] 2 /TU_RESET1
A12 [GPIO62] TPI_CLK CI_TS_CLK
[/TU_RESET1_TU] 25 AN17[TS1CLK] TS_OUT_CLK
TPI_VAL CI_TS_VAL
AM17[TS1VALID] TS_OUT_VAL
IF_P ADC_I_INP TPI_SOP CI_TS_SYNC
AP1 [VIFP] AN16[TS1SYNC] TS_OUT_SYNC
[IF_P] 6 IF_N FILTER ADC_I_INN
AP2 [VIFM] TPI_DATA[0-7]
[IF_N] 7 AN16~AP19 TPI_DATA[0-7]
TUNER_SIF 33Ω TS_OUT[0-7]
AN2[SIFP] [TPI_DATA[0-7]]
[TU_SIF_TU] 8
TU_CVBS FE_DEMOD1_TS_DATA [0-7] CI_MDI[0-7]
[TU_CVBS_TU] 9 AE5[CVBS0] AM14~AM15 TS_IN[0-7]
[TPO_DATA[0-7]]
33Ω
IF_AGC
[IF_AGC_TU] 3 AP3[IF_AGC]

Copyright ©
Jack Side SoC
Side
JK3802
COMP1_Y COMP1_Y
[GIN1P]
COMP1_Pb COMP1_Pb
6. Video/Audio In
[BIN1P]
COMP1_Pr COMP1_Pr

[RIN1P]
AV1_CVBS_IN AV1_CVBS_IN
[CVBS1]
COMP1/AV1/DVI_L_IN COMP1/AV1/DVI_L_IN
[LINE_IN_0L]
COMP1/AV1/DVI_R_IN COMP1/AV1/DVI_R_IN
[LINE_IN_0R]

SCART
SC_CVBS_IN SC_CVBS_IN LM14A
[CVBS2]
- 26 -
SC_FB/ID SC_FB/ID
[VSYNC0,HSYNC0]
SC_R/G/B SC_R/G/B
[RIN0P,GIN0P,BIN0P]
SC_L/R_IN SC_L/R_IN
[LINE_IN_1L,LINE_IN_1R]
DTV/MNT_V_OUT DTV/MNT_V_OUT
[CVBSOUT1]
DTV/MNT_L/R_OUT SCART_L/Rout
[LINEOUT_L2, LINEOUT_R2]
JK4600
Tuner TU_CVBS_TU TU_CVBS

[CVBS0]
TUNER_SIF, IF_P/N_TU TUNER_SIF, IF_P/N

[SIFP,VIFP/VIFM]
FE_DEMOD1/2_TS_ERROR,CLK,SYNC,VAL FE_DEMOD1/2_TS_ERROR,CLK,SYNC,VAL
[TS0CLK,TS0SYNC,TS0VALID]

Copyright ©
7. Audio Out
SCART
SCART_L/ Rout IC6000 DTV/MNT_L/R_OUT

[ LINEOUT_L2]
COMP1/ AV1/ DVI_L_IN AZ4580MTR LPF
[ LINEOUT_R2]
COMP1/ AV1/ DVI_R_IN

[ LINEIN_L0] OP AMP
[ LINE_N_R0]
Mute CTRL
JK3802 (TR)
JK4600
DVB only
SCART
SCART_MUTE

SC_L_IN / SC_R_IN [ LINEIN_L1] AUD_LRCK
[ I2S_OUT_WS/ GPIO98]
[ LINE_N_R1]
AUD_LRCH
[ I2S_OUT_SD/ GPIO101] 4P WAFER
AUD_SCK
[ I2S_OUT_BCK/ GPIO100]
IC5800 LPF SPEAKER_L
DVB only I2C_SDA4
Audio AMP
JK4600 [ GPIO20/ [ LED1] / GPIO75]
NTP7515 LPF SPEAKER_R
[ GPIO19/ [ LED0] / GPIO74]
I2C_SCL4
- 27 -
[ PWM3/ GPIO155] AMP_RESET_N
LM14A AMP_MUTE
Tuner
TUNER_SIF
TR BUF [ SIFP]
IC3000
MICOM
SPDIF_OUT
[ SPDIF_OUT]
JK3800

Copyright ©
8. HDMI
[DDCDD_CK/GPIO44] DDC_SCL_3
DDC_SDA_3
[DDCDD_DA/GPIO45]
TMDS Link 8bits
HDMI2&External EDID
IC3301 HDMI1.4(ARC)

LM14A EDID External
EDID

- 28 -
CEC_REMOTE
DDC_SCL_1
[DDCDA_CK/GPIO38]
DDC_SDA_1
[DDCDA_DA/GPIO39]
TMDS Link 8bits
MHL_DET_LM15
[GPIO_PM[14]/GPIO24]
HDMI1&MHL
HDMI2.0
X-Tal(X3000) RENESAS
32.768kHz MICOM(IC3000) Q3001
* TMDS Link 8bits = TMDS DATA 6bits(DATA0,1,2)+ TMDS CLK 2bits HDMI_CEC_MICOM

Copyright ©
USB_DM3 USB1
[DM_P2] +5V_USB_3
[DP_P2] USB_DP3
[TGPIO0/GPIO157] /USB_OCD3
OCP USB2.0
[TGPIO1/GPIO158] IC2302
USB_CTL3

[DM_PSS1]
[DP_PSS1]
[SAR0/GPIO46]
[SAR1/GPIO47]

[DM_PSS]
9. USB / WIFI / M-REMOTE / UART
[DP_PSS]
LM14A
[SSUSB_RXP/N]
[SSUSB_TXP/N]
- 29 -
[GPIO_PM[1]/PM_UART1/GPIO11]
[GPIO_PM[5]/PM_UART1/GPIO15]
WIFI_DM
[DM_P0]
[DP_P0] WIFI_DP
WIFI only
M_RFModule_RESET
[GPIO_PM[10]/[SPI-CZ2N]/GPIO20]
SOC_TX
[GPIO3/TX1/GPIO58]
SOC_RX
[GPIO4/RX1] RS232C_Debug(4P wafer)
RENESAS MICOM(IC3000)

EXPLODED VIEW
IMPORTANT SAFETY NOTICE
Many electrical and mechanical parts in this chassis have special safety-related characteristics. These
parts are identified by in the Schematic Diagram and EXPLODED VIEW.
It is essential that these special safety parts should be replaced with the same components as
recommended in this manual to prevent Shock, Fire, or other Hazards.
Do not modify the original design without permission of manufacturer.
900
400
901
570
800
571
521
120
540
121
530
(Option)
LV2
LV1
820
500
Set + Stand
A10
A2
200
LD59R
(LM14A)
Copyright © 2015 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
SPI_CK_SOC COMPENSATION_DONE OLED
LM14A+URSA9
SPI_DI_SOC TXVBY1_0N
FAN_ON LM14A UF68/64
+3.3V_NORMAL SPI_DO_SOC FRC_FLASH_SEL_SOC TXVBY1_0P
CHIP CONFIG NVRAM +3.3V_NORMAL
/SPI_CS TXVBY1_1N /TU_RESET2
Rohm_NVRAM
IC101-*1
FRC_FLASH_WP GST_A LM14A UF74
BR24G256FJ-3
EAN62389502 TXVBY1_1P
ROHM Semiconductor KOREA CORPORATION
TXOSD_3P LOCKAn_OSD GCLK_A
4.7K
4.7K
4.7K
Atmel_NVRAM WOL_WAKE_UP_SOC
4.7K
A0 VCC
IC101 1 8
TXOSD_3N URSA9_CONNECT MCLK_A PMIC_RESET 5V_DET_HDMI_1

AT24C256C-SSHL-T C100 A1
2 7
WP
Data_Format_1
OPT
EO_A
OPT
EAN61133501
ATMEL CORPORATION
0.1uF A2
3 6
SCL
TXOSD_2P DATA_FORMAT_1_SOC LM14A_ONLY LOCKOUT12 /USB_OCD3
GND
4 5
SDA
TXOSD_2N Data_Format_0
R108
R110
R115
DATA_FORMAT_0_SOC USB_CTL3
R122
TXOSD_1P URSA_RESET_SoC
A0 VCC HTPDAn_OSD
1 8 L/D_VSYNC_SOC
TXOSD_1N
HTPDAn_Video IC100
Write Protection L/D_CLK_SOC
LED1 A1 WP
TXOSD_0P LGE5332(LM14A)
2 7
TXOSD_0N L/D_DI_SOC
SPI_DI_SOC - Low : Normal Operation IC100
- High : Write Protection EB_DATA[0-7]
LED0 A2
3 A0’h SCL LGE5332(LM14A)
6
EB_DATA[0]
PWM_PM I2C_SCL1
V-BY-ONE AH14
4.7K
4.7K
4.7K
FE_DEMOD1_TS_DATA[0-7]
4.7K
EB_DATA[1] PCM_D[0]/GPIO147 FE_DEMOD1_TS_DATA[0]

GND SDA I2C_SDA1 AG13 AH13
4 5 PCM_D[1]/GPIO148 TS1_D0/GPIO182
EB_DATA[2] FE_DEMOD1_TS_DATA[1]
OPT
OPT
33 D9 AF32 AG12 AG11

AR101 PWM_DIM TXVBY1_0N PCM_D[2]/GPIO149 TS1_D1/GPIO181
PWM0/GPIO152 LVSYNC/[VX1_0-] EB_DATA[3] AK22 AG10 FE_DEMOD1_TS_DATA[2]
F10 AF31
R109
TXVBY1_0P
R111
R116
PWM_DIM2
R123
PWM1/GPIO153 LHSYNC/[VX1_0+] EB_DATA[4] PCM_D[3]/GPIO119 TS1_D2/GPIO180 FE_DEMOD1_TS_DATA[3]

F8 AG32 AK21 AJ11
FAN_ON TXVBY1_1N PCM_D[4]/GPIO120 TS1_D3/GPIO179
PWM2/GPIO154 LDE/[VX1_1-] EB_DATA[5] AL21 AH10 FE_DEMOD1_TS_DATA[4]
E9 AG31 TXVBY1_1P
AMP_RESET_N PWM3/GPIO155 LCK/[VX1_1+] EB_DATA[6] PCM_D[5]/GPIO121 TS1_D4/GPIO178 FE_DEMOD1_TS_DATA[5]
AM23 AJ13
EB_DATA[7] PCM_D[6]/GPIO122 TS1_D5/GPIO177 FE_DEMOD1_TS_DATA[6]
N5 AH31 AH20 AG9
PWM_PM TXVBY1_2N EB_ADDR[0-14] PCM_D[7]/GPIO123 TS1_D6/GPIO176
PWM_PM/GPIO7 R_ODD[7]/LVB0N/[VX1_2-] AH9 FE_DEMOD1_TS_DATA[7]
AH30 TXVBY1_2P
R_ODD[6]/LVB0P/[VX1_2+] EB_ADDR[0] TS1_D7/GPIO175
F4 AJ31 AG14 AH11
TXVBY1_3N PCM_A[0]/GPIO146 TS1_CLK/GPIO172 FE_DEMOD1_TS_CLK
CHIP_CONFIG[3:0] /USB_OCD2 SAR0/GPIO46 R_ODD[5]/LVB1N/[VX1_3-] EB_ADDR[1] AL20 AJ10
G5 AJ32 TXVBY1_3P
{LED1, SPI_DI,LED0, PWM_PM} USB_CTL2 SAR1/GPIO47 R_ODD[4]/LVB1P/[VX1_3+] EB_ADDR[2] PCM_A[1]/GPIO145 TS1_VLD/GPIO174 FE_DEMOD1_TS_VAL
E5 AK32 AG15 AH12
FRC_FLASH_WP TXVBY1_4N PCM_A[2]/GPIO143 TS1_SYNC/GPIO173 FE_DEMOD1_TS_SYNC
Value Mode Description SAR2/GPIO48 R_ODD[3]/LVB2N/[VX1_4-] EB_ADDR[3] AH15
E4 AK31 TXVBY1_4P TPI_DATA[0-7]
4’b1000 SB51_ExtSPI 51 boot from SPI DDTS_TX SAR3/GPIO49 R_ODD[2]/LVB2P/[VX1_4+] EB_ADDR[4] PCM_A[3]/GPIO142 TPI_DATA[0]
4’b1001 HEMCU_ExtSPI ARM boot from SPI G4 AL32 AM19 AK17
TXVBY1_5N PCM_A[4]/GPIO141 TS0_D0/GPIO161
SAR5 R_ODD[1]/LVBCLKN/[VX1_5-] EB_ADDR[5] AJ17 AL18 TPI_DATA[1]
4’b1010 HEMCU_ROM_EMMC ARM boot from ROM; outer storage is eMMC AL31 TXVBY1_5P
4’b1011 HEMCU_ROM_NAND ARM boot from ROM; outer storage is NAND R_ODD[0]/LVBCLKP/[VX1_5+] EB_ADDR[6] PCM_A[5]/GPIO139 TS0_D1/GPIO162 TPI_DATA[2]
AK30 AJ16 AK18
4’b1100 DBUS for test only TXVBY1_6N PCM_A[6]/GPIO138 TS0_D2/GPIO163
G_ODD[7]/LVB3N/[VX1_6-] EB_ADDR[7] AH17 AL15 TPI_DATA[3]
4’b0000 SB51_ExtSPI + Authentication 51 boot from SPI with ARM authentication W5 AL30 TXVBY1_6P
SPI_CK_SOC PM_SPI_CK/GPIO1 G_ODD[6]/LVB3P/[VX1_6+] EB_ADDR[8] PCM_A[7]/GPIO137 TS0_D3 TPI_DATA[4]
4’b0001 SB51_ExtSPI + Authentication HEMCU_ExtSPI + Authentication V4 AK29 AM20 AL16
SPI_DI_SOC TXVBY1_7N PCM_A[8]/GPIO131 TS0_D4/GPIO165
4’b0011 HEMCU_ROM_NAND + Authentication ARM boot from ROM with authentication; PM_SPI_DI/GPIO2 G_ODD[5]/LVB4N/[VX1_7-] EB_ADDR[9] AH19 AK15 TPI_DATA[5]
V5 AL29 TXVBY1_7P
SPI_DO_SOC PM_SPI_DO/GPIO3 G_ODD[4]/LVB4P/[VX1_7+] EB_ADDR[10] PCM_A[9]/GPIO129 TS0_D5/GPIO166 TPI_DATA[6]
Y6 AJ20 AM16
/TU_RESET1 PM_SPI_CZ/GPIO0 EB_ADDR[11] PCM_A[10]/GPIO125 TS0_D6/GPIO167 TPI_DATA[7]
R167 0 Y4 AK28 TXOSD_0N
AK20 AK16
/SPI_CS GPIO_PM[6]/[SPI-CZ1N]/GPIO16 G_ODD[3]/LVA0N/[OSD_0-] EB_ADDR[12] PCM_A[11]/GPIO127 TS0_D7/GPIO168
OPT Y5 AM28 AG17 AL19
TXOSD_0P PCM_A[12]/GPIO136 TS0_CLK/GPIO171 TPI_CLK
GPIO_PM[10]/[SPI-CZ2N]/GPIO20 G_ODD[2]/LVA0P/[OSD_0+] EB_ADDR[13] AJ19 AM17
LM14 HW Option M_RFModule_RESET
G_ODD[0]/LVA1P/[OSD_1+]
AL28
AK27
TXOSD_1N
TXOSD_1P
EB_ADDR[14] AG18
PCM_A[13]/GPIO132 TS0_VLD/GPIO169
AL17
TPI_VAL
G_ODD[1]/LVA1N/[OSD_1-] PCM_A[14]/GPIO133 TS0_SYNC/GPIO170 TPI_SOP
AK26 TXOSD_2N
+3.3V_NORMAL B_ODD[7]/LVA2N/[OSD_2-] AH18 AH23
AL8 AL26 TXOSD_2P
DDCA_CK DDCA_CK/GPIO8 B_ODD[6]/LVA2P/[OSD_2+] SM_Vsel CAM_IREQ_N PCM_IRQA_N/GPIO135 TS3_D0/GPIO206 POL EPI
AK8 AM26 AM22 AH27
DDCA_DA TXOSD_3N SM_CLK EB_OE_N PCM_OE_N/GPIO126 TS3_D1/GPIO207 GST_A GST
DDCA_DA/GPIO9 B_ODD[5]/LVACLKN/[OSD_3-] AG20 AJ23
AK25 TXOSD_3P GCLK
B_ODD[4]/LVACLKP/[OSD_3+] SM_RST EB_BE_N1 PCM_IORD_N/GPIO128 TS3_D2/GPIO208 GCLK_A
AL25 AL22 AG27
B_ODD[3]/LVA3N/[LOCKN] LOCKAn_Video SM_IO /PCM_CE1 PCM_CE_N/GPIO124 TS3_D3/GPIO209 MCLK_A MCLK
AH28 AK24 AK19 AH24
10K
10K
10K
10K
10K
10K
10K
10K
EB_WE_N PCM_WE_N/GPIO134 OPT_P

10K
10K
TS3_D4/GPIO210
10K
10K
SOC_TX GPIO3/TX1/GPIO58 B_ODD[2]/LVA3P/[HTPDN] HTPDAn_Video SM_VCC

BIT2_1
BIT10_1
BIT11_1
BIT0_1
BIT1_1
BIT3_1
BIT4_1
BIT5_1
BIT6_1
BIT7_1
BIT8_1
AG21 AH26
BIT9_1
AH29 AL24
SOC_RX GPIO4/RX1 B_ODD[1]/LVA4N/[OSD_LOCKN] LOCKAn_OSD CAM_CD1_N PCM_CD_N/GPIO151 TS3_D5/GPIO211 SOE
AA4 AK23 AH16 AJ25
FRC_FLASH_SEL_SOC GPIO23/[TX3]/GPIO78 B_ODD[0]/LVA4P/[OSD_HTPDN] HTPDAn_OSD PCM_RESET PCM_RESET/GPIO150 TS3_D6/GPIO212 FB
W6 AJ14 AG26
R119
R112
R125
R128
R132
R135
R138
R140
R142
R146
R105
R148
/TU_RESET2 GPIO24/[RX3]/GPIO79 CAM_REG_N PCM_REG_N/GPIO144 TS3_D7/GPIO213 EO_A E/O

F14 AG19 AH25
I2C_SCL6 DIM2/TX4/GPIO112 SM_CD EB_BE_N0 PCM_IOWR_N/GPIO130 TS3_CLK/GPIO216 HCONV
F12 AG16 AJ26
BIT0 I2C_SDA6 DIM3/RX4/GPIO113 CAM_WAIT_N PCM_WAIT_N/GPIO140 TS3_VLD/GPIO214 DPM
AG24
BIT1 TS3_SYNC/GPIO215 LOCKOUT12 LOCK
AJ27
CPU_VID1 GPIO2/GPIO57
BIT2
C7
BIT3 BIT0 EMMC_IO15/[GPIO]/GPIO189
C6
BIT1 EMMC_IO17/[GPIO]/GPIO188
BIT4 AE2 C8 AJ28
GPIO_PM[0]/GPIO10 COMP1_DET EMMC_CMD EMMC_IO9/[EMMC_CMD]/GPIO183 GPIO8/[TS4_D[0]]/GPIO63 FE_DEMOD3_TS_DATA
B8 AG28
BIT2 EMMC_IO14/[GPIO]/GPIO185 GPIO5/[TS4_CLK]/GPIO60 FE_DEMOD3_TS_CLK
1K
R176
BIT5 U6 A9 AJ29
GPIO_PM[3]/GPIO13 DDTS_RX EMMC_CLK EMMC_IO10/[EMMC_CLK]/GPIO186 GPIO7/[TS4_VLD]/GPIO62 FE_DEMOD3_TS_VAL
P4 B7 AG29
BIT6 GPIO_PM[4]/GPIO14 PCM_5V_CTL R175 TCON_I2C_EN BIT3 EMMC_IO16/[GPIO]/GPIO187 GPIO6/[TS4_SYNC]/GPIO61 FE_DEMOD3_TS_SYNC
U5 22 B9
GPIO_PM[7]/GPIO17 EMMC_RST EMMC_IO11/[EMMC_RSTN]/GPIO190
AE5 A8
BIT7 PMIC_RESET BIT4 EMMC_IO12/[GPIO]/GPIO184
GPIO_PM[8]/GPIO18 C9
AJ7 AJ5
I2C_SCL3 GPIO28/SCK0/GPIO83 GPIO_PM[9]/GPIO19 COMPENSATION_DONE EMMC_STRB EMMC_IO8/[NAND-DQS]/GPIO191
BIT8 AH8 AG6 B6
I2C_SDA3 EMMC_DATA[0-7] BIT5 EMMC_IO13/[GPIO]/GPIO217
GPIO29/SDA0/GPIO84 GPIO_PM[13]/GPIO23 URSA9_CONNECT
E11
BIT9 I2C_SCL1 DDCR_CK/SCK3/GPIO54 EMMC_DATA[6] C10
E10
I2C_SDA1 DDCR_DA/SDA3/GPIO53 EMMC_DATA[7] EMMC_IO6/[EMMC_D6]/GPIO221
AJ6 B11
I2C_SCL2 GPIO30/SCK4/GPIO85 EMMC_DATA[2] EMMC_IO7/[EMMC_D7]/GPIO220
AG8 A11
I2C_SDA2 GPIO31/SDA4/GPIO86 EMMC_DATA[1] EMMC_IO2/[EMMC_D2]/GPIO219
BIT10 AH7 P5 C11
I2C_SCL5 GPIO32/SCK5/GPIO87 GPIO_PM[1]/PM_UART1/GPIO11 /USB_OCD1 EMMC_DATA[0] EMMC_IO1/[EMMC_D1]/GPIO218
AJ8 P6 A12 AL2
BIT11 I2C_SDA5 GPIO33/SDA5/GPIO88 GPIO_PM[5]/PM_UART1/GPIO15 USB_CTL1 EMMC_DATA[3] EMMC_IO0/[EMMC_D0]/GPIO194 VIFP
AJ4 B12 AM2
GPIO_PM[11]/PM_UART0/GPIO21 DATA_FORMAT_0_SOC EMMC_DATA[4] EMMC_IO3/[EMMC_D3]/GPIO193 VIFM
AH4 C12
GPIO_PM[12]/PM_UART0/GPIO22 DATA_FORMAT_1_SOC EMMC_DATA[5] EMMC_IO4/[EMMC_D4]/GPIO192
B13 AK1 Close to MSTAR DTV_IF
EMMC_IO5/[EMMC_D5]/GPIO222 SIFP
AK2
10K
10K
10K
10K
10K
10K
10K
10K
10K
SIFM
10K
10K
10K
L6 G7 R183 100 C103 0.1uF OPT IF_P

BIT10_0
BIT11_0
BIT2_0
BIT0_0
BIT1_0
BIT7_0
BIT8_0
BIT9_0
BIT4_0
BIT3_0
BIT5_0
BIT6_0
CPU_VID0 VID0/GPIO50 TESTPIN C107

M6 AK3 100pF
CORE_VID0 VID1/GPIO51 IFAGC
AD5
R126
LED0
R129
R106
R133
R136
R139
R141
LED0/GPIO29
R143
R147
R149
R113
R120
AD4
LED1 LED1/GPIO30 R184 100 C104 0.1uF OPT IF_N
AB5 AJ1 C109
WOL_WAKE_UP_SOC WOL_INT_OUT/[GPIO]/GPIO52 TGPIO0/GPIO157 /USB_OCD3 33pF OPT
E13 AJ2 C110
SPI1_DI/GPIO107 HP_DET TGPIO1/GPIO158 USB_CTL3 33pF
D12 R4
SPI1_CK/GPIO106 RF_SWITCH_CTL TGPIO2/SCK1/GPIO159 I2C_SCL7
F11 R5
SPI2_DI/GPIO109 L/D_DI_SOC TGPIO3/SDA1/GPIO160 I2C_SDA7
D11
SPI2_CK/GPIO108 L/D_CLK_SOC
E12
VSYNC_LIKE/GPIO105 L/D_VSYNC_SOC C101 0.1uF R185 47
D14 AM7 TU_SIF
DIM0/GPIO110 SC_DET NC_1 C102 0.1uF R186 47
E14 AL7 R188
DIM1/GPIO111 AV1_CVBS_DET NC_2 C105 300
AM8 1000pF
NC_3 ANALOG SIF OPT OPT
AK7
NC_4 Close to MSTAR
20150123 version AL5
NC_5
+3.3V_NORMAL
BIT(0/1) DVB ATSC JP AM5
GPIO34/GPIO89 CORE_VID1
M7 L100
00 TW/COL US NC_6 PZ1608U121-2R0TF
Low High
01 CN/HK KR JP
10 EU BR T-con I2C R182 C106
BIT8 16Kbit 32Kbit 0.1uF
BIT(2/3) EU/CIS AJJA TW/COL CN/HK KR North.AM BR JP Protocol 10K
11 AJJA CI BIT(6/7) B/E(FRC)
R187
00 T2/C/S2 PIP T2/C PIP T2/C PIP Default ATSC NIM+T2 Default ISDB PIP Default 0
00 LM14A only BIT9 Division NON_Division 4_Division IF_AGC
Low High
01 T2/C/S2 T2/C/S2 T2/C ATSC+T2 ISDB EXT
01 N/A C108
BIT4 Display LCD OLED 0.047uF
BIT10 Interface EPI Vx1
10 LM14A+URSA11 10 T/C T T/C ATSC 25V
ISDB INT
4K@60Hz
BIT5 Resolution FHD UHD 11 LM14A+URSA11 11 T2 BIT11 OS(DDR) WebOS Lite WebOS
ATSC PIP
4K@120Hz
+3.3V_TU
+3.3V_LNA_TU
+3.3V_NORMAL I2C PULL UP
GPIO PULL UP
Mstar Debug RS232C_Debug DDTS_Debug
+3.3V_NORMAL MSTAR_DEBUG_OLD
P101 +3.3V_NORMAL +3.3V_NORMAL
UART_4PIN_WAFER DDTS_Debug
R100
1.8K
R101
1.8K
R102
1.8K
R103
1.8K
R104
1.8K
R107
1.8K
R114
1.8K
R121
1.8K
R124
1.8K
R127
1.8K
R130
1.8K
R131
1.8K
R134
1.8K
R137
1.8K
MSTAR_DEBUG_NEW
12505WS-04A00
P100 P102 P103
12507WS-04L 12507WS-04L 12507WS-04L
10K
10K
10K
10K
10K
10K
10K
10K
10K
10K
I2C_SDA7
10K
10K
1
OPT
I2C for URSA9 (URSA9 Only)

OPT
I2C_SCL7
OPT
OPT
1 1
R152
1
R154
R164
I2C_SDA6
R156
R157
R161
R165
R170
R166
R168
I2C for LCD Module 2

R178
R180
I2C_SCL6
I2C_SDA1 2 SOC_RX 2
I2C for NAVRAM 2 DDTS_RX
I2C_SCL1
10K
10K
/TU_RESET1 DDCA_CK 3
I2C_SDA3
OPT
OPT
I2C for Micom RF_SWITCH_CTL 3 3
I2C_SCL3 3
AMP_RESET_N 4
R179
R181
I2C_SDA4 DDCA_DA
I2C for Main Amp / Woofer AMP TCON_I2C_EN
I2C_SCL4 4 4 SOC_TX 4
/USB_OCD3 5 DDTS_TX
I2C_SDA5
I2C for tuner USB_CTL3
I2C_SCL5 5 5 5
/USB_OCD2
I2C_SDA2 USB_CTL2
I2C for tuner&LNB M_RFModule_RESET
AR100 I2C_SCL2
33 PCM_5V_CTL
I2C_SDA_MICOM I2C_SDA3
I2C_SCL_MICOM I2C_SCL3
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES BSD-15Y-LM14A-001_00-HD

SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS LM14A 2015-01-23
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. MAIN1_SYSTEM 01
+1.1V_VDDC_CPU
+1.1V_Bypass Cap(CLOSE TO CHIP SIDE)
IC100
LGE5332(LM14A) 1st layer 4th layer
+1.1V_VDDC +1.1V_VDDC +1.1V_VDDC DVDD_DDR11

4th layer
0.1uF
0.1uF
0.1uF
J9 AC17 L226
10uF
VDDC_1 VDDC_24 PZ1608U121-2R0TF
J10 AC18 C263 C323
VDDC_2 VDDC_25
J11 AC19 10uF C208 0.1uF
VDDC_3 VDDC_26 10V 10uF 16V
C322
C276
C278
C299
J12 AC20
J13
VDDC_4 VDDC_27
AC21
10V 2A C257
VDDC_5 VDDC_28 C324
K9 AC22 0.47uF 0.47uF
VDDC_6 VDDC_29 6.3V 6.3V
K10 AD17
VDDC_7 VDDC_30
K11 AD18
VDDC_8 VDDC_31
K12 AD19 Close to chip side
VDDC_9 VDDC_32
K13 AD20
VDDC_10 VDDC_33
L9 AD21 Close to chip side
VDDC_11 VDDC_34
L10 AD22
VDDC_12 VDDC_35
L11 AE19
VDDC_13 VDDC_36 Close to chip side
L12 AE20
VDDC_14 VDDC_37
R11 AE21
VDDC_15 VDDC_38 +1.1V_VDDC
R12 AE22
VDDC_16 VDDC_39 AVDDL_MOD11
R13 1st layer 4th layer
VDDC_17 4th layer
T11 AE31
VDDC_18 VDD_SRAM_1 L202
T12 AC24 PZ1608U121-2R0TF
VDDC_19 VDD_SRAM_2
T13 AD23
0.1uF
0.1uF
0.1uF
VDDC_20 VDD_SRAM_3
10uF
U11
VDDC_21
U12
VDDC_22 CTRL_SRAMLDO
AE30
C205
10uF
C261
0.1uF 2A C320
U13 10V 16V C238
C250
C230
C234
C235
VDDC_23 0.47uF 0.47uF
6.3V 6.3V
AVDDL_MOD11 A6 AVDD_DMPLL
EMMC_CTRL
W21
AVDDL_PREDRV_1
Y21
AVDDL_PREDRV_2
AD29 V7
AVDDL_PREDRV_3 AVDD_NODIE Close to chip side
0.1uF
AD30
AVDDL_MOD_1 DVDD_DDR11
W20
AVDD15_MOD AVDDL_MOD_2 Close to chip side
Y20 L7
AVDDL_MOD_3 AVDDL_MHL3_1 AVDDP3P3_MHL Close to chip side
U19 N12
C227
AVDD15_MOD_1 AVDDL_MHL3_2
V19 R7
AVDD15_MOD_2 AVDD3P3_MHL3_1
DVDD_DDR11 AA13 T7
AVDDL_USB3_1 AVDD3P3_MHL3_2
AF11 AVDD33_ADC
AVDDL_USB3_2 AVDD_DMPLL
U21 Y7
VDDC_CPU_1 AVDD3P3_ETH
U22 AB7
+1.1V_VDDC_CPU VDDC_CPU_2 AVDD3P3_DADC_1
U23
U24
VDDC_CPU_3 AVDD3P3_DADC_2
AB8
AA7
+1.5V_Bypass Cap
VDDC_CPU_4 AVDD3P3_ADC_1 AVDD_DMPLL +1.5V_DDR AVDD_DDR
U25 AA8
VDDC_CPU_5 AVDD3P3_ADC_2
V23 G9
VDDC_CPU_6 AVDD3P3_USB_1
V24 G10 L227
VDDC_CPU_7 AVDD3P3_USB_2 PZ1608U121-2R0TF
V25 AB15
VDDC_CPU_8 AVDD3P3_USB3_1 1st layer 4th layer
W23 AF13 AVDD_AU33
VDDC_CPU_9 AVDD3P3_USB3_2 AVDDP3P3 L200 AVDD_DDR AVDD15_MOD
W24 AD7
VDDC_CPU_10 AVDD_AU33
W25 AE7
2A
0.47uF
VDDC_CPU_11 AVDD_EAR33 PZ1608U121-2R0TF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
Y23 AF8
VDDC_CPU_12 AVDD3P3_DMPLL OPT
L224
Y24
Y25
VDDC_CPU_13 VDDP_1
AE15
AF15
4A C207
10uF
C201
10uF
C247
C316
10uF
C223
10uF
C248
0.47uF
C249
0.47uF
0.47uF PZ1608U121-2R0TF
VDDC_CPU_14 VDDP_2 10V 10V 6.3V
C314
10V 10V 6.3V
0.1uF
C209
C224
C225
C226
0.1uF
AA22 6.3V
C203
C204
C287
VDDC_CPU_15
AA23
VDDC_CPU_16
AA24 V17
VDDC_CPU_17 AVDD_MOD_1
C307
AA25 V18
C308
AB24 W19
VDDC_CPU_19 AVDD_LPLL_1
AB25 Y19
Close to chip side Close to chip side
AE16
MCP_VDDC_1
AF16 N15
MCP_VDDC_2 AVDD_PLL_A
N16
AVDD_PLL_B
DVDD_NODIE VDDP_NAND_A VDDP_NAND_C
L13
DVDD_NODIE
DVDD_DDR11 H16
VDDP_3318_A/[3.3V/1.8V]
K21 K16
C200 DVDD_DDR_1 VDDP_3318_C/[3.3V/1.8V]
N21 AVDD_DDR
1uF DVDD_DDR_2
25V
M21 J21
DVDD_DDR_3 AVDD_DDR_A_1
L21 K17
K18
AVDD_DDR_A_3
K19
AVDD_DDR_A_4
AVDD_DDR_A_5
L17
GND JIG POINT +3.3V_Bypass Cap
L19
AVDD_DDR_A_6
L20
AVDD_DDR_A_7
J23
AVDD_DDR_B_1
K22
AVDD_DDR_B_2 4th layer
JP202
JP204
JP205
JP203
K23
AVDD_DDR_B_3 +3.3V_NORMAL AVDDP3P3
M22 +3.3V_NORMAL
AVDD_DDR_B_4
N22 AVDD_DMPLL
AVDD_DDR_B_5 1st layer 4th layer
N23
AVDD_DDR_B_6 L215
P23 L213 PZ1608U121-2R0TF
0.1uF
AVDD_DDR_B_7 PZ1608U121-2R0TF
0.1uF
0.47uF
0.1uF
C293
2A 0.47uF 2A C256 C217
C269
L18 6.3V C222 10uF
C268 10uF
AVDD_DDR_LDO_A 10uF
C274
10V 10V
C311
C253
L22 10uF 10V
AVDD_DDR_LDO_B 10V
AVDD5V_MHL
H7
AVDD_HDMI_5V_PA
R201 Close to chip side
0 AVDD_DDR
G8
GND_EFUSE
+3.3V_NORMAL VDDP_NAND_C 0
R207 Close to chip side Close to chip side
0.1uF
4th layer
C14 OPT
C229
AVDD_DDR_VBP_A_1 0.47uF C210

B14 L208
5V_HDMI_1 AVDD5V_MHL AVDD_DDR_VBP_A_2 AVDD33_ADC
J17 PZ1608U121-2R0TF
AVDD_DDR_VBP_A_3
J18 0.47uF C211
AVDD_DDR_VBP_A_4 L221
0.1uF
+5V_NORMAL 4th layer

R200
10 B15
2A C260
C266
0.1uF
PZ1608U121-2R0TF
AVDD_DDR_VBN_A_1 10uF R206

C15 0.47uF C212 C294 C295 C251 C252 AVDDP3P3_MHL
10V 10K
AVDD_DDR_VBN_A_2
2A
C219
J19 1uF 1uF 0.47uF 0.47uF
G
AVDD_DDR_VBN_A_3 10V 10V 6.3V 6.3V
J20 0.47uF C213 L201
AVDD_DDR_VBN_A_4 PZ1608U121-2R0TF
D
AC30
AVDD_DDR_VBP_B_1 0.47uF C214 RUE003N02 C240 C241
AC31
AVDD_DDR_VBP_B_2 0.1uF 0.47uF
K24 Q200
6.3V
AVDD_DDR_VBP_B_3 0.47uF C215
L24 Close to chip side
AVDD_DDR_VBP_B_4 VDDP_NAND_A
0.1uF
AD31 +1.8V
AVDD_DDR_VBN_B_1
AD32 C216
AVDD_DDR_VBN_B_2 0.47uF L209
C221
L23 PZ1608U121-2R0TF
AVDD_DDR_VBN_B_3 Close to chip side
M24
AVDD_DDR_VBN_B_4 0.47uF C220
4th layer
2A C236
C239
0.1uF
10uF AVDD_AU33
10V
L219
PZ1608U121-2R0TF
C292
2A 0.47uF
6.3V
Close to chip side
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES

THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. MAIN2_POWER 2
DDR_VTT DDR_VTT
AR400 AR407
M0_DDR_VREFDQ 56 56
Hynix_DDR3_4Gb_29n Hynix_DDR3_4Gb_29n M0_1_DDR_VREFDQ 1/16W 1/16W
IC400 IC401 C424 0.1uF C453 0.1uF
M0_DDR_A14 M1_DDR_A14
H5TQ4G63AFR-RDC H5TQ4G63AFR-RDC M0_DDR_A8 M1_DDR_A8
EAN63053201 EAN63053201 C425 0.1uF C454 0.1uF
M0_DDR_A6 M1_DDR_A6
M0_DDR_A0
N3
A0 DDR3 VREFCA
M8
M0_DDR_A0
N3
A0
DDR3 VREFCA
M8
AR401 AR408
P7 P7 4Gbit 56 56
M0_DDR_A1 A1 4Gbit M0_DDR_A1 A1 1/16W 1/16W
P3 P3
M0_DDR_A2 A2 (x16) M0_DDR_A2 A2 (x16) C426 0.1uF C455 0.1uF
N2 H1 N2 H1 M0_DDR_A1 M1_DDR_A1
M0_DDR_A3 A3 VREFDQ M0_DDR_A3 A3 VREFDQ
P8 P8 M0_DDR_A4 M1_DDR_A4
M0_DDR_A4 A4 M0_DDR_A4 A4
M0_DDR_A5 A5 M0_DDR_A5 A5 C427 0.1uF C456 0.1uF
R8 L8 R400 240 R8 L8 R403 240 M0_DDR_BA1 M1_DDR_BA1
M0_DDR_A6 A6 ZQ M0_DDR_A6 A6 ZQ
R2 AVDD_DDR R2 AR402 AR409
M0_DDR_A7 A7 M0_DDR_A7 A7 AVDD_DDR
T8 T8 56 56
M0_DDR_A8 A8 M0_DDR_A8 A8 1/16W 1/16W
R3 B2 R3 B2 C428 0.1uF C457 0.1uF
M0_DDR_A9 A9 VDD_1 M0_DDR_A9 A9 VDD_1
L7 D9 L7 D9
M0_DDR_A10 A10/AP VDD_2 M0_DDR_A10 A10/AP VDD_2 M0_DDR_A13 M1_DDR_A13
R7 G7 R7 G7
DDR3 1.5V bypass Cap - Place these caps near Memory

N7 K2 N7 K2 M0_DDR_A9 M1_DDR_A9
M0_DDR_A12 A12/BC VDD_4 M0_DDR_A12 C429 0.1uF C458 0.1uF
A12/BC VDD_4 M0_DDR_A7 M1_DDR_A7
T3 K8 T3 K8
T7 N1 T7 N1 AR403 AR410
M0_DDR_A14 A14 VDD_6 M0_DDR_A14 A14 VDD_6 56 56
M7 N9 M7 N9 1/16W 1/16W
M0_DDR_A15 NC_5 VDD_7 M0_DDR_A15 NC_5 VDD_7
R1 R1 C430 0.1uF C459 0.1uF
VDD_8 VDD_8 M0_DDR_A2 M1_DDR_A2
M2 R9 M2 R9
M0_DDR_BA0 BA0 VDD_9 M0_DDR_BA0 BA0 VDD_9 M0_DDR_A5 M1_DDR_A5
N8 N8
M0_DDR_BA1 BA1 M0_DDR_BA1 BA1 M0_DDR_A3 M1_DDR_A3
M3 M3 C431 0.1uF C460 0.1uF
A1 A1
VDDQ_1 VDDQ_1 AR404 AR411
J7 A8 J7 A8
M0_D_CLK CK VDDQ_2 M0_D_CLK CK VDDQ_2 56 56
K7 C1 K7 C1 1/16W 1/16W
M0_D_CLKN CK VDDQ_3 M0_D_CLKN CK VDDQ_3 C432 0.1uF C461 0.1uF
K9 C9 K9 C9 M0_DDR_BA0 M1_DDR_BA0
M0_DDR_CKE CKE VDDQ_4 M0_DDR_CKE CKE VDDQ_4
D2 D2 M0_DDR_BA2 M1_DDR_BA2
VDDQ_5 VDDQ_5
L2 E9 L2 E9 M0_DDR_A15 M1_DDR_A15
M0_DDR_CS1 CS VDDQ_6 M0_DDR_CS2 CS VDDQ_6 C433 0.1uF C462 0.1uF
K1 F1 K1 F1 M0_DDR_A10 M1_DDR_A10
M0_DDR_ODT ODT VDDQ_7 M0_DDR_ODT ODT VDDQ_7
J3 H2 C410 0.1uF J3 H2 C440 0.1uF
M0_DDR_RASN RAS VDDQ_8 M0_DDR_RASN RAS VDDQ_8 AR405 AR412
K3 H9 C411 0.1uF K3 H9 C441 0.1uF 56 56
M0_DDR_CASN CAS VDDQ_9 M0_DDR_CASN CAS VDDQ_9 1/16W 1/16W
L3 L3
M0_DDR_WEN WE M0_DDR_WEN WE C434 0.1uF C463 0.1uF
J1 J1 M0_DDR_WEN M1_DDR_WEN
NC_1 NC_1
T2 J9 T2 J9 M0_DDR_CASN M1_DDR_CASN
M0_DDR_RESET_N RESET NC_2 M0_DDR_RESET_N RESET NC_2
IC100 L1 L1 M0_DDR_ODT M1_DDR_ODT
NC_3 NC_3 C435 0.1uF C464 0.1uF
LGE5332(LM14A) L9 L9 M0_DDR_RASN M1_DDR_RASN
NC_4 NC_4
F3 F3 AR406 AR413
M0_DDR_DQS0 DQSL SS_DDR3_4Gb_25n Hynix_DDR3_4Gb_25n M0_DDR_DQS2 DQSL SS_DDR3_4Gb_25n
Hynix_DDR3_4Gb_25n
G3 IC400-*1 IC400-*2 G3
IC401-*1
K4B4G1646D-BCMA IC401-*2 SS_DDR3_2Gb
IC401-*3
Hynix_DDR3_2Gb
IC401-*4
56 56
K4B4G1646D-BCMA H5TQ4G63CFR_RDC H5TQ4G63CFR_RDC
M0_DDR_DQS_N0 DQSL M0_DDR_DQS_N2 DQSL EAN63391401 K4B2G1646Q-BCMA H5TQ2G63FFR-RDC 1/16W 1/16W
EAN63391401 EAN63053202 N3 M8 EAN63053202
F17 H28 N3
P7
A0 VREFCA
M8 N3
P7
A0 VREFCA
M8 P7
A0
A1
VREFCA N3
P7
A0 VREFCA
M8
N3
EAN63667401
M8 N3
EAN63648701
M8
C436 0.1uF C465 0.1uF
M0_DDR_A0 IO[3]/A-A0[AB-A0]/A-A6 IO[75]/B-A0[CD-A0]/B-A6 M1_DDR_A0 C7 A9 P3
A1
A2
P3
A1
A2
C7 A9
P3
N2
A2
H1 P3
A1
A2
P7
A0
A1
VREFCA
P7
A0
A1
VREFCA
M0_DDR_CKE M1_DDR_CKE
C17 K31 M0_DDR_DQS1 DQSU
N2
A3 VREFDQ
H1 N2
A3 VREFDQ
H1
M0_DDR_DQS3
P8
A3
A4
VREFDQ N2
A3 VREFDQ
H1 P3
A2
P3
A2
M0_DDR_A1 IO[2]/A-A1[AB-A1]/A-A5 IO[80]/B-A1[CD-A1]/B-A5 M1_DDR_A1 VSS_1 P8

P2
A4
P8
P2
A4 DQSU VSS_1 P2
R8
A5
L8
P8
P2
A4
N2
P8
A3 VREFDQ
H1 N2
P8
A3 VREFDQ
H1
E17 J29 B7 B3 R8
A5
A6 ZQ
L8 R8
A5
A6 ZQ
L8 B7 B3 R2
A6
A7
ZQ R8
A5
A6 ZQ
L8 P2
A4
A5
P2
A4
A5
M0_DDR_A2 IO[8]/A-A2[AB-A2]/A-A8 M1_DDR_A2 M0_DDR_DQS_N1 DQSU VSS_2

R2
A7
R2
A7
M0_DDR_DQS_N3 DQSU VSS_2 T8
A8
R2
A7
R8
R2
A6 ZQ
L8 R8
R2
A6 ZQ
L8
M0_D_CLKN M1_D_CLKN
IO[83]/B-A2[CD-A2]/B-A8 E1
T8
R3
A8
B2
T8
R3
A8
B2
E1
R3
L7
A9 VDD_1
B2
D9
T8
R3
A8
B2 T8
A7
T8
A7
F18 K27 L7
A9 VDD_1
D9 L7
A9 VDD_1
D9 R7
A10/AP VDD_2
G7 L7
A9 VDD_1
D9 R3
A8
B2 R3
A8
B2
C437 0.1uF C466 0.1uF
M0_DDR_A3 IO[12]/A-A3[AB-A3]/A-A4 IO[79]/B-A3[CD-A3]/B-A4 M1_DDR_A3 VSS_3 R7
A10/AP
A11
VDD_2
VDD_3
G7 R7
A10/AP
A11
VDD_2
VDD_3
G7
VSS_3 N7
A11
A12/BC
VDD_3
VDD_4
K2 R7
A10/AP
A11
VDD_2
VDD_3
G7 L7
A9
A10/AP
VDD_1
VDD_2
D9 L7
A9
A10/AP
VDD_1
VDD_2
D9
M0_D_CLK M1_D_CLK
B18 K30 E7 G8 N7
T3
A12/BC VDD_4
K2
K8
N7
T3
A12/BC VDD_4
K2
K8 E7 G8 T3
A13 VDD_5
K8
N1
N7
T3
A12/BC VDD_4
K2
K8
R7
N7
A11
A12/BC
VDD_3
VDD_4
G7
K2
R7
N7
A11
A12/BC
VDD_3
VDD_4
G7
K2
M0_DDR_A4 M1_DDR_A4 M0_DDR_DM0 DML VSS_4

A13 VDD_5
VDD_6
N1 T7
A13
A14
VDD_5
VDD_6
N1
M0_DDR_DM2 DML VSS_4 M7
VDD_6
N9 T7
A13
A14
VDD_5
VDD_6
N1 T3
A13 VDD_5
K8 T3
A13 VDD_5
K8
IO[11]/A-A4[AB-A4]/A-BA1 IO[87]/B-A4[CD-A4]/B-BA1 D3 J2
M7
NC_5 VDD_7
N9
R1
M7
NC_5 VDD_7
N9
R1 D3 J2
NC_5 VDD_7
VDD_8
R1 M7
NC_5 VDD_7
N9
R1 M7
VDD_6
N1
N9
T7
M7
A14 VDD_6
N1
N9
E18 J28 M0_DDR_DM1 DMU
M2
VDD_8
R9 M2
VDD_8
R9
M0_DDR_DM3
M2
BA0 VDD_9
R9
M2
VDD_8
R9
NC_5 VDD_7
R1
NC_5 VDD_7
R1
M0_DDR_A5 IO[14]/A-A5[AB-A5]/A-A0 IO[86]/B-A5[CD-A5]/B-A0 M1_DDR_A5 VSS_5 N8

BA0 VDD_9
N8
BA0 VDD_9
DMU VSS_5 N8
M3
BA1 N8
BA0 VDD_9
M2
BA0
VDD_8
VDD_9
R9 M2
BA0
VDD_8
VDD_9
R9
A17 K32 J8 M3
BA1
BA2
A1
M3
BA1
BA2
A1
J8 J7
BA2
VDDQ_1
A1
A8
M3
BA1
BA2
A1
N8
M3
BA1
N8
M3
BA1
M0_DDR_A6 IO[10]/A-A6[AB-A6]/A-A1 IO[90]/B-A6[CD-A6]/B-A1 M1_DDR_A6 VSS_6 J7

CK
VDDQ_1
VDDQ_2
A8 J7
CK
VDDQ_1
VDDQ_2
A8
VSS_6 K7
CK
CK
VDDQ_2
VDDQ_3
C1 J7
CK
VDDQ_1
VDDQ_2
A8
BA2
VDDQ_1
A1
BA2
VDDQ_1
A1
D17 H31 E3 M1 K7
K9
CK VDDQ_3
C1
C9
K7
K9
CK VDDQ_3
C1
C9 E3 M1 K9
CKE VDDQ_4
C9
D2
K7
K9
CK VDDQ_3
C1
C9
J7
K7
CK
CK
VDDQ_2
VDDQ_3
A8
C1
J7
K7
CK
CK
VDDQ_2
VDDQ_3
A8
C1
M0_DDR_A7 M1_DDR_A7 M0_DDR_DQ0 DQL0 VSS_7

CKE VDDQ_4
VDDQ_5
D2
CKE VDDQ_4
VDDQ_5
D2
M0_DDR_DQ16 DQL0 VSS_7 L2
VDDQ_5
E9
CKE VDDQ_4
VDDQ_5
D2 K9
CKE VDDQ_4
C9 K9
CKE VDDQ_4
C9
IO[13]/A-A7[AB-A7]/A-A2 IO[78]/B-A7[CD-A7]/B-A2 F7 M9
L2
K1
CS VDDQ_6
E9
F1
L2
K1
CS VDDQ_6
E9
F1 F7 M9
K1
CS
ODT
VDDQ_6
VDDQ_7
F1 L2
K1
CS VDDQ_6
E9
F1 L2
VDDQ_5
D2
E9 L2
VDDQ_5
D2
E9
C16 J32 M0_DDR_DQ1 DQL1
J3
ODT VDDQ_7
H2 J3
ODT VDDQ_7
H2
M0_DDR_DQ17
J3
RAS VDDQ_8
H2
J3
ODT VDDQ_7
H2 K1
CS VDDQ_6
F1 K1
CS VDDQ_6
F1
M0_DDR_A8 IO[0]/A-A8[AB-A8]/A-A9 IO[77]/B-A8[CD-A8]/B-A9 M1_DDR_A8 VSS_8 K3

RAS VDDQ_8
H9 K3
RAS VDDQ_8
H9 DQL1 VSS_8 K3
L3
CAS VDDQ_9
H9
K3
RAS VDDQ_8
H9 J3
ODT VDDQ_7
H2 J3
ODT VDDQ_7
H2
AVDD_DDR
E16 G30 F2 P1 L3
CAS
WE
VDDQ_9
J1
L3
CAS
WE
VDDQ_9
J1
F2 P1 T2
WE
NC_1
J1
J9
L3
CAS
WE
VDDQ_9
J1
K3
L3
RAS
CAS
VDDQ_8
VDDQ_9
H9 K3
L3
RAS
CAS
VDDQ_8
VDDQ_9
H9
M0_DDR_CKE
M0_DDR_A9 M1_DDR_A9 M0_DDR_DQ2 DQL2 VSS_9 T2
NC_1
J9 T2
NC_1
J9 M0_DDR_DQ18 DQL2 VSS_9 RESET NC_2
L1 T2
NC_1
J9
WE
J1
WE
J1
IO[5]/A-A9[AB-A9]/A-A11 IO[73]/B-A9[CD-A9]/B-A11 F8 P9
RESET NC_2
NC_3
L1
RESET NC_2
NC_3
L1
F8 P9
NC_3
L9
RESET NC_2
NC_3
L1 T2
RESET
NC_1
NC_2
J9 T2
RESET
NC_1
NC_2
J9
B19 L30 M0_DDR_DQ3 DQL3

NC_4
L9
NC_4
L9
M0_DDR_DQ19
F3
DQSL
NC_4
NC_6
T7
NC_4
L9
NC_3
L1
NC_3
L1
M0_DDR_A10 IO[9]/A-A10[AB-A10]/A-RASZ IO[93]/B-A10[CD-A10]/B-RASZ M1_DDR_A10 VSS_10 F3

G3
DQSL NC_6
T7 F3
G3
DQSL DQL3 VSS_10 G3
DQSL
F3
G3
DQSL
F3
NC_4
L9
T7 F3
NC_4
L9
H3 T1
1K
R418
B17 J30
DQSL DQSL
H3 T1 C7
DQSU VSS_1
A9
DQSL
G3
DQSL
DQSL
NC_6
G3
DQSL
DQSL
M0_DDR_DQ4 AVDD_DDR
OPT
C7 A9 C7 A9
M0_DDR_DQ20 C7 A9
1K
R405
M0_DDR_A11 IO[6]/A-A11[AB-A11]/A-A7 IO[84]/B-A11[CD-A11]/B-A7 M1_DDR_A11 DQL4 VSS_11 B7
DQSU VSS_1
B3 B7
DQSU VSS_1
B3 DQL4 VSS_11 B7
DQSU VSS_2
B3
E1 B7
DQSU VSS_1
B3 C7
DQSU VSS_1
A9 C7
DQSU VSS_1
A9
AVDD_DDR
D20 L29 H8 T9 E7
DQSU VSS_2
VSS_3
E1
G8 E7
DQSU VSS_2
VSS_3
E1
G8
H8 T9 E7
D3
DML
VSS_3
VSS_4
G8
J2 E7
DQSU VSS_2
VSS_3
E1
G8
B7
DQSU VSS_2
B3
E1
B7
DQSU VSS_2
B3
E1
M0_DDR_A12 IO[26]/A-A12[AB-A12]/A-BG0 M1_DDR_A12 M0_DDR_DQ5 DQL5 VSS_12 D3

DML VSS_4
J2 D3
DML VSS_4
J2 M0_DDR_DQ21 DQL5 VSS_12 DMU VSS_5
J8 D3
DML VSS_4
J2 E7
VSS_3
G8 E7
VSS_3
G8
IO[85]/B-A12[CD-A12]/B-BG0 G2
DMU VSS_5
VSS_6
J8
DMU VSS_5
VSS_6
J8
G2 E3
VSS_6
M1
DMU VSS_5
VSS_6
J8 D3
DML
DMU
VSS_4
VSS_5
J2 D3
DML
DMU
VSS_4
VSS_5
J2
F16 G31 M0_DDR_DQ6 DQL6

E3
DQL0 VSS_7
M1 E3
DQL0 VSS_7
M1
M0_DDR_DQ22
F7
DQL0
DQL1
VSS_7
VSS_8
M9 E3
DQL0 VSS_7
M1
VSS_6
J8
VSS_6
J8
M0_1_DDR_VREFDQ
M0_DDR_A13 IO[4]/A-A13[AB-A13]/A-PARITY IO[74]/B-A13[CD-A13]/B-PARITY M1_DDR_A13
F7
F2
DQL1 VSS_8
M9
P1
F7
F2
DQL1 VSS_8
M9
P1 DQL6 F2
F8
DQL2 VSS_9
P1
P9
F7
F2
DQL1 VSS_8
M9
P1
E3
F7
DQL0 VSS_7
M1
M9
E3
F7
DQL0 VSS_7
M1
M9
B16 J31 H7 F8
DQL2
DQL3
VSS_9
VSS_10
P9 F8
DQL2
DQL3
VSS_9
VSS_10
P9 H7 H3
DQL3
DQL4
VSS_10
VSS_11
T1 F8
DQL2
DQL3
VSS_9
VSS_10
P9 F2
DQL1
DQL2
VSS_8
VSS_9
P1 F2
DQL1
DQL2
VSS_8
VSS_9
P1
M0_DDR_VREFDQ M0_DDR_RESET_N
M0_DDR_A14 IO[7]/A-A14[AB-A14]/A-A13 M1_DDR_A14 M0_DDR_DQ7 DQL7
H3
DQL4 VSS_11
T1 H3
DQL4 VSS_11
T1
M0_DDR_DQ23 DQL7 H8
DQL5 VSS_12
T9 H3
DQL4 VSS_11
T1 F8
H3
DQL3 VSS_10
P9
T1
F8
H3
DQL3 VSS_10
P9
T1
IO[81]/B-A14[CD-A14]/B-A13 B1
H8
G2
DQL5 VSS_12
T9 H8
G2
DQL5 VSS_12
T9
B1
G2
H7
DQL6
H8
G2
DQL5 VSS_12
T9
H8
DQL4 VSS_11
T9 H8
DQL4 VSS_11
T9
E20 M28 DQL5 VSS_12 DQL5 VSS_12
R416
DQL6 DQL6 DQL6
1K 1%
H7 H7 DQL7 H7 G2 G2
B1
M0_DDR_A15 VSSQ_1 DQL7 DQL7

VSSQ_1 VSSQ_1 DQL7 DQL6 DQL6
R410
1K 1%
B1 B1 B1 H7 H7
IO[19]/A-A15[AB-A15]/A-A3 IO[96]/B-A15[CD-A15]/B-A3 M1_DDR_A15 D7 B9 D7

DQU0
VSSQ_1
VSSQ_2
B9 D7
DQU0
VSSQ_1
VSSQ_2
B9
D7 B9
D7
C3
DQU0 VSSQ_2
B9
D1 D7
DQU0
VSSQ_1
VSSQ_2
B9
DQL7
VSSQ_1
B1
DQL7
VSSQ_1
B1 1%
E19 L28 M0_DDR_DQ8 DQU0
C3
DQU1 VSSQ_3
D1 C3
DQU1 VSSQ_3
D1
M0_DDR_DQ24
C8
DQU1
DQU2
VSSQ_3
VSSQ_4
D8 C3
DQU1 VSSQ_3
D1 D7
DQU0 VSSQ_2
B9 D7
DQU0 VSSQ_2
B9
10K
M0_DDR_BA0 IO[24]/A-BA0[AB-BA0]/A-A10 IO[88]/B-BA0[CD-BA0]/B-A10 M1_DDR_BA0 VSSQ_2 C8
C2
DQU2 VSSQ_4
D8
E2
C8
C2
DQU2 VSSQ_4
D8
E2 DQU0 VSSQ_2 C2
A7
DQU3 VSSQ_5
E2
E8
C8
C2
DQU2 VSSQ_4
D8
E2
C3
C8
DQU1 VSSQ_3
D1
D8
C3
C8
DQU1 VSSQ_3
D1
D8
C18 L31 C3 D1 A7
DQU3
DQU4
VSSQ_5
VSSQ_6
E8 A7
DQU3
DQU4
VSSQ_5
VSSQ_6
E8 C3 D1 A2
DQU4
DQU5
VSSQ_6
VSSQ_7
F9 A7
DQU3
DQU4
VSSQ_5
VSSQ_6
E8 C2
DQU2
DQU3
VSSQ_4
VSSQ_5
E2 C2
DQU2
DQU3
VSSQ_4
VSSQ_5
E2
R445
M0_DDR_BA1 M1_DDR_BA1 M0_DDR_DQ9 DQU1 VSSQ_3
A2
DQU5 VSSQ_7
F9 A2
DQU5 VSSQ_7
F9
M0_DDR_DQ25 DQU1 VSSQ_3 B8
DQU6 VSSQ_8
G1 A2
DQU5 VSSQ_7
F9 A7
A2
DQU4 VSSQ_6
E8
F9
A7
A2
DQU4 VSSQ_6
E8
F9
IO[20]/A-BA1[AB-BA1]/A-CASZ IO[92]/B-BA1[CD-BA1]/B-CASZ C8 D8
B8
A3
DQU6 VSSQ_8
G1
G9
B8
A3
DQU6 VSSQ_8
G1
G9
C8 D8
A3
DQU7 VSSQ_9
G9 B8
A3
DQU6 VSSQ_8
G1
G9 B8
DQU5 VSSQ_7
G1 B8
DQU5 VSSQ_7
G1
F19 K28 M0_DDR_DQ10 DQU2

DQU7 VSSQ_9 DQU7 VSSQ_9
M0_DDR_DQ26
DQU7 VSSQ_9
A3
DQU6 VSSQ_8
G9 A3
DQU6 VSSQ_8
G9
M0_DDR_BA2 IO[21]/A-BA2[AB-BA2]/A-BA0 IO[82]/B-BA2[CD-BA2]/B-BA0 M1_DDR_BA2 VSSQ_4 DQU2 VSSQ_4 DQU7 VSSQ_9 DQU7 VSSQ_9
C479
G22 N28 C2 E2 C2 E2 C472 M0_D_CLK
1%
M0_DDR_RASN M1_DDR_RASN M0_DDR_DQ11 DQU3 VSSQ_5 M0_DDR_DQ27 DQU3 VSSQ_5 0.1uF
1%
IO[15]/A-RASZ[AB-RASZ]/A-ODT IO[97]/B-RASZ[CD-RASZ]/B-ODT A7 E8 A7 E8 0.1uF C483 R412
F21 N27
R417
M0_DDR_DQ12 DQU4 VSSQ_6 M0_DDR_DQ28 DQU4 VSSQ_6 C474 56 C477
R411
M0_DDR_CASN IO[17]/A-CASZ[AB-CASZ]/A-WEZ IO[94]/B-CASZ[CD-CASZ]/B-WEZ M1_DDR_CASN A2 F9 A2 F9 1000pF 0.01uF
E21 L27 M0_DDR_DQ13 DQU5 M0_DDR_DQ29 1000pF 50V 1%
M0_DDR_WEN M1_DDR_WEN VSSQ_7 DQU5 VSSQ_7
1K
IO[16]/A-WEZ[AB-WEZ]/A-A12 IO[89]/B-WEZ[CD-WEZ]/B-A12 B8 G1 B8 G1 50V 50V
1K
F20 M27 M0_DDR_DQ14 DQU6 M0_DDR_DQ30
M0_DDR_ODT IO[25]/A-ODT[AB-ODT]/A-ACTZ IO[95]/B-ODT[CD-ODT]/B-ACTZ M1_DDR_ODT VSSQ_8 DQU6 VSSQ_8
C19 M31 A3 G9 A3 G9 R413
M0_DDR_CKE IO[18]/A-CKE[AB-CKE]/A-CKE M1_DDR_CKE M0_DDR_DQ15 DQU7 VSSQ_9 SS_DDR3_2Gb Hynix_DDR3_2Gb M0_DDR_DQ31 DQU7 VSSQ_9 56
IO[91]/B-CKE[CD-CKE]/B-CKE IC400-*3
K4B2G1646Q-BCMA
IC400-*4
H5TQ2G63FFR-RDC
F15 G32 1%
M0_DDR_RESET_N IO[1]/A-RST[AB-RST]/A-RST IO[76]/B-RST[CD-RST]/B-RST M1_DDR_RESET_N N3
EAN63667401
M8 N3
EAN63648701
M8
A20 N32 P7
A0
A1
VREFCA
P7
A0
A1
VREFCA
M0_D_CLK IO[28]/A-MCLK[AB-MCLK]/A-MCLKZ IO[101]/B-MCLK[CD-MCLK]/B-MCLKZ M1_D_CLK P3

N2
A2
H1
P3
N2
A2
H1
B20 M30 P8
P2
A3
A4
VREFDQ
P8
P2
A3
A4
VREFDQ
M0_D_CLKN
M0_D_CLKN IO[27]/A-MCLKZ[AB-MCLKZ]/A-MCLK IO[100]/B-MCLKZ[CD-MCLKZ]/B-MCLK M1_D_CLKN R8
A5
A6 ZQ
L8 R8
A5
A6 ZQ
L8
E15 G29 R2
T8
A7
R2
T8
A7
M0_DDR_CS1 IO[23]/A-CSB1[AB-CSB1]/A-CSB1 IO[99]/B-CSB1[CD-CSB1]/B-CSB1 M1_DDR_CS1 R3

L7
A8
A9 VDD_1
B2
D9
R3
L7
A8
A9 VDD_1
B2
D9
D15 F32 R7
A10/AP
A11
VDD_2
VDD_3
G7 R7
A10/AP
A11
VDD_2
VDD_3
G7
M0_DDR_CS2 IO[22]/A-CSB2[AB-CSB2]/A-CSB2 IO[98]/B-CSB2[CD-CSB2]/B-CSB2 M1_DDR_CS2 N7

T3
A12/BC VDD_4
K2
K8
N7
T3
A12/BC VDD_4
K2
K8
M7
A13
NC_5
VDD_5
VDD_6
VDD_7
N1
N9
T7
M7
A13
A14
NC_5
VDD_5
VDD_6
VDD_7
N1
N9 AVDD_DDR M1_DDR_CKE
R1 R1
VDD_8 VDD_8
M2 R9 M2 R9
BA0 VDD_9 BA0 VDD_9
N8 N8
BA1 BA1
M3 M3
BA2 BA2
A1 A1
C23 T31 J7
CK
VDDQ_1
VDDQ_2
A8 J7
CK
VDDQ_1
VDDQ_2
A8
M0_DDR_DQ0 M1_DDR_DQ0 K7 C1 K7 C1
AVDD_DDR
1K
R433
IO[47]/A-DQ[0][A-DQL0]/A-DQ[0] IO[120]/B-DQ[0][C-DQL0]/B-DQ[0] K9
CK VDDQ_3
C9 K9
CK VDDQ_3
C9 AVDD_DDR
B22 P30 CKE VDDQ_4
VDDQ_5
D2
CKE VDDQ_4
VDDQ_5
D2
M0_DDR_DQ1 IO[31]/A-DQ[1][A-DQL1]/A-DQ[1] IO[104]/B-DQ[1][C-DQL1]/B-DQ[1] M1_DDR_DQ1 L2 E9 L2 E9
+1.5V_Bypass Cap
CS VDDQ_6 CS VDDQ_6
K1 F1 K1 F1
OPT
1K
R422
+1.5V_Bypass Cap
ODT VDDQ_7 ODT VDDQ_7
B24 T30 J3
K3
RAS VDDQ_8
H2
H9
J3
K3
RAS VDDQ_8
H2
H9
M1_1_DDR_VREFDQ
M0_DDR_DQ2 IO[48]/A-DQ[2][A-DQL2]/A-DQ[2] IO[121]/B-DQ[2][C-DQL2]/B-DQ[2] M1_DDR_DQ2 L3
CAS
WE
VDDQ_9
L3
CAS
WE
VDDQ_9
C21 P31 NC_1

J1
NC_1
J1
M1_DDR_VREFDQ
M0_DDR_DQ3
B25
IO[29]/A-DQ[3][A-DQL3]/A-DQ[3] IO[102]/B-DQ[3][C-DQL3]/B-DQ[3]
U30
M1_DDR_DQ3 Close to DDR Power Pin T2
F3
RESET NC_2
NC_3
NC_4
J9
L1
L9
T7
T2
F3
RESET NC_2
NC_3
NC_4
J9
L1
L9
Close to DDR Power Pin
R414
1K 1%
DQSL NC_6 DQSL
R408
1K 1%
M0_DDR_DQ4 IO[50]/A-DQ[4][A-DQL4]/A-DQ[6] IO[123]/B-DQ[4][C-DQL4]/B-DQ[6] M1_DDR_DQ4 G3
DQSL
G3
DQSL
M1_DDR_RESET_N
C20 N31 C7
B7
DQSU VSS_1
A9
B3
C7
B7
DQSU VSS_1
A9
B3
M0_DDR_DQ5 IO[30]/A-DQ[5][A-DQL5]/A-DQ[7] IO[105]/B-DQ[5][C-DQL5]/B-DQ[7] M1_DDR_DQ5 E7
DQSU VSS_2
VSS_3
E1
G8 E7
DQSU VSS_2
VSS_3
E1
G8
C24 U31
R446
DML VSS_4 DML VSS_4
D3 J2 D3 J2
DMU VSS_5 DMU VSS_5
M0_DDR_DQ6 M1_DDR_DQ6
10K
J8 J8
IO[49]/A-DQ[6][A-DQL6]/A-DQ[4] IO[122]/B-DQ[6][C-DQL6]/B-DQ[4] E3
VSS_6
M1 E3
VSS_6
M1
1%
B21 N30 F7
DQL0
DQL1
VSS_7
VSS_8
M9 F7
DQL0
DQL1
VSS_7
VSS_8
M9
AVDD_DDR
M0_DDR_DQ7 IO[32]/A-DQ[7][A-DQL7]/A-DQ[5] IO[103]/B-DQ[7][C-DQL7]/B-DQ[5] M1_DDR_DQ7 AVDD_DDR
F2
F8
DQL2
DQL3
VSS_9
VSS_10
P1
P9
F2
F8
DQL2
DQL3
VSS_9
VSS_10
P1
P9
C22 R31 H3
H8
DQL4 VSS_11
T1
T9
H3
H8
DQL4 VSS_11
T1
T9 C516 C518
1%
M0_DDR_DM0 M1_DDR_DM0 DQL5 VSS_12 DQL5 VSS_12
1%
IO[33]/A-DQM[0][A-DML]/A-DQM[0] IO[106]/B-DQM[0][C-DML]/B-DQM[0] G2
H7
DQL6
G2
H7
DQL6
0.1uF 0.1uF
A23 T32 DQL7
B1
DQL7
B1 C519 M1_D_CLK
R415
C517
R409
VSSQ_1 VSSQ_1
M0_DDR_DQS0 IO[42]/A-DQS[0][A-DQSL]/A-DQS[0] IO[115]/B-DQS[0][C-DQSL]/B-DQS[0] M1_DDR_DQS0 D7
C3
DQU0 VSSQ_2
B9
D1
D7
C3
DQU0 VSSQ_2
B9
D1
1000pF R427
B23 R30 C8
C2
DQU1
DQU2
VSSQ_3
VSSQ_4
D8
E2
C8
C2
DQU1
DQU2
VSSQ_3
VSSQ_4
D8
E2
1000pF C497
M0_DDR_DQS_N0 IO[41]/A-DQSB[0][A-DQSLB]/A-DQSB[0] IO[114]/B-DQSB[0][C-DQSLB]/B-DQSB[0] M1_DDR_DQS_N0 A7
DQU3 VSSQ_5
E8 A7
DQU3 VSSQ_5
E8
50V 50V 56
1K
0.01uF
1K
A2 F9 A2 F9
B8
A3
DQU6
DQU7
VSSQ_8
VSSQ_9
G1
G9
B8
A3
DQU6
DQU7
VSSQ_8
VSSQ_9
G1
G9 1% 50V
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
D23 P27 R428

M0_DDR_DQ8 IO[35]/A-DQ[8][A-DQU0]/A-DQ[15] IO[109]/B-DQ[8][C-DQU0]/B-DQ[15] M1_DDR_DQ8 56
D26 U29 1%
M0_DDR_DQ9 IO[45]/A-DQ[9][A-DQU1]/A-DQ[10] IO[116]/B-DQ[9][C-DQU1]/B-DQ[10] M1_DDR_DQ9
E22 P28
C403
C404
C405
C400
C401
C402
D27 U27 M1_D_CLKN

M0_DDR_DQ11 IO[46]/A-DQ[11][A-DQU3]/A-DQM[1] IO[119]/B-DQ[11][C-DQU3]/B-DQM[1] M1_DDR_DQ11
F23 R28
E26 V28
D22 P29
E25 U28
E24 T28
M0_DDR_DM1 IO[37]/A-DQM[1][A-DMU]/A-DQ[14] IO[110]/B-DQM[1][C-DMU]/B-DQ[14] M1_DDR_DM1
D24 T27
M0_DDR_DQS1 IO[40]/A-DQS[1][A-DQSU]/A-DQS[1] IO[113]/B-DQS[1][C-DQSU]/B-DQS[1] M1_DDR_DQS1
E23 R27
M0_DDR_DQS_N1 IO[39]/A-DQSB[1][A-DQSUB]/A-DQSB[1] IO[112]/B-DQSB[1][C-DQSUB]/B-DQSB[1] M1_DDR_DQS_N1
M1_DDR_VREFDQ Hynix_DDR3_4Gb_29n
Hynix_DDR3_4Gb_29n M1_1_DDR_VREFDQ
C28 AA31 IC403 IC404
M0_DDR_DQ16 IO[69]/A-DQ[16][B-DQL0]/A-DQ[16] IO[145]/B-DQ[16][D-DQL0]/B-DQ[16] M1_DDR_DQ16 H5TQ4G63AFR-RDC H5TQ4G63AFR-RDC
C26 W31
M0_DDR_DQ17 IO[53]/A-DQ[17][B-DQL1]/A-DQ[17] IO[126]/B-DQ[17][D-DQL1]/B-DQ[17] M1_DDR_DQ17
B29 AA30
M0_DDR_DQ18 IO[70]/A-DQ[18][B-DQL2]/A-DQ[18] IO[143]/B-DQ[18][D-DQL2]/B-DQ[18] M1_DDR_DQ18 EAN63053201 EAN63053201
A26 W32
C29 AB31 M1_DDR_A0
N3
A0 DDR3 VREFCA
M8
M1_DDR_A0
N3
A0
DDR3 VREFCA
M8
M0_DDR_DQ20 IO[72]/A-DQ[20][B-DQL4]/A-DQ[22] IO[142]/B-DQ[20][D-DQL4]/B-DQ[22] M1_DDR_DQ20 P7 P7 4Gbit
M0_DDR_DQ21
C25
IO[52]/A-DQ[21][B-DQL5]/A-DQ[23] IO[124]/B-DQ[21][D-DQL5]/B-DQ[23]
V31
M1_DDR_DQ21 M1_DDR_A1 A1 4Gbit M1_DDR_A1 A1
P3 P3
M0_DDR_DQ22
A29
AB32
M1_DDR_DQ22 M1_DDR_A2 A2 (x16) M1_DDR_A2 A2 (x16)
B26 V30 N2 H1 N2 H1
M0_DDR_DQ23 M1_DDR_DQ23 M1_DDR_A3 A3 VREFDQ M1_DDR_A3 A3 VREFDQ
IO[51]/A-DQ[23][B-DQL7]/A-DQ[21] IO[125]/B-DQ[23][D-DQL7]/B-DQ[21] P8 P8
B27 W30 M1_DDR_A4 A4 M1_DDR_A4
M0_DDR_DM2 IO[55]/A-DQM[2][B-DML]/A-DQM[2] IO[128]/B-DQM[2][D-DML]/B-DQM[2] M1_DDR_DM2 A4
B28 Y30 P2 P2
M0_DDR_DQS2 M1_DDR_DQS2 M1_DDR_A5 A5 M1_DDR_A5 A5
IO[64]/A-DQS[2][B-DQSL]/A-DQS[2] IO[137]/B-DQS[2][D-DQSL]/B-DQS[2] R8 L8 R404 R8 L8 R419
C27 Y31 M1_DDR_A6 240 M1_DDR_A6 240
M0_DDR_DQS_N2 IO[63]/A-DQSB[2]/[B-DQSLB]/A-DQSB[2] IO[136]/B-DQSB[2][D-DQSLB]/B-DQSB[2] M1_DDR_DQS_N2 A6 ZQ A6 ZQ
R2 AVDD_DDR R2

T8 T8 AVDD_DDR
E29 Y28 R3 B2 R3 B2
M0_DDR_DQ24 M1_DDR_DQ24 M1_DDR_A9 A9 VDD_1 M1_DDR_A9 A9 VDD_1
IO[58]/A-DQ[24][B-DQU0]/A-DQ[31] IO[131]/B-DQ[24][D-DQU0]/B-DQ[31] L7 D9 L7 D9
C31 AB27 M1_DDR_A10 A10/AP VDD_2 M1_DDR_A10
M0_DDR_DQ25 IO[67]/A-DQ[25][B-DQU1]/A-DQ[26] IO[141]/B-DQ[25][D-DQU1]/B-DQ[26] M1_DDR_DQ25 A10/AP VDD_2
R7 G7 R7 G7
E27 V27 M1_DDR_A11 A11 VDD_3 M1_DDR_A11

M0_DDR_DQ26 IO[56]/A-DQ[26][B-DQU2]/A-DQ[29] IO[130]_/B-DQ[26][D-DQU2]/B-DQ[29] M1_DDR_DQ26 A11 VDD_3
D31 AB29 N7 K2 N7 K2
M0_DDR_DQ27 M1_DDR_DQ27 M1_DDR_A12 A12/BC VDD_4 M1_DDR_A12 A12/BC VDD_4
IO[66]/A-DQ[27][B-DQU3]/A-DQM[3] IO[140]/B-DQ[27][D-DQU3]/B-DQM[3] T3 K8 T3 K8
D29 W28 M1_DDR_A13 A13 VDD_5 M1_DDR_A13
M0_DDR_DQ28 IO[59]/A-DQ[28][B-DQU4]/A-DQ[25] IO[129]/B-DQ[28][D-DQU4]/B-DQ[25] M1_DDR_DQ28 A13 VDD_5
D30 AB28 T7 N1 T7 N1
IO[65]/A-DQ[29][B-DQU5]/A-DQ[28] IO[139]/B-DQ[29][D-DQU5]/B-DQ[28] M7 N9 M7 N9
E28 W27 M1_DDR_A15 NC_5 VDD_7 M1_DDR_A15
M0_DDR_DQ30 IO[57]/A-DQ[30][B-DQU6]/A-DQ[27] IO[132]/B-DQ[30][D-DQU6]/B-DQ[27] M1_DDR_DQ30 NC_5 VDD_7
C30 AA27 R1 R1
M0_DDR_DQ31 IO[60]/A-DQ[31][B-DQU7]/A-DQ[24] IO[138]/B-DQ[31][D-DQU7]/B-DQ[24] M1_DDR_DQ31 VDD_8 VDD_8
B31 Y27 M2 R9 M2 R9
M0_DDR_DM3 M1_DDR_DM3 M1_DDR_BA0 BA0 VDD_9 M1_DDR_BA0 BA0 VDD_9
IO[68]/A-DQM[3][B-DMU]/A-DQ[30] IO[133]/B-DQM[3][D-DMU]/B-DQ[30] N8 N8
A31 AA28 M1_DDR_BA1 BA1 M1_DDR_BA1
M0_DDR_DQS3 IO[62]/A-DQS[3][B-DQSU]/A-DQS[3] IO[135]/B-DQS[3][D-DQSU]/B-DQS[3] M1_DDR_DQS3 BA1
B30 Y29 M3 M3
M0_DDR_DQS_N3 M1_DDR_DQS_N3 M1_DDR_BA2 BA2 M1_DDR_BA2 BA2
IO[61]/A-DQSB[3][B-DQSUB]/A-DQSB[3] IO[134]/B-DQSB[3][D-DQSUB]/B-DQSB[3] A1 A1
VDDQ_1 VDDQ_1
J7 A8 J7 A8
M1_D_CLK CK VDDQ_2 M1_D_CLK CK VDDQ_2
K7 C1 K7 C1
M1_D_CLKN CK VDDQ_3 M1_D_CLKN CK VDDQ_3
K9 C9 K9 C9
D2 D2
VDDQ_5 VDDQ_5
L2 E9 L2 E9
M1_DDR_CS1 CS VDDQ_6 M1_DDR_CS2 CS VDDQ_6
K1 F1 K1 F1
J3 H2 C468 0.1uF J3 H2 C490 0.1uF
M1_DDR_RASN RAS VDDQ_8 M1_DDR_RASN RAS VDDQ_8
K3 H9 C469 0.1uF K3 H9 C491 0.1uF
M1_DDR_CASN CAS VDDQ_9 M1_DDR_CASN CAS VDDQ_9
L3 L3
M1_DDR_WEN WE M1_DDR_WEN WE
J1 J1 * DDR_VTT
NC_1 NC_1
T2 J9 T2 J9
L1 L1
NC_3 NC_3
L9 L9 SS_DDR3_4Gb_25n
IC404-*1
Hynix_DDR3_4Gb_25n
IC404-*2
SS_DDR3_2Gb
IC404-*3
Hynix_DDR3_2Gb
IC404-*4
NC_4 NC_4 K4B4G1646D-BCMA H5TQ4G63CFR_RDC K4B2G1646Q-BCMA H5TQ2G63FFR-RDC
F3 F3 EAN63391401 EAN63053202 EAN63667401 EAN63648701
M1_DDR_DQS0 DQSL SS_DDR3_4Gb_25n

IC403-*1
Hynix_DDR3_4Gb_25n
IC403-*2
SS_DDR3_2Gb Hynix_DDR3_2Gb M1_DDR_DQS2 DQSL N3
A0 VREFCA
M8 N3
A0 VREFCA
M8 N3
A0 VREFCA
M8 N3
A0 VREFCA
M8
AVDD_DDR
G3 K4B4G1646D-BCMA H5TQ4G63CFR_RDC
IC403-*3
K4B2G1646Q-BCMA
IC403-*4
H5TQ2G63FFR-RDC G3 P7
P3
A1
A2
P7
P3
A1
A2
P7
P3
A1
A2
P7
P3
A1
A2
+3.3V_NORMAL
M1_DDR_DQS_N0 DQSL EAN63391401 EAN63053202 EAN63667401 EAN63648701 M1_DDR_DQS_N2 DQSL N2
P8
A3
A4
VREFDQ
H1 N2
P8
A3
A4
VREFDQ
H1 N2
P8
A3
A4
VREFDQ
H1 N2
P8
A3
A4
VREFDQ
H1
N3 M8 N3 M8 N3 M8 N3 M8 P2 P2 P2 P2
A0 VREFCA A0 VREFCA A0 VREFCA A0 VREFCA A5 A5 A5 A5
P7 P7 P7 P7 R8 L8 R8 L8 R8 L8 R8 L8
C7 A9
P3
N2
P8
A1
A2
A3 VREFDQ
H1
P3
N2
P8
A1
A2
A3 VREFDQ
H1
P3
N2
P8
A1
A2
A3 VREFDQ
H1
P3
N2
P8
A1
A2
A3 VREFDQ
H1
C7 A9
R2
T8
R3
A6
A7
A8
ZQ
B2
R2
T8
R3
A6
A7
A8
ZQ
B2
R2
T8
R3
A6
A7
A8
ZQ
B2
R2
T8
R3
A6
A7
A8
ZQ
B2
IC402
M1_DDR_DQS1 DQSU VSS_1 P2
R8
A4
A5
L8
P2
R8
A4
A5
L8
P2
A4
A5
P2
A4
A5 M1_DDR_DQS3 DQSU VSS_1 L7
A9
A10/AP
VDD_1
VDD_2
D9 L7
A9
A10/AP
VDD_1
VDD_2
D9 L7
A9
A10/AP
VDD_1
VDD_2
D9 L7
A9
A10/AP
VDD_1
VDD_2
D9
AP2303MPTR-G1 [EP]
B7 B3 R2
A6
A7
ZQ
R2
A6
A7
ZQ
R8
R2
A6
A7
ZQ
L8 R8
R2
A6
A7
ZQ
L8
B7 B3 R7
N7
A11
A12/BC
VDD_3
VDD_4
G7
K2
R7
N7
A11
A12/BC
VDD_3
VDD_4
G7
K2
R7
N7
A11
A12/BC
VDD_3
VDD_4
G7
K2
R7
N7
A11
A12/BC
VDD_3
VDD_4
G7
K2
M1_DDR_DQS_N1 DQSU VSS_2 T8 T8 T8 T8

M1_DDR_DQS_N3 DQSU VSS_2 T3 K8 T3 K8 T3 K8 T3 K8
CIS21J121
A8 A8 A8 A8 A13 VDD_5 A13 VDD_5 A13 VDD_5 A13 VDD_5
R3 B2 R3 B2 R3 B2 R3 B2 N1 T7 N1 N1 T7 N1
E1 L7
R7
A9
A10/AP
VDD_1
VDD_2
D9
G7
L7
R7
A9
A10/AP
VDD_1
VDD_2
D9
G7
L7
R7
A9
A10/AP
VDD_1
VDD_2
D9
G7
L7
R7
A9
A10/AP
VDD_1
VDD_2
D9
G7
E1 M7
NC_5
VDD_6
VDD_7
N9
R1
M7
A14
NC_5
VDD_6
VDD_7
N9
R1
M7
NC_5
VDD_6
VDD_7
N9
R1
M7
A14
NC_5
VDD_6
VDD_7
N9
R1
VSS_3 N7
A11 VDD_3
K2 N7
A11 VDD_3
K2 N7
A11 VDD_3
K2 N7
A11 VDD_3
K2 VSS_3 M2
VDD_8
R9 M2
VDD_8
R9 M2
VDD_8
R9 M2
VDD_8
R9
C544
L401
A12/BC VDD_4 A12/BC VDD_4 A12/BC VDD_4 A12/BC VDD_4 BA0 VDD_9 BA0 VDD_9 BA0 VDD_9 BA0 VDD_9
E7 G8 T3
A13 VDD_5
K8
N1
T3
T7
A13 VDD_5
K8
N1
T3
A13 VDD_5
K8
N1
T3
T7
A13 VDD_5
K8
N1
E7 G8 N8
M3
BA1
N8
M3
BA1
N8
M3
BA1
N8
M3
BA1
VIN NC_3
NC_5
VDD_6
VDD_7
N9
R1
M7
A14
NC_5
VDD_6
VDD_7
N9
R1
M7
NC_5
VDD_6
VDD_7
N9 M7
A14
NC_5
VDD_6
VDD_7
N9
M1_DDR_DM2 DML VSS_4 BA2
VDDQ_1
A1
BA2
VDDQ_1
A1
BA2
VDDQ_1
A1
BA2
VDDQ_1
A1
1 8 10uF
D3 J2 M2
BA0
VDD_8
VDD_9
R9 M2
BA0
VDD_8
VDD_9
R9 M2
BA0
VDD_8
VDD_9
R1
R9 M2
BA0
VDD_8
VDD_9
R1
R9 D3 J2 J7
K7
CK
CK
VDDQ_2
VDDQ_3
A8
C1
J7
K7
CK
CK
VDDQ_2
VDDQ_3
A8
C1
J7
K7
CK
CK
VDDQ_2
VDDQ_3
A8
C1
J7
K7
CK
CK
VDDQ_2
VDDQ_3
A8
C1
10V
M1_DDR_DM1 DMU VSS_5 N8 N8 N8 N8
M1_DDR_DM3 DMU VSS_5 K9 C9 K9 C9 K9 C9 K9 C9
C421
THERMAL
BA1 BA1 BA1 BA1 CKE VDDQ_4 CKE VDDQ_4 CKE VDDQ_4 CKE VDDQ_4
M3 M3 M3 M3 D2 D2 D2 D2
J8 J7
BA2
VDDQ_1
A1
A8 J7
BA2
VDDQ_1
A1
A8 J7
BA2
VDDQ_1
A1
A8 J7
BA2
VDDQ_1
A1
A8
J8 L2
K1
CS
VDDQ_5
VDDQ_6
E9
F1
L2
K1
CS
VDDQ_5
VDDQ_6
E9
F1
L2
K1
CS
VDDQ_5
VDDQ_6
E9
F1
L2
K1
CS
VDDQ_5
VDDQ_6
E9
F1 10uF
VSS_6 K7
CK
CK
VDDQ_2
VDDQ_3
C1 K7
CK
CK
VDDQ_2
VDDQ_3
C1 K7
CK
CK
VDDQ_2
VDDQ_3
C1 K7
CK
CK
VDDQ_2
VDDQ_3
C1 VSS_6 J3
ODT
RAS
VDDQ_7
VDDQ_8
H2 J3
ODT
RAS
VDDQ_7
VDDQ_8
H2 J3
ODT
RAS
VDDQ_7
VDDQ_8
H2 J3
ODT
RAS
VDDQ_7
VDDQ_8
H2
GND NC_2
9
E3 M1 K9
CKE VDDQ_4
C9
D2
K9
CKE VDDQ_4
C9
D2
K9
CKE VDDQ_4
C9
D2
K9
CKE VDDQ_4
C9
D2
E3 M1 K3
L3
CAS VDDQ_9
H9 K3
L3
CAS VDDQ_9
H9 K3
L3
CAS VDDQ_9
H9 K3
L3
CAS VDDQ_9
H9
10V 2 7
K1
CS
VDDQ_5
VDDQ_6
E9
F1
L2
K1
CS
VDDQ_5
VDDQ_6
E9
F1
L2
CS
VDDQ_5
VDDQ_6
E9 L2
CS
VDDQ_5
VDDQ_6
E9
M1_DDR_DQ16 DQL0 VSS_7 WE
NC_1
J1
WE
NC_1
J1
WE
NC_1
J1
WE
NC_1
J1
F7 M9 J3
ODT
RAS
VDDQ_7
VDDQ_8
H2 J3
ODT
RAS
VDDQ_7
VDDQ_8
H2
K1
J3
ODT
RAS
VDDQ_7
VDDQ_8
F1
H2
K1
J3
ODT
RAS
VDDQ_7
VDDQ_8
F1
H2 F7 M9 T2
RESET NC_2
NC_3
J9
L1
T2
RESET NC_2
NC_3
J9
L1
T2
RESET NC_2
NC_3
J9
L1
T2
RESET NC_2
NC_3
J9
L1 DDR_VTT
M1_DDR_DQ1 DQL1 VSS_8 K3
L3
CAS VDDQ_9
H9 K3
L3
CAS VDDQ_9
H9 K3
L3
CAS VDDQ_9
H9 K3
L3
CAS VDDQ_9
H9
M1_DDR_DQ17 DQL1 VSS_8 F3
NC_4
L9
T7 F3
NC_4
L9
F3
NC_4
L9
T7 F3
NC_4
L9
R443
F2 P1 WE
NC_1
J1
WE
NC_1
J1 WE
J1
WE
J1
F2 P1 G3
DQSL NC_6
G3
DQSL
G3
DQSL NC_6
G3
DQSL
VREFEN VCNTL
M1_DDR_DQ2 DQL2 VSS_9
T2
RESET NC_2
J9
L1
T2
RESET NC_2
J9
L1
T2
RESET
NC_1
NC_2
J9 T2
RESET
NC_1
NC_2
J9
M1_DDR_DQ18 DQL2 VSS_9
DQSL DQSL DQSL DQSL
10K
F8 P9
NC_3
L9
NC_3
L9 NC_3
L1
L9
NC_3
L1
L9
F8 P9
C7
B7
DQSU VSS_1
A9
B3
C7
B7
DQSU VSS_1
A9
B3
C7
B7
DQSU VSS_1
A9
B3
C7
B7
DQSU VSS_1
A9
B3 3 6
CIS21J121
NC_4 NC_4 NC_4 NC_4 DQSU VSS_2 DQSU VSS_2 DQSU VSS_2 DQSU VSS_2
F3 T7 F3 F3 T7 F3 E1 E1 E1 E1
M1_DDR_DQ3 DQL3 VSS_10 G3
DQSL
DQSL
NC_6
G3
DQSL
DQSL
G3
DQSL
DQSL
NC_6
G3
DQSL
DQSL M1_DDR_DQ19 DQL3 VSS_10 E7
DML
VSS_3
VSS_4
G8 E7
DML
VSS_3
VSS_4
G8 E7
DML
VSS_3
VSS_4
G8 E7
DML
VSS_3
VSS_4
G8
1/16W
H3 T1 C7 A9 C7 A9 H3 T1 D3
DMU VSS_5
J2 D3
DMU VSS_5
J2 D3
DMU VSS_5
J2 D3
DMU VSS_5
J2
L400
C7 A9 C7 A9 J8 J8 J8 J8
DQSU VSS_1 DQSU VSS_1 DQSU VSS_1 DQSU VSS_1 VSS_6 VSS_6 VSS_6 VSS_6
M1_DDR_DQ4 DQL4 VSS_11 B7
DQSU VSS_2
B3
E1
B7
DQSU VSS_2
B3
E1
B7
DQSU VSS_2
B3
E1
B7
DQSU VSS_2
B3
E1
M1_DDR_DQ20 DQL4 VSS_11 E3
F7
DQL0 VSS_7
M1
M9
E3
F7
DQL0 VSS_7
M1
M9
E3
F7
DQL0 VSS_7
M1
M9
E3
F7
DQL0 VSS_7
M1
M9
1% VOUT NC_1
H8 T9 E7
D3
DML
VSS_3
VSS_4
G8
J2
E7
D3
DML
VSS_3
VSS_4
G8
J2
E7
DML
VSS_3
VSS_4
G8 E7
DML
VSS_3
VSS_4
G8
H8 T9 F2
DQL1
DQL2
VSS_8
VSS_9
P1 F2
DQL1
DQL2
VSS_8
VSS_9
P1 F2
DQL1
DQL2
VSS_8
VSS_9
P1 F2
DQL1
DQL2
VSS_8
VSS_9
P1
4 5
M1_DDR_DQ5 DQL5 VSS_12 DMU VSS_5
VSS_6
J8
DMU VSS_5
VSS_6
J8
D3
DMU VSS_5
VSS_6
J2
J8
D3
DMU VSS_5
VSS_6
J2
J8 M1_DDR_DQ21 DQL5 VSS_12
F8
H3
DQL3
DQL4
VSS_10
VSS_11
P9
T1
F8
H3
DQL3
DQL4
VSS_10
VSS_11
P9
T1
F8
H3
DQL3
DQL4
VSS_10
VSS_11
P9
T1
F8
H3
DQL3
DQL4
VSS_10
VSS_11
P9
T1
G2 E3
F7
DQL0 VSS_7
M1
M9
E3
F7
DQL0 VSS_7
M1
M9
E3
F7
DQL0 VSS_7
M1
M9
E3
F7
DQL0 VSS_7
M1
M9 G2 H8
G2
DQL5 VSS_12
T9 H8
G2
DQL5 VSS_12
T9 H8
G2
DQL5 VSS_12
T9 H8
G2
DQL5 VSS_12
T9
M1_DDR_DQ6 DQL6 F2
F8
DQL1
DQL2
VSS_8
VSS_9
P1
P9
F2
F8
DQL1
DQL2
VSS_8
VSS_9
P1
P9
F2
DQL1
DQL2
VSS_8
VSS_9
P1 F2
DQL1
DQL2
VSS_8
VSS_9
P1
M1_DDR_DQ22 DQL6 H7
DQL6
DQL7
H7
DQL6
DQL7
H7
DQL6
DQL7
H7
DQL6
DQL7
H7 H3
DQL3
DQL4
VSS_10
VSS_11
T1 H3
DQL3
DQL4
VSS_10
VSS_11
T1
F8
H3
DQL3
DQL4
VSS_10
VSS_11
P9
T1
F8
H3
DQL3
DQL4
VSS_10
VSS_11
P9
T1 H7 D7
DQU0
VSSQ_1
VSSQ_2
B1
B9 D7
DQU0
VSSQ_1
VSSQ_2
B1
B9 D7
DQU0
VSSQ_1
VSSQ_2
B1
B9 D7
DQU0
VSSQ_1
VSSQ_2
B1
B9
M1_DDR_DQ7 DQL7 H8
G2
DQL5 VSS_12
T9 H8
G2
DQL5 VSS_12
T9 H8
G2
DQL5 VSS_12
T9 H8
G2
DQL5 VSS_12
T9
M1_DDR_DQ23 DQL7 C3
C8
DQU1 VSSQ_3
D1
D8
C3
C8
DQU1 VSSQ_3
D1
D8
C3
C8
DQU1 VSSQ_3
D1
D8
C3
C8
DQU1 VSSQ_3
D1
D8
B1 H7
DQL6
DQL7
B1
H7
DQL6
DQL7
B1
H7
DQL6
DQL7
B1
H7
DQL6
DQL7
B1
B1 C2
A7
DQU2
DQU3
VSSQ_4
VSSQ_5
E2
E8
C2
A7
DQU2
DQU3
VSSQ_4
VSSQ_5
E2
E8
C2
A7
DQU2
DQU3
VSSQ_4
VSSQ_5
E2
E8
C2
A7
DQU2
DQU3
VSSQ_4
VSSQ_5
E2
E8
VSSQ_1 D7
DQU0
VSSQ_1
VSSQ_2
B9 D7
DQU0
VSSQ_1
VSSQ_2
B9 D7
DQU0
VSSQ_1
VSSQ_2
B9 D7
DQU0
VSSQ_1
VSSQ_2
B9 VSSQ_1 A2
DQU4
DQU5
VSSQ_6
VSSQ_7
F9 A2
DQU4
DQU5
VSSQ_6
VSSQ_7
F9 A2
DQU4
DQU5
VSSQ_6
VSSQ_7
F9 A2
DQU4
DQU5
VSSQ_6
VSSQ_7
F9
D7 B9 C3
C8
DQU1 VSSQ_3
D1
D8
C3
C8
DQU1 VSSQ_3
D1
D8
C3
C8
DQU1 VSSQ_3
D1
D8
C3
C8
DQU1 VSSQ_3
D1
D8 D7 B9 B8
A3
DQU6 VSSQ_8
G1
G9
B8
A3
DQU6 VSSQ_8
G1
G9
B8
A3
DQU6 VSSQ_8
G1
G9
B8
A3
DQU6 VSSQ_8
G1
G9
M1_DDR_DQ8 DQU0 VSSQ_2 C2
A7
DQU2
DQU3
VSSQ_4
VSSQ_5
E2
E8
C2
A7
DQU2
DQU3
VSSQ_4
VSSQ_5
E2
E8
C2
DQU2
DQU3
VSSQ_4
VSSQ_5
E2 C2
DQU2
DQU3
VSSQ_4
VSSQ_5
E2
M1_DDR_DQ24 DQU0 VSSQ_2 DQU7 VSSQ_9 DQU7 VSSQ_9 DQU7 VSSQ_9 DQU7 VSSQ_9
C414 C417 C535

C3 D1 A2
DQU4
DQU5
VSSQ_6
VSSQ_7
F9 A2
DQU4
DQU5
VSSQ_6
VSSQ_7
F9
A7
A2
DQU4
DQU5
VSSQ_6
VSSQ_7
E8
F9
A7
A2
DQU4
DQU5
VSSQ_6
VSSQ_7
E8
F9 C3 D1
A3
DQU6 VSSQ_8
G1
G9
B8
A3
DQU6 VSSQ_8
G1
G9
B8
A3
DQU6 VSSQ_8
G1
G9
B8
A3
DQU6 VSSQ_8
G1
G9 M1_DDR_DQ25 DQU1 VSSQ_3 10uF 10uF 10uF
C8 D8 DQU7 VSSQ_9 DQU7 VSSQ_9 DQU7 VSSQ_9 DQU7 VSSQ_9
C8 D8 10V 10V 10V
M1_DDR_DQ10 DQU2 VSSQ_4 M1_DDR_DQ26 DQU2 VSSQ_4 C543
1%
1/16W
10K
R444
C2 E2 C2 E2
M1_DDR_DQ11 DQU3 VSSQ_5 M1_DDR_DQ27 DQU3 VSSQ_5 0.1uF
A7 E8 A7 E8 16V
M1_DDR_DQ12 DQU4 VSSQ_6 M1_DDR_DQ28 DQU4 VSSQ_6
A2 F9 A2 F9
B8 G1 B8 G1
A3 G9 A3 G9
+1.5V_Bypass Cap +1.5V_Bypass Cap

Close to DDR Power Pin Close to DDR Power Pin
AVDD_DDR
AVDD_DDR
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
C475
C480
C476
C444
C445
C446

SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. BSD-15Y-LM14A-004_00-HD
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS 2014-12-30
LM14A
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. LM14A DDR 04
COMPENSATION_DONE_1
OLED Clock for MSD808KWD
DPC_CTRL
+3.3V_NORMAL
MAIN Clock(24Mhz)
Jtag I/F
X-TAL_1
12V_ON 5pF
GND_1
XIN_MAIN
C600 For Main C614
R612 JTAG
R614 JTAG
R616 JTAG
0.1uF
R635
JTAG
24MHz
X600
1M
1K
1K
1K
SW600
JS2235S P600
4
12505WS-10A00
X-TAL_2
GND_2
JTAG
1
5pF
TRST_N0 XOUT_MAIN
TDI0 1 6 TDO0
2
C615
R602 R604 TDI0
0 0
3
OPT OPT TDO0
TDI0_1 2 5 TDO0_1 System Clock for Analog block(24Mhz)
4
R603 JTAG R605 TMS0
0 0
OPT OPT 5
TCK0
3 4
6
SOC_RESET
7
JTAG
1K
R609
8
10
11
IC100
LGE5332(LM14A) IC100
LGE5332(LM14A)
R624 33 0.047uF C620

T2 AF6 SC_R
D0-_HDMI1 A_RX0N LINEIN_L0 COMP1/AV1/DVI_L_IN AA2 B1
T3 AE6 2.2uF C601 RIN0P TN EPHY_TDN
D0+_HDMI1 A_RX0P LINEIN_R0 COMP1/AV1/DVI_R_IN R625 68 0.047uF C621 AA1 C1
U1 AF2 2.2uF C602 GIN0M TP EPHY_TDP
D1-_HDMI1 A_RX1N LINEIN_L1 SC_L_IN Y3 A2
V2 AF1 2.2uF C603 R626 33 C622 GIN0P RN EPHY_RDN
D1+_HDMI1 A_RX1P LINEIN_R1 SC_R_IN 0.047uF B2
V3 AG5 2.2uF C604 SC_G
D2-_HDMI1 RP EPHY_RDP
A_RX2N LINEIN_L2 Y1
W2 AG4 BIN0P
D2+_HDMI1 A_RX2P LINEIN_R2 R628 33 0.047uF C624
R1 SC_B
CK-_HDMI1 A_RXCN AA6
R2 SC_ID HSYNC0
CK+_HDMI1 A_RXCP AA5 D4
R6 SC_FB VSYNC0 GPIO19/[LED0]/GPIO74 I2C_SCL4
DDC_SCL_1 DDCDA_CK/GPIO38 T6
T5 AF3 GPIO20/[LED1]/GPIO75 I2C_SDA4
HDMI 1.4b &2.0 DDC_SDA_1 DDCDA_DA/GPIO39 MICCM0
MHL OPT Y2 AG1
HDMI_HPD_1 HOTPLUGA MICIN0 R630 33 0.047uF C627 AA3
V6 AH2 COMP1_Pr 0.047uF RIN1P
CEC0/GPIO5 LINEOUT_L2 SCART_Lout R631 68 C628 AC1
URSA_RESET_SoC U4 AH3
5V_DET_HDMI_1 SCART_Rout R632 33 0.047uF C629 GIN1M
HOTPLUGA_HDMI20_5V/GPIO34 LINEOUT_R2 COMP1_Y AC2
GIN1P
L1 AF4
D0-_HDMI2 B_RX0N EARPHONE_OUTL HP_LOUT R634 33 0.047uF C631 AB2
M2 AF5 COMP1_Pb BIN1P
D0+_HDMI2 B_RX0P EARPHONE_OUTR HP_ROUT 1000pF C632 AB3
M3 SOGIN1
D1-_HDMI2 B_RX1N C605 1uF
N2 P3
D1+_HDMI2 B_RX1P ARC0/GPIO6 HDMI_ARC
P2
D2-_HDMI2 B_RX2N AD3 D5
P1 RIN2P RESET SOC_RESET
D2+_HDMI2 B_RX2P AD2
K2 AG3 GIN2M
CK-_HDMI2 B_RXCN VAG AD1 AM4
K3 AG2 C606 L600 GIN2P XTAL_IN XIN_MAIN
CK+_HDMI2 B_RXCP AVSS_VRM_ADC 1uF AK4
L4 10uF PZ1608U121-2R0TF
C609 XTAL_OUT XOUT_MAIN
DDC_SCL_2 DDCDB_CK/GPIO40 10V AC3
L5 BIN2P
DDC_SDA_2 DDCDB_DA/GPIO41 F5
M4 IRIN/GPIO4 BIT11
HDMI_HPD_2 HOTPLUGB/GPIO31
M5 D8
5V_DET_HDMI_2 HOTPLUGB_HDMI20_5V/GPIO35 I2S_IN_BCK/GPIO94 TRST_N0
D6 JTAG 0 R606
47K
+3.3V_NORMAL
JTAG
R615
I2S_IN_SD/GPIO95 TCK0 A4
D2 C5 JTAG 1K R608 DM_P0 WIFI_DM
C_RX0N I2S_IN_WS/GPIO93 B4
D3 R610 DP_P0 WIFI_DP
C_RX0P 22 C4
E2 G6 R619 68 DM_P1
C_RX1N I2S_OUT_BCK/GPIO100 AUD_SCK C613 0.047uF AD6 B3
E3 E6 R611 VCOM DP_P1
C_RX1P I2S_OUT_MCK/GPIO99 22 AL6
F2 F6 R618 DM_P2 USB_DM3
C_RX2N I2S_OUT_WS/GPIO98 AUD_LRCK R620 33 C616 0.047uF AC6 AK6
F1 E8 22 TU_CVBS USB_DP3
AUD_LRCH CVBS0 DP_P2 AC-coupling CAP
C_RX2P I2S_OUT_SD/GPIO101 R621 33 C617 0.047uF AC5 AM14 C633 0.1uF
C3 F9 AV1_CVBS_IN CVBS1 SSUSB_TXP SSUSB_TXP
C_RXCN I2S_OUT_SD1/GPIO102 BIT10 R622 33 C618 0.047uF AB6 AL14 C634 0.1uF Place near by MST
D1 E7 C607 SC_CVBS_IN CVBS2 SSUSB_TXN SSUSB_TXN
C_RXCP I2S_OUT_SD2/GPIO103 DPC_CTRL AM13
H6 F7 22pF DM_PSS USB_DM1
BIT6 DDCDC_CK/GPIO42 I2S_OUT_SD3/GPIO104 12V_ON AK13
H5 DP_PSS USB_DP1
BIT7 DDCDC_DA/GPIO43 C608 C611 C612 AK12
K6 AG7 0 R644 SSUSB_RXP
BIT8 MHL_DET_LM15 22pF 22pF 1000pF SSUSB_RXP
HOTPLUGC/GPIO32 GPIO_PM[14]/GPIO24 50V AL13
J6 AH6 OPT SSUSB_RXN SSUSB_RXN
BIT9 HOTPLUGC_HDMI20_5V/GPIO36 GPIO_PM[15]/GPIO25 COMPENSATION_DONE_1 AK9
AH5 SSUSB_TXP1
GPIO_PM[16]/GPIO26 /MHL_OCP AL10
G2 SSUSB_TXN1
D0-_HDMI3 D_RX0N AM10
G3 DM_PSS1 USB_DM2
D0+_HDMI3 D_RX0P AC4 AK10
H2 DTV/MNT_V_OUT CVBS_OUT1 DP_PSS1 USB_DP2
D1-_HDMI3 D_RX1N JTAG AM11
H3 SSUSB_RXP1
D1+_HDMI3 D_RX1P R613 AL11
J2 0 SSUSB_RXN1
D2-_HDMI3 D_RX2N
J1 TDO0_1
D2+_HDMI3 D_RX2P
F3
CK-_HDMI3 D_RXCN
G1
CK+_HDMI3 D_RXCP
J4
DDC_SCL_3 DDCDD_CK/GPIO44
K5
DDC_SDA_3 DDCDD_DA/GPIO45
H4
HDMI_HPD_3 HOTPLUGD/GPIO33
J5
5V_DET_HDMI_3 HOTPLUGD_HDMI20_5V/GPIO37
R600 JTAG
0
TMS0 B5
SPDIF_IN/GPIO96
A5
SPDIF_OUT SPDIF_OUT/GPIO97
JTAG
R601
0
TDI0_1

THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. MAIN4_EXT_IN/OUTPUT 06
IC100
LGE5332(LM14A)
A15 T23
GND_1 GND_171
A18 T24
GND_2 GND_172
A21 T25
GND_3 GND_173
A24 T26
GND_4 GND_174
A27 U2
GND_5 GND_175
A30 U3
GND_6 GND_176
B10 U8
GND_7 GND_177
B32 U9
GND_8 GND_178
C2 U10
GND_9 GND_179
C13 U14
GND_10 GND_180
C32 U15
GND_11 GND_181
D18 U16
GND_12 GND_182
D21 U17
GND_13 GND_183
D25 U18
GND_14 GND_184
D28 U20
GND_15 GND_185
D32 U26
GND_16 GND_186
E30 V1
GND_17 GND_187
E31 V8
GND_18 GND_188
E32 V9
GND_19 GND_189
F22 V10
GND_20 GND_190
F24 V11
GND_21 GND_191
F25 V12
GND_22 GND_192
F26 V13
GND_23 GND_193
F27 V14
GND_24 GND_194
F28 V15
GND_25 GND_195
F29 V16
GND_26 GND_196
F30 V20
GND_27 GND_197
F31 V21
GND_28 GND_198
G11 V22
GND_29 GND_199
G12 V26
GND_30 GND_200
G13 V29
GND_31 GND_201
G14 V32
GND_32 GND_202
G15 W3
GND_33 GND_203
G16 W8
GND_34 GND_204
G17 W9
GND_35 GND_205
G18 W10
GND_36 GND_206
G19 W11
GND_37 GND_207
G20 W12
GND_38 GND_208
G21 W13
GND_39 GND_209
G23 W14
GND_40 GND_210
G24 W15
GND_41 GND_211
G25 W16
GND_42 GND_212
G26 W17
GND_43 GND_213
G27 W18
GND_44 GND_214
G28 W22
GND_45 GND_215
H8 W26
GND_46 GND_216
H9 Y8
GND_47 GND_217
H10 Y9
GND_48 GND_218
H11 Y10
GND_49 GND_219
H12 Y11
GND_50 GND_220
H13 Y12
GND_51 GND_221
H14 Y13
GND_52 GND_222
H15 Y14
GND_53 GND_223
H17 Y15
GND_54 GND_224
H18 Y16
GND_55 GND_225
H19 Y17
GND_56 GND_226
H20 Y18
GND_57 GND_227
H21 Y22
GND_58 GND_228
H22 Y26
GND_59 GND_229
H23 AA9
GND_60 GND_230
H24 AA10
GND_61 GND_231
H25 AA11
GND_62 GND_232
H26 AA12
GND_63 GND_233
H27 AA14
GND_64 GND_234
H30 AA15
GND_65 GND_235
J3 AA16
GND_66 GND_236
J7 AA17
GND_67 GND_237
J8 AA18
GND_68 GND_238
J14 AA21
GND_69 GND_239
J15 AA26
GND_70 GND_240
J16 AA29
GND_71 GND_241
J22 AA32
GND_72 GND_242
J24 AB9
GND_73 GND_243
J25 AB10
GND_74 GND_244
J26 AB11
GND_75 GND_245
J27 AB12
GND_76 GND_246
K7 AB13
GND_77 GND_247
K8 AB14
GND_78 GND_248
K14 AB16
GND_79 GND_249
K15 AB17
GND_80 GND_250
K25 AB18
GND_81 GND_251
K26 AB19
GND_82 GND_252
L2 AB20
GND_83 GND_253
L3 AB21
GND_84 GND_254
L8 AB22
GND_85 GND_255
L14 AB23
GND_86 GND_256
L15 AB26
GND_87 GND_257
L16 AB30
GND_88 GND_258
L25 AC7
GND_89 GND_259
L26 AC8
GND_90 GND_260
M1 AC9
GND_91 GND_261
M8 AC10
GND_92 GND_262
M9 AC11
GND_93 GND_263
M10 AC12
GND_94 GND_264
M11 AC13
GND_95 GND_265
M12 AC16
GND_96 GND_266
M13 AC23
GND_97 GND_267
M14 AC25
GND_98 GND_268
M15 AC26
GND_99 GND_269
M16 AC27
GND_100 GND_270
M17 AC28
GND_101 GND_271
M18 AD8
GND_102 GND_272
M19 AD9
GND_103 GND_273
M20 AD10
GND_104 GND_274
M25 AD11
GND_105 GND_275
M26 AD12
GND_106 GND_276
M29 AD13
GND_107 GND_277
M32 AD14
GND_108 GND_278
N3 AD15
GND_109 GND_279
N7 AD16
GND_110 GND_280
N8 AD24
GND_111 GND_281
N9 AD25
GND_112 GND_282
N10 AD26
GND_113 GND_283
N11 AD27
GND_114 GND_284
N13 AD28
GND_115 GND_285
N14 AE3
GND_116 GND_286
N17 AE8
GND_117 GND_287
N18 AE9
GND_118 GND_288
N19 AE10
GND_119 GND_289
N20 AE11
GND_120 GND_290
N24 AE12
GND_121 GND_291
N25 AE13
GND_122 GND_292
N26 AE14
GND_123 GND_293
P8 AE17
GND_124 GND_294
P9 AE18
GND_125 GND_295
P10 AE23
GND_126 GND_296
P11 AE24
GND_127 GND_297
P12 AE25
GND_128 GND_298
P13 AE26
GND_129 GND_299
P14 AE27
GND_130 GND_300
P15 AE28
GND_131 GND_301
P16 AE29
GND_132 GND_302
P17 AF9
GND_133 GND_303
P18 AF10
GND_134 GND_304
P19 AF17
GND_135 GND_305
P20 AF18
GND_136 GND_306
P24 AF19
GND_137 GND_307
P25 AF20
GND_138 GND_308
P26 AF21
GND_139 GND_309
R3 AF22
GND_140 GND_310
R8 AF23
GND_141 GND_311
R9 AF24
GND_142 GND_312
R10 AF25
GND_143 GND_313
R14 AF26
GND_144 GND_314
R15 AF27
GND_145 GND_315
R16 AF28
GND_146 GND_316
R17 AF29
GND_147 GND_317
R18 AF30
GND_148 GND_318
R19 AG22
GND_149 GND_319
R20 AG23
GND_150 GND_320
R21 AG30
GND_151 GND_321
R22 AH21
GND_152 GND_322
R23 AH22
GND_153 GND_323
R24 AJ3
GND_154 GND_324
R25 AJ22
GND_155 GND_325
R26 AJ30
GND_156 GND_326
R29 AK5
GND_157 GND_327
R32 AK11
GND_158 GND_328
T8 AK14
GND_159 GND_329
T9 AL1
GND_160 GND_330
T10 AL3
GND_161 GND_331
T14 AL4
GND_162 GND_332
T15 AL9
GND_163 GND_333
T16 AL12
GND_164 GND_334
T17 AL23
GND_165 GND_335
T18 AL27
GND_166 GND_336
T19 AM25
GND_167 GND_337
T20 AM29
GND_168 GND_338
T21 AM31
GND_169 GND_339
T22
GND_170

THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. LM14A_GND 07
CI Region * Option name of this page : CI_SLOT
(because of Hong Kong)
CI SLOT
+5V_CI_ON
CI_DATA[0-7]
CI TS INPUT
CI_SLOT
+5V_NORMAL CI_SLOT AR903 33
C902 FE_DEMOD1_TS_DATA[7]
10uF CI_MDI[7] FE_DEMOD1_TS_DATA[6]
CI_SLOT 10V CI_MDI[6]
@netLa
FE_DEMOD1_TS_DATA[5]
R906
CI_MDI[5] FE_DEMOD1_TS_DATA[4]
10K
CI_SLOT CI_MDI[4]
/CI_CD1 JK900
10125901-115LF CI_SLOT
CI_SLOT AR902 33
R912 FE_DEMOD1_TS_DATA[3]
35 1 CI_MDI[3]
CI_SLOT 100 CI_DATA[3] FE_DEMOD1_TS_DATA[2]
36 2 CI_MDI[2]
AR901 CI_DATA[4] FE_DEMOD1_TS_DATA[1]
33 37 3 CI_MDI[1]
CI_DATA[5] R916 FE_DEMOD1_TS_DATA[0]
TPI_DATA[4] 38 4 10K CI_MDI[0]
CI_DATA[6]
TPI_DATA[5] 39 5
CI_DATA[7]
TPI_DATA[6] 40 6 FE_DEMOD1_TS_DATA[0-7]
TPI_DATA[7] 41 7 R914 47 CI_SLOT R918 33 CI_SLOT
CI_ADDR[10] /PCM_CE1 CI_MISTRT FE_DEMOD1_TS_SYNC
42 8 R919 33 CI_SLOT
CI_MIVAL_ERR FE_DEMOD1_TS_VAL
CI_SLOT R908 10K 43 9 R920 100 CI_SLOT
CI_ADDR[11] CI_OE CI_MCLKI FE_DEMOD1_TS_CLK
CI_IORD 44 10 +5V_NORMAL
CI_ADDR[9]
CI_IOWR 45 11
CI_ADDR[8]
46 12 R917
CI_ADDR[13] 10K
CI_MDI[0] 47 13
CI_ADDR[14]
CI_MDI[1] 48 14 CI_SLOT
CI_MDI[2] 49 15 CI_WE
50 16 R915 100
CI_MDI[3] CI_SLOT CAM_IREQ_N
51 17 CI_SLOT
GND
C901
0.1uF
52
53
18
19
C903
0.1uF
C904
0.1uF
CI HOST I/F
CI_MDI[4] CI_SLOT CI_SLOT
GND
CI_MDI[5] 54 20
+5V_NORMAL CI_ADDR[12]
CI_MDI[6] 55 21 CLOSE TO MSTAR
CI_ADDR[7]
R900 56 22 GND
CI_MDI[7] R909 10K CI_ADDR[6] CI_SLOT
10K CI_SLOT 57 23
CI_ADDR[5] AR906
CI_SLOT R901 47 CI_SLOT 58 24
PCM_RESET CI_ADDR[4] 33
R902 47 CI_SLOT 59 25
CAM_WAIT_N CI_ADDR[3] CI_ADDR[0] EB_ADDR[0]
CLOSE TO MSTAR 60 26
REG CI_ADDR[2] CI_ADDR[1] EB_ADDR[1]
R903 33 CI_SLOT 61 27
TPI_CLK CI_ADDR[1] CI_ADDR[2] EB_ADDR[2]
R904 33 CI_SLOT 62 28
TPI_VAL CI_ADDR[3] EB_ADDR[3]
R905 33 CI_SLOT CI_ADDR[0]
TPI_SOP 63 29
CI_DATA[0]
CI_SLOT 64 30
AR900 33 CI_DATA[1]
65 31 CI_ADDR[0-14]
TPI_DATA[0] CI_DATA[2]
66 32 OLED_CI_SLOT CI_SLOT
TPI_DATA[1] 67 33 JK900-*1
AR907
10125901-015LF
TPI_DATA[2] 68 34 35 1
33
TPI_DATA[3] 36 2
37 3 CI_ADDR[4] EB_ADDR[4]
G2 69 G1 38 4
R910 39 5 CI_ADDR[5] EB_ADDR[5]

40 6
100 41 7 CI_ADDR[6] EB_ADDR[6]
/CI_CD2 42 8
CI_SLOT 43 9 CI_ADDR[7] EB_ADDR[7]

+5V_NORMAL GND 44 10
45 11
46
47
12
13
CI_SLOT
CI_SLOT GND 48 14
AR908 33
C900 49 15
50 16
2pF 51 17
CI_ADDR[8] EB_ADDR[8]
R907
50V 52 18
10K GND 53 19
54 20
CLOSE TO MSTAR CI_SLOT
55
56
21
22
57 23
58 24
59 25
60 26
61 27
62 28
CI_SLOT
63 29
CI_MISTRT 64 30
AR909 33
CI_MIVAL_ERR 65 31
66 32
67 33
68 34
CI_MCLKI G2 69 G1 CI_ADDR[14] EB_ADDR[14]
REG CAM_REG_N
CI_SLOT
AR913 33
CI_OE EB_OE_N
CI_WE EB_WE_N
CI_IORD EB_BE_N1
CI DETECT +3.3V_NORMAL
CI_IOWR EB_BE_N0
CI_SLOT
IC900
74LVC1G32GW +3.3V_NORMAL
B 1 5 VCC
/CI_CD2
CI_SLOT
A 2
/CI_CD1 AR904 33
GND 3 4 Y R911 CI_DATA[0] EB_DATA[0]
10K CI_DATA[1] EB_DATA[1]
CI_DATA[2] EB_DATA[2]
OR_GATE_CI_TI OR_GATE_CI_TOSHIBA CI_DATA[3] EB_DATA[3]
IC900-*1 IC900-*2
SN74LVC1G32DCKR TOSHIBA ELECTRONICS KOREA CORPORATION
EB_DATA[0-7]
@netLa
A VCC IN_B VCC
CI_SLOT
1 5 1 5
CAM_CD1_N AR905 33
B IN_A R913 CI_DATA[4] EB_DATA[4]
2 2
47 CI_DATA[5] EB_DATA[5]
GND Y GND OUT_Y
3 4 3 4
CI_DATA[0-7]
CI POWER ENABLE CONTROL EB_DATA[0-7]
IC901
+5V_NORMAL
AP2151WG-7 +5V_CI_ON
IN OUT
5 1
C905 CI_SLOT
0.1uF C906
50V GND
2 1uF
CI_SLOT R923
25V
CI_SLOT 10K
R922
100 EN FLG CI_SLOT
PCM_5V_CTL 4 3
R921
10K
CI_SLOT

THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. PCMCI 9
+12V
+3.5V_ST ’15 UHD 13V ONLY POWER PANEL_POWER TYP 6000mA

Power_DET
+12V
PANEL_VCC R2327
100K +3.5V_ST
R2306 L2311 +12V
1
10K UBW2012-121F R2332

RESET_IC_KEC(MULTI)
R2324
1/16W
ADUC 20S 02 010L
RL_ON R2301 C2327 C2330 C2331 10K
IC2306
15K
10uF 0.1uF 0.01uF AOS_PANEL_POWER_FET OPT
1%
IC2309
25V 50V KIC7529M2
2
AO4447A
10K L2302 25V
Q2300 UBW2012-121F OPT R2330
ICVS0505201FR
12P_POWER_WAFER
3
S_1
1 8
D_4 POWER_DET
MMBT3906(NXP) VCC OUT 100
Multi_Innochips
OPT 3 2
+12V
OPT S_2 D_3
R2329 C2367 C2315 2 7
VA2301-*1
P2301 10uF 1uF C2333 1
VA2302
10K S_3 D_2
R2325
1/16W
SMAW200-H12S5K(BK)(LTR) C2304 C2347 3 6
C2345 UF77:12V R2359 R2360 0.1uF GND
5.6K
C2335 25V 25V C2369
20V
0.1uF 10uF 2K 2K C2370 25V
10uF 0.1uF G D_1
10uF
1%
Default_Amotech 4 5
0.1uF
OPT
VA2301 10V 50V 50V 25V UF68/64:13V OPT OPT 25V 25V C2334
5.6V OPT 0.1uF
AMOTECH CO., LTD. R2331
R2361 16V
100 0 1.8K
1 2 PWM_DIM2 RL_ON
R2341 C ROHM_PANEL_POWER_FET
ADUC 20S 02 010L
IC2309-*1
3 4 EPI R2362 R2328 RRH140P03TB
+24V_AMP
UF77:24V_AMP Default_Amotech 0 10K B Q2321
L2313 5 6 PANEL_CTL 2N3904S S_1 D_4
VA2303 R2363
UBW2012-121F UF68/64:13V_AMP
1 8
R2312 not to RESET at 8kV ESD
5.6V 4.7K 0 C2371 KEC_PANEL_CTL_TR S_2 D_3
RESET_IC_DIODES(MULTI)
7 8 AMOTECH CO., LTD. OPT 10uF E 2 7 IC2306-*1
OPT C APX803E29
C2348 10V S_3
3 6
D_2
0.1uF 9 10 B Q2321-*1 VCC RESET

G D_1 3 2
VA2305
50V 100 MMBT3904(NXP) 4 5
11 12
20V
PWM_DIM NXP_PANEL_CTL_TR 1
R2309 E
OPT
13 14 EPI GND
R2311
Default_Amotech Default_Amotech 4.7K
VA2300 15 16 VA2304 OPT 13V-->3.53V
5.6V 5.6V R2310
AMOTECH CO., LTD. AMOTECH CO., LTD. 33
17 OPT
+3.3V_NORMAL C2302 PWM_TOUT
0.1uF 16P_POWER_WAFER
ICVS0505201FR
ICVS0505201FR
50V P2302 R2340

Multi_Innochips
Multi_Innochips
SMAW200-H16S5K(BK)(LTR) 33
VA2304-*1
Vx1
VA2300-*1
PWM_TIN
R2300
ICVS0505201FR
1K
Multi_Innochips
INV_CTL
VA2303-*1
R2304
100
+12V
DDR +1.5V +1.5V_DDR

+5V_Normal & +5V_USB with OCP
POWER_ON/OFF1
+3.3V - eMMC L2309
PZ1608U121-2R0TF
POWER_ON/OFF2_3
+12V
TI_TPS54327_1.5V_DDR_DCDC
+3.3V_NORMAL IC2303-*1 L2308
R2338
+3.3V_NORMAL 3.3V_EMMC +1.8V DVDD18_EMMC TPS54327DDAR [EP]GND
10K
50V
C2340
10uF
C2322 C2324 ROHM_BD9D321_1.5V_DDR_DCDC
25V
EN VIN 0.0068uF
3.3V_LED
10uF
1 8 C2337
0.1uF 10uF
THERMAL
C2346
25V VFB VBST
LD2300
25V
9
2 7
IC2303
L2304 L2305 R2326 VREG5 SW
BD9D321EFJ [EP]
[EP]GND
3 6
PZ1608U121-2R0TF PZ1608U121-2R0TF 10K
PGND_2
PGND_1
PGOOD
VIN_2
VIN_1
SS GND
4 5
ESD_DCDC R2334
OPT
V7V
3.3V_LED
100K
R2315
0.1uF EN VIN C2320

3.3K
C2308 C2307 1 8 100pF OPT +5V_NORMAL

C2309 C2312 C2336 50V
0.1uF 0.1uF C2341 L2310
THERMAL
22uF 22uF 0.1uF
24
23
22
21
20
19
16V 16V C2349 0.047uF 4.7uH
10V 10V 25V 25V
R2320 R2321 FB BOOT EN BST
9
2 7 C2326
R2318 4700pF 1 DCDC_Diode
18
4.7K 50V THERMAL ZD2303
R1 18K
1%
4.7K
1%
L2312 +3.3V_NORMAL COMP 25 LX_2 R2337 C2343 C2344
2.2uH 2 17 18K
VREG SW 82pF 22uF
3 6 OPT SS LX_1 1% 50V 16V
C2325 R2333 3 16
100pF PS064T-2R2MS OPT 0 IC2302 R1
1.5V_DCDC_TI 50V DCDC_Diode ROSC FB
SS GND R2317 4 15
C2332-*1
3300pF R2322
4
3A 5 C2338
22uF
C2339
22uF
10V
ZD2302
2.5V
4.7K
EN_SW2
5
TPS65282REGR
14
SW_IN_2 R2
50V 22K
C2328 C2332
10V
USB_CTL3
EN_SW1
6
4A 13
SW_IN_1
R2339
3.3K
1% 1uF 2200pF 1%
+1.8V - LM15U, eMMC
10
11
12
10V 50V
9
+3.3V_NORMAL C2342
1.5V_DCDC_ROHM +5V_USB_3 10uF
Switching freq: 700K R2 10V
FAULT2
FAULT1
SW_OUT2
RLIM
AGND
SW_OUT1
& Vx1 pull-up
Vout=0.765*(1+R1/R2)=1.554V R2335
10K OPT
R2336
15K
+1.8V 5%
+3.3V_NORMAL
+3.5V_ST
/USB_OCD3
+3.5V_ST
IC2301
AZ1117EH-ADJTRG1
IC2304 Vout=0.8*(1+R1/R2)
0.1uF
IN OUT
TPS563200
DCDC_Diode
C2323
16V
ADJ/GND
ZD2304
1%
1/16W
75
2.5V
R2307
GND VBST
+12V 1 6
ESD_DCDC
C2310 C2311 L2307 0.1uF
10uF 10uF DCDC_Diode 2.2uH C2350
SW EN R1
1%
1/16W
33
ZD2301 2 5
R2308
10V 10V
PS064T-2R2MS
VIN
3A VFB
1% 1%
1/16W 1/16W
3 4
R2
BLM18PG121SN1D
L2303
150K 33K
R2319 R2323
C2321
LM15 Power SEQUENCE
1/16W
R2316
R2313
C2316 C2318 C2319

22uF
10K
51K
10uF 0.1uF 22uF

1%
25V 25V 10V 10V

50V
10pF
C2329
POWER_ON/OFF1(5V)
Vout=0.765*(1+R1/R2)
+12V
+3.3V_NORMAL +3.3V_NORMAL
POWER_ON/OFF2_1(3.3V)
L2300
POWER_ON/OFF2_1
PZ1608U121-2R0TF
TI_TPS54327_1.5V_DDR_DCDC
IC2300-*1
TPS54327DDAR [EP]GND
C2300 C2301 ROHM_BD9D321_1.5V_DDR_DCDC EN VIN
10uF 0.1uF 1 8
THERMAL
25V 25V
IC2300 VFB VBST POWER_ON/OFF2_4(1.1V)
9
2 7
R2314
BD9D321EFJ [EP] VREG5
3 6
SW
10K
SS GND
4 5
ESD_DCDC
C2372 EN VIN
1 8
0.1uF
16V
THERMAL
0.1uF
R2302 R2303 FB BOOT C2313
9
2 7
R1 18K
1%
1K L2306
1% VREG SW 2.2uH
3 6
C2303
3.3V_DCDC_TI 100pF PS064T-2R2MS DCDC_Diode
50V
SS GND ZD2300
C2306-*1
3300pF
50V
R2305
4
3A 5 C2314
22uF
10V
C2317
22uF
10V
5.6K
C2305 C2306
1% 1uF 2200pF
10V 50V
3.3V_DCDC_ROHM
Switching freq: 700K R2
Vout=0.765*(1+R1/R2)=3.36V

FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS LM14A(UF68/UF64) 2015-01-23
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. LM14A_PWR_1_13V_only 23
MAX 3A
LM14A CPU +1.1V_VDDC_CPU LM14A CORE
+12V
L2502
PZ1608U121-2R0TF
+1.1V_VDDC
Placed on SMD-TOP +12V
DCDC_DIODE_0DTKE00018A(KEC)
UF64/68 UF64/68 UF77 UF77
C2510-*1 C2512-*1 C2510 C2512 C2513
10uF 10uF 10uF 0.1uF
10uF 16V 16V 16V R1 IC2502
IC2501 L2501
25V BD86106EFJ
R2521
25V OPT C2514 L2500
0DTKE00018A
TPS54427DDA 2uH
5.6K
[EP]GND EAN62653301
100pF [EP]
10K PZ1608U121-2R0TF
ZD2501
1%
50V R2524 EN
1 8
VIN 16V PGND SW_2
0.1uF 1 8
THERMAL
C2517
THERMAL
DCDC_DIODE_0DTKE00018A(KEC)
POWER_ON/OFF2_4 VFB VBST Placed on SMD-TOP
9
2 7 L2503 VIN SW_1

OPT OPT OPT
9
2 7
2.2uH R2510
VREG5 SW OPT C2504 C2505 C2506 C2507 C2508 C2509 15K R1
R2 3 6
C2500 C2501 C2502
AGND
3 6
EN
0.0068uF 10uF 10uF 100uF 10uF 10uF 1%
PS064T-2R2MS R2500 50V
R2522
SS GND 10uF 10uF 0.1uF 6.8K 10V 10V 10V 10V C2511
4
4A
5 FB
4
6A 5
COMP
47pF
11K
R2519-*1 25V 25V 25V 50V

1%
C2518 C2519
0DTKE00018A
27K 22uF
22uF
ZD2500
10V 10V
R2523
CPU_VID_LM14_A0
1/16W
10K
POWER_ON/OFF2_4
1%
1%
R2-1.13V
R2511
1/16W
R2501
CPU_VID_LM14_A1
R2515
R2519
1/16W
56K
C2503 10K
1%
LM14A_A0_ONLY
22K
75K
0.1uF
1/16W
R2504
1%
1%
KEC_CPU_CORE_VID_FET(MAIN)
KEC_CPU_CORE_VID_FET(MAIN)
DCDC_DIODE_0DR050008AA(SEMTECH) 16V 15K
R2512
1/16W
0DR050008AA
6.2K
+3.3V_NORMAL +3.3V_NORMAL C2515 C2516 1%
ZD2501-*1 R2
KEC_CPU_CORE_VID_FET
R2516
1%
R2520
1uF 2200pF
1.6K
75K
10V 50V
1%
1%
LM14A_A0_ONLY
1/16W
+3.3V_NORMAL R2505
56K
R2513 D R2517 D 1%
2N7002KA
2N7002KA
10K 10K LM14A_A0_ONLY

R2502 D
R2514 R2518
2N7002KA
Q2502
Q2503
G G 10K DCDC_DIODE_0DR050008AA(SEMTECH)
CPU_VID0 CPU_VID1 0DR050008AA
S S R2503
Q2500
0 5% 0 5% G ZD2500-*1
CORE_VID0
D D 0 5% S
Q2502-*1 Q2503-*1 LM14A_A0_ONLY
G G
2N7002K 2N7002K
S S LM14_A1
DIODEDS_CPU_CORE_VID_FET(SUB) DIODEDS_CPU_CORE_VID_FET(SUB) R2-1 R2-2 LM14_A0 LM14_A1 LM14_A0
V_out V_out V_out V_out
Delete this part when LM14A0 used all.
Boot High High 1.06 1.163
Boot 0.98 1.15
Kernel High Low 1.01 1.013 D
Kernel Q2500-*1
0.98 0.98 G
Kernel Low Low 0.96 0.969 2N7002K
S
DIODEDS_CPU_CORE_VID_FET
LM14A1 CORE_VID1 NOT USE.
Vout=0.765*(1+R1/R2) Vout=0.8*(1+R1/R2) CORE_VID1

THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. LM15U_PWR_2_ALL 25
Renesas MICOM
For Debug EPSON_MICOM_CRYSTAL(MAIN)

C3002-*1
+3.5V_ST EAW30067102 18pF
X3000-*1
50V
EPSON_MICOM_CRYSTAL(MAIN)
32.768KHz C3003-*1
EPSON_MICOM_CRYSTAL(MAIN) 15pF
50V
MICOM_DEBUG
DAISHINKU_MICOM_CRYSTAL(SUB)
R3016 1K
R3014 10K
MICOM_DEBUG Don’t remove R3016,

P3000
12507WS-04L
not making float P40 50V 50V
12pF 12pF
C3002 C3003 LOGO_LIGHT
MICOM_DEBUG
1
LOGO_LIGHT
MICOM_RESET
2
MICOM_DEBUG EAW58239602
X3000
WIFI_EN
3
4
MICOM_RESET 32.768KHz +3.5V_ST
5
HDMI_WAUP:HDMI_INIT R3028
4.7M
MHL_DET_LM15 OPT
0 R3037
MHL_DET_LM15
10K
POWER_DET_1
R3032
10K
R3030
MICOM_RESET_SW
GND
MICOM_RESET_22OHM
SW3000
JTP-1127WEM
2 1
33
R3031
1%
1/16W
270K
OPT
C3004
P124/XT2/EXCLKS
0.47uF
0.1uF
+3.5V_ST 4 3
16V
R3029
P122/X2/EXCLK
P41/TI07/TO07
C3001
P137/INTP0
P120/ANI19
P40/TOOL0
P123/XT1
C3000
P121/X1
0.1uF MICOM_RESET_33OHM
R3029-*1 33
RESET
+3.5V_ST
REGC
VDD
VSS
R3021-*1
LCD
OLED
R3021
LM14A Power SEQUENCE
1K
10K 5%
1/16W
48
47
46
45
44
43
42
41
40
39
38
37
POWER_ON/OFF1(5V) P60/SCLA0 1 36 P140/PCLBUZ0/INTP6 RL_ON
SCART_MUTE
I2C_SCL_MICOM
P61/SDAA0 2 35 P00/TI00/TXD1 POWER_ON/OFF2_4
I2C_SDA_MICOM SCART_MUTE
P62 3 34 P01/TO00/RXD1
3D&L_DIM_EN POWER_ON/OFF2_4
P63 4 33 P130
PANEL_CTL
P31/TI03/TO03/INTP4 IC3000 P20/ANI0/AVREFP
POWER_ON/OFF2_1
WOL/WIFI_POWER_ON 5 32 KEY2
IR
P75/KR5/INTP9/SCK01/SCL01 6 R5F100GEAFB#30 31 P21/ANI1/AVREFM
KEY1
R3000
100 P74/KR4/INTP8/SI01/SDA01 7 30 P22/ANI2
HDMI_CEC_MICOM
POWER_ON/OFF2_4(1.1V) P73/KR3/SO01 8 29 P23/ANI3

MODEL1_OPT_3
POWER_ON/OFF2_3
P72/KR2/SO21 9 28 P24/ANI4
MODEL1_OPT_0
P71/KR1/SI21/SDA21 10 27 P25/ANI5
SOC_RESET EYE_SDA SIDE_HP_MUTE
P70/KR0/SCK21/SCL21 11 26 P26/ANI6
EYE_SCL MHL_EN MHL_EN
P30/INTP3/RTC1HZ/SCK11/SCL11 12 25 P27/ANI7
MODEL1_OPT_1
13
14
15
16
17
18
19
20
21
22
23
24
AR3000
3.3K
EYE_Q
+3.5V_ST
P50/INTP1/SI11/SDA11
P51/INTP2/SO11
P17/TI02/TO02
P16/TI01/TO01/INTP5
P15/PCLBUZ1/SCK20/SCL20
P14/RXD2/SI20/SDA20
P13/TXD2/SO20
P12/SO00/TXD0/TOOLTXD
P11/SI00/RXD0/TOOLRXD/SDA00
P10/SCK00/SCL00
P146
P147/ANI18
MICOM MODEL OPTION
+3.5V_ST
MICOM MODEL OPTION

10K
10K
10K
MICOM_OLED
MICOM_LOGO
MICOM_H15
R3006
R3008
R3013
0 1
MODEL_OPT_0 NON LOGO LOGO
MODEL1_OPT_0 MODEL_OPT_1 LCD OLED

MODEL1_OPT_1
MODEL1_OPT_3
MODEL_OPT_3 LM15U/LM14A H15
SOC_RX
POWER_DET
EDID_WP
URSA_RESET_MICOM
URSA_RESET_MICOM
AMP_MUTE
WOL_WAKE_UP
INV_CTL
MICOM_LM15U/LM14A
POWER_ON/OFF1
WOL_CTL
SOC_TX
LED_R
MICOM_NON_LOGO
10K
10K
10K
MICOM_LCD
R3009
R3012
R3004
For CEC
R3015
10K +3.5V_ST
CEC_DIODE(SUB)
MICOM_LM14A
EAH62792701
LED_R
SOC_RESET
D3000-*1
30V
BAT54_TSC
R3033 R3034
27K 120K
LM14A : Active high reset
G
D3000
BAT54_SUZHO
CEC_REMOTE HDMI_CEC_MICOM
S
CEC_DIODE(MAIN)
EAH61433701 Q3001
RUE003N02
G
ROHM_CEC_FET(MAIN) Q3001-*1
EBK61731401 SI1012CR-T1-GE3
D
VISHAY_CEC_FET(SUB)
EBK61731301
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. MICOM 30
5V_HDMI_1 5V_DET_HDMI_1
R3324
OPT 1.8K
ESD_HDMI
R3335
R3302
VA3308
OPT
3.3K
1K R3336 R3305
33
4.7K
OPT C OPT
SHIELD R3300 Q3300 R3303
100K 2N3904S B 1K
HDMI_HPD_1
20
OPT
ESD_HDMI
VA3312
E
19
HPD
18 AR3301
+5V_POWER 33
17 1/16W
DDC/CEC_GND
DDC_SDA_1
16
SDA DDC_SCL_1
15
SCL VA3311
14 ESD_HDMI
NC VA3309
CEC_REMOTE ESD_HDMI
13
CEC
AR3306
12 5.1
CLK- 1/16W
11
CLK_SHIELD CK-_HDMI1
10 CK+_HDMI1
CLK+
D0-_HDMI1
9 D0+_HDMI1
DATA0-
8
DATA0_SHIELD
7
DATA0+
AR3307
6 5.1
DATA1- 1/16W
5
DATA1_SHIELD D1-_HDMI1
4 D1+_HDMI1
DATA1+
D2-_HDMI1
5V_HDMI_3 3
DATA2- D2+_HDMI1
5V_DET_HDMI_3
R3308 2
DATA2_SHIELD
1.8K
ESD_HDMI
1
R3310
VA3301
R3304 DATA2+
3.3K
1K R3307
4.7K
C NON_HDMI_EXT_EDID
Q3301 R3306 YKF45-7058V
2N3904S B 1K
SHIELD HDMI_HPD_3 JK3302
R3301
100K R3339
20 E
4.7K AR3300
KEC_HDMI_HPD_TR 33
HDMI_EXT_EDID
ESD_HDMI
C
VA3303
1/16W
19
HPD Q3301-*1 B DDC_SDA_3
18 MMBT3904(NXP)
+5V_POWER NXP_HDMI_HPD_TR DDC_SCL_3
E
17
DDC/CEC_GND VA3305 VA3307
ESD_HDMI
HDMI1(6G)
16 ESD_HDMI
SDA
15
SCL
HDMI_ARC
14
NC
CEC_REMOTE
13
CEC AR3304
12
CLK-
5.1
1/16W EDID external EEPROM +5V_NORMAL
11 CK-_HDMI3 E
CLK_SHIELD 5V_HDMI_3
10 CK+_HDMI3
MMBT3904(NXP)
CLK+ D0-_HDMI3 Q3302-*1 B
A1
A2
9 D0+_HDMI3
DATA0- C MMBD6100
8 NXP_HDMI_EXT_EDID_TR D3309
DATA0_SHIELD
C
7
DATA0+ E
6 KEC_HDMI_EXT_EDID_TR
ATMEL_HDMI_EXT_EDID
DATA1- 2N3904S EDID_WP
ROHM_HDMI_EXT_EDID
5 IC3301 Q3302 B IC3301-*1
DATA1_SHIELD
BR24G02FJ-3GTE2 C AT24C02C-SSHM-T
4 AR3303
DATA1+ 5.1
3 1/16W
DATA2- A0 VCC HDMI_EXT_EDID A0 VCC
D1-_HDMI3 1 8 1 8
2
DATA2_SHIELD D1+_HDMI3
R3323 AR3305
1 D2-_HDMI3 A1 WP 4.7K A1 WP
DATA2+ 2 7 1/16W 2 7
D2+_HDMI3 47K
A2 SCL A2 SCL
YKF45-7058V 3 6 3 6
JK3300
GND SDA GND SDA
4 5 4 5
R3321
22
DDC_SCL_3
HDMI_EXT_EDID
R3322
22
DDC_SDA_3
HDMI_EXT_EDID
DDC pull-up
5V_HDMI_1 +5V_NORMAL
A1
A2
MMBD6100
D3305
C
AR3302
1/16W
47K
DDC_SDA_1
DDC_SCL_1

FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS LM14A(UF64/68)_5.1ohm 2015-01-14
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. HDMI 33
AV/COMPONENT REAR
Place JACK Side
1608 sizs For EMI/ESD
3.3 R3832 @netLa

AV1_CVBS_IN
R3808
C3822 C3805 C3806
1/4W
VA3806 150pF 27pF 100pF C3811 COMP1_Y
75
1%
5.5V OPT 50V 50V 47pF R3831
50V 0
OPT OPT
HON_HAI_OPTIC_JACK(SUB)
JK3800-*1
2F01TC1-CLM97-4F
GND +3.3V_NORMAL
1
Fiber Optic
PPJ245-31 PPJ245N2-01
VCC 2
SPDIF OUT JK3802-*1
[RD2]E-LUG
JK3802
[ GN/YL]E-LUG
6A
R3807
10K
VIN 6E R3803
3
1K 1608 sizs For EMI/ESD
+3.3V_NORMAL 4 5E [RD2]O-SPRING
5A
[GN/YL]O-SPRING AV1_CVBS_DET
SOLTEAM_OPTIC_JACK(MAIN) 1608 sizs For EMI/ESD
SHIELD
4A
[GN/YL]CONTACT
4E [RD2]CONTACT VA3803
GND 3.3 R3811
5.6V COMP1_Pb
1
Fiber Optic
JST1223-001
5B [BL]O-SPRING SIGN380006 +3.3V_NORMAL

5D [WH]O-SPRING
JK3800
C3810 C3812
VCC 27pF 27pF R3816 C3815
2
7C [RD1]E-LUG-S VA3804 75 10pF

4C [RD1]CONTACT 50V 50V
5.5V R3810 OPT 50V
OPT 1%
VINPUT 5C 10K
SPDIF_OUT [RD1]O-SPRING
3
5C [RD1]O-SPRING
4
C3800 VA3807 C3818 VA3805 R3802

4C
18pF 5.5V 0.1uF [RD1]E-LUG-S [RD1]CONTACT 1K
FIX_POLE
7C 5.5V
50V 16V COMP1_DET 1608 sizs For EMI/ESD
OPT 5D 3.3 R3809
[BL]O-SPRING [WH]O-SPRING COMP1_Pr
5B VA3800
5.6V
4E C3809 C3813 C3814
[GN/YL]CONTACT [RD2]CONTACT R3800 R3817
4A VA3801 27pF 27pF 75 10pF
5.6V 470K 50V 50V 50V
5E FOR EMI 1%
[GN/YL]O-SPRING [RD2]O-SPRING OPT OPT
5A
6E [RD2]E-LUG
6A [GN/YL]E-LUG
1608 sizs For EMI
R3812
R3805 10K
Non_shield_Component jack shield_Component jack COMP1/AV1/DVI_L_IN
VA3802 R3801
0
5.6V 470K
C3801 C3803 C3807 R3814
560pF 100pF 1000pF 12K
50V
50V 50V OPT
OPT OPT
1608 sizs For EMI

R3813
R3806 10K
COMP1/AV1/DVI_R_IN
0
C3802 C3804 C3808 R3815

560pF 100pF 1000pF 12K
50V
50V 50V OPT
OPT OPT

FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS LM15U 2015-01-23
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. JACK_COMMON_H_W/O HP 38
P4100
SMAW200-H14S5K +3.3V_NORMAL
C4110
C4108 22uF
0.1uF
1 1 2 2 10V
WIFI_BT_COMBO
R4111 R4113
M_RFModule_RESET
100 3 3 4 4 0
WIFI_DM
VA4102
C4103
RCLAMP0502BA
0.1uF ESD_WIFI_COMBO
R4114
WIFI_BT_COMBO 5 5 6 6 0
Place Near Wafer WIFI_DP
EYE_SENSOR
D4100
AR4100 C4107 C4109
100
1/16W
7 7 8 8 5pF
50V
5pF
50V
EYE_SDA
VA4100 WIFI_DMDP_ESD
ESD_WIFI_COMBO
+3.5V_ST
EYE_SCL
9 9 10 10
R4110 VA4103 VA4105 +3.5V_ST
10K ESD_WIFI_COMBO ESD_WIFI_COMBO
5%
11 11 12 12 +3.5V_ST
IR R4116
VA4101 VA4104 R4115
C4105 ESD_WIFI_COMBO C4106 UF68 10K 10K
100pF ESD_WIFI_COMBO
1000pF R4117 1%
50V 13 13 14 14 50V 100
1%
OPT KEY1
LED_R
R4109 R4118
1.8K 100
LED_R KEY2
OPT
15
R4100
C4102
UF64
0.1uF
15
16V C4111 C4112
0.1uF 0.1uF
0
OPT OPT
IR
+3.5V_ST
IC4101
AO-R123C7G-LG
R4103
1/16W
R4105
1/10W
IR_PROTO
IR_PROTO
IR_PROTO
330
5%
47
5%
GND
G
VS
V
OUT
O

FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS UF64/6800 2015-01-21
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. IR/KEY 41
+5V_USB_3
USB1
MAX 1.0A
JK4302
3AU04S-305-ZC-(LG)
USB DOWN STREAM
R4300
2.2
2
USB_DM3
R4301
2.2
3
USB_DP3
DF3D6.8MS
C4322 C4323
D4301
D4302
4
10uF 22uF
10V
10V
5
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. USB 43
+3.3V_NORMAL
EU
CLOSE TO JUNCTION
R4601
10K
EU
R4602
100
SC_DET
EU
VA4601 C4604
5.6V 0.1uF
EU
SC_CVBS_IN
Full Scart 1% EU
1/4W
75
R4607
VA4609
EU
C4605
5.5V 47pF
EU 50V
EU
EU R4615
AV_DET 0
22
COM_GND VA4610 DTV/MNT_V_OUT
21 5.5V
SYNC_IN EU EU OPT OPT
75 C4606 C4607
20
SYNC_OUT R4604 68pF 68pF
19 50V 50V
SYNC_GND2
18
SYNC_GND1 EU
R4614
17 22
RGB_IO
16 SC_FB
R_OUT VA4602
15 5.6V
RGB_GND EU
EU
14 R4610
R_GND 75
13
D2B_OUT
12 VA4603 SC_R
G_OUT
5.5V EU
11 EU
D2B_IN R4608
75
10
G_GND
9
ID
8 VA4604 SC_G
B_OUT
5.5V EU
7
AUDIO_L_IN R4611
EU 75
6
B_GND
5
AUDIO_GND
4
SC_B
ICVL0518100Y500FR_
AUDIO_L_OUT VA4605
EU_ESD_SC_ID(SUB)
3 5.5V EU
AUDIO_R_IN EU R4609
2 75
AUDIO_R_OUT
1
VA4600-*1
VA4600 EU
20V R4616
EU_ESD_SC_ID(MAIN) SIGN460005 15K
PSC008-01 SC_ID
JK4600 EU
R4605
10K R4617
SC_L_IN 3.9K
VA4611 R4612
5.6V EU 12K
R4600 EU
EU 470K
EU
R4606
10K
SC_R_IN
VA4606
5.6V
R4613
EU EU 12K
R4603 EU
470K
EU
BLM18PG121SN1D
L4600
DTV/MNT_L_OUT
VA4607 EU EU
5.6V C4600 C4602
EU 1000pF 4700pF
50V
EU
BLM18PG121SN1D
L4601
DTV/MNT_R_OUT
VA4608
EU EU
5.6V C4603
EU C4601 4700pF
1000pF
50V

BSD-15Y-LM14A-046_00-HD
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. SCART JACK_H 46
SCART_JACK_H
Ethernet Block
C5000 C5001
0.1uF 0.01uF
16V 50V
T-36TM9G_30150_02HF EAG35781015 EAG35781010
NEW_LAN_JACK_3SIM NEW_LAN_JACK_ESD(1st) OLD_LAN_JACK
JK5000-*2 JK5000-*1 JK5000
36TM9G-30150-02HF BS-RV30330 RJ45VT-01SN002
FREEPORT RESOURCES ENTERPRISES CORP. U.D. ELECTRONIC CORP XML KOREA CO., LTD
1 1 1
1 1 1
EPHY_TDP
2 2 2
2 2 2
3 3 3
3 3 3
EPHY_TDN
4 4 4
4 4 4
EPHY_RDP
5 5 5
5 5 5
6 6 6
6 6 6
EPHY_RDN
7 7 7
7 7 7
VA5000 VA5001 VA5002 VA5003
8 8 8 5.5V 5.5V 5.5V 5.5V
8 8 8
LAN_ESD(MAIN)
9 9 9
LAN_ESD(MAIN) LAN_ESD(MAIN) LAN_ESD(MAIN)

SHIELD 9 9
ICVS0518150FR_
ICVS0518150FR_
ICVS0518150FR_
ICVS0518150FR_
LAN_ESD(SUB)
LAN_ESD(SUB)
LAN_ESD(SUB)
LAN_ESD(SUB)
VA5000-*1
VA5001-*1
VA5002-*1
VA5003-*1

THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. LAN_H 50
AUDIO AMP(NTP7515) SM-6045-100
GET_AMP_COIL
L5802-*1
10.0uH
+3.3V_NORMAL
R5805
AMP_RESET_N 100
TAIYO_AMP_COIL
NRS6045T100MMGK
1/16W
R5806 C5806 L5802
L5801 10.0uH
4.7K 1000pF
PZ1608U121-2R0TF 50V SPK_L+
50V
AUD_SCK
+24V_AMP
22000pF
R5807
1/10W
C5807
3.3
R5811
5%
C5821
C5805 0.1uF 4.7K
50V
[EP]GND
0.1uF C5813
C5809 390pF
VDD_IO
GND_IO
PGND1A
PVDD1A
PVDD1B
16V 10uF 50V
CLK_I
RESET
BST1A
OUT1A
35V
C5819
0.47uF
50V
AD
C5814
390pF
50V C5822 R5812
R5808
1/10W
TAIYO_AMP_COIL
0.1uF SPEAKER_L
3.3
50V 4.7K
5%
NRS6045T100MMGK
40
39
38
37
36
35
34
33
32
31
L5805
NC_1 1 30 OUT1B 10.0uH
SPK_L-
VDD_PLL 2 29 PGND1B C5811

THERMAL 22000pF SM-6045-100
NC_2 3 41 28 BST1B 50V GET_AMP_COIL
C5800
1uF L5805-*1
10V GND 4 27 VDR1 10.0uH
NC_3 5 IC5800 26 NC_5

C5801
1uF
10V
DVDD 6 NTP7515 25 AGND
AUD_LRCH
SDATA 7 24 VDR2
WCK 0x54 BST2A
C5817
1uF
C5818
1uF SM-6045-100
AUD_LRCK 8 23 10V 10V GET_AMP_COIL
NC_4 9 22 PGND2A C5812 L5803-*1

10.0uH
22000pF
AR5800
100 SDA 10 21 OUT2A 50V
I2C_SDA4
11
12
13
14
15
16
17
18
19
I2C_SCL4
20
TAIYO_AMP_COIL
NRS6045T100MMGK
C5802 C5804
33pF 33pF L5803
50V 50V 10.0uH
SCL
FAULT
MONITOR_0
MONITOR_1
MONITOR_2
BST2B
PGND2B
OUT2B
PVDD2B
PVDD2A
SPK_R+
+3.3V_NORMAL
R5809
1/10W
+24V_AMP
3.3
5%
C5823 R5813
R5801 0.1uF 4.7K
10K C5815 C5820 50V
390pF 0.47uF
R5804 C5810 50V
C5816
50V
SPEAKER_R
C 100 10uF 390pF
35V 50V TAIYO_AMP_COIL
R5800 C5803 C5824 R5814
R5810
1/10W
B Q5800 C5808 NRS6045T100MMGK
AMP_MUTE 1000pF 0.1uF 4.7K
3.3
2N3904S 50V
5%
10K 22000pF L5804 50V
E KEC_AMP_MUTE_TR
WOOFER_MUTE
50V 10.0uH
I2S_AMP
SPK_R-
SM-6045-100
GET_AMP_COIL
L5804-*1
C 10.0uH 4P Box type
B WAFER-ANGLE
Q5800-*1
MMBT3904(NXP)
NXP_AMP_MUTE_TR
E
TP5801 WOOFER_MUTE SPK_L+
4
TP5802 I2S_AMP
SPK_L-
3
SPK_R+
2
SPK_R-
1
P5800

NTP_AMP 58
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
+12V
EU
L6000
IC6000
AUD_OUT >> EU/CHINA_HOTEL_OPT AZ4580MTR-E1 EU
C6004
EU EU 0.1uF
C6000 50V
DTV/MNT_L_OUT
R6000 OUT1
1 8 VCC
EU
[SCART AUDIO MUTE]
10uF 2.2K EU
OPT OPT EU R6011 C6008
C6002 R6002 R6004 33K IN1- 7 OUT2 SIGN600007 2.2K
2 DTV/MNT_R_OUT DTV/MNT_L_OUT
6800pF 470K
C6003 33pF 10uF
EU
IN1+ EU 6 IN2- R6008
EU
33K
OPT
R6010
OPT
3 C6007
470K EU
C6005 33pF 6800pF C
R6013
VEE 5 IN2+ Q6000 B 1K
4 EU
MMBT3904(NXP) EU_SCART_MUTE_ISAHAYA
SCART_AMP_L_FB
E EU Q6002
RT1P141C-T112
R6007
1/16W
E
100K
EU SCART_AMP_R_FB SCART_MUTE
OPT
5%
EU
R6012
1/16W
R6006 R6020
100K
5.6K 0
OPT
B
SCART_Lout
5%
EU
1/16W EU
R6009
1/16W
R6021 R6016
100K
330pF 220K 5% DTV/MNT_R_OUT PDTA114ET

OPT
C6009 R6005 0 5.6K

5%
Q6002-*1
EU EU SCART_Rout
E
EU
R6015
1/16W
1/16W
100K
5% EU EU C
OPT
R6017 C6012 R6014

5%
220K 330pF Q6001 B 1K
B
MMBT3904(NXP)
EU_SCART_MUTE_NXP
CLOSE TO MSTAR E EU
CLOSE TO MSTAR
Near Place Scart AMP

EU
R6019
0 EU
SCART_AMP_R_FB
1/16W 10K
5% R6003
EU
R6018
0 EU
SCART_AMP_L_FB
1/16W 10K
5% R6001

FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. SCART AMP
1. should be guarded by ground
2. No via on both of them
3. Signal Width >= 12mils
close to Tuner Signal to Signal Width = 12mils
+3.3V_TUNER Ground Width >= 24mils
L6500
PZ1608U121-2R0TF close to TUNER
1 +3.3V_LNA_TU C6501
0.1uF TU_K/M/W_TW/BR/CO R6507 1K
TU_K/M/W_TW/BR/CO TU_K/M/W_TW/BR/CO
2 RF_SWITCH_CTL_TU RF_SWITCH_CTL
C6504 R6503
0.1uF 10K
TU_ALL_IntDemod
R6506 1K
3 IF_AGC_TU IF_AGC
C6502 close to Tuner TU_ALL_IntDemod
0.1uF TU_ALL TU_W_BR/TW
16V
AR6500 AR6500-*1
33 200
1/16W 1/16W
+3.3V_NORMAL
PZ1608U121-2R0TF
4 I2C_SCL5_TU I2C_SCL5
C6505
I2C_SDA5 +3.3V_TUNER
47pF
L6504
5 50V
I2C_SDA5_TU +3.3V_TUNER 1608 perallel
C6503 OPT
because of derating
47pF
50V
OPT TU_ALL_2178B TU_SIF TU_ALL_2178B
TU_ALL_2178B
R6513 0 R6516 R6517
R6504 200 200
10
6 IF_P_TU C6519 IF_P C6517 C6508
TU_ALL_IntDemod 33pF 22uF 0.1uF
L6502 TU_CVBS
should be guarded by ground,Match GND VIA R6505 OPT 10V 16V
10 TU_H/M_EU/BR/TW/CO/KR E
7 IF_N_TU C6520 IF_N
TU_ALL_IntDemod 33pF KEC_TU_ALL_2178B_TR
TU_H/M_EU/BR/TW/CO/KR B Q6502
2N3906S-RTK
8 TU_SIF_TU C
E
TU_M_KR/EU // W_ALL
9 TU_CVBS_TU NXP_TU_ALL_2178B_TR
L6501 +3.3V_TUNER B Q6502-*1
Global F/E Option Name PZ1608U121-2R0TF MMBT3906(NXP)
1. TU C
10
2. Tuner Name = TDJ’H’,TDj’M’... C6510
3. Country Name = KR,US,BR,EU ... 0.1uF
11 +3.3V_TU
TU_M_KR/EU // W_ALL
T2 : Max 1.7A
Example of Option name else : Max 0.7A
12 FE_DEMOD1_TS_ERROR close to Tuner
TU_ALL_IntDemod = All Tuner type for Internal demod
TU_M/W = apply TDSM&TDSW Type Tuner FE_DEMOD1_TS_ERROR
TU_M/W_1.2V
14 FE_DEMOD1_TS_CLK FE_DEMOD1_TS_CLK TU_M/W Demod_Core
R6519-*1 R6521-*1
IC6500
TU_M/W_1.1V TU_M/W_1.1V
14’ Tuner Type for Global
15 AP2132MP-2.5TRG1
[EP]
TDJ’H’-G101D : Half NIM for EU,AJJA FE_DEMOD1_TS_SYNC FE_DEMOD1_TS_SYNC
18K
10K
R6521
TDJ’H’-H101F : Half NIM for US, KR
TDJ’K’-T101F : Half NIM for TW FE_DEMOD1_TS_VAL FE_DEMOD1_TS_VAL TU_M/W PG GND R2
16 1 8
TDJ’M’-C301D,F : FULL NIM for China
THERMAL
+3.3V_NORMAL C6516
10.5K
R6519
TU_M/W_1.2V
TDJ’M’-B101F : Brazil NIM with Isolater Type 0.1uF
16K
EN ADJ
9
17 FE_DEMOD1_TS_DATA[0] 2 7
TDJ’M’-K101F : colombia NIM R1
R6500
TU_M/W
10K
TDJ’M’-G101D,G105D,G151D : EU Combo&Full NIM VIN VOUT
18 FE_DEMOD1_TS_DATA[1] FE_DEMOD1_TS_DATA[0-7]
TDJ’M’-H101F,H151F : Korea PIP tuner 3 6
TDJ’W’-A151D : AJJA T2 PIP @netLa
19 FE_DEMOD1_TS_DATA[2] @netLa +5V_NORMAL
VCTRL
4 2A 5
NC
@netLa ESD_TU_M/W TU_M/W

ZD6501 TU_M/W
FE_DEMOD1_TS_DATA[3]
20 FE_DEMOD1_TS_DATA[3] 5V C6500 C6518
0.1uF 10uF
@netLa 16V 10V
FE_DEMOD1_TS_DATA[4] TU_M/W
21 @netLa
C6515
@netLa 1uF
FE_DEMOD1_TS_DATA[5] @netLa 25V
22
23 FE_DEMOD1_TS_DATA[6]
Vout=0.6*(1+R1/R2)
24 FE_DEMOD1_TS_DATA[7]
TU_M/W
R6501
TU_M/W 100 /TU_RESET1 +3.3V_TUNER
25 /TU_RESET1_TU
C6507
TU_M/W
L6503
16V PZ1608U121-2R0TF
0.1uF
26 +3.3V_DEMOD_TU
C6511 TU_M/W TU_M/W
0.1uF AR6501
27 TU_M/W 33
I2C_SCL2_TU
L6505 1/16W I2C_SCL2
Demod_Core
PZ1608U121-2R0TF OPT
C6513
28 D_Demod_Core TU_M/W 18pF
C6506 50V
0.1uF OPT
29 LNB_TX LNB_TX I2C_SDA2
C6512
18pF
50V
30 I2C_SDA2_TU
31 LNB_OUT LNB_OUT

THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. TU_CIRCUIT 65
TU_H_US
TU_H_BR TU_H_T2_KR TU_M_EU
TU6705 TU6701 TU6704 TU6702

TDJH-H301F TDJK-T301F TDJM-H401F TDJM-G301D
+3.3V +3.3V +3.3V +3.3V

1 1 1 1 +3.3V_LNA_TU 1
NC_1 NC NC_1 NC_1
2 2 2 2 RF_SWITCH_CTL_TU 2
DIF_AGC DIF_AGC NC_2 AIF_AGC
3 3 3 3 IF_AGC_TU 3
SCL_RF SCL_RF SCL_RF SCL_RF
4 4 4 4 I2C_SCL5_TU 4
SDA_RF SDA_RF SDA_RF SDA_RF
5 5 5 5 I2C_SDA5_TU 5
DIF[P] DIF[P] NC_3 AIF[P]
6 6 6 6 IF_P_TU 6
DIF[N] DIF[N] NC_4 AIF[N]
7 7 7 7 IF_N_TU 7
SIF SIF SIF SIF
8 8 8 8 TU_SIF_TU 8
TDJH-G301D CVBS CVBS CVBS CVBS
9 9 9 9 TU_CVBS_TU 9
TU6705-*1
TDJH-G301D NC_5 NC_2
10 10 10
A1 B1 A1 B1 +3.3V_RF +3.3V_RF
1
+3.3V A1 B1 A1 B1 11 11 +3.3V_TU 11
2
NC_1 47 47 ERROR ERROR
12 12 FE_DEMOD1_TS_ERROR 12
TU_GND_B
TU_GND_B
IF_AGC
TU_GND_A
TU_GND_A
3
GND_1 GND_1
4
SCL_RF SHIELD SHIELD 13 13 13
5
SDA_RF MCLK MCLK
14 14 FE_DEMOD1_TS_CLK 14
IF[P]
6
SYNC SYNC
7
IF[N] 15 15 FE_DEMOD1_TS_SYNC
8
SIF VAILD VALID
16 16 FE_DEMOD1_TS_VAL 16
CVBS
9
D0 D0
17 17 FE_DEMOD1_TS_DATA[0] 17
A1
A1 B1
B1 D1 D1
47 TU_H_T2_CO
TU6704-*1 D2 D2
SHIELD
TDJM-K301F 19 19 FE_DEMOD1_TS_DATA[2] 19
+3.3V
1
NC_1
D3 D3
2
NC_2
3
SCL_RF
4
SDA_RF
D4 D4
5
NC_3
6
EMS Page --> Sheet : 135 7
8
NC_4
SIF
CVBS
22
D5
22
D5
9
NC_5
10
+3.3V_RF
D6 D6
11
ERROR
12
GND_1
13
MCLK
D7 D7
14
SYNC
15
VAILD
16
D0
RESET_DEMOD RESET_DEMOD
17
D1
25 25 /TU_RESET1_TU 25
18
D2
19
D3
+3.3V_DEMOD +3.3V_DEMOD
20
D4
26 26 +3.3V_DEMOD_TU 26
21
D5
22
D6
SCL_DEMOD SCL_DEMOD
23
D7
27 27 I2C_SCL2_TU 27
24
RESET_DEMOD
25
+3.3V_DEMOD
+1.2V_DEMOD +1.2V_DEMOD
26
SCL_DEMOD
28 28 D_Demod_Core
27
+1.2V_DEMOD
28
NC_6
NC_6 NC_3
29
SDA_DEMOD
29 29 LNB_TX
30
A1 B1
SDA_DEMOD SDA_DEMOD
A1
47
B1
30 30 I2C_SDA2_TU 30
SHIELD
LNB
31 LNB_OUT 31
A1 B1 GND
A1 B1 32 32
47
33
TU_GND_B
TU_GND_A
A1 B1
SHIELD A1 B1 34
47
35
TU_GND_B
TU_GND_A
SHIELD 36
40
41
42
TDJM-C401D TDJM-B301F
TU_M_AJ TU_M_CN
TU6702-*4 TU6702-*3 TU6702-*2 TU6702-*1
TDJM-C401D TDJM-B301F TDJM-G305D TDJM-C301D 43
+3.3V +3.3V +3.3V B1[+3.3V]
1 1 1 1
2
NC_1
2
NC_1
2
NC_1
2
RF_SW_CTL 44
NC_2 NC_2 NC_2 NC_1
3 3 3 3
SCL_RF SCL_RF SCL_RF SCL_RF
4 4 4 4
5
SDA_RF
5
SDA_RF
5
SDA_RF
5
SDA_RF 45
NC_3 NC_3 NC_3 NC_2
6 6 6 6
NC_4 NC_4 NC_4 NC_3
7 7 7 7
8
SIF
8
SIF
8
SIF
8
SIF 46
CVBS CVBS CVBS CVBS
9 9 9 9
NC_5 NC_5 NC_5 NC_4
10 10 10 10
11
+3.3V_RF
11
+3.3V_RF
11
+3.3V_RF
11
NC_5 47
ERROR ERROR ERROR ERROR
12 12 12 12
GND_1 GND_1 GND_1 GND_1
13 13 13 13
14
MCLK
14
MCLK
14
MCLK
14
MCLK 48
SYNC SYNC SYNC SYNC
15 15 15 15
VAILD VAILD VAILD VAILD
16 16 16 16
17
D0
17
D0
17
D0
17
D0 49
D1 D1 D1 D1
18 18 18 18
D2 D2 D2 D2
19 19 19 19
D3 D3 D3 D3
20 20 20 20
D4 D4 D4 D4
21 21 21 21
D5 D5 D5 D5
22 22 22 22
D6 D6 D6 D6
23 23 23 23
D7 D7 D7 D7
24 24 24 24
RESET_DEMOD RESET_DEMOD RESET_DEMOD RESET_DEMOD
25 25 25 25
+3.3V_DEMOD +3.3V_DEMOD +3.3V_DEMOD B2[+3.3V]
26 26 26 26
SCL_DEMOD SCL_DEMOD SCL_DEMOD SCL_DEMOD
27 27 27 27
+1.2V_DEMOD +1.2V_DEMOD +1.2V_DEMOD B3[+1.1V]
28 28 28 28
NC_6 NC_6 NC_6 NC_6
29 29 29 29
SDA_DEMOD SDA_DEMOD SDA_DEMOD SDA_DEMOD
30 30 30 30
A1 B1 A1 B1 A1 B1 A1 B1
A1 B1 A1 B1 A1 B1 A1 B1
47 47 47 47
SHIELD SHIELD SHIELD SHIELD

THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. TU_SYMBOL_H 67
DVB-S2 LNB Part
(Option:LNB) Input trace widths should be sized to conduct at least 3A
Ouput trace widths should be sized to conduct at least 2A

3A
+12V_M
LNB_SUZHOU
D6902-*2
SS2040LL-LG
2A
D6904-*1
40V Max 1.3A
LNB
40V LPH6050T-150M-R
LNB_TSC LNB_SX34 L6900
D6902-*1 D6902 3.5A
SS23L LNB_ONSEMI D6904
30V 40V 15uH

30V
LNB_SMAB34
C6909
10uF
C6903 C6905 C6906 C6907 25V
0.01uF 10uF 10uF 10uF LNB
40V 50V 25V 25V 25V
LNB LNB LNB LNB
C6908 0.1uF
SS2040LL-LG
close to Boost pin(#1)
LNB_Allegro
D6901-*2 A_GND A_GND
LNB_SUZHOU
30V
[EP]GND
close to VIN pin(#15) Caution!! need isolated GND
BOOST
GNDLX
R6904
NC_3
NC_2
SS23L C6910 0
A_GND
LX
D6901-*1 0.1uF
LNB_TSC 50V
20
19
18
17
16
LNB
D6901 VCP 1 15 VIN
MBR230LSFT1G THERMAL A_GND
LNB 2 14 GND
LNB_OUT 21
30V D6903 LNB
NC_1 3 13 VREG
LNB_ONSEMI C6904 C6902 LNB_SMAB34
0.1uF 0.22uF IC6900 R6903
C6900 C6901 R6900 40V TDI ISET 39K
2.2K LNB 50V 25V A8303SESTR-T
4 12
0.1uF 33pF LNB
D6900 1W D6903-*1 LNB 1/16W
LNB LNB TDO 5 11 TCAP C6912
LNB LNB LNB_SX34 1%
10
40V LNB
6
0.1uF
IRQ
SCL
SDA
ADD
TONECTRL
LNB_DMBT
0.22uF
BOOST
[EP]
NC_4
NC_3
PGND
Close to Tuner
LX
+3.3V_NORMAL
Surge protectioin
20
19
18
17
16
NC_1 1 15 VIN
THERMAL
LNB
LNB 2 14 GND
21
NC_2 3 13 VREG
R6907
IC6900-*1
3.3K
C6911
OPT
TDI 4 DT1803 12 ISET
TDO 5 11 TCAP
10
6
9
IRQ
SCL
SDA
ADD
TONECTRL
NXP_Obsolete
LNB
R6906
Q6901
+12V +12V_M
PMV48XP
0
D
C6913 R6911 C6914
0.1uF 36K 0.1uF
G
50V 50V
AOS
Q6901-*1
LNB_NON_Tx
R6909
R6901 33
R6902 33
AO3435
LNB_Tx
150K
LNB
0
R6905
LNB
D
0
R6908
+3.3V_NORMAL
C
R6910
10K
G
B Q6902
OPT MMBT3904(NXP)
1/16W
5% C6915 E
I2C_SCL2
I2C_SDA2
LNB_TX
4.7uF
10V

SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. LM14A(UF64/68)
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS 2015-01-21
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR 69
LNB
CLK8
R7728
VCOMLFB
0
VCOMFB1 CLK7
R7727 CLK6
VCOMRFB 0 CLK5
CLK4
CLK3
CLK2
R7730 CLK1
VCOMLFB VCOMFB2
0
VGH_EVEN
<T-CON POWER BLOCK>
R7717
1/16W
VGH_ODD
C7744
R7716
1/16W
C7741
GIP_RST
C7734 C7737 C7748 C7750 C7753
C7729 R7729 560pF C7755
560pF 560pF 560pF 560pF 560pF 560pF
4.7uF 560pF
CLK6
10
5%
CLK8
CLK5
CLK7
CLK4
CLK1
CLK2
CLK3
VST
10
5%
VCOMRFB 0 50V 50V 50V 50V 50V 50V
50V 50V 50V
RE
R7702
47 R7704
EO_A EO VDD RE RE
0
OPT Improve the Vertical dot noise
VGH
FROM SOC C7703
VGH
R7709
OPT
R7706
OPT
15pF R7766 R7705

0
0
10K 0
50V
OPT
[EP]AGND
R7710
OPT
R7707
OPT
R7711
VGH_E/O
0
0
30K
1/16W
RESET
R7703
CLK1
CLK2
CLK3
CLK4
CLK5
CLK6
CLK7
CLK8
EVEN
OPT L7702
ODD
VST
47
22.0uH
RE
GST_A GST
R7718 OPT 40V
VDD
FROM SOC C7704 0
56
55
54
53
52
51
50
49
48
47
46
45
44
43
15pF R7767 PM_VCC R7719 OPT SX34
5%
1/10W
9.1K
10K C7738 C7740 C7742 C7746 D7701 C7756
R7731
50V GCLK VGH 0
GCLK 1 42 4.7uF 4.7uF 4.7uF 4.7uF 10uF
MCLK 2 THERMAL 41 VGH_SW 50V 50V 50V 50V 25V
R7713 MCLK 57
GST 3 40 HGND
10K GST R7721
R7700 E/O 4 39 VCOMFB2
1/16W EO PMIC(SW5094A)_SILICONWORKS 0 VCOMFB2
47 L/S_GND VCOM2
MCLK_A MCLK 5 38 VCOM2
L/S_VGL 6 37 VCOM1
C7701 LS_VGL IC7700 R7720 VCOM1
FROM SOC VGL 7 36 VCOM
15pF R7768 VGL_FB SW5094A 0 VCOMFB1
10K C7713 C7719 SWN 8 35 GMA_N6
50V SWN GMA18
10uF 10uF CTRLN GMA_N5
16V 9 34 GMA14
25V CTRLN
RST[T-CON] 10 33 GMA_N4
R7701 PM_VCC GMA10
47 OUT1 11 32 GMA_P3
GCLK_A GCLK GMA9
SWB1 12 31 GMA_P2
L7700 GMA5
R7715
R7714
FROM SOC C7702 AGND 13 30 GMA_P1
R7769 GMA1
15pF 10K PVINB1 COMP
47
14 29
47
50V R7708 C7708 C7709 C7711 C7712 C7715 C7718 22.0uH COMP
2K 10uF 10uF 10uF 10uF 10uF 1uF D7700 C7730 C7732 C7733 C7735 C7736 C7739
15
16
17
18
19
20
21
22
23
24
25
26
27
28
1/16W 10V 10V 10V 10V 10V 10V SX34 C7725 150pF 150pF 150pF 150pF 150pF 150pF
40V 4700pF 50V 50V 50V 50V 50V 50V
PVINB3
SWB3
OUT3
PGND3
SCL
SDA
VL
TCOMP
PGND
SW
SWI
SWO
SWG
SS
PMIC_SW 50V
C7726 VL
2200pF
50V
PANEL_VCC
VGH_E/O
RESET
[EP]
CLK1
CLK2
CLK3
CLK4
CLK5
CLK6
CLK7
CLK8
EVEN
SS
ODD
VST
RE
COMP
R7722
EPI 8-Lane (RIGHT)
56
55
54
53
52
51
50
49
48
47
46
45
44
43
GCLK VGH
47K C7752
R7726
1/16W
1 42
AR7700 MCLK 2 THERMAL 41 VGH_SW
C7720 C7721 R7764 57 0.1uF
56K
GST 3 40 PGND_4
C7723
1%
10uF 10uF I2C_SCL6 0 E/O 4
PMIC(RT6923)_RICHTEK
39 VCOMFB2
16V
25V 25V 4.7uF I2C_SDA6 SS LS_VGL
AGND 5
6
38
37
VCOM2
VCOM1
C7731
TCOMP C7747
IC7700-*1 68pF
VGL 7 36 VCOMFB1
50V RT6923 1uF
VL
SWN 8 35 GMA_N6
R7723 C7745 50V
TCOMP
SWG
1/16W CTRLN 9 34 GMA_N5
25V TH7700
33 RST GMA_N4 120K 1000pF OPT
10 33
47k-ohm
OUT1
SWB1
11 32 GMA_P3
GMA_P2
1% 50V
12 31
PGND_1 13 30 GMA_P1
C7727 C7728 PVINB1 14 29 COMP
10uF 10uF
15
16
17
18
19
20
21
22
23
24
25
26
27
28
HVDD 25V 25V
PVINB3
SWB3
OUT3
PGND_2
SCL
SDA
VL
TCOMP
PGND_3
SW
SWI
SWO
SWG
SS
L7701
10.0uH
OPT R7712 C7722 C7724
SWI
SWO
2.7K
SWG
10uF 10uF
PM_VCC
R7735
300 16V 16V
PM_VCC
SWO
1/16W
5% R7737 R7740 R7742 R7745
0 0 0 0 INSTEAD OF AMCC0208
1/16W 1/16W 1/16W 1/16W
R7743
0
Q7701
MMBT3904(NXP)
VGL_FB
40V
OPT
R7741 100K
E
SX34
D7703
1/16W 5% D7705 PMIC_RT
PMIC_SW
1N4148W 40V
CTRLN PMIC_RT C7778
OPT
180K
SX34
B
G
R7739
C7769 560pF D7704
100V R7763 50V
4700pF
0 50V R7761
S
SWN
D
VGL1 0 VDD
C7775 C7777 1/16W SSM3J332R
D7702
SX34
D7706
40V
C7794 R7759
5%
1/16W
9.1K
1uF 1uF 1.5K C7798 C7799 Q7700 C7781 C7783 C7785 C7788 C7790 C7793 C7796
1N4148W
R7760
25V 25V 0.1uF 1/16W 10uF 10uF
100V 5% 10uF 10uF 10uF 10uF 10uF 1uF 0.1uF
25V 16V 16V R1 25V 25V 25V 25V 25V 25V 25V
EPI_43inch
EPI_49inch
EPI_55inch
3.9K
1%
1/16W
R7747
1%
1/16W
15K
R7733
1%
1/16W
22K
R7762
R7734 C7774
3.3 1uF
25V
1/16W Vout=1.25x(1+R1/R2)
50V
820pF
C7764
50V
820pF
C7766
<VGL Block> 5% C7768

10uF
R7748
1/16W
25V
COMP2
120K
SWI
SS
FB
1%
Ref R7747 R7733 R7762
R2
FB
1%
1/16W
24K
R7749
1%
1/16W
22K
R7744
INCH 43 49 55
TAIYO_PMIC_COIL
[EP]GND
VALUE 3.9K 15K 22K
COMP2
L7703-*1
NC_4
GND
EN2
FB2
SWO
10.0uH
C7779
10uF
25V
R1
1%
1/16W
150K
24
23
22
21
20
19
R7736 C7787 GET_PMIC_COIL
R7757
PANEL_VCC
0.033uF
10 0.22uF L7703 NC_1 IN2
16V 1 18
C7780
10.0uH THERMAL
1/16W SW2_1 NC_3
50V
5% IC7703 2 25 17
TPS63700DRCR [EP]
C7776 OPT SW2_2 SS2
4700pF C7758 C7759 3 IC7702 16
Vout=1.213x(-R2/R1) 10uF 10uF
C7760 C7761
PGND2 PVCC FB_Vcore
C7770 50V 10uF 10uF RT5043A
COMP VREF 25V 25V 4 15 PVCC
0.1uF 1 10 25V 25V
C7792
SS FB RT SW
10pF
16V TP7701 Location No.

THERMAL
FB_Vcore
50V
5 14
PGND1 EN
11
GND FB
2 9 6 13
D7700 X 0
10
11
12
7
9
R7755
1/16W
VIN
3 8
OUT R2
SW_1
SW_2
BOOT
NC_2
VIN_1
VIN_2
1M
1%
C7778 560pF X
1/16W
100K
R7758
PM_VCC
R7756
1/16W
EN PS_GND
240K
4 7
R7739 X 180Kohm
1%
IN SW
5 6
C7767 R7734 3.3ohm 3.3ohm
10uF
10V
40V
VGL2
R7769 4.7nF X
SX34 C7795 C7797
10.0uH
L7705
D7707 10uF 10uF

16V 16V
COMP2
PVCC
EPI_49/55inch C7749
1/16W
100K
R7732
R7754 1uF OPT
VGL1 LS_VGL 25V
0 C7754
R7753 1uF
VGL2 C7751 25V
0 330pF
EPI_43inch
50V
<2VGL_2 Block>

THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. T-Con 77
EPI 2 EPI 1
+1.8V VDD
+1.8V VDD
C7900 C7901 C7902

1uF 1uF 0.1uF C7904 C7905 C7907
16V 25V 25V 1uF 1uF 0.1uF
16V 25V 25V
60P_EPI_Wafer
60P_EPI_Wafer P7901
P7900 FF05T-60P
FF05T-60P
1
1
GMA1 2
2 CLK1
GMA4 3
3 CLK2
GMA5 4 Vcore
4 CLK3
GMA7 5
5 CLK4
GMA9 6
6 CLK5
GMA10 7
R7900
7 CLK6
GMA12 8
8 CLK7
OPT
GMA14 9
CLK8
0
9 GMA15 10
10 VGH
GMA18 11 JP7957
11 JP7955
VGH_ODD
12
12 JP7954
VGH_EVEN
13
13 LS_VGL
14
14 TXVBY1_7P
GIP_RST
15
15 TXVBY1_7N JP7953
VST
16
16 JP7956 VGL1
17
17 TXVBY1_6P
VCOM2
18
18 TXVBY1_6N
VCOMRFB
19
19 VCOM1
20
20 TXVBY1_5P
21 JP7952
21 TXVBY1_5N
22
22 23
C7906 1uF
23 TXVBY1_4P
24
24 TXVBY1_4N
25
25
HVDD
26 JP7950 JP7951
26 TXVBY1_3P
27
27 TXVBY1_3N
28
28
Vcore
29
29 TXVBY1_2P LOCKOUT6
30
30 TXVBY1_2N
31 HTPDAn_OSD
31 32 LOCKAn_OSD
32
LOCKOUT6 33
33
Vcore 34 HTPDAn_Video
34 35
C7903 1uF LOCKAn_Video
35 36
36
HVDD 37 TXOSD_3P
37 38 TXOSD_3N
+3.3V_NORMAL
38 39 +1.8V
39 40 TXOSD_2P
40 41 TXOSD_2N
41 42
LOCKOUT12_3.3VPullup
LOCKOUT12_3.3VPullup R7905
42 R7904
VCOM1 43 TXOSD_1P
10K
10K
43 LOCKOUT12
VCOMLFB 44 TXOSD_1N LOCKOUT12_3.3VPullup
R7906 C
44
VCOM2 45 LOCKOUT12_3.3VPullup 10K B Q7902
45 R7902 2N3904S C
VGL1 46 TXOSD_0P
10K
E
KEC_LOCKOUT12
B Q7902-*2
46
VST 47 TXOSD_0N
LOCKOUT12_3.3VPullup C
MMBT3904(NXP)
47 R7903 NXP_LOCKOUT12
GIP_RST 48 100 B Q7901
E
48 2N3904S
LS_VGL 49
LOCKOUT12-I LOCKOUT12-I
KEC_LOCKOUT12 C
49 E
VGH_EVEN 50 B Q7901-*1
50 MMBT3904(NXP)
VGH_ODD 51
TP7900 GMA1 OPT
51 VGH 52 R7907 E NXP_LOCKOUT12
52 TP7901 GMA4 0
CLK8 53
TP7902 GMA5
53
CLK7 54
TP7903 GMA7
54
CLK6 55
TP7904 GMA9
55
CLK5 56
TP7905 GMA10
56
CLK4 57
TP7906 GMA12
57
CLK3 58
TP7907 GMA14
58
CLK2 59
TP7908 GMA15
59
CLK1 60
TP7909 GMA18
60
61
61

THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. EPI WAFER 79
eMMC I/F
DVDD18_EMMC 3.3v power delete, 131120
R8116
R8117
1/16W
10K
AR8104
1/16W
10K
AR8103
10K
10K
SAMSUNG ELECTRONIC CO.,LTD
EAN63829501
IC8100 IC8100-*1 IC8100-*2
IC8100-*3
THGBMBG5D1KBAIL THGBMBG6D1KBAIL H26M41103HPR
EMMC_DATA[0-7] KLM4G1FEPD-B031
AR8100
EMMC_DATA[0] 0
1/16W
EMMC_DATA[1] A3 C8 A3 C8 A3 C7
EMMC_DATA[2] DAT0 NC_23 DAT6 DAT0 NC_23 DAT0 NC_22 A3 C7
A4 C9 A4 C9 A4 C8 DAT0 NC_22
DAT1 NC_24 DAT1 NC_24 DAT1 NC_23 A4 C8
EMMC_DATA[3] A5 C10 A5 C10 A5 C9 DAT1 NC_23
DAT2 NC_25 DAT2 NC_25 DAT2 NC_24 A5 C9
EMMC_DATA[4] B2 C11 B2 C11 B2 C10 DAT2 NC_24
DAT3 NC_26 DAT3 NC_26 DAT3 NC_25 B2 C10
B5 C14 B5 C14 B5 C13 DAT5 NC_27
EMMC_DATA[7] DAT6 NC_29 DAT6 NC_29 DAT6 NC_28 B5 C13
B6 D1 B6 D1 B6 C14 DAT6 NC_28
DAT7 NC_30 DAT5 DAT7 NC_30 DAT7 NC_29 B6 C14
D2 D2 D1 DAT7 NC_29
0 R8104 NC_31 NC_31 NC_30 D1
D3 D3 D2 NC_30
0 R8105 NC_32 NC_32 NC_31 D2
M6 D4 M6 D4 M6 D3 NC_31
0 R8106 CLK NC_33 CLK NC_33 CLK NC_32 M6 D3
M5 D12 M5 D12 M5 D4 CLK NC_32
0 R8107 CMD NC_34 CMD NC_34 CMD NC_33 M5 D4
D13 D13 D12 CMD NC_33
eMMC V5.0 GND NC_35 NC_35 NC_34 D12
D14 D14 D13 NC_34
NC_36 NC_36 NC_35 D13
A6 E1 A6 E1 A7 D14 NC_35
VSS_1 NC_37 VSS_1 NC_37 RFU_1 NC_36 A7 D14
A7 E2 A7 E2 E5 E1 RFU_1 NC_36
RFU_2 NC_38 RFU_2 NC_38 RFU_2 NC_37 E5 E1
C5 E3 C5 E3 G3 E2 RFU_2 NC_37
NC_21 NC_39 NC_21 NC_39 RFU_3 NC_38 G3 E2
AR8102 E5 E12 E5 E12 K6 E3 RFU_3 NC_38
RFU_4 NC_40 RFU_4 NC_40 RFU_4 NC_39 K6 E3
0 1/16W E8 E13 E8 E13 K7 E12 RFU_4 NC_39
RFU_5 NC_41 RFU_5 NC_41 RFU_5 NC_40 K7 E12
E9 E14 E9 E14 E8 E13 RFU_5 NC_40
EMMC_CLK VSF_1 NC_42 VSF_1 NC_42 VSF_1 NC_41 E8 E13
E10 F1 E10 F1 E9 E14 RFU_6 NC_41
DAT7
EMMC_CMD VSF_2 NC_43 VSF_2 NC_43 VSF_2 NC_42 E9 E14
F10 F2 F10 F2 E10 F1 RFU_7 NC_42
EMMC_RST VSF_3 NC_44 VSF_3 NC_44 VSF_3 NC_43 E10 F1
G3 F3 G3 F3 F10 F2 RFU_8 NC_43
RFU_9 NC_45 RFU_9 NC_45 VSF_4 NC_44 F10 F2
G10 F12 G10 F12 G10 F3 RFU_9 NC_44
RFU_10 NC_46 RFU_10 NC_46 VSF_5 NC_45 G10 F3
H5 F13 H5 F13 K10 F12 RFU_10 NC_45
DS NC_47 DS NC_47 VSF_6 NC_46 K10 F12
J5 F14 J5 F14 P10 F13 RFU_11 NC_46
C8107 VSS_5 NC_48 VSS_5 NC_48 VSF_7 NC_47 P10 F13
OPT 10pF K6 G1 K6 G1 H5 F14 RFU_13 NC_47
RFU_13 NC_49 RFU_13 NC_49 DS NC_48 H5 F14
50V K7 G2 K7 G2 G1 DS NC_48
RFU_14 NC_50 RFU_14 NC_50 NC_49 G1
EMMC_STRB K10 G12 K10 G12 G2 NC_49
RFU_15 NC_51 RFU_15 NC_51 NC_50 G2
P7 G13 P7 G13 G12 NC_50
R8103
RFU_16 NC_52 RFU_16 NC_52 NC_51 G12
P10 G14 P10 G14 G13 NC_51
10K
RFU_17 NC_53 RFU_17 NC_53 NC_52 G13
H1 H1 G14 NC_52
NC_54 EMMC_STRB NC_54 NC_53 G14
H2 H2 H1 NC_53
NC_55 NC_55 NC_54 H1
K5 H3 K5 H3 K5 H2 NC_54
RSTN NC_56 RSTN NC_56 RSTN NC_55 K5 H2
H12 H12 H3 RSTN NC_55
C8100 DVDD18_EMMC H3
EMMC5.0_4G_TOSHIBA
NC_57 NC_57 NC_56
H13 H13 H12
EMMC5.0_8G_TOSHIBA
OPT 0.1uF NC_56
NC_58 NC_58 NC_57 H12
16V C6 H14 C6 H14 C6 H13 NC_57
VCCQ_1 NC_59 VCCQ_1 NC_59 VCCQ_1 NC_58 C6 H13
3.3V_EMMC M4 J1 M4 J1 M4 H14 VDD_1 NC_58
VCCQ_2 NC_60 VCCQ_2 NC_60 VCCQ_2 NC_59 M4 H14
N4 J2 N4 J2 N4 J1 VDD_2 NC_59
EMMC5.0_8G_HYNIX
VCCQ_3 NC_61 VCCQ_3 NC_61 VCCQ_3 NC_60 N4 J1
P3 J3 P3 J3 P3 J2 VDD_3 NC_60
VCCQ_4 NC_62 VCCQ_4 NC_62 VCCQ_4 NC_61 P3 J2
Bottom P5 J12 P5 J12 P5 J3 VDD_4 NC_61
VCCQ_5 NC_63 VCCQ_5 NC_63 VCCQ_5 NC_62 P5 J3
DAT3
DAT4
DAT5
DAT6
EMMC_CLK_BALL
EMMC_CMD_BALL
EMMC_RESET_BALL
OPT OPT J13 J13 J12 VDD_5 NC_62

C8108 C8109 C8105 C8106 NC_64 NC_64 NC_63 J12
0.1uF 2.2uF 0.1uF 2.2uF J14 EMMC_RESET_BALL J14 J13 NC_63
EMMC5.0_4G_SAMSUNG
NC_65 NC_65 NC_64 J13
16V 10V 16V 10V E6 K1 E6 K1 E6 J14 NC_64
VCC_1 NC_66 VCC_1 NC_66 VCC_1 NC_65 E6 J14
F5 K2 F5 K2 F5 K1 VDDF_1 NC_65
VCC_2 NC_67 VCC_2 NC_67 VCC_2 NC_66 F5 K1
J10 K3 J10 K3 J10 K2 VDDF_2 NC_66
VCC_3 NC_68 VCC_3 NC_68 VCC_3 NC_67 J10 K2
K9 K12 K9 K12 K9 K3 VDDF_3 NC_67
VCC_4 NC_69 VCC_4 NC_69 VCC_4 NC_68 K9 K3
K13 K13 K12 VDDF_4 NC_68
NC_70 NC_70 NC_69 K12
EMMC_VDDI K14 K14 K13 NC_69
Bottom pattern 0.2mm NC_71 NC_71 NC_70 K13
C2 L1 C2 L1 C2 K14 NC_70
VDDI NC_72 VDDI NC_72 VDDI NC_71 C2 K14
OPT L2 L2 L1 VDDI NC_71
C8101 C8104 NC_73 NC_73 NC_72 L1
1uF 2.2uF L3 L3 L2 NC_72
NC_74 NC_74 NC_73 L2
10V 10V E7 L12 E7 L12 C4 L3 NC_73
VSS_2 NC_75 VSS_2 NC_75 VSSQ_1 NC_74 C4 L3
G5 L13 G5 L13 N2 L12 VSS_1 NC_74
VSS_3 NC_76 VSS_3 NC_76 VSSQ_2 NC_75 N2 L12
H10 L14 H10 L14 N5 L13 VSS_2 NC_75
VSS_4 NC_77 VSS_4 NC_77 VSSQ_3 NC_76 N5 L13
K8 M1 K8 M1 P4 L14 VSS_3 NC_76
VSS_6 NC_78 VSS_6 NC_78 VSSQ_4 NC_77 P4 L14
C8102 C8103 C8111 C4 M2 C4 M2 P6 M1 VSS_4 NC_77
0.1uF 2.2uF 4.7uF VSSQ_1 NC_79 VSSQ_1 NC_79 VSSQ_5 NC_78 P6 M1
N2 M3 EMMC_CLK_BALL N2 M3 A6 M2 VSS_5 NC_78
16V 10V 10V VSSQ_2 NC_80 VSSQ_2 NC_80 VSS_1 NC_79 A6 M2
OPT N5 M7 N5 M7 E7 M3 VSS_6 NC_79
VSSQ_3 NC_81 VSSQ_3 NC_81 VSS_2 NC_80 E7 M3
P4 M8 P4 M8 G5 M7 VSS_7 NC_80
VSSQ_4 NC_82 VSSQ_4 NC_82 VSS_3 NC_81 G5 M7
P6 M9 P6 M9 H10 M8 VSS_8 NC_81
VSSQ_5 NC_83 VSSQ_5 NC_83 VSS_4 NC_82 H10 M8
M10 M10 J5 M9 VSS_9 NC_82
NC_84 NC_84 VSS_5 NC_83 J5 M9
M11 M11 K8 M10 VSS_10 NC_83
NC_85 NC_85 VSS_6 NC_84 K8 M10
M12 M12 M11 VSS_11 NC_84
NC_86 NC_86 NC_85 M11
A1 M13 A1 M13 M12 NC_85
DAT3 NC_1 NC_87 NC_1 NC_87 NC_86 M12
A2 M14 A2 M14 A1 M13 NC_86
DAT4 NC_2 NC_88 NC_2 NC_88 NC_1 NC_87 A1 M13
A8 N1 A8 N1 A2 M14 NC_1 NC_87
DAT7 NC_3 NC_89 NC_3 NC_89 NC_2 NC_88 A2 M14
A9 N3 EMMC_CMD_BALL A9 N3 A8 N1 NC_2 NC_88
NC_4 NC_90 NC_4 NC_90 NC_3 NC_89 A8 N1
A10 N6 A10 N6 A9 N3 NC_3 NC_89
NC_5 NC_91 NC_5 NC_91 NC_4 NC_90 A9 N3
A11 N7 A11 N7 A10 N6 NC_4 NC_90
NC_6 NC_92 NC_6 NC_92 NC_5 NC_91 A10 N6
A12 N8 A12 N8 A11 N7 NC_5 NC_91
NC_7 NC_93 NC_7 NC_93 NC_6 NC_92 A11 N7
A13 N9 A13 N9 A12 N8 NC_6 NC_92
NC_8 NC_94 NC_8 NC_94 NC_7 NC_93 A12 N8
A14 N10 A14 N10 A13 N9 NC_7 NC_93
NC_9 NC_95 NC_9 NC_95 NC_8 NC_94 A13 N9
B1 N11 B1 N11 A14 N10 NC_8 NC_94
NC_10 NC_96 NC_10 NC_96 NC_9 NC_95 A14 N10
B7 N12 B7 N12 B1 N11 NC_9 NC_95
NC_11 NC_97 NC_11 NC_97 NC_10 NC_96 B1 N11
B8 N13 B8 N13 B7 N12 NC_10 NC_96
NC_12 NC_98 NC_12 NC_98 NC_11 NC_97 B7 N12
B9 N14 B9 N14 B8 N13 NC_11 NC_97
DAT6 NC_13 NC_99 NC_13 NC_99 NC_12 NC_98 B8 N13
B10 P1 B10 P1 B9 N14 NC_12 NC_98
NC_14 NC_100 NC_14 NC_100 NC_13 NC_99 B9 N14
B11 P2 B11 P2 B10 P1 NC_13 NC_99
NC_15 NC_101 NC_15 NC_101 NC_14 NC_100 B10 P1
B12 P8 B12 P8 B11 P2 NC_14 NC_100
Don’t Connect Power At VDDI EMMC_VDDI DVDD18_EMMC B13
B14
NC_16
NC_17
NC_102
NC_103
P9
P11
B13
B14
NC_16
NC_17
NC_102
NC_103
P9
P11
B12
B13
NC_15
NC_16
NC_101
NC_102
P7
P8
B11
B12
NC_15
NC_16
NC_101
RFU_12
P2
P7
NC_18 NC_104 NC_18 NC_104 NC_17 NC_103 B13 P8
C1 P12 C1 P12 B14 P9 NC_17 NC_102
(Just Interal LDO Capacitor) DAT5
C3
NC_19
NC_20
NC_105
NC_106
P13 C3
NC_19
NC_20
NC_105
NC_106
P13 C1
NC_18
NC_19
NC_104
NC_105
P11
B14
C1
NC_18 NC_103
P9
P11
C7 P14 C7 P14 C3 P12 NC_19 NC_104
NC_22 NC_107 NC_22 NC_107 NC_20 NC_106 C3 P12
C5 P13 NC_20 NC_105
NC_21 NC_107 C5 P13
P14 NC_21 NC_106
NC_108 P14
NC_107

FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS LM14A
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. eMMC
[LM14A_ONLY]
CLIP Top Side for Covershield
M13500 M13502
EAG64250901 EAG64250901
CLIP 1 - PUSH TYPE
SMD Bottom Side for ESD
SMD_BOT_COMP2_10.5T
GASKET_8.0X6.0X10.5H GASKET_8.0X6.0X10.5H GASKET_8.0X6.0X10.5H GASKET_8.0X6.0X10.5H
M13501 OPT M13503 OPT M13505 M13507 OPT
MDS62110225 MDS62110225 MDS62110225 MDS62110225

THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. LM14A_ONLY 135
LM14A UF64/68 UF64/68 Error Pin TP - page 30.
TUNER EMS GND SEPERATION Only 13V DET Delete WOL

POWER_DET_1 WIFI_EN
TU_GND_B
TU_GND_A
WOL/WIFI_POWER_ON
WOL_WAKE_UP
TU_GND_A4_22nF WOL_CTL
TU_GND_B1_22nF
C6700 C6703
TU_GND_A2_1nF TU_GND_A3_0ohm 0.022uF 0.022uF
TU_GND_A6_3.3nF TU_GND_A1_0ohm C6706 TU_GND_B3_1nF TU_GND_B4_1nF
R6700 630V 630V TU_EU
C6710 R6701 C6707 C6708 C6709
3300pF 1000pF 0 TU_GND_B2_22ohm
0 TU_GND_A5_22ohm 1000pF 1000pF 3300pF
630V 630V R6703 R6704 630V 630V 630V
22 22
UF64/68 Error Pin TP - page 6.
TU_GND_B2_0ohm TU_GND_B3_22nF TU_GND_B4_22nF

TU_GND_A1_1nF TU_GND_A2_22nF
TU_GND_A3_22nF Delete USB1/2 Delete HDMI2
R6701-*1 C6706-*1 C6707-*1 C6708-*1
R6700-*1 TU_GND_A4_1nF 0 0.022uF 0.022uF
1000pF 0.022uF R6704-*1 SSUSB_TXP D2-_HDMI2
0.022uF C6700-*1 630V 630V
630V 630V 630V
1000pF
SSUSB_TXN
630V D1+_HDMI2
SSUSB_RXP
GND_A GND_B D0-_HDMI2
SSUSB_RXN
HDMI_HPD_2
USB_DM1
/MHL_OCP
TU_GND_A EU/CIS AJJA TW/COL CN/HK KR North.AM BR JP TU_GND_B EU/CIS AJJA TW/COL CN/HK KR North.AM BR JP USB_DP1
CK+_HDMI2
GND A_1 0 ohm 0 ohm X 0 ohm X 0 ohm USB_DP2
GND B_1 X X 22 nF X 22 nF X DDC_SCL_2
GND A_2 X X 22 nF 22 nF 1 nF
X USB_DM2
GND B_2
X X 22 ohm X 22 ohm X DDC_SDA_2
GND A_3 X 0 ohm X 0 ohm 22 nF 0 ohm
D0+_HDMI2
22 nF GND B_3 1 nF 1 nF 22 nF 1 nF 22 nF 1 nF
GND A_4 X X X 22 nF 1 nF
D2+_HDMI2
22 ohm 22 ohm GND B_4 1 nF 22 nF
GND A_5 X X 22 ohm X 1 nF 1 nF 22 nF 1 nF
D1-_HDMI2
CK-_HDMI2
SMD_BOT SMD_BOT_1_10.5T SMD_BOT_COMP_10.5T SMD_BOT
GASKET_8.0X6.0X10.5H GASKET_8.0X6.0X10.5H GASKET_8.0X6.0X10.5H GASKET_8.0X6.0X10.5H 5V_DET_HDMI_2
M13700 M13705 M13713 M13717 EU/CIS AJJA TW/COL CN/HK KR North.AM BR JP
MDS62110225 MDS62110225 SMD_BOT_TU
MDS62110225 MDS62110225
TU1 O
SMD_BOT SMD_BOT SMD_BOT
SMD_BOT_TU2
GASKET_8.0X6.0X10.5H GASKET_8.0X6.0X10.5H GASKET_8.0X6.0X10.5H
M13701 M13707 M13714
GASKET_8.0X6.0X10.5H
M13718 TU2 O UF64/68 Error Pin TP - page 1.
MDS62110225 MDS62110225 MDS62110225
MDS62110225
SMD_BOT SMD_BOT SMD_BOT

TU3
X Delete USB1 Delete JP Tuner
USB_CTL1 FE_DEMOD3_TS_CLK
M13702 M13708 M13715
MDS62110225 MDS62110225 MDS62110225

/USB_OCD1 FE_DEMOD3_TS_SYNC
SMD_BOT SMD_BOT SMD_BOT_TU1 FE_DEMOD3_TS_VAL

M13704 M13709 M13716
MDS62110225 FE_DEMOD3_TS_DATA
MDS62110225 MDS62110225
Delete EARPHONE AMP

SMD_BOT_HDMI2_10.5T SMD_BOT_HDMI1_10.5T SMD_BOT_2_10.5T SMD_BOT_LAN_10.5T SMD_BOT_USB_10.5T
HP_ROUT_MAIN
GASKET_8.0X6.0X10.5H GASKET_8.0X6.0X10.5H GASKET_8.0X6.0X10.5H GASKET_8.0X6.0X10.5H GASKET_8.0X6.0X10.5H
M13703 M13706 M13710 M13711 M13712
MDS62110225 MDS62110225 MDS62110225 MDS62110225 MDS62110225 HP_ROUT_MAIN
SIDE_HP_MUTE
SMD_BOT_HDMI2_8.5H SMD_BOT_HDMI1_8.5H SMD_BOT_2_8.5H SMD_BOT_LAN_8.5H SMD_BOT_USB_8.5H

GASKET_8.0X6.0X8.5H GASKET_8.0X6.0X8.5H GASKET_8.0X6.0X8.5H GASKET_8.0X6.0X8.5H GASKET_8.0X6.0X8.5H
M13703-*1 M13706-*1 M13710-*1 M13711-*1 M13712-*1
MDS62110216 MDS62110216 MDS62110216 MDS62110216 MDS62110216
SMD_BOT_USB_7.5H
GASKET_8.0X6.0X7.5H
M13712-*2
MDS62110215

FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS LM14A(UF64/68) 2015-01-12
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR Tuner_GND_for UF64 137
LD5ZR
(LM14A+URSA11)
SPI_CK_SOC COMPENSATION_DONE OLED
LM14A+URSA9
SPI_DI_SOC TXVBY1_0N
FAN_ON LM14A UF68/64
+3.3V_NORMAL SPI_DO_SOC FRC_FLASH_SEL_SOC TXVBY1_0P
CHIP CONFIG NVRAM +3.3V_NORMAL
/SPI_CS TXVBY1_1N /TU_RESET2
Rohm_NVRAM
IC101-*1
FRC_FLASH_WP GST_A LM14A UF74
BR24G256FJ-3
EAN62389502 TXVBY1_1P
ROHM Semiconductor KOREA CORPORATION
TXOSD_3P LOCKAn_OSD GCLK_A
4.7K
4.7K
4.7K
Atmel_NVRAM WOL_WAKE_UP_SOC
4.7K
A0 VCC
IC101 1 8
TXOSD_3N URSA9_CONNECT MCLK_A PMIC_RESET 5V_DET_HDMI_1

AT24C256C-SSHL-T C100 A1
2 7
WP
Data_Format_1
OPT
EO_A
OPT
EAN61133501
ATMEL CORPORATION
0.1uF A2
3 6
SCL
TXOSD_2P DATA_FORMAT_1_SOC LM14A_ONLY LOCKOUT12 /USB_OCD3
GND
4 5
SDA
TXOSD_2N Data_Format_0
R108
R110
R115
DATA_FORMAT_0_SOC USB_CTL3
R122
TXOSD_1P URSA_RESET_SoC
A0 VCC HTPDAn_OSD
1 8 L/D_VSYNC_SOC
TXOSD_1N
HTPDAn_Video IC100
Write Protection L/D_CLK_SOC
LED1 A1 WP
TXOSD_0P LGE5332(LM14A)
2 7
TXOSD_0N L/D_DI_SOC
SPI_DI_SOC - Low : Normal Operation IC100
- High : Write Protection EB_DATA[0-7]
LED0 A2
3 A0’h SCL LGE5332(LM14A)
6
EB_DATA[0]
PWM_PM I2C_SCL1
V-BY-ONE AH14
4.7K
4.7K
4.7K
4.7K
EB_DATA[1] PCM_D[0]/GPIO147 FE_DEMOD1_TS_DATA[0]

GND SDA I2C_SDA1 AG13 AH13
4 5 PCM_D[1]/GPIO148 TS1_D0/GPIO182
EB_DATA[2] FE_DEMOD1_TS_DATA[1]
OPT
OPT
33 D9 AF32 AG12 AG11

AR101 PWM_DIM TXVBY1_0N PCM_D[2]/GPIO149 TS1_D1/GPIO181
PWM0/GPIO152 LVSYNC/[VX1_0-] EB_DATA[3] AK22 AG10 FE_DEMOD1_TS_DATA[2]
F10 AF31
R109
TXVBY1_0P
R111
R116
PWM_DIM2
R123
PWM1/GPIO153 LHSYNC/[VX1_0+] EB_DATA[4] PCM_D[3]/GPIO119 TS1_D2/GPIO180 FE_DEMOD1_TS_DATA[3]

F8 AG32 AK21 AJ11
FAN_ON TXVBY1_1N PCM_D[4]/GPIO120 TS1_D3/GPIO179
PWM2/GPIO154 LDE/[VX1_1-] EB_DATA[5] AL21 AH10 FE_DEMOD1_TS_DATA[4]
E9 AG31 TXVBY1_1P
AMP_RESET_N PWM3/GPIO155 LCK/[VX1_1+] EB_DATA[6] PCM_D[5]/GPIO121 TS1_D4/GPIO178 FE_DEMOD1_TS_DATA[5]
AM23 AJ13
EB_DATA[7] PCM_D[6]/GPIO122 TS1_D5/GPIO177 FE_DEMOD1_TS_DATA[6]
N5 AH31 AH20 AG9
PWM_PM TXVBY1_2N EB_ADDR[0-14] PCM_D[7]/GPIO123 TS1_D6/GPIO176
PWM_PM/GPIO7 R_ODD[7]/LVB0N/[VX1_2-] AH9 FE_DEMOD1_TS_DATA[7]
AH30 TXVBY1_2P
R_ODD[6]/LVB0P/[VX1_2+] EB_ADDR[0] TS1_D7/GPIO175
F4 AJ31 AG14 AH11
TXVBY1_3N PCM_A[0]/GPIO146 TS1_CLK/GPIO172 FE_DEMOD1_TS_CLK
CHIP_CONFIG[3:0] /USB_OCD2 SAR0/GPIO46 R_ODD[5]/LVB1N/[VX1_3-] EB_ADDR[1] AL20 AJ10
G5 AJ32 TXVBY1_3P
{LED1, SPI_DI,LED0, PWM_PM} USB_CTL2 SAR1/GPIO47 R_ODD[4]/LVB1P/[VX1_3+] EB_ADDR[2] PCM_A[1]/GPIO145 TS1_VLD/GPIO174 FE_DEMOD1_TS_VAL
E5 AK32 AG15 AH12
FRC_FLASH_WP TXVBY1_4N PCM_A[2]/GPIO143 TS1_SYNC/GPIO173 FE_DEMOD1_TS_SYNC
Value Mode Description SAR2/GPIO48 R_ODD[3]/LVB2N/[VX1_4-] EB_ADDR[3] AH15
E4 AK31 TXVBY1_4P TPI_DATA[0-7]
4’b1000 SB51_ExtSPI 51 boot from SPI DDTS_TX SAR3/GPIO49 R_ODD[2]/LVB2P/[VX1_4+] EB_ADDR[4] PCM_A[3]/GPIO142 TPI_DATA[0]
4’b1001 HEMCU_ExtSPI ARM boot from SPI G4 AL32 AM19 AK17
TXVBY1_5N PCM_A[4]/GPIO141 TS0_D0/GPIO161
SAR5 R_ODD[1]/LVBCLKN/[VX1_5-] EB_ADDR[5] AJ17 AL18 TPI_DATA[1]
4’b1010 HEMCU_ROM_EMMC ARM boot from ROM; outer storage is eMMC AL31 TXVBY1_5P
4’b1011 HEMCU_ROM_NAND ARM boot from ROM; outer storage is NAND R_ODD[0]/LVBCLKP/[VX1_5+] EB_ADDR[6] PCM_A[5]/GPIO139 TS0_D1/GPIO162 TPI_DATA[2]
AK30 AJ16 AK18
4’b1100 DBUS for test only TXVBY1_6N PCM_A[6]/GPIO138 TS0_D2/GPIO163
G_ODD[7]/LVB3N/[VX1_6-] EB_ADDR[7] AH17 AL15 TPI_DATA[3]
4’b0000 SB51_ExtSPI + Authentication 51 boot from SPI with ARM authentication W5 AL30 TXVBY1_6P
SPI_CK_SOC PM_SPI_CK/GPIO1 G_ODD[6]/LVB3P/[VX1_6+] EB_ADDR[8] PCM_A[7]/GPIO137 TS0_D3 TPI_DATA[4]
4’b0001 SB51_ExtSPI + Authentication HEMCU_ExtSPI + Authentication V4 AK29 AM20 AL16
SPI_DI_SOC TXVBY1_7N PCM_A[8]/GPIO131 TS0_D4/GPIO165
4’b0011 HEMCU_ROM_NAND + Authentication ARM boot from ROM with authentication; PM_SPI_DI/GPIO2 G_ODD[5]/LVB4N/[VX1_7-] EB_ADDR[9] AH19 AK15 TPI_DATA[5]
V5 AL29 TXVBY1_7P
SPI_DO_SOC PM_SPI_DO/GPIO3 G_ODD[4]/LVB4P/[VX1_7+] EB_ADDR[10] PCM_A[9]/GPIO129 TS0_D5/GPIO166 TPI_DATA[6]
Y6 AJ20 AM16
/TU_RESET1 PM_SPI_CZ/GPIO0 EB_ADDR[11] PCM_A[10]/GPIO125 TS0_D6/GPIO167 TPI_DATA[7]
R167 0 Y4 AK28 TXOSD_0N
AK20 AK16
/SPI_CS GPIO_PM[6]/[SPI-CZ1N]/GPIO16 G_ODD[3]/LVA0N/[OSD_0-] EB_ADDR[12] PCM_A[11]/GPIO127 TS0_D7/GPIO168
OPT Y5 AM28 AG17 AL19
TXOSD_0P PCM_A[12]/GPIO136 TS0_CLK/GPIO171 TPI_CLK
GPIO_PM[10]/[SPI-CZ2N]/GPIO20 G_ODD[2]/LVA0P/[OSD_0+] EB_ADDR[13] AJ19 AM17
LM14 HW Option M_RFModule_RESET
G_ODD[0]/LVA1P/[OSD_1+]
AL28
AK27
TXOSD_1N
TXOSD_1P
EB_ADDR[14] AG18
PCM_A[13]/GPIO132 TS0_VLD/GPIO169
AL17
TPI_VAL
G_ODD[1]/LVA1N/[OSD_1-] PCM_A[14]/GPIO133 TS0_SYNC/GPIO170 TPI_SOP
AK26 TXOSD_2N
+3.3V_NORMAL B_ODD[7]/LVA2N/[OSD_2-] AH18 AH23
AL8 AL26 TXOSD_2P
DDCA_CK DDCA_CK/GPIO8 B_ODD[6]/LVA2P/[OSD_2+] SM_Vsel CAM_IREQ_N PCM_IRQA_N/GPIO135 TS3_D0/GPIO206 POL EPI
AK8 AM26 AM22 AH27
DDCA_DA TXOSD_3N SM_CLK EB_OE_N PCM_OE_N/GPIO126 TS3_D1/GPIO207 GST_A GST
DDCA_DA/GPIO9 B_ODD[5]/LVACLKN/[OSD_3-] AG20 AJ23
AK25 TXOSD_3P GCLK
B_ODD[4]/LVACLKP/[OSD_3+] SM_RST EB_BE_N1 PCM_IORD_N/GPIO128 TS3_D2/GPIO208 GCLK_A
AL25 AL22 AG27
B_ODD[3]/LVA3N/[LOCKN] LOCKAn_Video SM_IO /PCM_CE1 PCM_CE_N/GPIO124 TS3_D3/GPIO209 MCLK_A MCLK
AH28 AK24 AK19 AH24
10K
10K
10K
10K
10K
10K
10K
10K
EB_WE_N PCM_WE_N/GPIO134 OPT_P

10K
10K
TS3_D4/GPIO210
10K
10K
SOC_TX GPIO3/TX1/GPIO58 B_ODD[2]/LVA3P/[HTPDN] HTPDAn_Video SM_VCC

BIT2_1
BIT10_1
BIT11_1
BIT0_1
BIT1_1
BIT3_1
BIT4_1
BIT5_1
BIT6_1
BIT7_1
BIT8_1
AG21 AH26
BIT9_1
AH29 AL24
SOC_RX GPIO4/RX1 B_ODD[1]/LVA4N/[OSD_LOCKN] LOCKAn_OSD CAM_CD1_N PCM_CD_N/GPIO151 TS3_D5/GPIO211 SOE
AA4 AK23 AH16 AJ25
FRC_FLASH_SEL_SOC GPIO23/[TX3]/GPIO78 B_ODD[0]/LVA4P/[OSD_HTPDN] HTPDAn_OSD PCM_RESET PCM_RESET/GPIO150 TS3_D6/GPIO212 FB
W6 AJ14 AG26
R119
R112
R125
R128
R132
R135
R138
R140
R142
R146
R105
R148
/TU_RESET2 GPIO24/[RX3]/GPIO79 CAM_REG_N PCM_REG_N/GPIO144 TS3_D7/GPIO213 EO_A E/O

F14 AG19 AH25
I2C_SCL6 DIM2/TX4/GPIO112 SM_CD EB_BE_N0 PCM_IOWR_N/GPIO130 TS3_CLK/GPIO216 HCONV
F12 AG16 AJ26
BIT0 I2C_SDA6 DIM3/RX4/GPIO113 CAM_WAIT_N PCM_WAIT_N/GPIO140 TS3_VLD/GPIO214 DPM
AG24
BIT1 TS3_SYNC/GPIO215 LOCKOUT12 LOCK
AJ27
CPU_VID1 GPIO2/GPIO57
BIT2
C7
BIT3 BIT0 EMMC_IO15/[GPIO]/GPIO189
C6
BIT1 EMMC_IO17/[GPIO]/GPIO188
BIT4 AE2 C8 AJ28
GPIO_PM[0]/GPIO10 COMP1_DET EMMC_CMD EMMC_IO9/[EMMC_CMD]/GPIO183 GPIO8/[TS4_D[0]]/GPIO63 FE_DEMOD3_TS_DATA
B8 AG28
BIT2 EMMC_IO14/[GPIO]/GPIO185 GPIO5/[TS4_CLK]/GPIO60 FE_DEMOD3_TS_CLK
1K
R176
BIT5 U6 A9 AJ29
GPIO_PM[3]/GPIO13 DDTS_RX EMMC_CLK EMMC_IO10/[EMMC_CLK]/GPIO186 GPIO7/[TS4_VLD]/GPIO62 FE_DEMOD3_TS_VAL
P4 B7 AG29
BIT6 GPIO_PM[4]/GPIO14 PCM_5V_CTL R175 TCON_I2C_EN BIT3 EMMC_IO16/[GPIO]/GPIO187 GPIO6/[TS4_SYNC]/GPIO61 FE_DEMOD3_TS_SYNC
U5 22 B9
GPIO_PM[7]/GPIO17 EMMC_RST EMMC_IO11/[EMMC_RSTN]/GPIO190
AE5 A8
BIT7 PMIC_RESET BIT4 EMMC_IO12/[GPIO]/GPIO184
GPIO_PM[8]/GPIO18 C9
AJ7 AJ5
I2C_SCL3 GPIO28/SCK0/GPIO83 GPIO_PM[9]/GPIO19 COMPENSATION_DONE EMMC_STRB EMMC_IO8/[NAND-DQS]/GPIO191
BIT8 AH8 AG6 B6
I2C_SDA3 EMMC_DATA[0-7] BIT5 EMMC_IO13/[GPIO]/GPIO217
GPIO29/SDA0/GPIO84 GPIO_PM[13]/GPIO23 URSA9_CONNECT
E11
BIT9 I2C_SCL1 DDCR_CK/SCK3/GPIO54 EMMC_DATA[6] C10
E10
I2C_SDA1 DDCR_DA/SDA3/GPIO53 EMMC_DATA[7] EMMC_IO6/[EMMC_D6]/GPIO221
AJ6 B11
I2C_SCL2 GPIO30/SCK4/GPIO85 EMMC_DATA[2] EMMC_IO7/[EMMC_D7]/GPIO220
AG8 A11
I2C_SDA2 GPIO31/SDA4/GPIO86 EMMC_DATA[1] EMMC_IO2/[EMMC_D2]/GPIO219
BIT10 AH7 P5 C11
I2C_SCL5 GPIO32/SCK5/GPIO87 GPIO_PM[1]/PM_UART1/GPIO11 /USB_OCD1 EMMC_DATA[0] EMMC_IO1/[EMMC_D1]/GPIO218
AJ8 P6 A12 AL2
BIT11 I2C_SDA5 GPIO33/SDA5/GPIO88 GPIO_PM[5]/PM_UART1/GPIO15 USB_CTL1 EMMC_DATA[3] EMMC_IO0/[EMMC_D0]/GPIO194 VIFP
AJ4 B12 AM2
GPIO_PM[11]/PM_UART0/GPIO21 DATA_FORMAT_0_SOC EMMC_DATA[4] EMMC_IO3/[EMMC_D3]/GPIO193 VIFM
AH4 C12
GPIO_PM[12]/PM_UART0/GPIO22 DATA_FORMAT_1_SOC EMMC_DATA[5] EMMC_IO4/[EMMC_D4]/GPIO192
B13 AK1 Close to MSTAR DTV_IF
EMMC_IO5/[EMMC_D5]/GPIO222 SIFP
AK2
10K
10K
10K
10K
10K
10K
10K
10K
10K
SIFM
10K
10K
10K
L6 G7 R183 100 C103 0.1uF OPT IF_P

BIT10_0
BIT11_0
BIT2_0
BIT0_0
BIT1_0
BIT7_0
BIT8_0
BIT9_0
BIT4_0
BIT3_0
BIT5_0
BIT6_0
CPU_VID0 VID0/GPIO50 TESTPIN C107

M6 AK3 100pF
CORE_VID0 VID1/GPIO51 IFAGC
AD5
R126
LED0
R129
R106
R133
R136
R139
R141
LED0/GPIO29
R143
R147
R149
R113
R120
AD4
LED1 LED1/GPIO30 R184 100 C104 0.1uF OPT IF_N
AB5 AJ1 C109
WOL_WAKE_UP_SOC WOL_INT_OUT/[GPIO]/GPIO52 TGPIO0/GPIO157 /USB_OCD3 33pF OPT
E13 AJ2 C110
SPI1_DI/GPIO107 HP_DET TGPIO1/GPIO158 USB_CTL3 33pF
D12 R4
SPI1_CK/GPIO106 RF_SWITCH_CTL TGPIO2/SCK1/GPIO159 I2C_SCL7
F11 R5
SPI2_DI/GPIO109 L/D_DI_SOC TGPIO3/SDA1/GPIO160 I2C_SDA7
D11
SPI2_CK/GPIO108 L/D_CLK_SOC
E12
VSYNC_LIKE/GPIO105 L/D_VSYNC_SOC C101 0.1uF R185 47
D14 AM7 TU_SIF
DIM0/GPIO110 SC_DET NC_1 C102 0.1uF R186 47
E14 AL7 R188
DIM1/GPIO111 AV1_CVBS_DET NC_2 C105 300
AM8 1000pF
NC_3 ANALOG SIF OPT OPT
AK7
NC_4 Close to MSTAR
20150123 version AL5
NC_5
+3.3V_NORMAL
BIT(0/1) DVB ATSC JP AM5
GPIO34/GPIO89 CORE_VID1
M7 L100
00 TW/COL US NC_6 PZ1608U121-2R0TF
Low High
01 CN/HK KR JP
10 EU BR T-con I2C R182 C106
BIT8 16Kbit 32Kbit 0.1uF
BIT(2/3) EU/CIS AJJA TW/COL CN/HK KR North.AM BR JP Protocol 10K
11 AJJA CI BIT(6/7) B/E(FRC)
R187
00 T2/C/S2 PIP T2/C PIP T2/C PIP Default ATSC NIM+T2 Default ISDB PIP Default 0
00 LM14A only BIT9 Division NON_Division 4_Division IF_AGC
Low High
01 T2/C/S2 T2/C/S2 T2/C ATSC+T2 ISDB EXT
01 N/A C108
BIT4 Display LCD OLED 0.047uF
BIT10 Interface EPI Vx1
10 LM14A+URSA11 10 T/C T T/C ATSC 25V
ISDB INT
4K@60Hz
BIT5 Resolution FHD UHD 11 LM14A+URSA11 11 T2 BIT11 OS(DDR) WebOS Lite WebOS
ATSC PIP
4K@120Hz
+3.3V_TU
+3.3V_LNA_TU
+3.3V_NORMAL I2C PULL UP
GPIO PULL UP
Mstar Debug RS232C_Debug DDTS_Debug
+3.3V_NORMAL MSTAR_DEBUG_OLD
P101 +3.3V_NORMAL +3.3V_NORMAL
UART_4PIN_WAFER DDTS_Debug
R100
1.8K
R101
1.8K
R102
1.8K
R103
1.8K
R104
1.8K
R107
1.8K
R114
1.8K
R121
1.8K
R124
1.8K
R127
1.8K
R130
1.8K
R131
1.8K
R134
1.8K
R137
1.8K
MSTAR_DEBUG_NEW
12505WS-04A00
P100 P102 P103
12507WS-04L 12507WS-04L 12507WS-04L
10K
10K
10K
10K
10K
10K
10K
10K
10K
10K
I2C_SDA7
10K
10K
1
OPT
I2C for URSA9 (URSA9 Only)

OPT
I2C_SCL7
OPT
OPT
1 1
R152
1
R154
R164
I2C_SDA6
R156
R157
R161
R165
R170
R166
R168
I2C for LCD Module 2

R178
R180
I2C_SCL6
I2C_SDA1 2 SOC_RX 2
I2C for NAVRAM 2 DDTS_RX
I2C_SCL1
10K
10K
/TU_RESET1 DDCA_CK 3
I2C_SDA3
OPT
OPT
I2C for Micom RF_SWITCH_CTL 3 3
I2C_SCL3 3
AMP_RESET_N 4
R179
R181
I2C_SDA4 DDCA_DA
I2C for Main Amp / Woofer AMP TCON_I2C_EN
I2C_SCL4 4 4 SOC_TX 4
/USB_OCD3 5 DDTS_TX
I2C_SDA5
I2C for tuner USB_CTL3
I2C_SCL5 5 5 5
/USB_OCD2
I2C_SDA2 USB_CTL2
I2C for tuner&LNB M_RFModule_RESET
AR100 I2C_SCL2
33 PCM_5V_CTL
I2C_SDA_MICOM I2C_SDA3
I2C_SCL_MICOM I2C_SCL3

THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. MAIN1_SYSTEM 01
+1.1V_VDDC_CPU
+1.1V_Bypass Cap(CLOSE TO CHIP SIDE)
IC100
LGE5332(LM14A) 1st layer 4th layer
+1.1V_VDDC +1.1V_VDDC +1.1V_VDDC DVDD_DDR11

4th layer
0.1uF
0.1uF
0.1uF
J9 AC17 L226
10uF
VDDC_1 VDDC_24 PZ1608U121-2R0TF
J10 AC18 C263 C323
VDDC_2 VDDC_25
J11 AC19 10uF C208 0.1uF
VDDC_3 VDDC_26 10V 10uF 16V
C322
C276
C278
C299
J12 AC20
J13
VDDC_4 VDDC_27
AC21
10V 2A C257
VDDC_5 VDDC_28 C324
K9 AC22 0.47uF 0.47uF
VDDC_6 VDDC_29 6.3V 6.3V
K10 AD17
VDDC_7 VDDC_30
K11 AD18
VDDC_8 VDDC_31
K12 AD19 Close to chip side
VDDC_9 VDDC_32
K13 AD20
VDDC_10 VDDC_33
L9 AD21 Close to chip side
VDDC_11 VDDC_34
L10 AD22
VDDC_12 VDDC_35
L11 AE19
VDDC_13 VDDC_36 Close to chip side
L12 AE20
VDDC_14 VDDC_37
R11 AE21
VDDC_15 VDDC_38 +1.1V_VDDC
R12 AE22
VDDC_16 VDDC_39 AVDDL_MOD11
R13 1st layer 4th layer
VDDC_17 4th layer
T11 AE31
VDDC_18 VDD_SRAM_1 L202
T12 AC24 PZ1608U121-2R0TF
VDDC_19 VDD_SRAM_2
T13 AD23
0.1uF
0.1uF
0.1uF
VDDC_20 VDD_SRAM_3
10uF
U11
VDDC_21
U12
VDDC_22 CTRL_SRAMLDO
AE30
C205
10uF
C261
0.1uF 2A C320
U13 10V 16V C238
C250
C230
C234
C235
VDDC_23 0.47uF 0.47uF
6.3V 6.3V
AVDDL_MOD11 A6 AVDD_DMPLL
EMMC_CTRL
W21
AVDDL_PREDRV_1
Y21
AVDDL_PREDRV_2
AD29 V7
AVDDL_PREDRV_3 AVDD_NODIE Close to chip side
0.1uF
AD30
AVDDL_MOD_1 DVDD_DDR11
W20
AVDD15_MOD AVDDL_MOD_2 Close to chip side
Y20 L7
AVDDL_MOD_3 AVDDL_MHL3_1 AVDDP3P3_MHL Close to chip side
U19 N12
C227
AVDD15_MOD_1 AVDDL_MHL3_2
V19 R7
AVDD15_MOD_2 AVDD3P3_MHL3_1
DVDD_DDR11 AA13 T7
AVDDL_USB3_1 AVDD3P3_MHL3_2
AF11 AVDD33_ADC
AVDDL_USB3_2 AVDD_DMPLL
U21 Y7
VDDC_CPU_1 AVDD3P3_ETH
U22 AB7
+1.1V_VDDC_CPU VDDC_CPU_2 AVDD3P3_DADC_1
U23
U24
VDDC_CPU_3 AVDD3P3_DADC_2
AB8
AA7
+1.5V_Bypass Cap
VDDC_CPU_4 AVDD3P3_ADC_1 AVDD_DMPLL +1.5V_DDR AVDD_DDR
U25 AA8
VDDC_CPU_5 AVDD3P3_ADC_2
V23 G9
VDDC_CPU_6 AVDD3P3_USB_1
V24 G10 L227
VDDC_CPU_7 AVDD3P3_USB_2 PZ1608U121-2R0TF
V25 AB15
VDDC_CPU_8 AVDD3P3_USB3_1 1st layer 4th layer
W23 AF13 AVDD_AU33
VDDC_CPU_9 AVDD3P3_USB3_2 AVDDP3P3 L200 AVDD_DDR AVDD15_MOD
W24 AD7
VDDC_CPU_10 AVDD_AU33
W25 AE7
2A
0.47uF
VDDC_CPU_11 AVDD_EAR33 PZ1608U121-2R0TF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
Y23 AF8
VDDC_CPU_12 AVDD3P3_DMPLL OPT
L224
Y24
Y25
VDDC_CPU_13 VDDP_1
AE15
AF15
4A C207
10uF
C201
10uF
C247
C316
10uF
C223
10uF
C248
0.47uF
C249
0.47uF
0.47uF PZ1608U121-2R0TF
VDDC_CPU_14 VDDP_2 10V 10V 6.3V
C314
10V 10V 6.3V
0.1uF
C209
C224
C225
C226
0.1uF
AA22 6.3V
C203
C204
C287
VDDC_CPU_15
AA23
VDDC_CPU_16
AA24 V17
C307
AA25 V18
C308
AB24 W19
AB25 Y19
Close to chip side Close to chip side
AE16
MCP_VDDC_1
AF16 N15
MCP_VDDC_2 AVDD_PLL_A
N16
AVDD_PLL_B
DVDD_NODIE VDDP_NAND_A VDDP_NAND_C
L13
DVDD_NODIE
DVDD_DDR11 H16
VDDP_3318_A/[3.3V/1.8V]
K21 K16
C200 DVDD_DDR_1 VDDP_3318_C/[3.3V/1.8V]
N21 AVDD_DDR
1uF DVDD_DDR_2
25V
M21 J21
L21 K17
K18
AVDD_DDR_A_3
K19
AVDD_DDR_A_4
AVDD_DDR_A_5
L17
GND JIG POINT +3.3V_Bypass Cap
L19
AVDD_DDR_A_6
L20
AVDD_DDR_A_7
J23
AVDD_DDR_B_1
K22
AVDD_DDR_B_2 4th layer
JP202
JP204
JP205
JP203
K23
AVDD_DDR_B_3 +3.3V_NORMAL AVDDP3P3
M22 +3.3V_NORMAL
AVDD_DDR_B_4
N22 AVDD_DMPLL
AVDD_DDR_B_5 1st layer 4th layer
N23
AVDD_DDR_B_6 L215
P23 L213 PZ1608U121-2R0TF
0.1uF
AVDD_DDR_B_7 PZ1608U121-2R0TF
0.1uF
0.47uF
0.1uF
C293
2A 0.47uF 2A C256 C217
C269
L18 6.3V C222 10uF
C268 10uF
AVDD_DDR_LDO_A 10uF
C274
10V 10V
C311
C253
L22 10uF 10V
AVDD_DDR_LDO_B 10V
AVDD5V_MHL
H7
AVDD_HDMI_5V_PA
R201 Close to chip side
0 AVDD_DDR
G8
GND_EFUSE
+3.3V_NORMAL VDDP_NAND_C 0
R207 Close to chip side Close to chip side
0.1uF
4th layer
C14 OPT
C229
AVDD_DDR_VBP_A_1 0.47uF C210

B14 L208
5V_HDMI_1 AVDD5V_MHL AVDD_DDR_VBP_A_2 AVDD33_ADC
J17 PZ1608U121-2R0TF
AVDD_DDR_VBP_A_3
J18 0.47uF C211
AVDD_DDR_VBP_A_4 L221
0.1uF
+5V_NORMAL 4th layer

R200
10 B15
2A C260
C266
0.1uF
PZ1608U121-2R0TF
AVDD_DDR_VBN_A_1 10uF R206

C15 0.47uF C212 C294 C295 C251 C252 AVDDP3P3_MHL
10V 10K
AVDD_DDR_VBN_A_2
2A
C219
J19 1uF 1uF 0.47uF 0.47uF
G
AVDD_DDR_VBN_A_3 10V 10V 6.3V 6.3V
J20 0.47uF C213 L201
AVDD_DDR_VBN_A_4 PZ1608U121-2R0TF
D
AC30
AVDD_DDR_VBP_B_1 0.47uF C214 RUE003N02 C240 C241
AC31
AVDD_DDR_VBP_B_2 0.1uF 0.47uF
K24 Q200
6.3V
AVDD_DDR_VBP_B_3 0.47uF C215
L24 Close to chip side
AVDD_DDR_VBP_B_4 VDDP_NAND_A
0.1uF
AD31 +1.8V
AVDD_DDR_VBN_B_1
AD32 C216
AVDD_DDR_VBN_B_2 0.47uF L209
C221
L23 PZ1608U121-2R0TF
AVDD_DDR_VBN_B_3 Close to chip side
M24
AVDD_DDR_VBN_B_4 0.47uF C220
4th layer
2A C236
C239
0.1uF
10uF AVDD_AU33
10V
L219
PZ1608U121-2R0TF
C292
2A 0.47uF
6.3V
Close to chip side

THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. MAIN2_POWER 2
DDR_VTT DDR_VTT
AR400 AR407
M0_DDR_VREFDQ 56 56
Hynix_DDR3_4Gb_29n Hynix_DDR3_4Gb_29n M0_1_DDR_VREFDQ 1/16W 1/16W
IC400 IC401 C424 0.1uF C453 0.1uF
H5TQ4G63AFR-RDC H5TQ4G63AFR-RDC M0_DDR_A8 M1_DDR_A8
EAN63053201 EAN63053201 C425 0.1uF C454 0.1uF
M0_DDR_A6 M1_DDR_A6
M0_DDR_A0
N3
A0 DDR3 VREFCA
M8
M0_DDR_A0
N3
A0
DDR3 VREFCA
M8
AR401 AR408
P7 P7 4Gbit 56 56
M0_DDR_A1 A1 4Gbit M0_DDR_A1 A1 1/16W 1/16W
P3 P3
M0_DDR_A2 A2 (x16) M0_DDR_A2 A2 (x16) C426 0.1uF C455 0.1uF
N2 H1 N2 H1 M0_DDR_A1 M1_DDR_A1
M0_DDR_A3 A3 VREFDQ M0_DDR_A3 A3 VREFDQ
M0_DDR_A5 A5 M0_DDR_A5 A5 C427 0.1uF C456 0.1uF
R8 L8 R400 240 R8 L8 R403 240 M0_DDR_BA1 M1_DDR_BA1
M0_DDR_A6 A6 ZQ M0_DDR_A6 A6 ZQ
R2 AVDD_DDR R2 AR402 AR409
M0_DDR_A7 A7 M0_DDR_A7 A7 AVDD_DDR
T8 T8 56 56
M0_DDR_A8 A8 M0_DDR_A8 A8 1/16W 1/16W
R3 B2 R3 B2 C428 0.1uF C457 0.1uF
L7 D9 L7 D9
M0_DDR_A10 A10/AP VDD_2 M0_DDR_A10 A10/AP VDD_2 M0_DDR_A13 M1_DDR_A13
R7 G7 R7 G7

N7 K2 N7 K2 M0_DDR_A9 M1_DDR_A9
M0_DDR_A12 A12/BC VDD_4 M0_DDR_A12 C429 0.1uF C458 0.1uF
A12/BC VDD_4 M0_DDR_A7 M1_DDR_A7
T3 K8 T3 K8
T7 N1 T7 N1 AR403 AR410
M0_DDR_A14 A14 VDD_6 M0_DDR_A14 A14 VDD_6 56 56
M7 N9 M7 N9 1/16W 1/16W
M0_DDR_A15 NC_5 VDD_7 M0_DDR_A15 NC_5 VDD_7
R1 R1 C430 0.1uF C459 0.1uF
VDD_8 VDD_8 M0_DDR_A2 M1_DDR_A2
M2 R9 M2 R9
M0_DDR_BA0 BA0 VDD_9 M0_DDR_BA0 BA0 VDD_9 M0_DDR_A5 M1_DDR_A5
N8 N8
M3 M3 C431 0.1uF C460 0.1uF
A1 A1
VDDQ_1 VDDQ_1 AR404 AR411
J7 A8 J7 A8
M0_D_CLK CK VDDQ_2 M0_D_CLK CK VDDQ_2 56 56
K7 C1 K7 C1 1/16W 1/16W
M0_D_CLKN CK VDDQ_3 M0_D_CLKN CK VDDQ_3 C432 0.1uF C461 0.1uF
K9 C9 K9 C9 M0_DDR_BA0 M1_DDR_BA0
D2 D2 M0_DDR_BA2 M1_DDR_BA2
VDDQ_5 VDDQ_5
L2 E9 L2 E9 M0_DDR_A15 M1_DDR_A15
M0_DDR_CS1 CS VDDQ_6 M0_DDR_CS2 CS VDDQ_6 C433 0.1uF C462 0.1uF
K1 F1 K1 F1 M0_DDR_A10 M1_DDR_A10
J3 H2 C410 0.1uF J3 H2 C440 0.1uF
M0_DDR_RASN RAS VDDQ_8 M0_DDR_RASN RAS VDDQ_8 AR405 AR412
K3 H9 C411 0.1uF K3 H9 C441 0.1uF 56 56
M0_DDR_CASN CAS VDDQ_9 M0_DDR_CASN CAS VDDQ_9 1/16W 1/16W
L3 L3
M0_DDR_WEN WE M0_DDR_WEN WE C434 0.1uF C463 0.1uF
J1 J1 M0_DDR_WEN M1_DDR_WEN
NC_1 NC_1
T2 J9 T2 J9 M0_DDR_CASN M1_DDR_CASN
IC100 L1 L1 M0_DDR_ODT M1_DDR_ODT
NC_3 NC_3 C435 0.1uF C464 0.1uF
LGE5332(LM14A) L9 L9 M0_DDR_RASN M1_DDR_RASN
NC_4 NC_4
F3 F3 AR406 AR413
M0_DDR_DQS0 DQSL SS_DDR3_4Gb_25n Hynix_DDR3_4Gb_25n M0_DDR_DQS2 DQSL SS_DDR3_4Gb_25n
Hynix_DDR3_4Gb_25n
G3 IC400-*1 IC400-*2 G3
IC401-*1
K4B4G1646D-BCMA IC401-*2 SS_DDR3_2Gb
IC401-*3
Hynix_DDR3_2Gb
IC401-*4
56 56
K4B4G1646D-BCMA H5TQ4G63CFR_RDC H5TQ4G63CFR_RDC
M0_DDR_DQS_N0 DQSL M0_DDR_DQS_N2 DQSL EAN63391401 K4B2G1646Q-BCMA H5TQ2G63FFR-RDC 1/16W 1/16W
EAN63391401 EAN63053202 N3 M8 EAN63053202
F17 H28 N3
P7
A0 VREFCA
M8 N3
P7
A0 VREFCA
M8 P7
A0
A1
VREFCA N3
P7
A0 VREFCA
M8
N3
EAN63667401
M8 N3
EAN63648701
M8
C436 0.1uF C465 0.1uF
M0_DDR_A0 IO[3]/A-A0[AB-A0]/A-A6 IO[75]/B-A0[CD-A0]/B-A6 M1_DDR_A0 C7 A9 P3
A1
A2
P3
A1
A2
C7 A9
P3
N2
A2
H1 P3
A1
A2
P7
A0
A1
VREFCA
P7
A0
A1
VREFCA
M0_DDR_CKE M1_DDR_CKE
C17 K31 M0_DDR_DQS1 DQSU
N2
A3 VREFDQ
H1 N2
A3 VREFDQ
H1
M0_DDR_DQS3
P8
A3
A4
VREFDQ N2
A3 VREFDQ
H1 P3
A2
P3
A2
M0_DDR_A1 IO[2]/A-A1[AB-A1]/A-A5 IO[80]/B-A1[CD-A1]/B-A5 M1_DDR_A1 VSS_1 P8

P2
A4
P8
P2
A4 DQSU VSS_1 P2
R8
A5
L8
P8
P2
A4
N2
P8
A3 VREFDQ
H1 N2
P8
A3 VREFDQ
H1
E17 J29 B7 B3 R8
A5
A6 ZQ
L8 R8
A5
A6 ZQ
L8 B7 B3 R2
A6
A7
ZQ R8
A5
A6 ZQ
L8 P2
A4
A5
P2
A4
A5
M0_DDR_A2 IO[8]/A-A2[AB-A2]/A-A8 M1_DDR_A2 M0_DDR_DQS_N1 DQSU VSS_2

R2
A7
R2
A7
M0_DDR_DQS_N3 DQSU VSS_2 T8
A8
R2
A7
R8
R2
A6 ZQ
L8 R8
R2
A6 ZQ
L8
M0_D_CLKN M1_D_CLKN
IO[83]/B-A2[CD-A2]/B-A8 E1
T8
R3
A8
B2
T8
R3
A8
B2
E1
R3
L7
A9 VDD_1
B2
D9
T8
R3
A8
B2 T8
A7
T8
A7
F18 K27 L7
A9 VDD_1
D9 L7
A9 VDD_1
D9 R7
A10/AP VDD_2
G7 L7
A9 VDD_1
D9 R3
A8
B2 R3
A8
B2
C437 0.1uF C466 0.1uF
M0_DDR_A3 IO[12]/A-A3[AB-A3]/A-A4 IO[79]/B-A3[CD-A3]/B-A4 M1_DDR_A3 VSS_3 R7
A10/AP
A11
VDD_2
VDD_3
G7 R7
A10/AP
A11
VDD_2
VDD_3
G7
VSS_3 N7
A11
A12/BC
VDD_3
VDD_4
K2 R7
A10/AP
A11
VDD_2
VDD_3
G7 L7
A9
A10/AP
VDD_1
VDD_2
D9 L7
A9
A10/AP
VDD_1
VDD_2
D9
M0_D_CLK M1_D_CLK
B18 K30 E7 G8 N7
T3
A12/BC VDD_4
K2
K8
N7
T3
A12/BC VDD_4
K2
K8 E7 G8 T3
A13 VDD_5
K8
N1
N7
T3
A12/BC VDD_4
K2
K8
R7
N7
A11
A12/BC
VDD_3
VDD_4
G7
K2
R7
N7
A11
A12/BC
VDD_3
VDD_4
G7
K2
M0_DDR_A4 M1_DDR_A4 M0_DDR_DM0 DML VSS_4

A13 VDD_5
VDD_6
N1 T7
A13
A14
VDD_5
VDD_6
N1
VDD_6
N9 T7
A13
A14
VDD_5
VDD_6
N1 T3
A13 VDD_5
K8 T3
A13 VDD_5
K8
IO[11]/A-A4[AB-A4]/A-BA1 IO[87]/B-A4[CD-A4]/B-BA1 D3 J2
M7
NC_5 VDD_7
N9
R1
M7
NC_5 VDD_7
N9
R1 D3 J2
NC_5 VDD_7
VDD_8
R1 M7
NC_5 VDD_7
N9
R1 M7
VDD_6
N1
N9
T7
M7
A14 VDD_6
N1
N9
E18 J28 M0_DDR_DM1 DMU
M2
VDD_8
R9 M2
VDD_8
R9
M0_DDR_DM3
M2
BA0 VDD_9
R9
M2
VDD_8
R9
NC_5 VDD_7
R1
NC_5 VDD_7
R1
M0_DDR_A5 IO[14]/A-A5[AB-A5]/A-A0 IO[86]/B-A5[CD-A5]/B-A0 M1_DDR_A5 VSS_5 N8

BA0 VDD_9
N8
BA0 VDD_9
DMU VSS_5 N8
M3
BA1 N8
BA0 VDD_9
M2
BA0
VDD_8
VDD_9
R9 M2
BA0
VDD_8
VDD_9
R9
A17 K32 J8 M3
BA1
BA2
A1
M3
BA1
BA2
A1
J8 J7
BA2
VDDQ_1
A1
A8
M3
BA1
BA2
A1
N8
M3
BA1
N8
M3
BA1
M0_DDR_A6 IO[10]/A-A6[AB-A6]/A-A1 IO[90]/B-A6[CD-A6]/B-A1 M1_DDR_A6 VSS_6 J7

CK
VDDQ_1
VDDQ_2
A8 J7
CK
VDDQ_1
VDDQ_2
A8
VSS_6 K7
CK
CK
VDDQ_2
VDDQ_3
C1 J7
CK
VDDQ_1
VDDQ_2
A8
BA2
VDDQ_1
A1
BA2
VDDQ_1
A1
D17 H31 E3 M1 K7
K9
CK VDDQ_3
C1
C9
K7
K9
CK VDDQ_3
C1
C9 E3 M1 K9
CKE VDDQ_4
C9
D2
K7
K9
CK VDDQ_3
C1
C9
J7
K7
CK
CK
VDDQ_2
VDDQ_3
A8
C1
J7
K7
CK
CK
VDDQ_2
VDDQ_3
A8
C1
M0_DDR_A7 M1_DDR_A7 M0_DDR_DQ0 DQL0 VSS_7

CKE VDDQ_4
VDDQ_5
D2
CKE VDDQ_4
VDDQ_5
D2
VDDQ_5
E9
CKE VDDQ_4
VDDQ_5
D2 K9
CKE VDDQ_4
C9 K9
CKE VDDQ_4
C9
IO[13]/A-A7[AB-A7]/A-A2 IO[78]/B-A7[CD-A7]/B-A2 F7 M9
L2
K1
CS VDDQ_6
E9
F1
L2
K1
CS VDDQ_6
E9
F1 F7 M9
K1
CS
ODT
VDDQ_6
VDDQ_7
F1 L2
K1
CS VDDQ_6
E9
F1 L2
VDDQ_5
D2
E9 L2
VDDQ_5
D2
E9
C16 J32 M0_DDR_DQ1 DQL1
J3
ODT VDDQ_7
H2 J3
ODT VDDQ_7
H2
M0_DDR_DQ17
J3
RAS VDDQ_8
H2
J3
ODT VDDQ_7
H2 K1
CS VDDQ_6
F1 K1
CS VDDQ_6
F1
M0_DDR_A8 IO[0]/A-A8[AB-A8]/A-A9 IO[77]/B-A8[CD-A8]/B-A9 M1_DDR_A8 VSS_8 K3

RAS VDDQ_8
H9 K3
RAS VDDQ_8
H9 DQL1 VSS_8 K3
L3
CAS VDDQ_9
H9
K3
RAS VDDQ_8
H9 J3
ODT VDDQ_7
H2 J3
ODT VDDQ_7
H2
AVDD_DDR
E16 G30 F2 P1 L3
CAS
WE
VDDQ_9
J1
L3
CAS
WE
VDDQ_9
J1
F2 P1 T2
WE
NC_1
J1
J9
L3
CAS
WE
VDDQ_9
J1
K3
L3
RAS
CAS
VDDQ_8
VDDQ_9
H9 K3
L3
RAS
CAS
VDDQ_8
VDDQ_9
H9
M0_DDR_CKE
M0_DDR_A9 M1_DDR_A9 M0_DDR_DQ2 DQL2 VSS_9 T2
NC_1
J9 T2
NC_1
J9 M0_DDR_DQ18 DQL2 VSS_9 RESET NC_2
L1 T2
NC_1
J9
WE
J1
WE
J1
IO[5]/A-A9[AB-A9]/A-A11 IO[73]/B-A9[CD-A9]/B-A11 F8 P9
RESET NC_2
NC_3
L1
RESET NC_2
NC_3
L1
F8 P9
NC_3
L9
RESET NC_2
NC_3
L1 T2
RESET
NC_1
NC_2
J9 T2
RESET
NC_1
NC_2
J9
B19 L30 M0_DDR_DQ3 DQL3

NC_4
L9
NC_4
L9
M0_DDR_DQ19
F3
DQSL
NC_4
NC_6
T7
NC_4
L9
NC_3
L1
NC_3
L1
M0_DDR_A10 IO[9]/A-A10[AB-A10]/A-RASZ IO[93]/B-A10[CD-A10]/B-RASZ M1_DDR_A10 VSS_10 F3

G3
DQSL NC_6
T7 F3
G3
DQSL DQL3 VSS_10 G3
DQSL
F3
G3
DQSL
F3
NC_4
L9
T7 F3
NC_4
L9
H3 T1
1K
R418
B17 J30
DQSL DQSL
H3 T1 C7
DQSU VSS_1
A9
DQSL
G3
DQSL
DQSL
NC_6
G3
DQSL
DQSL
M0_DDR_DQ4 AVDD_DDR
OPT
C7 A9 C7 A9
M0_DDR_DQ20 C7 A9
1K
R405
M0_DDR_A11 IO[6]/A-A11[AB-A11]/A-A7 IO[84]/B-A11[CD-A11]/B-A7 M1_DDR_A11 DQL4 VSS_11 B7
DQSU VSS_1
B3 B7
DQSU VSS_1
B3 DQL4 VSS_11 B7
DQSU VSS_2
B3
E1 B7
DQSU VSS_1
B3 C7
DQSU VSS_1
A9 C7
DQSU VSS_1
A9
AVDD_DDR
D20 L29 H8 T9 E7
DQSU VSS_2
VSS_3
E1
G8 E7
DQSU VSS_2
VSS_3
E1
G8
H8 T9 E7
D3
DML
VSS_3
VSS_4
G8
J2 E7
DQSU VSS_2
VSS_3
E1
G8
B7
DQSU VSS_2
B3
E1
B7
DQSU VSS_2
B3
E1
M0_DDR_A12 IO[26]/A-A12[AB-A12]/A-BG0 M1_DDR_A12 M0_DDR_DQ5 DQL5 VSS_12 D3

DML VSS_4
J2 D3
DML VSS_4
J2 M0_DDR_DQ21 DQL5 VSS_12 DMU VSS_5
J8 D3
DML VSS_4
J2 E7
VSS_3
G8 E7
VSS_3
G8
IO[85]/B-A12[CD-A12]/B-BG0 G2
DMU VSS_5
VSS_6
J8
DMU VSS_5
VSS_6
J8
G2 E3
VSS_6
M1
DMU VSS_5
VSS_6
J8 D3
DML
DMU
VSS_4
VSS_5
J2 D3
DML
DMU
VSS_4
VSS_5
J2
F16 G31 M0_DDR_DQ6 DQL6

E3
DQL0 VSS_7
M1 E3
DQL0 VSS_7
M1
M0_DDR_DQ22
F7
DQL0
DQL1
VSS_7
VSS_8
M9 E3
DQL0 VSS_7
M1
VSS_6
J8
VSS_6
J8
M0_1_DDR_VREFDQ
M0_DDR_A13 IO[4]/A-A13[AB-A13]/A-PARITY IO[74]/B-A13[CD-A13]/B-PARITY M1_DDR_A13
F7
F2
DQL1 VSS_8
M9
P1
F7
F2
DQL1 VSS_8
M9
P1 DQL6 F2
F8
DQL2 VSS_9
P1
P9
F7
F2
DQL1 VSS_8
M9
P1
E3
F7
DQL0 VSS_7
M1
M9
E3
F7
DQL0 VSS_7
M1
M9
B16 J31 H7 F8
DQL2
DQL3
VSS_9
VSS_10
P9 F8
DQL2
DQL3
VSS_9
VSS_10
P9 H7 H3
DQL3
DQL4
VSS_10
VSS_11
T1 F8
DQL2
DQL3
VSS_9
VSS_10
P9 F2
DQL1
DQL2
VSS_8
VSS_9
P1 F2
DQL1
DQL2
VSS_8
VSS_9
P1
M0_DDR_VREFDQ M0_DDR_RESET_N
M0_DDR_A14 IO[7]/A-A14[AB-A14]/A-A13 M1_DDR_A14 M0_DDR_DQ7 DQL7
H3
DQL4 VSS_11
T1 H3
DQL4 VSS_11
T1
M0_DDR_DQ23 DQL7 H8
DQL5 VSS_12
T9 H3
DQL4 VSS_11
T1 F8
H3
DQL3 VSS_10
P9
T1
F8
H3
DQL3 VSS_10
P9
T1
IO[81]/B-A14[CD-A14]/B-A13 B1
H8
G2
DQL5 VSS_12
T9 H8
G2
DQL5 VSS_12
T9
B1
G2
H7
DQL6
H8
G2
DQL5 VSS_12
T9
H8
DQL4 VSS_11
T9 H8
DQL4 VSS_11
T9
E20 M28 DQL5 VSS_12 DQL5 VSS_12
R416
DQL6 DQL6 DQL6
1K 1%
H7 H7 DQL7 H7 G2 G2
B1
M0_DDR_A15 VSSQ_1 DQL7 DQL7

VSSQ_1 VSSQ_1 DQL7 DQL6 DQL6
R410
1K 1%
B1 B1 B1 H7 H7
IO[19]/A-A15[AB-A15]/A-A3 IO[96]/B-A15[CD-A15]/B-A3 M1_DDR_A15 D7 B9 D7

DQU0
VSSQ_1
VSSQ_2
B9 D7
DQU0
VSSQ_1
VSSQ_2
B9
D7 B9
D7
C3
DQU0 VSSQ_2
B9
D1 D7
DQU0
VSSQ_1
VSSQ_2
B9
DQL7
VSSQ_1
B1
DQL7
VSSQ_1
B1 1%
E19 L28 M0_DDR_DQ8 DQU0
C3
DQU1 VSSQ_3
D1 C3
DQU1 VSSQ_3
D1
M0_DDR_DQ24
C8
DQU1
DQU2
VSSQ_3
VSSQ_4
D8 C3
DQU1 VSSQ_3
D1 D7
DQU0 VSSQ_2
B9 D7
DQU0 VSSQ_2
B9
10K
M0_DDR_BA0 IO[24]/A-BA0[AB-BA0]/A-A10 IO[88]/B-BA0[CD-BA0]/B-A10 M1_DDR_BA0 VSSQ_2 C8
C2
DQU2 VSSQ_4
D8
E2
C8
C2
DQU2 VSSQ_4
D8
E2 DQU0 VSSQ_2 C2
A7
DQU3 VSSQ_5
E2
E8
C8
C2
DQU2 VSSQ_4
D8
E2
C3
C8
DQU1 VSSQ_3
D1
D8
C3
C8
DQU1 VSSQ_3
D1
D8
C18 L31 C3 D1 A7
DQU3
DQU4
VSSQ_5
VSSQ_6
E8 A7
DQU3
DQU4
VSSQ_5
VSSQ_6
E8 C3 D1 A2
DQU4
DQU5
VSSQ_6
VSSQ_7
F9 A7
DQU3
DQU4
VSSQ_5
VSSQ_6
E8 C2
DQU2
DQU3
VSSQ_4
VSSQ_5
E2 C2
DQU2
DQU3
VSSQ_4
VSSQ_5
E2
R445
M0_DDR_BA1 M1_DDR_BA1 M0_DDR_DQ9 DQU1 VSSQ_3
A2
DQU5 VSSQ_7
F9 A2
DQU5 VSSQ_7
F9
DQU6 VSSQ_8
G1 A2
DQU5 VSSQ_7
F9 A7
A2
DQU4 VSSQ_6
E8
F9
A7
A2
DQU4 VSSQ_6
E8
F9
IO[20]/A-BA1[AB-BA1]/A-CASZ IO[92]/B-BA1[CD-BA1]/B-CASZ C8 D8
B8
A3
DQU6 VSSQ_8
G1
G9
B8
A3
DQU6 VSSQ_8
G1
G9
C8 D8
A3
DQU7 VSSQ_9
G9 B8
A3
DQU6 VSSQ_8
G1
G9 B8
DQU5 VSSQ_7
G1 B8
DQU5 VSSQ_7
G1
F19 K28 M0_DDR_DQ10 DQU2

M0_DDR_DQ26
DQU7 VSSQ_9
A3
DQU6 VSSQ_8
G9 A3
DQU6 VSSQ_8
G9
M0_DDR_BA2 IO[21]/A-BA2[AB-BA2]/A-BA0 IO[82]/B-BA2[CD-BA2]/B-BA0 M1_DDR_BA2 VSSQ_4 DQU2 VSSQ_4 DQU7 VSSQ_9 DQU7 VSSQ_9
C479
G22 N28 C2 E2 C2 E2 C472 M0_D_CLK
1%
M0_DDR_RASN M1_DDR_RASN M0_DDR_DQ11 DQU3 VSSQ_5 M0_DDR_DQ27 DQU3 VSSQ_5 0.1uF
1%
IO[15]/A-RASZ[AB-RASZ]/A-ODT IO[97]/B-RASZ[CD-RASZ]/B-ODT A7 E8 A7 E8 0.1uF C483 R412
F21 N27
R417
M0_DDR_DQ12 DQU4 VSSQ_6 M0_DDR_DQ28 DQU4 VSSQ_6 C474 56 C477
R411
M0_DDR_CASN IO[17]/A-CASZ[AB-CASZ]/A-WEZ IO[94]/B-CASZ[CD-CASZ]/B-WEZ M1_DDR_CASN A2 F9 A2 F9 1000pF 0.01uF
E21 L27 M0_DDR_DQ13 DQU5 M0_DDR_DQ29 1000pF 50V 1%
M0_DDR_WEN M1_DDR_WEN VSSQ_7 DQU5 VSSQ_7
1K
IO[16]/A-WEZ[AB-WEZ]/A-A12 IO[89]/B-WEZ[CD-WEZ]/B-A12 B8 G1 B8 G1 50V 50V
1K
F20 M27 M0_DDR_DQ14 DQU6 M0_DDR_DQ30
M0_DDR_ODT IO[25]/A-ODT[AB-ODT]/A-ACTZ IO[95]/B-ODT[CD-ODT]/B-ACTZ M1_DDR_ODT VSSQ_8 DQU6 VSSQ_8
C19 M31 A3 G9 A3 G9 R413
M0_DDR_CKE IO[18]/A-CKE[AB-CKE]/A-CKE M1_DDR_CKE M0_DDR_DQ15 DQU7 VSSQ_9 SS_DDR3_2Gb Hynix_DDR3_2Gb M0_DDR_DQ31 DQU7 VSSQ_9 56
IO[91]/B-CKE[CD-CKE]/B-CKE IC400-*3
K4B2G1646Q-BCMA
IC400-*4
H5TQ2G63FFR-RDC
F15 G32 1%
M0_DDR_RESET_N IO[1]/A-RST[AB-RST]/A-RST IO[76]/B-RST[CD-RST]/B-RST M1_DDR_RESET_N N3
EAN63667401
M8 N3
EAN63648701
M8
A20 N32 P7
A0
A1
VREFCA
P7
A0
A1
VREFCA
M0_D_CLK IO[28]/A-MCLK[AB-MCLK]/A-MCLKZ IO[101]/B-MCLK[CD-MCLK]/B-MCLKZ M1_D_CLK P3

N2
A2
H1
P3
N2
A2
H1
B20 M30 P8
P2
A3
A4
VREFDQ
P8
P2
A3
A4
VREFDQ
M0_D_CLKN
M0_D_CLKN IO[27]/A-MCLKZ[AB-MCLKZ]/A-MCLK IO[100]/B-MCLKZ[CD-MCLKZ]/B-MCLK M1_D_CLKN R8
A5
A6 ZQ
L8 R8
A5
A6 ZQ
L8
E15 G29 R2
T8
A7
R2
T8
A7
M0_DDR_CS1 IO[23]/A-CSB1[AB-CSB1]/A-CSB1 IO[99]/B-CSB1[CD-CSB1]/B-CSB1 M1_DDR_CS1 R3

L7
A8
A9 VDD_1
B2
D9
R3
L7
A8
A9 VDD_1
B2
D9
D15 F32 R7
A10/AP
A11
VDD_2
VDD_3
G7 R7
A10/AP
A11
VDD_2
VDD_3
G7
M0_DDR_CS2 IO[22]/A-CSB2[AB-CSB2]/A-CSB2 IO[98]/B-CSB2[CD-CSB2]/B-CSB2 M1_DDR_CS2 N7

T3
A12/BC VDD_4
K2
K8
N7
T3
A12/BC VDD_4
K2
K8
M7
A13
NC_5
VDD_5
VDD_6
VDD_7
N1
N9
T7
M7
A13
A14
NC_5
VDD_5
VDD_6
VDD_7
N1
N9 AVDD_DDR M1_DDR_CKE
R1 R1
VDD_8 VDD_8
M2 R9 M2 R9
BA0 VDD_9 BA0 VDD_9
N8 N8
BA1 BA1
M3 M3
BA2 BA2
A1 A1
C23 T31 J7
CK
VDDQ_1
VDDQ_2
A8 J7
CK
VDDQ_1
VDDQ_2
A8
M0_DDR_DQ0 M1_DDR_DQ0 K7 C1 K7 C1
AVDD_DDR
1K
R433
IO[47]/A-DQ[0][A-DQL0]/A-DQ[0] IO[120]/B-DQ[0][C-DQL0]/B-DQ[0] K9
CK VDDQ_3
C9 K9
CK VDDQ_3
C9 AVDD_DDR
B22 P30 CKE VDDQ_4
VDDQ_5
D2
CKE VDDQ_4
VDDQ_5
D2
M0_DDR_DQ1 IO[31]/A-DQ[1][A-DQL1]/A-DQ[1] IO[104]/B-DQ[1][C-DQL1]/B-DQ[1] M1_DDR_DQ1 L2 E9 L2 E9
+1.5V_Bypass Cap
CS VDDQ_6 CS VDDQ_6
K1 F1 K1 F1
OPT
1K
R422
+1.5V_Bypass Cap
ODT VDDQ_7 ODT VDDQ_7
B24 T30 J3
K3
RAS VDDQ_8
H2
H9
J3
K3
RAS VDDQ_8
H2
H9
M1_1_DDR_VREFDQ
M0_DDR_DQ2 IO[48]/A-DQ[2][A-DQL2]/A-DQ[2] IO[121]/B-DQ[2][C-DQL2]/B-DQ[2] M1_DDR_DQ2 L3
CAS
WE
VDDQ_9
L3
CAS
WE
VDDQ_9
C21 P31 NC_1

J1
NC_1
J1
M1_DDR_VREFDQ
M0_DDR_DQ3
B25
IO[29]/A-DQ[3][A-DQL3]/A-DQ[3] IO[102]/B-DQ[3][C-DQL3]/B-DQ[3]
U30
M1_DDR_DQ3 Close to DDR Power Pin T2
F3
RESET NC_2
NC_3
NC_4
J9
L1
L9
T7
T2
F3
RESET NC_2
NC_3
NC_4
J9
L1
L9
Close to DDR Power Pin
R414
1K 1%
DQSL NC_6 DQSL
R408
1K 1%
M0_DDR_DQ4 IO[50]/A-DQ[4][A-DQL4]/A-DQ[6] IO[123]/B-DQ[4][C-DQL4]/B-DQ[6] M1_DDR_DQ4 G3
DQSL
G3
DQSL
M1_DDR_RESET_N
C20 N31 C7
B7
DQSU VSS_1
A9
B3
C7
B7
DQSU VSS_1
A9
B3
M0_DDR_DQ5 IO[30]/A-DQ[5][A-DQL5]/A-DQ[7] IO[105]/B-DQ[5][C-DQL5]/B-DQ[7] M1_DDR_DQ5 E7
DQSU VSS_2
VSS_3
E1
G8 E7
DQSU VSS_2
VSS_3
E1
G8
C24 U31
R446
DML VSS_4 DML VSS_4
D3 J2 D3 J2
DMU VSS_5 DMU VSS_5
M0_DDR_DQ6 M1_DDR_DQ6
10K
J8 J8
IO[49]/A-DQ[6][A-DQL6]/A-DQ[4] IO[122]/B-DQ[6][C-DQL6]/B-DQ[4] E3
VSS_6
M1 E3
VSS_6
M1
1%
B21 N30 F7
DQL0
DQL1
VSS_7
VSS_8
M9 F7
DQL0
DQL1
VSS_7
VSS_8
M9
AVDD_DDR
M0_DDR_DQ7 IO[32]/A-DQ[7][A-DQL7]/A-DQ[5] IO[103]/B-DQ[7][C-DQL7]/B-DQ[5] M1_DDR_DQ7 AVDD_DDR
F2
F8
DQL2
DQL3
VSS_9
VSS_10
P1
P9
F2
F8
DQL2
DQL3
VSS_9
VSS_10
P1
P9
C22 R31 H3
H8
DQL4 VSS_11
T1
T9
H3
H8
DQL4 VSS_11
T1
T9 C516 C518
1%
M0_DDR_DM0 M1_DDR_DM0 DQL5 VSS_12 DQL5 VSS_12
1%
IO[33]/A-DQM[0][A-DML]/A-DQM[0] IO[106]/B-DQM[0][C-DML]/B-DQM[0] G2
H7
DQL6
G2
H7
DQL6
0.1uF 0.1uF
A23 T32 DQL7
B1
DQL7
B1 C519 M1_D_CLK
R415
C517
R409
VSSQ_1 VSSQ_1
M0_DDR_DQS0 IO[42]/A-DQS[0][A-DQSL]/A-DQS[0] IO[115]/B-DQS[0][C-DQSL]/B-DQS[0] M1_DDR_DQS0 D7
C3
DQU0 VSSQ_2
B9
D1
D7
C3
DQU0 VSSQ_2
B9
D1
1000pF R427
B23 R30 C8
C2
DQU1
DQU2
VSSQ_3
VSSQ_4
D8
E2
C8
C2
DQU1
DQU2
VSSQ_3
VSSQ_4
D8
E2
1000pF C497
M0_DDR_DQS_N0 IO[41]/A-DQSB[0][A-DQSLB]/A-DQSB[0] IO[114]/B-DQSB[0][C-DQSLB]/B-DQSB[0] M1_DDR_DQS_N0 A7
DQU3 VSSQ_5
E8 A7
DQU3 VSSQ_5
E8
50V 50V 56
1K
0.01uF
1K
A2 F9 A2 F9
B8
A3
DQU6
DQU7
VSSQ_8
VSSQ_9
G1
G9
B8
A3
DQU6
DQU7
VSSQ_8
VSSQ_9
G1
G9 1% 50V
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
D23 P27 R428

M0_DDR_DQ8 IO[35]/A-DQ[8][A-DQU0]/A-DQ[15] IO[109]/B-DQ[8][C-DQU0]/B-DQ[15] M1_DDR_DQ8 56
D26 U29 1%
E22 P28
C403
C404
C405
C400
C401
C402
D27 U27 M1_D_CLKN

M0_DDR_DQ11 IO[46]/A-DQ[11][A-DQU3]/A-DQM[1] IO[119]/B-DQ[11][C-DQU3]/B-DQM[1] M1_DDR_DQ11
F23 R28
E26 V28
D22 P29
E25 U28
E24 T28
M0_DDR_DM1 IO[37]/A-DQM[1][A-DMU]/A-DQ[14] IO[110]/B-DQM[1][C-DMU]/B-DQ[14] M1_DDR_DM1
D24 T27
M0_DDR_DQS1 IO[40]/A-DQS[1][A-DQSU]/A-DQS[1] IO[113]/B-DQS[1][C-DQSU]/B-DQS[1] M1_DDR_DQS1
E23 R27
M0_DDR_DQS_N1 IO[39]/A-DQSB[1][A-DQSUB]/A-DQSB[1] IO[112]/B-DQSB[1][C-DQSUB]/B-DQSB[1] M1_DDR_DQS_N1
M1_DDR_VREFDQ Hynix_DDR3_4Gb_29n
Hynix_DDR3_4Gb_29n M1_1_DDR_VREFDQ
C28 AA31 IC403 IC404
M0_DDR_DQ16 IO[69]/A-DQ[16][B-DQL0]/A-DQ[16] IO[145]/B-DQ[16][D-DQL0]/B-DQ[16] M1_DDR_DQ16 H5TQ4G63AFR-RDC H5TQ4G63AFR-RDC
C26 W31
B29 AA30
M0_DDR_DQ18 IO[70]/A-DQ[18][B-DQL2]/A-DQ[18] IO[143]/B-DQ[18][D-DQL2]/B-DQ[18] M1_DDR_DQ18 EAN63053201 EAN63053201
A26 W32
C29 AB31 M1_DDR_A0
N3
A0 DDR3 VREFCA
M8
M1_DDR_A0
N3
A0
DDR3 VREFCA
M8
M0_DDR_DQ20 IO[72]/A-DQ[20][B-DQL4]/A-DQ[22] IO[142]/B-DQ[20][D-DQL4]/B-DQ[22] M1_DDR_DQ20 P7 P7 4Gbit
M0_DDR_DQ21
C25
V31
M1_DDR_DQ21 M1_DDR_A1 A1 4Gbit M1_DDR_A1 A1
P3 P3
M0_DDR_DQ22
A29
AB32
M1_DDR_DQ22 M1_DDR_A2 A2 (x16) M1_DDR_A2 A2 (x16)
B26 V30 N2 H1 N2 H1
M0_DDR_DQ23 M1_DDR_DQ23 M1_DDR_A3 A3 VREFDQ M1_DDR_A3 A3 VREFDQ
IO[51]/A-DQ[23][B-DQL7]/A-DQ[21] IO[125]/B-DQ[23][D-DQL7]/B-DQ[21] P8 P8
B27 W30 M1_DDR_A4 A4 M1_DDR_A4
M0_DDR_DM2 IO[55]/A-DQM[2][B-DML]/A-DQM[2] IO[128]/B-DQM[2][D-DML]/B-DQM[2] M1_DDR_DM2 A4
B28 Y30 P2 P2
M0_DDR_DQS2 M1_DDR_DQS2 M1_DDR_A5 A5 M1_DDR_A5 A5
IO[64]/A-DQS[2][B-DQSL]/A-DQS[2] IO[137]/B-DQS[2][D-DQSL]/B-DQS[2] R8 L8 R404 R8 L8 R419
C27 Y31 M1_DDR_A6 240 M1_DDR_A6 240
M0_DDR_DQS_N2 IO[63]/A-DQSB[2]/[B-DQSLB]/A-DQSB[2] IO[136]/B-DQSB[2][D-DQSLB]/B-DQSB[2] M1_DDR_DQS_N2 A6 ZQ A6 ZQ
R2 AVDD_DDR R2

T8 T8 AVDD_DDR
E29 Y28 R3 B2 R3 B2
IO[58]/A-DQ[24][B-DQU0]/A-DQ[31] IO[131]/B-DQ[24][D-DQU0]/B-DQ[31] L7 D9 L7 D9
C31 AB27 M1_DDR_A10 A10/AP VDD_2 M1_DDR_A10
M0_DDR_DQ25 IO[67]/A-DQ[25][B-DQU1]/A-DQ[26] IO[141]/B-DQ[25][D-DQU1]/B-DQ[26] M1_DDR_DQ25 A10/AP VDD_2
R7 G7 R7 G7
E27 V27 M1_DDR_A11 A11 VDD_3 M1_DDR_A11

M0_DDR_DQ26 IO[56]/A-DQ[26][B-DQU2]/A-DQ[29] IO[130]_/B-DQ[26][D-DQU2]/B-DQ[29] M1_DDR_DQ26 A11 VDD_3
D31 AB29 N7 K2 N7 K2
M0_DDR_DQ27 M1_DDR_DQ27 M1_DDR_A12 A12/BC VDD_4 M1_DDR_A12 A12/BC VDD_4
IO[66]/A-DQ[27][B-DQU3]/A-DQM[3] IO[140]/B-DQ[27][D-DQU3]/B-DQM[3] T3 K8 T3 K8
D29 W28 M1_DDR_A13 A13 VDD_5 M1_DDR_A13
M0_DDR_DQ28 IO[59]/A-DQ[28][B-DQU4]/A-DQ[25] IO[129]/B-DQ[28][D-DQU4]/B-DQ[25] M1_DDR_DQ28 A13 VDD_5
D30 AB28 T7 N1 T7 N1
IO[65]/A-DQ[29][B-DQU5]/A-DQ[28] IO[139]/B-DQ[29][D-DQU5]/B-DQ[28] M7 N9 M7 N9
E28 W27 M1_DDR_A15 NC_5 VDD_7 M1_DDR_A15
M0_DDR_DQ30 IO[57]/A-DQ[30][B-DQU6]/A-DQ[27] IO[132]/B-DQ[30][D-DQU6]/B-DQ[27] M1_DDR_DQ30 NC_5 VDD_7
C30 AA27 R1 R1
M0_DDR_DQ31 IO[60]/A-DQ[31][B-DQU7]/A-DQ[24] IO[138]/B-DQ[31][D-DQU7]/B-DQ[24] M1_DDR_DQ31 VDD_8 VDD_8
B31 Y27 M2 R9 M2 R9
M0_DDR_DM3 M1_DDR_DM3 M1_DDR_BA0 BA0 VDD_9 M1_DDR_BA0 BA0 VDD_9
IO[68]/A-DQM[3][B-DMU]/A-DQ[30] IO[133]/B-DQM[3][D-DMU]/B-DQ[30] N8 N8
A31 AA28 M1_DDR_BA1 BA1 M1_DDR_BA1
M0_DDR_DQS3 IO[62]/A-DQS[3][B-DQSU]/A-DQS[3] IO[135]/B-DQS[3][D-DQSU]/B-DQS[3] M1_DDR_DQS3 BA1
B30 Y29 M3 M3
M0_DDR_DQS_N3 M1_DDR_DQS_N3 M1_DDR_BA2 BA2 M1_DDR_BA2 BA2
IO[61]/A-DQSB[3][B-DQSUB]/A-DQSB[3] IO[134]/B-DQSB[3][D-DQSUB]/B-DQSB[3] A1 A1
VDDQ_1 VDDQ_1
J7 A8 J7 A8
M1_D_CLK CK VDDQ_2 M1_D_CLK CK VDDQ_2
K7 C1 K7 C1
M1_D_CLKN CK VDDQ_3 M1_D_CLKN CK VDDQ_3
K9 C9 K9 C9
D2 D2
VDDQ_5 VDDQ_5
L2 E9 L2 E9
M1_DDR_CS1 CS VDDQ_6 M1_DDR_CS2 CS VDDQ_6
K1 F1 K1 F1
J3 H2 C468 0.1uF J3 H2 C490 0.1uF
M1_DDR_RASN RAS VDDQ_8 M1_DDR_RASN RAS VDDQ_8
K3 H9 C469 0.1uF K3 H9 C491 0.1uF
M1_DDR_CASN CAS VDDQ_9 M1_DDR_CASN CAS VDDQ_9
L3 L3
M1_DDR_WEN WE M1_DDR_WEN WE
J1 J1 * DDR_VTT
NC_1 NC_1
T2 J9 T2 J9
L1 L1
NC_3 NC_3
L9 L9 SS_DDR3_4Gb_25n
IC404-*1
Hynix_DDR3_4Gb_25n
IC404-*2
SS_DDR3_2Gb
IC404-*3
Hynix_DDR3_2Gb
IC404-*4
NC_4 NC_4 K4B4G1646D-BCMA H5TQ4G63CFR_RDC K4B2G1646Q-BCMA H5TQ2G63FFR-RDC
F3 F3 EAN63391401 EAN63053202 EAN63667401 EAN63648701
M1_DDR_DQS0 DQSL SS_DDR3_4Gb_25n

IC403-*1
Hynix_DDR3_4Gb_25n
IC403-*2
SS_DDR3_2Gb Hynix_DDR3_2Gb M1_DDR_DQS2 DQSL N3
A0 VREFCA
M8 N3
A0 VREFCA
M8 N3
A0 VREFCA
M8 N3
A0 VREFCA
M8
AVDD_DDR
G3 K4B4G1646D-BCMA H5TQ4G63CFR_RDC
IC403-*3
K4B2G1646Q-BCMA
IC403-*4
H5TQ2G63FFR-RDC G3 P7
P3
A1
A2
P7
P3
A1
A2
P7
P3
A1
A2
P7
P3
A1
A2
+3.3V_NORMAL
M1_DDR_DQS_N0 DQSL EAN63391401 EAN63053202 EAN63667401 EAN63648701 M1_DDR_DQS_N2 DQSL N2
P8
A3
A4
VREFDQ
H1 N2
P8
A3
A4
VREFDQ
H1 N2
P8
A3
A4
VREFDQ
H1 N2
P8
A3
A4
VREFDQ
H1
N3 M8 N3 M8 N3 M8 N3 M8 P2 P2 P2 P2
A0 VREFCA A0 VREFCA A0 VREFCA A0 VREFCA A5 A5 A5 A5
P7 P7 P7 P7 R8 L8 R8 L8 R8 L8 R8 L8
C7 A9
P3
N2
P8
A1
A2
A3 VREFDQ
H1
P3
N2
P8
A1
A2
A3 VREFDQ
H1
P3
N2
P8
A1
A2
A3 VREFDQ
H1
P3
N2
P8
A1
A2
A3 VREFDQ
H1
C7 A9
R2
T8
R3
A6
A7
A8
ZQ
B2
R2
T8
R3
A6
A7
A8
ZQ

Service Manual LG 43UF640

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Service Manual LG 43UF640

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Internal Use Only

North/Latin America http://aic.lgservice.com

MODEL : 43/49UF640* 43/49UF640*-ZA

P/NO : MFL69305903 (1506-REV00) Printed in Korea

SAFETY PRECAUTIONS ......................................................................... 3

EXPLODED VIEW ................................................................................... 30

SCHEMATIC CIRCUIT DIAGRAM ............................................ APPENDIX

TROUBLE SHOOTING GUIDE ................................................. APPENDIX

IMPORTANT SAFETY NOTICE

General Guidance Leakage Current Hot Check (See below Figure)

Before returning the receiver to the customer,

always perform an AC leakage current check on the exposed

Leakage Current Cold Check(Antenna Cold Check)

Fuse and Conventional Resistor

1. Application range 3. Test method

1) Temperature: 25 °C ± 5 °C(77 °F ± 9 °F), CST: 40 °C ± 5 °C

4. Model General Specification

DTV (MPEG2/4, DVB-T) : 26 countrie

DTV (MPEG2/4, DVB-T2) :11 countries

DTV (MPEG2/4, DVB-C) : 37 countries

Supported satellite : 35 satellites

No. Resolution H-freq(kHz) V-freq.(kHz) Pixel clock(MHz) Proposed Remarks

In case of keeping module is in the circumstance of 0 °C, it

In case of keeping module is in the circumstance of below

3.3.1. Equipment setting

3.5.2. Check the method of CI+ key value(RS232)

4) Check the model name Instart menu. → Factory name

* Checksum(HDMI 1/2) EDID Block 1, Bytes 128-255 [80H-FFH]

EDID Block 1, Bytes 128-255 [80H-FFH]

EDID Block 1, Bytes 128-255 [80H-FFH]

mode. (Warm, Medium, Cool)

4.3.7. EDGE & IOL LED White balance table

4.4. Local Dimming Function Check

2) Check the sound from the TV Set. 6. Audio

4.10. Ship-out mode check (In-stop)

(4) Updating is starting.

* After downloading, have to adjust Tool Option again.

Only for training and service purposes

LG Electronics. Inc. All rights reserved.

OPTIC SPDIF OUT

LGE Internal Use Only

Only for training and service purposes

LG Electronics. Inc. All rights reserved.

LGE Internal Use Only

Only for training and service purposes

URSA I2C_SDA7 8 lane

LG Electronics. Inc. All rights reserved.

LGE Internal Use Only

Only for training and service purposes

LG Electronics. Inc. All rights reserved.

LGE Internal Use Only

Only for training and service purposes

LG Electronics. Inc. All rights reserved.

Tuner TU_CVBS_TU TU_CVBS

TUNER_SIF, IF_P/N_TU TUNER_SIF, IF_P/N

LGE Internal Use Only

SCART_L/ Rout IC6000 DTV/MNT_L/R_OUT

Only for training and service purposes

LG Electronics. Inc. All rights reserved.

LGE Internal Use Only

Only for training and service purposes

LG Electronics. Inc. All rights reserved.

LGE Internal Use Only

Only for training and service purposes

4) Check the model name Instart menu. → Factory name