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Application Note 1020

Green Mode PWM Controller AP3101


-- Function Description and Design Consideration

Prepared by Wu Quanqing
System Engineering Dept.

Introduction
With the development of power technology, the Owing to low start-up current of 30µA and low oper-
demand for low standby power in power systems has ating current of 3mA, the AP3101 can reduce standby
increased. The AP3101 is a green current mode PWM power dissipation of the startup resistor, and improve
controller. Its input power can be less than 0. 3W in operating efficiency. In addition, totem driver output
265V AC input at no load condition. The target stage with 0. 6A current capacity is helpful for driving
AP3101 application fields consists of LCD Monitor/ MOSFET directly.
TV and other off-line AC-to-DC adapters.
With the built-in limited power control, the AP3101
This application note includes a general description, can turn off the PWM output after 23 ms in overload or
detailed description of major functions, and provides short circuit conditions, and the input power of a
notes for typical applications in SMPS. SMPS can drop close to zero. Also, the perfect protec-
tion against over-temperature is automatically per-
formed. Furthermore, leading edge blanking (LEB)
1. General Description technology is included in the AP3101 for noise immu-
The AP3101 acts as a programmable fixed frequency
nity; built-in slope compensation ensures the stability
PWM control during normal operation, and an external
of peak current mode control.
resistor is used to set the osillating frequency. When
output power of a SMPS falls below the given level,
Figure 1 is the functional block diagram of AP3101.
the IC automatically enters the skip cycle mode to
Figure 2 is AP3101's Pin Configuration.
reduce power consumption.

VCC
1
GND
ON/OFF
Driver 8
Q D GATE

CLK OSC
RB Short circuit
Protection
4 6V
RI
OTP Skip Cycle 4R
5 ADJ
R
6V
PWM
3 Internal Bias 2
VIN FB
2R
7 R
VCC Slope
UVLO Current Limit
Compensation

16V/10V 6
LEB SENSE
0.85V

Figure 1. Functional Block Diagram of AP3101

Jan. 2008 Rev. 1. 3 BCD Semiconductor Manufacturing Limited

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Application Note 1020
rent. When load power drops to a lower level, the VFB
decreases as well as the peak switch current. If peak
current drops to a given set point where the non-invert-
GND 1 8 GATE
ing voltage of the skip cycle comparator (VFB-0. 9V) is
FB 2 7 VCC lower than its inverting input (VADJ), the AP3101 will
VIN 3 6 SENSE enter skip cycle mode and start to blank its output
pulse.
RI 4 5 ADJ
144 RADJ 24 RADJ
VADJ = ( 96 + (V
) )
24 + RADJ 24 + RADJ
Figure 2. Pin Configuration of AP3101

ADJ
2. Pin Descriptions
GND (pin 1) The combined control circuitry and
power ground. AP3101 RADJ

FB (pin 2) The feedback voltage pin is connected to


GND
the external opto-coupler, and its typical source current
is 1. 3mA. This FB pin together with the current sense
pin will determine the PWM duty cycle.
Figure 3. RADJ(KΩ) Sets The Skip Cycle Point
VIN (pin 3) The pin is shorted to the VCC internally. It
can be pulled high to the rectified line input through a
resistor for startup.

RI (pin 4) Frequency set pin. A resistor between the RI


and GND will generate a constant current source, and
the current source will determine the oscillating fre-
quency by charging an internal capacitor.

ADJ (pin 5) An external resistor from this pin to


ground can adjust the voltage level when the system
enters the skip cycle mode.

Sense (pin 6) It is used for current mode control and


pulse-pulse current limit. A voltage proportional to the
inductor current is connected to this pin. Figure 4. The Skip Cycle Waveform

VCC (pin 7) The power supply for the device. Figure 4 illustrates the actual skip cycle waveform at
the gate pin. The power transfer now depends upon the
GATE (pin 8) The PWM output directly drives the length of the pulse bunches. Suppose we have the fol-
gate of MOSFET. lowing component values:
LP, primary inductance: 1mH;
3. Function Descriptions fS, oscillating frequency: 65kHz;
3. 1 Green Mode IP: 200 mA.
In normal operation with heavy load, the AP3101 At light load, the converter will enter the DCM
works at a fixed switching frequency, and the voltage mode. And the theoretical power transfer is therefore:
on the FB pin (VFB) corresponds to a larger peak cur- 0. 5*LP*IP2*fS=1. 3W.

Jan. 2008 Rev. 1. 3 BCD Semiconductor Manufacturing Limited

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Application Note 1020
If the device enters the skip cycle mode with a bunch
length of 15 ms over a recurrent period of 100 ms,
then the total power transfer is: 1. 3*15/100= 195 mW. 120

Oscillator Frequency (kHz)


3. 2 Start-up 100
For low standby power, the high resistance value of
the startup resistor is selected. However, it will cause
80
longer startup time. To reduce the startup time, we can
use a speedup startup circuit. The value of capacitor
C1 should be less than capacitor C2. (see Figure 5) 60

Moreover, the value of C1 and C2 should be selected 40


carefully in the actual design. Once the AP3101 starts 15 18 21 24 27 30 33 36 39 42

to work, the C2 will be charged by the transformer but Timing Resistor (kΩ)

the voltage for C1 will reduce rapidly because startup


current can't maintain the IC operation current. So, the
Figure 6. Frequency vs. Timing Resistor
C2 should also be charged as quickly as possible. Thus
the power of C2 through a transformer can take over The recommended oscillation range frequency is 50
the C1 smoothly and the output voltage will not drop kHz to 100 kHz. (see Figure 6)
or repeat many times during the startup process.
A small capacitor (not over 50pF) connected in par-
At last, the design of RSTART should meet the limi- allel with resistor RI can be utilized to avoid noise.
tation of IC startup condition and maximum voltage
operation condition with its maximum load, which 4. 4 Output Driver
always indicates the maximum and minimum equiva- Totem-pole output stage can directly drive MOS-
lent resistor of IC (V/I). FET, and its maximal output voltage is clamped at
22V. In addition, typical rise and fall time of output
pulse is 250ns and 50ns respectively.
Line VDC
4. 5 The Compensation.
RSTART The normal compensation mode is illustrated as
VCC Figure 7. Its feedback compensation network transfer
D1 D2 R1 function can be deduced as :

AP3101 C1 C2 VF B(s) RB 1 1 + s(R1 + RC )C1


GFB(s) = = ⋅ ⋅
VO(s) C1 R1 RD s 1 + sRB C B
GND

1
fP =
2πRB C B
Figure 5. Speedup Start-up Circuits
1
fZ =
4. 3 Oscillator 2π ( R1 + RC )C1
A resistor RI between RI and GND will generate a
constant current source, and the current source will In general design, the crossover frequency fC of the
determine the oscillating frequency by charging an power system can be determined with the main power
internal capacitor. parameter design. Then, we can place a compensator
zero (fZ) around fC/3 and place a compensator pole
The oscillating frequency can be expressed as: (fP) above 3fC. Thus, we can obtain a good response
feature and stability margin. In addition, the output LC
1690
f ≈ (kHz )
RI [kΩ]

Jan. 2008 Rev. 1. 3 BCD Semiconductor Manufacturing Limited

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Application Note 1020
filter should enable to bring some amount of phase Therefore, 0. 5 to 1kHz of skip cycle frequency is pre-
shift and should be considered for real application. ferred to compromise between standby power and
audio noise. In addition, the adhesives in the trans-
VO
former construction are required.
Vref

RD The snub capacitor C2 is another noise source.


RB
VFB Polypropylene capacitor can greatly reduce this noise.
AP3101 R1
FB (see Figure 8)
Rbias
CB
5. 3 PCB Layout
GND RC
C1 PCB layout is a critical portion of switching power
supply. Improper layout will adversely affect RFI radi-
R2
ation, component reliability, efficiency and stability.

Figure 7. AP3101 Normal Compensator with AZ431 Within an adapter, there are four major current
loops. Two of the loops conduct the high-level AC
4. 6 Over Temperature Protection currents needed by the supply. They are the power
The AP3101 will automatically turn off the PWM switch AC current loop and the output rectifier AC
output when junction temperature rises up to a given current loop. The currents are the typical trapezoidal
current pulses with very high peak current and very
value; the typical value is 150oC, with hysteresis of
rapid di/dt. The other two current loops are the input
25oC. source and the output load current loops, which carry
low frequency current being supplied from the voltage
5. Adapter Application source to and from the load respectively.
5. 1 How to Reduce Standby Power
First, a high value for the startup resistor is selected For the power switch AC current loop, current flows
to lower loss. In Figure 8, a start-up resistor R1 of from the input filter capacitor through the transformer
1.5MΩ is selected to ensure that VCC hold up capaci- winding and the power switch then back to the nega-
tor C3 is charged up to 16V even under low line volt- tive terminal of the input capacitor. Similarly, the out-
age of 85VAC, and the maximum power loss on R1 is put rectifier current loop's current flows from the
90mW. Once the AP3101 begins to work, an auxiliary secondary transformer winding, through the rectifier
winding of the transformer T1 will provide operating to the output filter capacitor and back to the winding.
current for the IC. The filter capacitors are the only components that can
source and sink the large levels of AC current in the
Second, adjusting the skip cycle level can reduce time needed by the switching power supply. The PCB
switching loss on MOSFET. The resistor RADJ on pin traces should be made as wide and as short as possible,
ADJ is used to adjust the skip cycle frequency; a which can minimize parasite resistive and inductive
larger resistor corresponds to a lower skip cycle fre- effects. These traces should be laid out fistly. As for
quency, so lower input power can be obtained. How- the input source and output load current loops, both of
ever, with the larger resistor it also needs a larger VCC these loops must be connected directly to their respec-
hold-up capacitor and the peak switching current will tive filter capacitor's terminals. All the current path
also become larger correspondingly. Also, a low-value loops, particularly with high frequency switching,
capacitor can't provide enough energy to the AP3101 should be as short as possible. Thus it will reduce the
at light load condition or less. so-called conduction or radiation interference.

5. 2 How to Avoid Audio Noise The grounds are extremely important to the proper
The transformer T1 is the main noise source. Under operation of the switching power supply. The analog
light or no load, the AP3101 will operate in skip cycle control ground should be connected first and then
mode with lower switching frequency, and audio noise connected to other circuitry. "One point grounding"
from the transformer T1 will probably be heard. must be used. Single-point grounding keeps the noise
sources separated from the sensitive control circuits.

Jan. 2008 Rev. 1. 3 BCD Semiconductor Manufacturing Limited

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Application Note 1020
Care must be taken that pin ADJ and pin RI are placed
away from noise sources which are sensitive or may
disturb the signal.

NTC R9
BD1

C5
R1 C1 R2 C2 J2
J1 T D3 L2

D1 C7
C6
C3 12V/3A

R3 D2

R4
Q1
7N60

R10
C8

R6
R7 0.5 R11

8 7 6 5
GATE VCC SENSE ADJ R12 Q2
AZ431
U1
AP3101
R13
620
GND FB VIN RI
1 2 3 4
R8 U2 p521
4 1
3 2
Cb

Figure 8. Typical Application of AP3101

Jan. 2008 Rev. 1. 3 BCD Semiconductor Manufacturing Limited