Design and Analysis of a Symmetric Phase Locked
Loop for Low Frequencies in 180 nm Technology
Prakriti Arya, Dinesh Jangid, Shree Prakash Tiwari1 and Mahima Arrawatia2
Department of Electrical Engineering, Indian Institute of Technology Jodhpur,
Jodhpur, Rajasthan- 342011
Email: 1 sptiwari@iitj.ac.in, 2 mahima@iitj.ac.in
Abstract—Design of a stable Phase Locked Loop (PLL)
working in MHz frequency range is proposed. Focus of this
work is to achieve a symmetric design, where rise and fall
time are equal for low operating frequencies. All the blocks of
PLL i.e Phase Frequency Detector (PFD), Charge Pump and
Loop Filter (CPLF), Voltage Controlled Oscillator (VCO) and
Frequency Divider (FD) are carefully designed and integrated.
PFD is implemented using D flip-flop and is made to detect
minimal phase errors. CPLF has differential design for noise
immunity and for avoiding floating conditions. The 15 stage VCO
gives frequency range of 30 MHz to 200 MHz for input voltage
range of 0.5 V to 1.05 V with a resistor for optimizing linearity.
The integrated PLL is stable in the output frequency range of
44 MHz to 200 MHz for given input frequency range of 11 MHz
to 50 MHz. The designs are implemented in 180 nm technology
and for a supply voltage of 1.8 V.
Keywords—linearity, low frequency, phase locked loop, sym-
metricity, zero deadzone
I. I NTRODUCTION
Phase Locked Loop (PLL) is a primary circuit that is
used in communication systems widely and find applications
in clock generation and data recovery, frequency synthe-
sizing, demodulating frequencies in receivers etc [1]. It is
a unique feedback system in itself because it is based on
phase/frequency errors unlike signal amplitudes found in most
systems. Because of its usefulness in variety of applications,
various PLL designs are proposed that helps in improving
many parameters including size, stability, power, operating
frequency [2], [3], [4].
PLL in operation consists of four primary blocks: Phase
Frequency Detector (PFD), Charge Pump and Loop Filter
(CPLF), Voltage Controlled Oscillator (VCO) and Frequency
Divider (FD) as shown in Fig. 1. The PFD compares two
incoming signals, reference input frequency (ref clk) and VCO
output frequency (vco clk). The obtained phase/frequency
difference is detected and given as an input to CPLF which
generates appropriate control voltage that modifies the VCO
frequency according to the error. The main purpose of CPLF
is to convert digital logic output of phase detector to analog
values and remove any high frequency components and ripples
in the output. The design and type of CPLF often depends upon
the type of phase detector used. VCO converts the generated
control voltage into appropriate output frequency. With time,
this frequency adjusts itself according to the input and thus,
minimizes the error to match the reference frequency. When
978-1-5386-1716-8/17/$31.00 
c 2017 IEEE
both frequencies are equal, the PLL goes into ’lock’ condition
[5], [6].
Fig. 1: Basic block diagram of PLL
A conventional tri-state PFD is build using D flip-flops
and AND gate. The main drawbacks of this type of PFD are
deadzone and blindzone. Deadzone occurs when the two inputs
have a minute phase/frequency difference such that the PFD
is unable to detect it and therefore, the PLL gets locked to an
incorrect phase or frequency in that region [7]. Another case i.e
blindzone, occurs when the phase/frequency difference reaches
around 2π, because of which the error detection range of PFD
decreases [8]. Many topologies of PFD have been proposed in
order to simplify the circuit, reduce the deadzone and increase
the error detection range [8]. [9]. The PFD implemented here
has no extra circuitry but it shows zero deadzone and is ideal
for detecting minute phase/frequency errors because of low
frequency operation. Also at low operating frequencies, it is
able to detect errors close to 2π.
A typical VCO efficiently controls the working of PLL.
It has to satisfy many design requirements like tuning range,
tuning linearity, supply and common mode rejection etc. Lin-
earity is an important parameter required for ideal VCO design
[10]. VCO can be designed using LC resonant circuits or
ring oscillators. Current Starved VCO (CS-VCO) is a popular
area of research nowadays [11], [12], [13]. It has favorable
properties like less jitter, less area requirement and a wide
tuning range [14], [15]. It is a modified ring oscillator but with
more control on current in hand. FD divides the VCO output
frequency to get the required range of output frequencies. As
a frequency synthesizer, it is especially required to generate
very stable and accurate clock at high frequency ranges where
quartz crystal fails because of its low frequency operation. The
whole PLL is integrated in the end with all the symmetrically
designed blocks.
 II. D ESIGN OF B LOCKS AND I NTEGRATION its error detection range. The phase difference vs voltage
characteristics with and without deadzone are shown in Fig. 3
A. Symmetric Inverter Design
[9]. For eliminating deadzone, the reset path of the PFD should
In order to design symmetric circuits, it is crucial to have have a requisite delay that can make the pulses wide enough
equal rise and fall time of outputs. Symmetric inverter is to switch on the charge pump. If the switches are getting on
an important design requirement for all the blocks of PLL. even when there is no phase difference then the PFD is able
Symmetricity can be achieved by choosing the ratio of widths to detect even minute errors easily. Ideally, the conventional
(β) of PMOS and NMOS such that charging and discharging PFD has a linear phase detection range from -2π to +2π. Due
currents are almost the same [16]. For Semi-Conductor Labora- to some non idealities like delay in reset path, the PFD fails
tory Process Design Kit (SCL-PDK), this ratio was decided by to detect the positive edges of clock pulses and thus the range
analyzing DC Characteristics of only PMOS and only NMOS. reduces to 2π-Δ as shown in Fig. 4 [7]. This invisible region
It was found that for VGS at 0.9 V, drain current (ID ) for (Δ) where PFD cannot detect the phase errors is often termed
NMOS saturates to about 48 μA and for PMOS it saturates to as blindzone [8]. The blindzone is a function of reset time
about 12 μA and the ratio of width at which PMOS current and reference frequency as given in Eq.1. So for decreasing
equalize to NMOS current is 3.45. Hence, ratio of widths of blindzone, best way is to have a low operating frequency since
PMOS to NMOS can be taken as approximately 3.45 to 4 for high reset time is required for removing deadzone.
symmetric design. The proposed circuits are designed with the
ratio of 3.45. Treset
Δ = 2π ∗ (1)
Tref clk
B. Design of PFD
A conventional tri-state PFD detects both phase and fre-
quency errors. It consists of two edge triggered D flip-flops
with an AND gate whose output is a feedback to reset the
flip-flops as shown in Fig. 2 [6]. For low frequency range, a
positive edge triggered D flip-flop in master slave configuration
with extra inputs like preset (to set) and clear (to reset) is used.
The master and slave latches are symmetric NAND Gate based
latches which are able to drive some load capacitance. The
output of flip-flop follows input pulse at each positive edge
of a clock pulse. The inputs D of flip-flops are connected to (a) Zero deadzone (b) Finite deadzone
VDD (logical High ’1’) and the clock inputs are connected to
reference clock frequency (ref clk) and VCO clock frequency Fig. 3: Phase error vs average output voltage characteristics
(vco clk) respectively. When the ref clk leads vco clk in of PFD showing deadzone
phase or frequency, Up output goes high and when vco clk
leads ref clk, Down output goes high. When both the outputs
are high, output of AND gate goes high and resets the flip-
flops. Due to this, the outputs Up and Down go low again [5].
Table I shows all the states of PFD [17].

(a) Ideal curve (b) Non ideal curve with Blindzone

Fig. 4: Phase error vs average output voltage characteristics

of PFD showing blindzone

Fig. 2: A conventional tri-state PFD C. Charge Pump and Loop Filter (CPLF)
It consists of mainly current sources and switches. It
converts the digital output from PFD into an appropriate
current signal which is then integrated through a loop filter
TABLE I: PFD Input and Output States
to generate control voltage for CS-VCO. A typical CPLF with
PFD Outputs PFD Inputs differential design is shown in Fig. 5 which offers two poles
Up = 0, Down = 0 Both input frequencies are matched for the closed loop PLL, where one is at origin. The amount of
Up = 1, Down = 0 ref clk leads vco clk control voltage depends on the pulse width of the input signals.
Up = 0, Down = 1 vco clk leads ref clk This design is preferred because it is immune to variations
from power supply or ground [5]. Moreover, there is always a
Deadzone and Blindzone are the two important phase direct path for current to flow from source to output or from
characteristics of PFD that makes it erroneous and decrease output to sink, which avoids floating condition.
 applications. A classical method to divide the frequencies is
by using an arrangement of flip-flops [18]. An edge triggered D
flip-flop serves the purpose by dividing the incoming frequency
by 2. Here 2 D flip-flops are used to divide the frequency by
4 for scaling purpose as shown in Fig. 7.

Fig. 7: Divide by 4 frequency divider

Fig. 5: Differential CPLF F. PLL Integration

The present work focuses on design of type 2 and order 3
PLL. Total number of poles at origin are 2 (type 2) and total
D. CS-VCO Design number of poles in the closed loop PLL are 3 (order 3). Once
the individual blocks are designed, they are integrated together
The design of CS-VCO is shown in Fig. 6. It offers one
to form a whole PLL system [5].
pole at origin for the closed loop PLL. For MHz frequency
range, a 15 stage ring oscillator is used where last stage is Gain of PFD is given by KP F D . It’s value is
connected as feedback to the first stage. One more inverter
VDD 1.8
is added after the last stage to remove non idealities from KP F D = = = 0.286 (2)
the feedback loop and produce more accurate waveform. 2.π 2.π
Transistors M5 and M6 produce a drain current which is
mirrored in each following stage. Changing the power supply Gain of VCO is given by KV CO . It’s value in radians is
changes the current and hence the frequency of oscillation. KV CO = 2.π ∗ 309M Hz/V = 1941.5M radians/V s (3)
Here, the transistors M1 and M4 help to change the current
through the inverter stages and thereby changing the frequency Transfer function for loop filter neglecting C2 is
of oscillation. This makes it possible to vary the frequency with 1 + sRC1
an input control voltage. The gain of VCO is made constant TF = (4)
sC1
over a large range by adding resistor and wide NMOS M7. The
resistor helps in controlling the frequency of VCO more easily
Then the total feedback loop transfer function is
as the desired frequency range can be obtained by altering its
value. The width of NMOS M7 is increased so that dependency KP F D KV CO Ipump (1 + sRC1 )
of its gate to source voltage on control voltage is reduced and T = KP F D KV CO Ipump
(5)
s2 + s( KP F DN
KV CO R
)+ N C1
is approximately equal to threshold voltage [5].
This is a second order transfer function. The natural
frequency ωn is given by

KP F D KV CO Ipump
ωn = (6)
N C1
where N is the FD scaler value and damping factor ζ is given
by
ωn
ζ= .RC1 (7)
2
The lock range ωL is given by
ωL = 4πζωn (8)
Fig. 6: CS-VCO
Initially, for designing purpose, some lock range has to be
assumed. Generally it should be more than the required range
to account for any discrepancies in the corner values. Lock
E. Frequency Divider
range (ωL ) is assumed to be 55 MHz for a possible range of
PLL is generally assumed as a good source of generating 50 MHz. For stability, damping factor (ζ) is chosen as 1.
frequencies and is used as a frequency synthesizer in many
 Putting the value of ωL in Eq. 8, natural frequency ωn is Similarly, when the two incoming signals are different in
found to be frequencies, the output pulses vary according to the positive
edges of input signals, as shown in Fig. 9. Here ref clk is 50
ωn = 26.5 × 106 radians/V.s (9) MHz and vco clk is 200 MHz with a little delay of 2 ns.

Putting the value of ωn and ζ = 1 in Eq. 7, following result

is obtained
RC1 = 50ns (10)

R and C1 values are chosen as R = 5 KΩ and C1 = 10 pF.

C2 should be chosen less than that of C1 [5]. Generally, it is
half to one-tenth of value of C1 ; so here C2 is 5 pF.
So from all the parameters given above, Ipump can be
calculated by Eq. 6 which is found out to be 50 μA.
These values are used for CPLF and mentioned in Table II.
Once all the values of the required parameters are calculated,
PLL is integrated to study its behavior.

III. RESULTS AND DISCUSSION

A. PFD Results Fig. 9: Input and output states of PFD when input
Although the highest operating frequency of PFD is 50 frequencies are different
MHz, the implemented PFD is easily operable for frequencies
up to 200 MHz. The transient analysis is done for various
input test cases as mentioned in Table 1 where both incoming Because of the wider reset pulse width or glitches, the PFD
frequencies are set at 50 MHz (time period 20 ns). has zero deadzone and also negligible blindzone as shown in
When both input frequencies are perfectly matched, the Fig. 10. At low operating frequencies, the PFD is able to show
Up and Down outputs will show some glitches as shown in variations in output voltage for any phase difference between
Fig. 8. Ideally, the output pulses should be zero but in D flip- inputs and also the error detection range of PFD goes from -2π
flop based circuits, the glitches remain. These glitches have to +2π (20 ns here). Hence, both the drawbacks are eliminated
an added advantage in reducing the deadzone. If the pulses easily. Also, the maximum power dissipation of PFD is around
are sufficiently wide enough to drive the switches of charge 600 μW at 50 MHz.
pump, then the PFD will be able to detect minimal differences
easily [6]. The PFD proposed here is doing the same, the pulse
widths of Up and Down are 1.6 ns, which are too wide for
a charge pump circuit to detect easily. Also, when both the
pulses are high, flip flops are reset and the reset pulse width
is 1.4 ns. The output pulses are delayed by 630 ps.

Fig. 10: Output characteristics of PFD showing zero

deadzone and blindzone

B. CPLF Results
The values of various parameters with reference to Fig.
5 are given in Table II. It uses the symmetric inverter for
inversion of signals. Values are chosen in such a way that
Fig. 8: Input and output states of PFD when both frequencies devices related to current reference are in saturation. Power
match dissipation is found to be 215 μW on an average.
 TABLE II: Parameter values of components used in
differential CPLF
Parameter Value
Width of PMOS M1, M2, M3 4 μm
Length of PMOS M1 0.18 μm
Length of PMOS M2, M3 0.54 μm
Width of NMOS M0, M4, M5, M6 1 μm
Length of NMOS M0 0.18 μm
Length of NMOS M4, M5, M6 0.54 μm
Value of Current Source Ipump 50 μA
Value of Resistor R 5 kΩ
Value of Capacitor C1 10 pF
Value of Capacitor C2 5 pF

When only Up output from PFD is high and Down output Fig. 11: Frequency vs input voltage for 15 stage CS-VCO
is low, then control voltage goes high. For the opposite case,
the control voltage goes low. This can be seen in the control
voltage waveform (Vcontrol ) in Fig. 12.
D. PLL Integration Results

C. CS-VCO Results
The values of various parameters used in design of 15 stage
CS-VCO with reference to Fig. 6 are given in Table III. Some
amount of load capacitance is considered at the end of each
inverter stage. The value of resistor is chosen as 4 kΩ.
The simulation curves of PLL outputs for input frequency
of 11 MHz is shown in Fig. 12. It can be seen that after some
pull in time of 700 ns, PLL starts becoming stable at this
frequency. Power dissipation is found to be around 400 μW
here.

TABLE III: Parameters used in design of CS-VCO

Parameter Value (μm)
Width of current starved PMOS (M4) 1.45
Width of current starved NMOS (M1) 0.42
Width of PMOS in inverter stage (M3) 1.45
Width of NMOS in inverter stage (M2) 0.42
Width of M5 0.42
Width of M6 0.65
Width of M7 4.2
Width of M8 1.45
Length of all transistors 0.18

Width of M6 is chosen in such a way that rise and fall

time of the output waveform are almost the same and design
becomes symmetric. The values of rise time and fall time
analyzed at three different input control voltages are given in
Table IV.
Fig. 12: Simulation result of PLL for input frequency of 11
TABLE IV: Rise time and fall time values for different MHz
inputs in 15 stage CS-VCO
Input Voltage (V) Rise Time (ps) Fall Time (ps)
1.8 168 179 The simulation curves of PLL outputs for input frequency
1.0 210 197 of 50 MHz is shown in Fig. 13. This is the maximum input
0.5 854 841 frequency possible for PLL when considering VCO linear
range. It can be seen from the figure that the Vcontrol is
showing overdamped nature which signifies stability.
The variation of output frequency with respect to input
voltage is shown in Fig. 11. Gain of VCO is constant for a Thus, overall PLL is found to be stable from 11 MHz to 50
wide range of 0.5 V to 1.05 V. Frequency varies from 30 MHz MHz of input frequency and 44 MHz to 200 MHz of output
to 200 MHz approximately in the linear range. Gain of VCO frequency. However, PLL will work till 232 MHz, which is
here is 309 MHz/V. the highest frequency of VCO, but it will be completely stable

Fig. 13: Simulation result of PLL for input frequency of 50
MHz
in the given range only. Maximum power dissipation is found
to be approximately 1 mW at output frequency of 200 MHz.
IV. C ONCLUSION
A symmetric design of PLL (type 2, order 3) in the output
frequency range of 44 MHz to 200 MHz for input frequency
range of 11 MHz to 50 MHz is demonstrated. The design
is implemented in 180 nm technology using SCL-PDK with
power supply of 1.8 V. All the blocks are found to be almost
symmetric in terms of rise time and fall time variations.
Maximum power dissipation is found to be approximately 1
mW for 200 MHz frequency. The performance of individual
blocks is also discussed. The symmetrical PFD has zero
deadzone and error detection range from -2π to +2π at highest
input frequency of 50 MHz, with a power dissipation of 600
μW. Values of various parameters for CPLF are extracted using
design equations and transfer function of closed loop PLL.
Loop filter values are chosen to ensure stable PLL design.
Power dissipation for CPLF is found to be 215 μW on an
average for all the possible cases. VCO exhibits a high gain
of 309 MHz/V and decent linearity is achieved in the tuning
range from 30 MHz to 200 MHz for an input control voltage
variation from 0.5 V to 1.05 V. Maximum power dissipation
is found to be under 500 μW at 200 MHz frequency.
ACKNOWLEDGMENT
The authors would like to thank Semi-Conductor Labora-
tory (SCL) for providing the PDK that is used in the design of
all the circuitry. This work is sponsored by Special Manpower
Development Program for Chip to System Design (SMDP-
C2SD) Project, an initiative of Ministry of Electronics and
Information Technology (MeitY).
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