Advanced Node Experience From Cadence

Confidential
Advanced Node Experience Sharing
DSG Cadence
2016.10.13
16FF+
Process Evolution N10
N7
2012 2013 2014 2015 2016 2017
16FFP N10 Node N7 Node

Vertical Edge
FinFet Trim Metal
Constraint
DPT (soft) / G0 Fixed Color

M0
Wider wrong No wrong way
way width routing
Horizontal Edge Rect only on “dirty” std. cell
Constraint Mx/Mxa
2 © 2015 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
N7 Node
N7
• A new LEF layer TRIMMETAL is introduced in

implementation flow.
– A lot of new LEF rules are applied on that layer.
– Place & route tools need to utilize this trim metal concept to achieve better QoR.
– DEF in/out & GDS stream out need to support trim metal for RC extraction &
physical verification.
• 1st routing layer become “M0”

– This layer will be used for power rail connection.
• Standard cell library may violate DRC rules

– Require router to patch on PIN & OBS to fix MAR and/or enclosure violations as
an example.
N7
16FF+
Agenda N10
N7
• Standard. Cell
• Fin/Poly/Site
• Metallization
• Floorplan
• Powerplan
• Place
• Clock
• Route
• Data Out & Sign Off
Standard Cell
16FF+
Standard Cell Difference Overview N10
N7
16FFP N10 N7
Std. Cell Height 9T: 64X9=576nm H360: 69x2+45x4+42=360nm H240 : 240nm
7.5T: 64X7.5=480nm H300 : 300nm
H360 : 360nm
Std. Cell Color No Color Fixed Color Fixed Color
Std. Cell Signal Pin M1 / M2 M1 / M2 Fat Pin M1 / M2 Fat Pin
Std. Cell VT Type svt / lvt / ulvt svt / lvt / ulvt svt / lvt / ulvt
Std. Cell Channel
Length 16 / 20 10 / 14 8 / 11
Nominal Voltage (core) 0.8V (1.05V max) 0.75V (1.0V max) 0.75V (0.96V max)
16FF+
VT*_P/VT*_N N10
N7
Standard Cell – N10 Node N10
M0 pin shape M1 pin shape M1 routing
PW
Cell bndry
M0
VSS
Cell difference between Nodes N10
N7
• Only BAR shape PIN is allowed on M1 and M2.
• Cell PIN need to be colored in cell LEF.
• Cell designer need to color all cell objects.
• Cell objects’ color need to match track color.

– Innovus is not allowed to change cell color.
– Cell PIN center need to align to TRACK.
• PIN WIDTH can be different but it needs to be same as the TRACK WIDTH
(N10 Node)
Q’s
• What kind of impacts may “fixed color” bring?

– Bad?
– Good?
• What kind of impacts may “dirty cells” bring?

– Bad?
– Good?
• How do you think “M0 is routing layer”? Will you use?
Fin/Poly/Site
16FF+
Fin/Poly/Site Difference Overview N10
N7
16FFP N10 N7
Std. Cell Height 9T: 64X9=576nm H360: 69x2+45x4+42=360nm H240 : 240nm

7.5T: 64X7.5=480nm H300 : 300nm
H360 : 360nm
Fin Grid 48nm 32nm 30nm
9T: 12Fin
7.5T: 10Fin
90nm(PODE) /
Core Site 96nm(CPODE) 66nm 57nm
90nm(PODE)
Poly Pitch 96nm(CPODE) 66nm 57nm
TPO N10
N7
TPO (Trim-Poly) is marker layer for different Lg (channel length) cells.
0.228=4*0.057
Q’s
• Why we don’t call xT cells in N10 node and N7 Node?
• Pls. choose the correct pitch on M1 in N7 Node.

– 40nm?
– 44nm?
– 57nm?
• Below is a violation or not in N7 Node?

H8 3
H11 cell sites
H11 cell
• In N10 Node, Fin is 32nm, H360 cell is 360nm, Can you tell
the relationship between die size and Fin Grid in N10 node?
Metallization
16FF+
Metalization Information Overview N10
N7
16FFP N10 N7
Metal Stack 1P11M_2Xa1Xd3Xe2Y2R 1P11M_2X1Ya5Y2R 1P11M_2X1Ya5Y2R
M0 Horizontal
M0 Pitch 40nm/20nm/20nm (p/w/s)
M1 Horizontal (X) Horizontal (X) Vertical (X)
M1 Pitch 64nm/32nm/32nm (p/w/s) 42nm/20nm/22nm (p/w/s) 57nm/37nm/20nm (p/w/s)
M2 Verticla (Xa) Vertical (X) Horizontal (X)
M3 Horizontal (Xa) Horizontal (X) Vertical (X)
M4 Vertical (Xd) Vertical (Ya) Horizontal (Ya)
M5 Horizontal (Xe) Horizontal (Y) Vertical (Y)
M6 Vertical (Xe) Vertical (Y) Horizontal (Y)
M7 Horizontal (Xe) Horizontal (Y) Vertical (Y)
M8 Vertical (Y) Vertical (Y) Horizontal (Y)
M9 Horizontal (Y) Horizontal (Y) Vertical (Y)
16FF+
16FF+ -- 1P9M_2Xa1Xd3Xe2Z
The general 16FF+ logic process supports a single poly and thirteen metal layers(1P13M)
Metal Type Code W/S(um) Mask Layer

M1 M1 0.032/0.032 M1 only
Mx: M2, max: 1 layer
1X Metal Mx/Mxa 0.032/0.032 Mxa: M2~M5, max: 4 layers
1.25X Metal Mxd 0.040/0.040 M4/M6: max: 1 layer
1.25X Metal Mxe 0.040/0.040 M5~M10, max: 4 layers
2X Metal My 0.062/0.064 M7~M10, max: 2 layers
4X Metal Myy 0.126/0.126 M7~M11, max: 2 layers
5.6X Metal Myz 0.18/0.18 max: 1 layer
11X Metal Mz 0.36/0.36 M7~M12, max: 2 layers
14X Metal Mr 0.45/0.45 M8~M13, max: 2 layers
Ultra Think
Metal Mu 1.8/0.9 max: 1 layer
AI RDL AP 1.8/1.8 AP
Sample: 2Xa1Xd3Xe2Y2R
N10 Node – 1P7M_1X1Xa1Yz1Y2Z N10
The general N Node logic process supports a single poly and fourteen metal layers(1P14M)
Metal Type Code W/S(um)

M1 M1 0.020/0.022
1X Metal Mx 0.020/0.022
1X Metal Mxa 0.020/0.022
2X Metal Mya 0.040/0.040
2X Metal My 0.040/0.040
3X Metal Myy 0.062/0.064
6X Metal Myx 0.126/0.126
9X Metal Myz 0.180/0.180
18X Metal Mz 0.360/0.360
22.5X Metal Mr 0.450/0.450
AI RDL AP 1.8/1.8
Sample: 2X1Ya4Y2R
Sample:
10M_2X1Ya4Y2R_UTRDL_M2P44
_W22S22_M3P42_W20S22_M4P8
0_W40S40_M5P80_W40S40_M6P
80_W40S40_M7P80_W40S40_M8
P80_CPP66_0.5_1a.tlef
N7 Node – 1P12M_1X1Xa1Ya5Y1Yy2Z N7
The general N7 Node logic process supports a single poly and fourteen metal layers(1P14M)
Metal Type Code W/S(um)

M0 M0 0.020/0.020
1.4X Metal M1 0.037/0.020
1X Metal Mx 0.020/0.020
1X Metal Mxa 0.020/0.020
2X Metal Mya 0.038/0.038
2X Metal My 0.038/0.038
3X Metal Myy 0.062/0.064
6X Metal Myx 0.126/0.126
9X Metal Myz 0.180/0.180
18X Metal Mz 0.360/0.360
22.5X Metal Mr 0.450/0.450
AI RDL AP 1.8/1.8
Sample: 2X1Ya5Y2R
Floorplan
16FF+
Floorplan Requirement Overview N10
N7
16FFP N10 N7
Fin Grid 48nm 32nm 30nm
9T: 12Fin
7.5T: 10Fin
Core Site 90nm(PODE) / 96nm(CPODE) 66nm 57nm
Floorplan Std. cell/IO/IP/Block on Fin Grid IO/IP/Block on Fin Grid IO/IP/Block on Fin Grid
core to die boundary:
n*4row
1row = 11.25Fin
core to die boundary: 4row = 45Fin core to die boundary:
Track offset:
First M2 track: GREEN
Track offset: Track offset: MASK2
M2 0.011 Offset: 20nm
macro spacing/Pin macro spacing: 12 site macro spacing: 10 site
boundary cell boundary cell boundary cell
Welltap Welltap Welltap
checkFPlan checkFPlan checkFPlan
16FF+
FinGrid & Core2Die Boundary N10
N7
16FF+
N10 Node
• tLef FinFet Pitch only apply to Macro, no Std. Cell

• Partition cut line need to be the multiply of 4 Row:
– Because 360nmx4 = 32nmx45
• Still better to put first Row on FinGrid in hierarchical design
• DIEAREA needs to be a mulitple of FinFET grid
N7 Node
16FF+
FinGrid & Core2Die Boundary N10
N7
DIEAREA needs to be a
mulitple of FinFET grid
NOCORECELL;
Macro – same length poly number N10
N7
• In a group of continuous poly stripes with the same length, the number of poly
must >= N
• In a group of continuous poly stripes with the same length, the number of poly
< N, must have poly stripes >= N on the both right and left sides.
checkFPlan -checkSameLengthSite -minimalSites 12 # N10 Node
N7
* if there are three

macros, no need
to check macro 1
to macro 2
distance.
* Only care about
macro 1 to macro
3 and
macro 3 to macro
2.
N7

Macro pin N10
N7
 Hard Macro’s default width pin need

to align to track color
 Hard Macro’s fat pin need to put in

reversed color track to maximal
routing resource
Macro pin N10
N7
 checkFPlan can be used to check

macropin snapping
 snapFPlan –macroPin can be use

to snap macro pin to color track
 After snapping, if still have

violation, it should be library issue.
Boundary Cell – even site requirement N10
N7
Number of poly track in a row for macro or placement blockage must be even/odd
after insert boundary cell.
even Macro even
even
even
even even
even even
Placement blockage
Odd/Even Row Sites Setting N7
For N7,user must set the setFPlanMode –rowSiteWidth & -rowSiteHeight options
correctly.
- Example, if a design is using TSMC N7 even library, user must set these
two variables to value 2(even) to ensure width to be of “even sites” and
height to be “even rows”
Even/Odd Row Sites Setting - Examples N7
• Set the constraint for even or odd site width/height row

– 16.21 or older
set fpgOddEvenSitesRowConstraint 2 ( 0 : non, 1 : odd, 2 : even )
set fpgOddEvenSitesHeightConstraint 2
- 16.22/17.1 or later
setFPlanMode -rowSiteWidth even (any, odd, even )
setFPlanMode -rowSiteHeight even (any, odd, even )
• Check even or odd site/row
- 16.2 or older
checFPlan -OddEvenSiteRow
- 17.1 or later
setFPlanMode –checkTypes {oddEvenSiteRow}
checkFPlan
• Snap all Macros to site grid
- 16.2 or older
fpiSetSnapRule -for BLK -grid IG
snapFPlan -block
- 17.1 or later
setFPlanMode –snapBlockGrid inst
snapFPlan -block
• To make the inside rows to be even or odd sites
cutRow
Boundary cell (endcap) setting- Examples N7
• Boundary cell setup

setEndCapMode \
-avoidTwoSitesCellAbut true \
-bottomEdge {BOUNDARY_NROW8_H240_L11_P57_S BOUNDARY_NROW4_H240_L11_P57_S BOUNDARY_NROW2_H240_L11_P57_S} \
-boundary_tap false \
-leftBottomCornerEven BOUNDARY_NCORNER_H240_L11_P57_S \
-leftBottomCornerOdd BOUNDARY_NCORNER_H240_L11_P57_S \
-leftEdgeEven BOUNDARY_RIGHT_H240_L11_P57_S \
-leftEdgeOdd BOUNDARY_RIGHT_H240_L11_P57_S \
-leftTopCornerEven BOUNDARY_PCORNER_H240_L11_P57_S \
-leftTopCornerOdd BOUNDARY_PCORNER_H240_L11_P57_S \
-rightBottomEdgeEven BOUNDARY_NINCORNER_H240_L11_P57_S \
-rightBottomEdgeOdd BOUNDARY_NINCORNER_H240_L11_P57_S \
-rightEdgeEven BOUNDARY_LEFT_H240_L11_P57_S \
-rightEdgeOdd BOUNDARY_LEFT_H240_L11_P57_S \
-rightTopEdgeEven BOUNDARY_PINCORNER_H240_L11_P57_S \
-rightTopEdgeOdd BOUNDARY_PINCORNER_H240_L11_P57_S \
-topEdge {BOUNDARY_PROW8_H240_L11_P57_S BOUNDARY_PROW4_H240_L11_P57_S BOUNDARY_PROW2_H240_L11_P57_S} \
-useEvenOddSite even
addEndCap
verifyEndCap
Tap Cell Insertion
N7
• Tap cells need to be space by 3 sites in horizontal direction.
addWellTap -cell TAPCELL_NOM_H240_L11_P57_S \

-cellInterval 200 –checkerboard \
-avoidAbutment -siteOffset 3
verifyWellTap
• Tapcell-to-Tapcell abutment is prohibited neither vertical nor

horizontally.
T T T
T T T T T
• Tapcell mirrow-Y is not allow

• Insertion should be done by native command with an option to avoid
tap cell abutment
Tap Cell insertion N7
1. The same row 2 1 1 2

2 T 1 1 T 2
Abutment 1 site spacing 3 sites spacing Macro 2 T 1 Macro1 T 2
2 1 1 2
2 T 1 1 T 2
Tapcell Tapcell Tapcell Tapcell Tapcell Tapcell 2 2 T 2
2 T T T 2
2 T 2
2 T T T 2
2 2
2. The different row
overlap Overlap 1 poly pitch Point touch Spacing 1 poly pitch
Tapcell Tapcell
Tapcell Tapcell
Tapcell Tapcell
Tapcell Tapcell
Track N10
• M1 tracks are non-uniform M2

• M1 tracks need to be aligned
with standcell pin
– generateTracks -
snapM1TrackToCellPins
• M2 track need to have an offset
– generateTracks -m2VOffset
0.011
M1
Track N7
M0 tracks are non-uniform,
or offset 0.02 with uniform
Track
N7
M2 track need to have an offset 0.02
M2 Pins on Grid N7
H240:
add_tracks \
-pitch_pattern {m0 offset 0.0 pitch 0.06 {pitch 0.04 repeat 3} pitch 0.06
pitch 0.06 {pitch 0.04 repeat 3} pitch 0.06} \
-mask_pattern {m0 2 1 2 1 2 1 2 1 2 1 m1 2 1 m2 2 1 m3 1 2} \
-offset {m1 vert 0.0 m2 horiz 0.02 m3 vert 0.0 m4 horiz 0.0 m5 vert 0.0 m6
horiz 0.0 m7 vert 0.0 m8 horiz 0.0 M9 vert 0.0 ap horiz 0.0 }
Powerplan
Power plan – N10 Node N10
M2 is Vertical
Power plan – N7 node N7
M1 is Vertical
Layer width space reference comments

M0 0.06 0.24 sroute
VIA0 VIA01_PG_LONG_CA
M1 0.037 0.02 pitch=0.057*20
VIA1 VIA12_1cut_BW37_UW20
M2 0.02 0.22 pitch=0.48
M3 0.024 0.152 pitch=0.057*20
M4 0.038 0.494 pitch=1.216
VIA4 VIA45_PG
M5
VIA5 VIA56_PG
M6
VIA6 VIA67_PG
M7
VIA7 VIA78_PG
M8 0.114 0.494 pitch=1.216
VIA8 VIA89_LONG_V_BW76_UW114_PG
M9 0.114 0.494 pitch=1.216
Sample Power Plan – M1/M2/M3 N7
Sample Power Plan – M1 N7
Place
16FF+
par.lef – left/right N10
N7
xxxxx.par.lef
xxxxx.lef
par.lef – top/bottom N10
N7
• Vertical constraint was introduced since N, and also applied to N7 Node.

• It’s to define “push-out” requirement in vertical direction between different cell
groups.
par.lef – top/bottom N10
N7
xxxxx.par.lef
PROPERTYDEFINITIONS
LIBRARY LEF58_CELLEDGESPACINGTABLE STRING "
CELLEDGESPACINGTABLE
EDGETYPE GROUP7 GROUP2 0.001
EDGETYPE GROUP10 GROUP10 0.001 ;
Constraint define
" ; the relation for
END PROPERTYDEFINITIONS each group(From
par.lef or TCL)
xxxxx.lef
MACRO cell_name
...
PROPERTY LEF58_EDGETYPE "
EDGETYPE BOTTOM GROUP1 RANGE 0.132 0.198 ;
EDGETYPE TOP GROUP4 RANGE 0.132 0.198 ;
” ;
Each cell has it’s
... own edge group
END cell_name defined for it’s top
& bottom
TPO Layer N10
N7
Lg 14 10 10 14
Vt SVT SVT LVT LVT
• TPO (Trim-Poly) is marker layer for
different Lg (channel length) cells.
• Rule (example)
– TPO width and space rule are 4
pitch
• In tech Lef should provide SVT_P LVT_P
three parameter
SVT_N LVT_N
– TPO min. width
– TPO min. spacing
– TPO min. area Lg14 Lg10 Lg14
• TPO and Vt rule should be

independent for pessimism
>= W1 >= S1 >= W1
reduction
• Both placement/Legalizer and
Filler-insertion should be
enabled
>=A1 >=A1
• verify_drc can check-out TPO
layer violation
TPO Cell NonTPO Cell
TPO Layer N10
N7
• Placement and Filler insertion

– Innovus Command Usage
setPlaceMode -honorTPORules true(default)
• Verification
– Innovus command “verify_drc”
support TPO if there are TPO
syntax in tech LEF.
OD Jog Aware Placement N10
N7
• Innovus consider OD layer in TSMC CNOD library.

• Innovus Command Usage
setPlaceMode –checkDiffusionWidth true
setPlaceMode –checkUTLshapeOD true
setPlaceMode –allowUseFiller1 true
• Tech LEF Syntax Usage
LAYER OD
TYPE MASTERSLICE ;
PROPERTY LEF58_TYPE "TYPE DIFFUSION ; " ;
PROPERTY LEF58_COREEDGELENGTH "
COREEDGELENGTH xxx CONCAVECORNER ;
COREEDGELENGTH yyy CONVEXCORNER ;
COREEDGELENGTH zzz MIXEDCORNER ; " ;
END OD
OD Jog Aware Placement N10
N7
• Syntax Definition:
• CONCAVECORNER mean the U shape
U shape
OD
• CONVEXCORNER mean the T shape T shape
OD
• MIXEDCORNER mean the L shape

L shape
OD
Placement Settings
setDesignMode -flowEffort standard -process 7
# Enable use of one site filler without diffusion

setPlaceMode -place_detail_use_no_diffusion_one_site_filler
true
#design depended, more cong iter

setPlaceMode -congRepairForceIter 4
setPlaceMode -congRepairMaxIter 6
setPlaceMode -place_max_pin_density 0.4
Clock
NDR N10
N7
 Trunk NDR
 No VIA defined in NDR definition
 M1/M2’s width/spacing is regular: 1W1S
 M3’s width is regular, with double spacing: 1W2S or 1W1S
 M4-M8 are 2W2S
Route
RECTONLY layers in N10 & N7: N10
N7
• In N10 & N7 Node, Mx are RECTONLY:
Violation: M1~M3 only allow

Mx Pin Mx route
rectangles
X
OK: But tool need patching the
Mx Pin Mx route wire to satisfy the RECTONLY
requirement
Mx route Violation: No solution if M1~M3

Mx Pin pin not on grid.
X
M1~M3 pins has to be on-grid.
M0 in N7 Node is 1st routing layer: N7
M0(1) means tech LEF name of “M0”

and Innvous first routing layer.
dbGet head.layers.name
 Will get internal DB’s layer name (1)
dbGet head.layers.extName
Will get tech LEF’s layer name (M0)
M1 Trim Metal N7
Trim Metal Formation N7
Real Layout Picture
Trim Metal Formation N7
Recommended Cell Object Extension: NR option
setNanoRouteMode \
-quiet \
-routeExpWithTrimMetal \
"-layer 2 \
-mask2 {-pitch 0.24 -core_offset 0.095 -width 0.03 } \
-mask1 {-pitch 0.24 -core_offset 0.145 -width 0.03 }”
This option is cell library dependent, but not design specific.

In other words, given a cell library & corresponding recommended trim metal
locations, the above option can always be used.
M2 Trim Metal N7
LEF TRIMMETAL
N7
• Trim (cut) metal is used to shrink the end-to-end spacing and MAR,
which should be always sandwiched by 2 wire line-ends
MAR: Min Area Rule EOL: End Of Line
wire1 wire2 wire3
wire1 wire2 wire3

wire3
Trim metal width is fixed

TRIMMETAL Definition
N7
• As a masterslice layer with PROPERTY LEF58_TYPE “TYPE TRIMMETAL ; “ ;
– PROPERTY LEF58_TRIMMEDMETAL
“TRIMMEDMETAL metalLayer [MASK maskNum] ; “ ;
– PROPERTY LEF58_TRIMSHAPE
“TRIMSHAPE EXTENSIONMODEL
{ADJACENTTRACK|MIDTRACK|EXTENSION extension}
EXACTWIDTH [MAXLENGTH maxLength]
[EXCEPTSPACING spacing] [EXCEPTWIDTH width]
[USEMETALMASK] ; “ ;
– PROPERTY LEF58_SPACING
“SPACING spacing [PRLSPACING prlSpacing1 prlSpacing2]
[ENDTOEND endToEndSpacing [PRL prl]]
[EXACTALIGNED exactAlignedSpacing] [SAMEMASK] ; “ ;…
– MASK maskNum ;
TRIMSHAPE Definition M1 example
N7
Wire with width

<= 0.037
Width of
TRIMMETAL must 0.03 Wire with width > 0.037 does
be exactly 0.03 not allow TRIMMETAL, and
spacing must be >= 0.12
TRIMMETAL
0.0635
TRIMMETAL color Spacing >= 0.12 does

must match wire color not need TRIMMETAL
Example of
LAYER CM1
TYPE MASTERSLICE ;
MASK 2 ;
PROPERTY LEF58_TYPE "TYPE TRIMMETAL ; " ;
PROPERTY LEF58_TRIMMEDMETAL "TRIMMEDMETAL M1 ; " ;
PROPERTY LEF58_TRIMSHAPE "
TRIMSHAPE EXTENSIONMODEL EXTENSION 0.0635
EXACTWIDTH 0.030 EXCEPTSPACING 0.120 EXCEPTWIDTH 0.037 USEMETALMASK ; " ;
END CM1
TRIMSHAPE Definition M2 example N7
Wire with width <= 0.02
TRIMMETAL
0.024
Mask 1 (red) must use Only allow TRIMMETAL on

spacing of >= 0.116 Mask 2 (green)
Example of
LAYER CM2
TYPE MASTERSLICE ;
PROPERTY LEF58_TRIMMEDMETAL "TRIMMEDMETAL M2 MASK 2 ; " ;
EXACTWIDTH 0.024 EXCEPTSPACING 0.124 EXCEPTWIDTH 0.020 ; " ;
END CM2
TRIM Spacing M2 example N7
Spacing of >= 0.084 is

needed on adjacent track
TRIMMETAL
Spacing of 0.05 < 0.108 Exact aligned spacing of

0.050 is fine
< 0.032
Spacing of
TRIMMETAL on the
same track is same as
MAR of metal
Example of
LAYER CM2
TYPE MASTERSLICE ;
PROPERTY LEF58_TRIMMEDMETAL "TRIMMEDMETAL M2 MASK 2 ; " ;
EXACTWIDTH 0.024 EXCEPTSPACING 0.124 EXCEPTWIDTH 0.020 ; " ;
PROPERTY LEF58_SPACING "SPACING 0.084 ENDTOEND 0.108 PRL -0.032
EXACTALIGNED 0.050 ; " ;
END CM2
Trim Metal Formation for Routing Wires N7
Trim metal
Large EOL
spacing
O X Trim metal
OR
Router can optimize
the location of trim
metal to avoid
violations
metal
metal patch
PROPERTY LEF58_TRIMSHAPE " trim metal

TRIMSHAPE … EXACTWIDTH W1 EXCEPTSPACING SP1 … ; “ ;
Trim Metal Aware Area Rule N7
Trim metal on
both ends
Trim metal on
one end
No trim metal
AREA 0.00408 ;
PROPERTY LEF58_AREA " Area is smaller
AREA 0.00306 LAYER CM1 OVERLAP 1 ; with trim metal
AREA 0.00272 LAYER CM1 OVERLAP 2 ; " ;
Trim Metal Aware Enclosure Rule N7
Enclosure is smaller with

trim metal
PROPERTY LEF58_ENCLOSURETABLE "
ENCLOSURETABLE CUTCLASS xxx
WIDTH 0.000 0.015 0.015 0.000 0.000
WIDTH 0.000 0.010 0.010 0.000 0.000 LAYER CM1 OVERLAP 1
…;“;
NanoRouteMode settings For N7
setNanoRouteMode -dbProcessNode N7
## design dependend
setNanoRouteMode -routeBottomRoutingLayer 2
setNanoRouteMode -routeTopRoutingLayer 8
## N7 route setting
setNanoRouteMode -routeConcurrentMinimizeViaCountEffort high
setNanoRouteMode -drouteExpAdvancedSearchFix true
setNanoRouteMode -drouteEndIteration default
## 1 D routing for M0~M3

setNanoRouteMode -drouteMinimizeLithoEffectOnLayer {t t t t}
setNanoRouteMode -drouteOnGridOnly {wire 1:10}
## For N7 stdCell pin style

setNanoRouteMode -drouteExpDynamicPinAccess false
setNanoRouteMode -routeExpAdaptivePinAccess true
setNanoRouteMode -routeWithViaInPin false
setNanoRouteMode -routeWithViaOnlyForStandardCellPin false
# Use pin pattern for M1(2)

setNanoRouteMode -routeExpAdvancedPinAccess 2
# TrimMetal handling
setNanoRouteMode -drouteExpCheckWithTrimMetalFilled true
setNanoRouteMode -drouteExpFixOnlyIteration true
setNanoRouteMode -dbExpFloatingObject true
setNanoRouteMode -drouteExpEnableBlockMaskRepair "mar_enc_patch"
setNanoRouteMode -drouteExpFixSpecialNetOnNonCoreArea true
# TrimMetal prefer grid definition

setNanoRouteMode -routeExpWithTrimMetal "-layer 2 -mask2 {-pitch 0.24 -core_offset 0.225 -width 0.03 } \
-mask1 {-pitch 0.24 -core_offset 0.145 -width 0.03 }"
### multiCutViaEffort set to high in CTS then turn to default in routeDesign

setNanoRouteMode -drouteUseMultiCutViaEffort default
setNanoRouteMode -droutePostRouteSwapVia none
setNanoRouteMode -drouteExpSwapViaAfterEcoRoute false
setNanoRouteMode -drouteExpConcurrentMinimizeViaCountCost 64
## Better topology for timing

setNanoRouteMode -grouteExpMinimizeS2sEffort high
## Add this options for verify_drc to check out EOLK

setNanoRouteMode -drouteExpEnableBlockMaskCheckInVerifyDrc true
# For EM tappering
setNanoRouteMode -drouteUseLefPinTaperRule true
setNanoRouteMode -routeExpForbiddenTrimMetalNonStandardCell {0 0}
setNanoRouteMode -droutePostRouteSpreadWire false
# for MAR/TRIM Metal estimation during NR extraction

setNanoRouteMode -extractMarsEstimateForTa true
setNanoRouteMode -extractTrimPatchEstimateForTa true
# to optimize/cleanup unused or unoptimized Patch

setNanoRouteMode -drouteExpOptimizeTrimPatch true
# to access M2 Macro pin with VIA only

setNanoRouteMode -routeWithViaOnlyForMacroCellPin 2:2
# to allow multiple NDR on a net for EM fixing

setNanoRouteMode -drouteUseLefPinTaperRule true; #default is true
# to enable new TrackOpt flow if desired

setNanoRouteMode -routeWithOpt true
Data out & Signoff
Manufacturing (sign-off DRC) vs APR View N7
• Need to output metal to fill the gap between line-end in

– GDS
– DEF
– OA
– Internal routing checker (FGC)
N7
DEF Representation patch
• Patch
– Signal net wires or pins: RECT in NETS section
- NET_A …
NEW M1 (x x) MASK 2 RECT (x x x x)
Wire or pin of NET_A Patch of NET_A
– Special net wires or pins: Corresponding net with DRCFILL tag in

SPECIALNETS section
- SPECIAL_NET_A …
+ ROUTED + SHAPE DRCFILL + MASK 2 + RECT M2 (x x) (x x)
Wire or pin of SPECIAL_NET_A Patch of SPECIAL_NET_A
N7
DEF Representation patch
• Patch
– OBS/unconnected pins: _SADP_FILLS_RESERVED with DRCFILL tag in
SPECIALNETS section
- _SADP_FILLS_RESERVED …
+ ROUTED + SHAPE DRCFILL + MASK 2 + RECT M2 (x x) (x x)
OBS Patch of _SADP_FILLS_RESERVED
– Floating: FILLS section (stored in a dummy net, _FILLS_RESERVED, in

Innovus)
- LAYER M2 + MASK 2 RECT (x x) (x x)
TM1 TM1
NET_A Floating patch of _FILLS_RESERVED NET_B
DEF Representation trim metal N7
• Trim metal
– All of trim metals would be in FILLS section
- LAYER TM1 + MASK 1
RECT TM1 (x x) (x x) …
- LAYER TM1 + MASK 2
RECT TM1 (x x) (x x) …
TM1 TM1
SPECIAL_NET_A NET_B _SADP_FILLS_RESERVED NET_B
TM1
Floating patch of _FILLS_RESERVED Floating patch of _FILLS_RESERVED
N7
DEF Representation
• Metal to fill gap between line-end
– Metal shapes would be created under a dummy net of
_TRIMMETAL_FILLS_RESERVED with DRCFILL tag in SPECIALNETS
section
- _TRIMMETAL_FILLS_RESERVED …
+ SHAPE DRCFILL + MASK 2 + RECT M2 (x x) (x x) …
TM1 TM1
SPECIAL_NET_A NET_B _SADP_FILLS_RESERVED NET_B
TM1
Floating patch of _FILLS_RESERVED Floating patch of _FILLS_RESERVED
N7
DEF option
• Patch would be output by default if exists.
Default in DEF
• Trim metal would be output by default if exists.

– Option –skip_trimmetal_layers would be used to turn off outputting trim metal.
Default in DEF
• Metal to fill gap between line-end would be output

ONLY if option -trimmetal_gap_fill is specified.
– Since those filled/short metal would mess up connectivity model in Innovus, defIn
would automatically ignore them.
Default NOT in DEF
GDS stream out N7
• Trim metal & metal to fill gap between line-end is controlled in the map
file.
Example:
#Layer name #LAYER OBJECT #gds layer #gds sub layer
TRM1 TRIM:MASK:1 301 1
TRM1 TRIM:MASK:2 301 2
TRM1 LEFOBS:MASK:1 301 3
TRM1 LEFOBS:MASK:2 301 4
TRM1 SHORT:MASK:1 31 5
TRM1 SHORT:MASK:2 31 6
• Trim metal shapes of TRM1 would be written out as object type of

TRIM on GDS trim layer of 301 if they are generated by router on the fly
or as
LEFOBS if they are pre-defined in standard cells
The missing metal to fill gap between line-end would be written out as
SHORT on GDS metal (M1) layer of 31.
Summary
16FF+
N7
2012 2013 2014 2015 2016 2017

Vertical Edge
FinFet Trim Metal
Constraint
DPT (soft) / G0 Fixed Color

M0
Wider wrong No wrong way
way width routing
Constraint Mx/Mxa
2016 2017
N7 Node
Vertical Edge
FinFet Trim Metal
Constraint
Fixed Color
M0
No wrong way
routing
Constraint Mx/Mxa
N7
To start N7 node, you need ….
1. std. cell par.lef / std. cell lef

2. tlef
3. qrcTechFile
4. DRM
5. Innovus setting / scripts
6. The notes in this slides with
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2012 2013 2014 2015 2016 2017

16FFP N10 Node N7 Node

DPT (soft) / G0 Fixed Color

• A new LEF layer TRIMMETAL is introduced in

• 1st routing layer become “M0”

• Standard cell library may violate DRC rules

• Data Out & Sign Off

Std. Cell Height 9T: 64X9=576nm H360: 69x2+45x4+42=360nm H240 : 240nm

7.5T: 64X7.5=480nm H300 : 300nm

Std. Cell Color No Color Fixed Color Fixed Color

Std. Cell Signal Pin M1 / M2 M1 / M2 Fat Pin M1 / M2 Fat Pin

M0 pin shape M1 pin shape M1 routing

• Only BAR shape PIN is allowed on M1 and M2.

• Cell PIN need to be colored in cell LEF.

• Cell designer need to color all cell objects.

• Cell objects’ color need to match track color.

• What kind of impacts may “fixed color” bring?

• What kind of impacts may “dirty cells” bring?

• How do you think “M0 is routing layer”? Will you use?

Std. Cell Height 9T: 64X9=576nm H360: 69x2+45x4+42=360nm H240 : 240nm

TPO (Trim-Poly) is marker layer for different Lg (channel length) cells.

• Why we don’t call xT cells in N10 node and N7 Node?

• Pls. choose the correct pitch on M1 in N7 Node.

• Below is a violation or not in N7 Node?

Metal Type Code W/S(um) Mask Layer

Metal Type Code W/S(um)

Metal Type Code W/S(um)

• tLef FinFet Pitch only apply to Macro, no Std. Cell

* if there are three

checkFPlan -checkSameLengthSite -minimalSites 12 # N10 Node

 Hard Macro’s default width pin need

 Hard Macro’s fat pin need to put in

 checkFPlan can be used to check

 snapFPlan –macroPin can be use

 After snapping, if still have

even Macro even

• Set the constraint for even or odd site width/height row

• Boundary cell setup

addWellTap -cell TAPCELL_NOM_H240_L11_P57_S \

• Tapcell-to-Tapcell abutment is prohibited neither vertical nor

• Tapcell mirrow-Y is not allow

1. The same row 2 1 1 2

• M1 tracks are non-uniform M2

Layer width space reference comments

• Vertical constraint was introduced since N, and also applied to N7 Node.

• TPO and Vt rule should be

TPO Cell NonTPO Cell

• Placement and Filler insertion

• Innovus consider OD layer in TSMC CNOD library.

• Tech LEF Syntax Usage

• MIXEDCORNER mean the L shape

setDesignMode -flowEffort standard -process 7

# Enable use of one site filler without diffusion

#design depended, more cong iter

 No VIA defined in NDR definition

 M1/M2’s width/spacing is regular: 1W1S

 M3’s width is regular, with double spacing: 1W2S or 1W1S

 M4-M8 are 2W2S

• In N10 & N7 Node, Mx are RECTONLY:

Violation: M1~M3 only allow

Mx route Violation: No solution if M1~M3