DSG Cadence
2016.10.13
16FF+
Process Evolution N10
N7
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N7 Node
N7
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N7
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16FF+
Agenda N10
N7
• Standard. Cell
• Fin/Poly/Site
• Metallization
• Floorplan
• Powerplan
• Place
• Clock
• Route
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Standard Cell
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16FF+
Standard Cell Difference Overview N10
N7
16FFP N10 N7
H360 : 360nm
Std. Cell VT Type svt / lvt / ulvt svt / lvt / ulvt svt / lvt / ulvt
Std. Cell Channel
Length 16 / 20 10 / 14 8 / 11
Nominal Voltage (core) 0.8V (1.05V max) 0.75V (1.0V max) 0.75V (0.96V max)
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16FF+
VT*_P/VT*_N N10
N7
16FFP N10 Node N7 Node
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Standard Cell – N10 Node N10
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Standard Cell – N7 Node N7
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Standard Cell – N7 Node N7
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Standard Cell – N7 Node N7
PW
Cell bndry
M0
VSS
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Cell difference between Nodes N10
N7
• PIN WIDTH can be different but it needs to be same as the TRACK WIDTH
(N10 Node)
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Q’s
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Fin/Poly/Site
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16FF+
Fin/Poly/Site Difference Overview N10
N7
16FFP N10 N7
90nm(PODE)
Poly Pitch 96nm(CPODE) 66nm 57nm
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TPO N10
N7
0.228=4*0.057
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Q’s
• In N10 Node, Fin is 32nm, H360 cell is 360nm, Can you tell
the relationship between die size and Fin Grid in N10 node?
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Metallization
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16FF+
Metalization Information Overview N10
N7
16FFP N10 N7
Metal Stack 1P11M_2Xa1Xd3Xe2Y2R 1P11M_2X1Ya5Y2R 1P11M_2X1Ya5Y2R
M0 Horizontal
M0 Pitch 40nm/20nm/20nm (p/w/s)
M1 Horizontal (X) Horizontal (X) Vertical (X)
M1 Pitch 64nm/32nm/32nm (p/w/s) 42nm/20nm/22nm (p/w/s) 57nm/37nm/20nm (p/w/s)
M2 Verticla (Xa) Vertical (X) Horizontal (X)
M2 Pitch 64nm/32nm/32nm (p/w/s) 44nm/22nm/22nm (p/w/s) 40nm/20nm/20nm (p/w/s)
M3 Horizontal (Xa) Horizontal (X) Vertical (X)
M3 Pitch 64nm/32nm/32nm (p/w/s) 42nm/20nm/22nm (p/w/s) 40nm/20nm/20nm (p/w/s)
M4 Vertical (Xd) Vertical (Ya) Horizontal (Ya)
M4 Pitch 80nm/40nm/40nm (p/w/s) 80nm/40nm/40nm (p/w/s) 76nm/38nm/38nm (p/w/s)
M5 Horizontal (Xe) Horizontal (Y) Vertical (Y)
M5 Pitch 80nm/40nm/40nm (p/w/s) 80nm/40nm/40nm (p/w/s) 76nm/38nm/38nm (p/w/s)
M6 Vertical (Xe) Vertical (Y) Horizontal (Y)
M6 Pitch 80nm/40nm/40nm (p/w/s) 80nm/40nm/40nm (p/w/s) 76nm/38nm/38nm (p/w/s)
M7 Horizontal (Xe) Horizontal (Y) Vertical (Y)
M7 Pitch 80nm/40nm/40nm (p/w/s) 80nm/40nm/40nm (p/w/s) 76nm/38nm/38nm (p/w/s)
M8 Vertical (Y) Vertical (Y) Horizontal (Y)
M8 Pitch 80nm/40nm/40nm (p/w/s) 80nm/40nm/40nm (p/w/s) 76nm/38nm/38nm (p/w/s)
M9 Horizontal (Y) Horizontal (Y) Vertical (Y)
M9 Pitch 80nm/40nm/40nm (p/w/s) 80nm/40nm/40nm (p/w/s) 76nm/38nm/38nm (p/w/s)
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16FF+
16FF+ -- 1P9M_2Xa1Xd3Xe2Z
The general 16FF+ logic process supports a single poly and thirteen metal layers(1P13M)
Sample: 2Xa1Xd3Xe2Y2R
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N10 Node – 1P7M_1X1Xa1Yz1Y2Z N10
The general N Node logic process supports a single poly and fourteen metal layers(1P14M)
Sample: 2X1Ya4Y2R
Sample:
10M_2X1Ya4Y2R_UTRDL_M2P44
_W22S22_M3P42_W20S22_M4P8
0_W40S40_M5P80_W40S40_M6P
80_W40S40_M7P80_W40S40_M8
P80_CPP66_0.5_1a.tlef
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N7 Node – 1P12M_1X1Xa1Ya5Y1Yy2Z N7
The general N7 Node logic process supports a single poly and fourteen metal layers(1P14M)
Sample: 2X1Ya5Y2R
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Floorplan
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16FF+
Floorplan Requirement Overview N10
N7
16FFP N10 N7
Fin Grid 48nm 32nm 30nm
9T: 12Fin
7.5T: 10Fin
Core Site 90nm(PODE) / 96nm(CPODE) 66nm 57nm
Floorplan Std. cell/IO/IP/Block on Fin Grid IO/IP/Block on Fin Grid IO/IP/Block on Fin Grid
core to die boundary:
n*4row
1row = 11.25Fin
core to die boundary: 4row = 45Fin core to die boundary:
Track offset:
First M2 track: GREEN
Track offset: Track offset: MASK2
M2 0.011 Offset: 20nm
macro spacing/Pin macro spacing: 12 site macro spacing: 10 site
boundary cell boundary cell boundary cell
Welltap Welltap Welltap
checkFPlan checkFPlan checkFPlan
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16FF+
FinGrid & Core2Die Boundary N10
N7
16FF+
N10 Node
N7 Node
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16FF+
FinGrid & Core2Die Boundary N10
N7
DIEAREA needs to be a
mulitple of FinFET grid
NOCORECELL;
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Macro – same length poly number N10
N7
• In a group of continuous poly stripes with the same length, the number of poly
must >= N
• In a group of continuous poly stripes with the same length, the number of poly
< N, must have poly stripes >= N on the both right and left sides.
checkFPlan -checkSameLengthSite -minimalSites 12 # N10 Node
checkFPlan -checkSameLengthSite -minimalSites 10 # N7 Node
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Macro – same length poly number N10
N7
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Macro – same length poly number N10
N7
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Macro pin N10
N7
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Macro pin N10
N7
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Boundary Cell – even site requirement N10
N7
Number of poly track in a row for macro or placement blockage must be even/odd
after insert boundary cell.
even
even
even even
even even
Placement blockage
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Odd/Even Row Sites Setting N7
For N7,user must set the setFPlanMode –rowSiteWidth & -rowSiteHeight options
correctly.
- Example, if a design is using TSMC N7 even library, user must set these
two variables to value 2(even) to ensure width to be of “even sites” and
height to be “even rows”
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Even/Odd Row Sites Setting - Examples N7
addEndCap
verifyEndCap
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Tap Cell Insertion
N7
• Tap cells need to be space by 3 sites in horizontal direction.
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Tap Cell insertion N7
Tapcell Tapcell
Tapcell Tapcell
Tapcell Tapcell
Tapcell Tapcell
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Track N10
M1
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Track N7
M0 tracks are non-uniform,
or offset 0.02 with uniform
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Track
N7
M2 track need to have an offset 0.02
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M2 Pins on Grid N7
H240:
add_tracks \
-pitch_pattern {m0 offset 0.0 pitch 0.06 {pitch 0.04 repeat 3} pitch 0.06
pitch 0.06 {pitch 0.04 repeat 3} pitch 0.06} \
-mask_pattern {m0 2 1 2 1 2 1 2 1 2 1 m1 2 1 m2 2 1 m3 1 2} \
-offset {m1 vert 0.0 m2 horiz 0.02 m3 vert 0.0 m4 horiz 0.0 m5 vert 0.0 m6
horiz 0.0 m7 vert 0.0 m8 horiz 0.0 M9 vert 0.0 ap horiz 0.0 }
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Powerplan
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Power plan – N10 Node N10
M2 is Vertical
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Power plan – N7 node N7
M1 is Vertical
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Sample Power Plan – M1/M2/M3 N7
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Sample Power Plan – M1 N7
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Sample Power Plan – M0 N7
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Sample Power Plan – M0 N7
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Place
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16FF+
par.lef – left/right N10
N7
xxxxx.par.lef
xxxxx.lef
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par.lef – top/bottom N10
N7
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par.lef – top/bottom N10
N7
xxxxx.par.lef
PROPERTYDEFINITIONS
LIBRARY LEF58_CELLEDGESPACINGTABLE STRING "
CELLEDGESPACINGTABLE
EDGETYPE GROUP7 GROUP2 0.001
EDGETYPE GROUP10 GROUP10 0.001 ;
Constraint define
" ; the relation for
END PROPERTYDEFINITIONS each group(From
par.lef or TCL)
xxxxx.lef
MACRO cell_name
...
PROPERTY LEF58_EDGETYPE "
EDGETYPE BOTTOM GROUP1 RANGE 0.132 0.198 ;
EDGETYPE TOP GROUP4 RANGE 0.132 0.198 ;
” ;
Each cell has it’s
... own edge group
END cell_name defined for it’s top
& bottom
53 © 2015 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
TPO Layer N10
N7
Lg 14 10 10 14
Vt SVT SVT LVT LVT
• TPO (Trim-Poly) is marker layer for
different Lg (channel length) cells.
• Rule (example)
– TPO width and space rule are 4
pitch
• In tech Lef should provide SVT_P LVT_P
three parameter
SVT_N LVT_N
– TPO min. width
– TPO min. spacing
– TPO min. area Lg14 Lg10 Lg14
54 © 2015 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
TPO Layer N10
N7
• Verification
– Innovus command “verify_drc”
support TPO if there are TPO
syntax in tech LEF.
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OD Jog Aware Placement N10
N7
LAYER OD
TYPE MASTERSLICE ;
PROPERTY LEF58_TYPE "TYPE DIFFUSION ; " ;
PROPERTY LEF58_COREEDGELENGTH "
COREEDGELENGTH xxx CONCAVECORNER ;
COREEDGELENGTH yyy CONVEXCORNER ;
COREEDGELENGTH zzz MIXEDCORNER ; " ;
END OD
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OD Jog Aware Placement N10
N7
• Syntax Definition:
• CONCAVECORNER mean the U shape
U shape
OD
• CONVEXCORNER mean the T shape T shape
OD
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Placement Settings
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Clock
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NDR N10
N7
Trunk NDR
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Route
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RECTONLY layers in N10 & N7: N10
N7
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M0 in N7 Node is 1st routing layer: N7
dbGet head.layers.name
Will get internal DB’s layer name (1)
dbGet head.layers.extName
Will get tech LEF’s layer name (M0)
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M1 Trim Metal N7
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Trim Metal Formation N7
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Trim Metal Formation N7
setNanoRouteMode \
-quiet \
-routeExpWithTrimMetal \
"-layer 2 \
-mask2 {-pitch 0.24 -core_offset 0.095 -width 0.03 } \
-mask2 {-pitch 0.24 -core_offset 0.225 -width 0.03 } \
-mask1 {-pitch 0.24 -core_offset 0.015 -width 0.03 } \
-mask1 {-pitch 0.24 -core_offset 0.145 -width 0.03 }”
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M2 Trim Metal N7
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LEF TRIMMETAL
N7
• Trim (cut) metal is used to shrink the end-to-end spacing and MAR,
which should be always sandwiched by 2 wire line-ends
– PROPERTY LEF58_TRIMMEDMETAL
“TRIMMEDMETAL metalLayer [MASK maskNum] ; “ ;
– PROPERTY LEF58_TRIMSHAPE
“TRIMSHAPE EXTENSIONMODEL
{ADJACENTTRACK|MIDTRACK|EXTENSION extension}
EXACTWIDTH [MAXLENGTH maxLength]
[EXCEPTSPACING spacing] [EXCEPTWIDTH width]
[USEMETALMASK] ; “ ;
– PROPERTY LEF58_SPACING
“SPACING spacing [PRLSPACING prlSpacing1 prlSpacing2]
[ENDTOEND endToEndSpacing [PRL prl]]
[EXACTALIGNED exactAlignedSpacing] [SAMEMASK] ; “ ;…
– MASK maskNum ;
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TRIMSHAPE Definition M1 example
N7
Width of
TRIMMETAL must 0.03 Wire with width > 0.037 does
be exactly 0.03 not allow TRIMMETAL, and
spacing must be >= 0.12
TRIMMETAL
0.0635
Example of
LAYER CM1
TYPE MASTERSLICE ;
MASK 2 ;
PROPERTY LEF58_TYPE "TYPE TRIMMETAL ; " ;
PROPERTY LEF58_TRIMMEDMETAL "TRIMMEDMETAL M1 ; " ;
PROPERTY LEF58_TRIMSHAPE "
TRIMSHAPE EXTENSIONMODEL EXTENSION 0.0635
EXACTWIDTH 0.030 EXCEPTSPACING 0.120 EXCEPTWIDTH 0.037 USEMETALMASK ; " ;
END CM1
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TRIMSHAPE Definition M2 example N7
TRIMMETAL
0.024
Example of
LAYER CM2
TYPE MASTERSLICE ;
PROPERTY LEF58_TYPE "TYPE TRIMMETAL ; " ;
PROPERTY LEF58_TRIMMEDMETAL "TRIMMEDMETAL M2 MASK 2 ; " ;
PROPERTY LEF58_TRIMSHAPE "
TRIMSHAPE EXTENSIONMODEL EXTENSION 0.055
EXACTWIDTH 0.024 EXCEPTSPACING 0.124 EXCEPTWIDTH 0.020 ; " ;
END CM2
71 © 2015 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
TRIM Spacing M2 example N7
< 0.032
Spacing of
TRIMMETAL on the
same track is same as
MAR of metal
Example of
LAYER CM2
TYPE MASTERSLICE ;
PROPERTY LEF58_TYPE "TYPE TRIMMETAL ; " ;
PROPERTY LEF58_TRIMMEDMETAL "TRIMMEDMETAL M2 MASK 2 ; " ;
PROPERTY LEF58_TRIMSHAPE "
TRIMSHAPE EXTENSIONMODEL EXTENSION 0.055
EXACTWIDTH 0.024 EXCEPTSPACING 0.124 EXCEPTWIDTH 0.020 ; " ;
PROPERTY LEF58_SPACING "SPACING 0.084 ENDTOEND 0.108 PRL -0.032
EXACTALIGNED 0.050 ; " ;
END CM2
72 © 2015 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
Trim Metal Formation for Routing Wires N7
Trim metal
Large EOL
spacing
O X Trim metal
OR
Router can optimize
the location of trim
metal to avoid
violations
metal
metal patch
Trim metal on
both ends
Trim metal on
one end
No trim metal
AREA 0.00408 ;
PROPERTY LEF58_AREA " Area is smaller
AREA 0.00306 LAYER CM1 OVERLAP 1 ; with trim metal
AREA 0.00272 LAYER CM1 OVERLAP 2 ; " ;
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Trim Metal Aware Enclosure Rule N7
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NanoRouteMode settings For N7
setNanoRouteMode -dbProcessNode N7
## design dependend
setNanoRouteMode -routeBottomRoutingLayer 2
setNanoRouteMode -routeTopRoutingLayer 8
## N7 route setting
setNanoRouteMode -routeConcurrentMinimizeViaCountEffort high
setNanoRouteMode -drouteExpAdvancedSearchFix true
setNanoRouteMode -drouteEndIteration default
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NanoRouteMode settings For N7
# TrimMetal handling
setNanoRouteMode -drouteExpCheckWithTrimMetalFilled true
setNanoRouteMode -drouteExpFixOnlyIteration true
setNanoRouteMode -dbExpFloatingObject true
setNanoRouteMode -drouteExpEnableBlockMaskRepair "mar_enc_patch"
setNanoRouteMode -drouteExpFixSpecialNetOnNonCoreArea true
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NanoRouteMode settings For N7
# For EM tappering
setNanoRouteMode -drouteUseLefPinTaperRule true
setNanoRouteMode -routeExpForbiddenTrimMetalNonStandardCell {0 0}
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Data out & Signoff
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Manufacturing (sign-off DRC) vs APR View N7
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N7
DEF Representation patch
• Patch
– Signal net wires or pins: RECT in NETS section
- NET_A …
NEW M1 (x x) MASK 2 RECT (x x x x)
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N7
DEF Representation patch
• Patch
– OBS/unconnected pins: _SADP_FILLS_RESERVED with DRCFILL tag in
SPECIALNETS section
- _SADP_FILLS_RESERVED …
+ ROUTED + SHAPE DRCFILL + MASK 2 + RECT M2 (x x) (x x)
TM1 TM1
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DEF Representation trim metal N7
• Trim metal
– All of trim metals would be in FILLS section
- LAYER TM1 + MASK 1
RECT TM1 (x x) (x x) …
- LAYER TM1 + MASK 2
RECT TM1 (x x) (x x) …
TM1 TM1
SPECIAL_NET_A NET_B _SADP_FILLS_RESERVED NET_B
TM1
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N7
DEF Representation
• Metal to fill gap between line-end
– Metal shapes would be created under a dummy net of
_TRIMMETAL_FILLS_RESERVED with DRCFILL tag in SPECIALNETS
section
- _TRIMMETAL_FILLS_RESERVED …
+ SHAPE DRCFILL + MASK 2 + RECT M2 (x x) (x x) …
TM1 TM1
TM1
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N7
DEF option
• Patch would be output by default if exists.
Default in DEF
Default in DEF
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GDS stream out N7
• Trim metal & metal to fill gap between line-end is controlled in the map
file.
Example:
#Layer name #LAYER OBJECT #gds layer #gds sub layer
TRM1 TRIM:MASK:1 301 1
TRM1 TRIM:MASK:2 301 2
TRM1 LEFOBS:MASK:1 301 3
TRM1 LEFOBS:MASK:2 301 4
TRM1 SHORT:MASK:1 31 5
TRM1 SHORT:MASK:2 31 6
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Summary
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16FF+
Process Evolution N10
N7
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Process Evolution N7
2016 2017
N7 Node
Vertical Edge
FinFet Trim Metal
Constraint
Fixed Color
M0
No wrong way
routing
Horizontal Edge Rect only on “dirty” std. cell
Constraint Mx/Mxa
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N7
To start N7 node, you need ….
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Back Up
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