Testing Faults in SRAM Memory of Virtex-4 FPGA
Mohammed Niamat, Manoj Lalla,
Department of EECS, Department of EECS,
University of Toledo, University of Toledo,
Toledo, USA. Toledo, USA.
mniamat@utnet.utoledo.edu manoj.lalla@utoledo.edu
Abstract
Various algorithms and testing schemes have been
developed in the past for testing memories for the
presence of faults. Due to the increasing popularity of
FPGAs, some schemes have specifically been developed
for testing memories in these devices. FPGAs, when used
in airborne space applications, are exposed to radiations
which can produce faults within their memory. Faults may
also develop during the manufacturing process. In the
past, testing embedded memories within Field
Programmable Gate Arrays has been limited to the
detection of stuck-at faults. Recent studies have shown
that FPGA memories are also prone to address decoder,
transient, and inversion coupling faults. To address these
faults, the current research proposes to develop a Built-in
Self Test (BIST) technique for testing embedded SRAM
memories of Virtex-4 FPGAs for the presence of address
decoder, inverse coupling, transient and also stuck-at
faults. The technique is modeled using VHDL. Simulation
results are presented to verify fault detection.
1. Introduction
Testing is performed in various stages of product
compilation like design phase, manufacturing phase and
system operation phase. During the design phase, the
product is tested for presence of any logical errors in the
design which may result in unexpected logical output.
During the manufacturing phase, testing is performed to
check for any physical faults like shorts or open resistive
paths present on the board. When the product is
manufactured, it is then tested while it is in operation for
failing components due to severe operating conditions. In
case of Field Programmable Gate Arrays (FPGAs) faults
may occur due to high temperature, severe environmental
conditions or electro migration due to exposure to gamma
radiations. As a result, testing of FPGAs on a periodic
basis increases the dependability of such reconfigurable
systems. The regular and symmetric architecture of an
978-1-4244-4480-9/09/$25.00 ©2009 IEEE 965
Junghwan Kim,
Department of EECS,
University of Toledo,
Toledo, USA.
jkim@eecs.utoledo.edu
FPGA makes it a good candidate for implementing BIST
schemes.
The basic idea of BIST is to develop a circuit that can
test itself and determine whether it is fault free or faulty.
BIST requires additional components like Test Pattern
Generators (TPGs) and Output Response Analyzers
(ORAs) to diagnose the Circuit under Test (CUT) for
presence of faults. The TPG generates vectors which are
fed to the CUT. Responses from the CUT are compared
by the ORA against expected values to detect the presence
of faults.
Past testing schemes for FPGAs have mostly targeted:
(1) Look up Tables (LUTs) within the Configurable Logic
Blocks (CLBs), and (2), the Interconnects between the
CLBs [1-4]. However, limited work has been done in the
area of testing distributed RAM in FPGAs. Also, in the
past, memories in FPGAs have been tested for the
presence of stuck-at faults only [5-8]. The current research
proposes to develop a new BIST scheme to test the
memory of Virtex-4 series FPGA for presence of address
decoder, transient, inversion coupling, and also stuck-at
faults using the March X Algorithm [13]. In this research,
the Virtex-4 FPGA is modeled in VHDL at the equivalent
gate level and simulation results are presented using
ModelSim.
2. Overview of Virtex-4 FPGA
Xilinx Virtex-4 series represent SRAM programmable
FPGAs. The Virtex-4 family greatly enhances the
programmable logic design capabilities, making it a
powerful alternative to ASIC technology. Virtex-4
includes Input/Output blocks, Configurable Logic Blocks
(CLBs), distributed SRAM, Block RAM, DSP slices and
digital clock managers. A CLB contains four
interconnected slices. Slice M indicates a pair of slices in
the left column and Slice L indicates a pair of slices in the
right column. The elements common to both slice pairs
are two logic function generators (or Look-up Tables),
two storage elements (D-flip flops), wide function
multiplexers, carry logic, and arithmetic gates. Slice M, in are accessed. In case of multiple stuck-at faults within the
addition, contains distributed RAMs and 16-bit shift AND gate inputs, many addresses may access the same
registers. cell.
The control signals [12] including the clock (CLK),
clock-enable (CE), and set-reset (SR) are common to both S0 S1 S2 S3 (b)
the storage elements in a slice. Other control signals for
distributed RAM are Write Enable and Data in. For write Y0
operation, the Write Enable signal must be set high and
Y1
for the read operation, it must be set low. For testing (a)
SRAM memory, a simplified functional model (refer Y2
Figure 1) consisting of address decoder, memory array
and multiplexer is used. Y3

Y4
LUT Y5
Input
4: 16
Y6
Address 16:1 LUT
Decoder MUX Output Y7

Y8

Y9
SRAM
Array Y10

Figure 1: LUT/ RAM functional model. Y11

Y12
During a write operation, the decoder output is used to
select the memory cell where information is to be stored Y13
or written. The LUT output is kept in a high impedance
state during this operation. During a read operation, the Y14
MUX outputs the value stored in the cell. Y15

3. Memory Faults
Figure 2: Address Decoder stuck at (a)
A critically important fault that can occur in a memory Decoder input line (b) AND gate input.
is the address decoder fault. The address decoder faults
may result in wrong memory cell being accessed at the
wrong time. It may also result in no memory location S0 S1 S2 S3
being accessed or more than one location being accessed
simultaneously. Address decoder faults may occur due to
an entire input line being stuck at 1 or 0 (refer Figure 2) or I0
due to open input lines [14]. I1
We investigate address decoder faults by considering I2 Y0
I3
the AND gate inputs present in the decoder to be stuck at
1 or stuck at 0 (refer Figure 3). Since, in our example,
there are four inputs to each AND gate, we can have 16 AND gate I3
different combinations of AND gate inputs that could be input stuck at 1
stuck. We consider single stuck at faults at the inputs of
the AND gates of the decoder. Multiple faults are not Figure 3: Stuck-at 1 fault inserted at AND
considered in this paper. As an example, for the address gate of decoder.
0000, consider a stuck at 1 fault at input I3 of the AND
Table 1 shows the addresses that could be generated to
gate. When address 0000 is generated, the output of the
access cell 0 for various combinations of the AND gate
AND gate Y0 is 1 indicating that address 0000 accesses
inputs stuck at 1 for the actual address 0000. A different
cell 0. However, when address 0001 is generated, then
type of address decoder fault where a cell is never
both Y0 and Y1 are 1 indicating that both cell 0 and cell 1

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accessed due to an open input at the AND gate in the 1(address 0001) is coupled to cell 0 (address 0000). When
address decoder may also occur. In case of opens in gate a 1 is written in cell 0 (previously containing a 0), cell 1
inputs, the address is undefined and hence some cells may content gets inverted and so instead of reading a 0, cell 1
not be accessed. For example, for address 0000, if any reads a 1.
AND gate input is stuck-open, the decoder output will not
be generated and hence cell 0 will never be accessed.
In addition to address decoder faults, memory cells
0 0 0 0
may be affected by stuck-at, transient, and inverse 0
10
0
0 0
coupling faults. 0 0
0 0
Din = 1 Din = 1
0 0 1 0
TABLE 1: FAULTY ADDRESS DUE TO GATE INPUT 1 1 1 1
STUCK AT 1. F G F G
M1 M1
Cell 0 accessed with
AND gate input stuck at following addresses
Actual Address WE=1 WE=0
1 due to the fault at AND
gate input stuck at 1 0 0 0 0 0 0 0 1
S0 S1 S2 S3 I3 I2 I1 I0 S0’msb S1’ S2’ S3’
- - - SA1 0 0 0 1 Figure 4: Demonstration of inversion coupling
- - SA1 - 0 0 1 0 fault.
- - SA1 SA1 0 0 1 1
- SA1 - - 0 1 0 0
4. Memory test March X algorithm
- SA1 - SA1 0 1 0 1
- SA1 SA1 - 0 1 1 0 There are many types of March tests [5-10] and they
- SA1 SA1 SA1 0 1 1 1 all have different fault coverage. In this research, because
SA1 - - - 1 0 0 0 of its time efficiency, we use the March X algorithm [13]
SA1 - - SA1 1 0 0 1 for detecting the four types of memory faults under
discussion. The March X scheme is shown in Figure 5.
0 0 0 0 SA1 - SA1 - 1 0 1 0
SA1 - SA1 SA1 1 0 1 1
SA1 SA1 - - 1 1 0 0 {↕(w0); ↑(r0,w1); ↓(r1,w0); ↕(r0); }
SA1 SA1 - SA1 1 1 0 1
SA1 SA1 SA1 - 1 1 1 0 M0 M1 M2 M3
SA1 SA1 SA1 SA1 1 1 1 1
Figure 5: March X algorithm.
Stuck-at faults cause content of the memory cells to be
permanently stuck at 1 or 0. The content does not change Stuck-at faults are detected since each cell is read with
during any write operation. The SA0 fault can be detected expected value 0 by operation M1 and M3 and with
by a read operation following a w0 (write 0) operation on expected value 1 by M2. Up-transient faults are detected
the faulty cell while the SA1 fault can be detected by a by M1 followed by M2 and down-transients by M2
w1(write 1) operation followed by a read operation. followed by M3. Address decoder faults (AFs) are
Transient faults occur when the cell fails to undergo a 0 detected since each cell is written with a zero during M0
to 1 transition when a 1 is written in a cell in state 0 up- operation and then read with expected value 0. Also, a 1
transition fault) or a 1 to 0 transition (down-transition) is written in operation M1 at the same memory location.
when a 0 is written in a cell in state 1. Transition faults Inversion coupling faults are detected by March element
cannot be treated as stuck-at faults because other faults M1 when the coupled cell has a higher address than the
such as coupling faults may bring the cell back into the coupling cell.
opposite state.
A coupling fault is present when a write operation that 5. Proposed BIST scheme
makes an up or down transition in one cell causes the
content of the other cell to change. In case of inversion The proposed BIST scheme for testing is designed
coupling faults, any transition in one memory cell causes based on two factors: 1) The time taken for testing the
content in adjacent memory cell to get inverted. The cell FPGA and 2) the ease of detecting the location of fault in
on which the write operation takes place is known as the the device. In the past, some BIST schemes to test
coupling cell and the cell whose value gets inverted is embedded memories have been developed, each having its
called the coupled cell. As shown in Figure 4, cell own advantages and disadvantages.

967
The BIST scheme implemented in [5] makes use of three one for each LUT, which makes detection of the faulty
CLBs, one each for a TPG (Test Pattern Generator), CUT LUT/ RAM (F or G) possible. If the fault is present in the
(Circuit Under Test), and ORA (Output Response first CLB in the chain then the fault signal will transverse
Analyzer) while the one mentioned in [6] takes a more the entire path to the output. If all the ORA outputs F1-F4
distributed approach. In this approach, the TPG and ORA or G1-G4 show “1111” then it can be concluded that the
are combined in a single CLB thus reducing the test fault is present in the first CLB in the chain. Similar
sessions to two. It also divides the FPGA into two halves conclusion can be reached when ORA outputs show
and uses a scan-chain mechanism to scan the fault signal “0111” (CLB#2), or “0011” (CLB#3), or “0001”
at the output. The advantage is that time taken for fault to (CLB#4). The address at which the fault is present can be
get detected at the I/O pins is reduced to half when found from the TPG address as soon as the faulty signal
compared with the schemes in [7-8] which make use of goes high.
single long scan chain but the disadvantage of this
approach is that it uses external components for testing 6. Simulation results
and diagnosis.
From CUT in CLB#1 of other
The functional model of the Xilinx Virtex-4 FPGA for
Faulty a single chain of four CLBs is implemented using VHDL.
chain
F4
The March X algorithm is applied on the model for testing
CLB#2 CLB#3 CLB#4
CLB#1 purposes.
F
F
2
F Initially, the simulations are done without introducing
0 1 3
O O O O any faults. The simulations are then done for each of the
R R R R individual faults: address decoder, inversion coupling,
A A A A stuck-at, and transient faults.
Faulty
G4
CASE 1: Address Decoder fault at address 0010 of G
LUT.
C C C
C The ‘Bitofaddress’ signal is used to select the AND gate
U U U U input to be stuck at 1 or 0. In case of our simulation, I3
T T T T input of gate (Bitofaddress value = “0001”) is stuck-at 1.
Hence, address 0011 allows access to both cells 2 and 3 of
the memory. Figure 7 shows the simulation results. In
Figure 7, the blue lines show high impedance state, red
TP TP TP TP
lines show unknown state and the green lines show logic
G1 G2 G3 G4 level ‘1’ or logic level ‘0’ (read value).
CASE 2: Memory Stuck-at 1 fault at address 0100 of F
LUT and Inversion Coupling Fault at address 0001 of F
CLB# n CLB# n+1 CLB# n+2 CLB# n+3
LUT in CLB #1
The stuck-at fault is also present in memory where the
Figure 6: Proposed BIST Architecture content of the cell is stuck at 1 or 0. The stuck-at 1 fault is
(Single Chain). placed at address 0100. Therefore cell 4 always reads
In our scheme (refer Figure 6), the ORA and CUT value 1. The inversion coupling fault is placed at address
(memory) are combined in a single CLB. The TPG is a 4- 0001 of the same CLB and is also coupled to address
bit up/down address counter. A separate CLB is used for 0000. Figure 8 shows the simulation results for both the
each TPG. The ORA is a simple XOR gate. The entire faults.
FPGA array is divided to form two scan chains in each CASE 3: Open address line fault at address 0011 of G
row. Each CUT in the same row receives address from a LUT and transient (0 to 1) fault at address 0001 of F LUT
different TPG. The advantage of this technique is to in CLB # 1.
eliminate a faulty TPG sending wrong address to the Simulation results for the above condition are done in a
CUTs. The ORA compares the output of the memory similar way.
under test with the memory output in the adjacent CLB Both these faults are detected during the M2 March
and the comparison signal of the previous ORA. Since element operation. Due to the stuck open fault, cell 3 is
CLB #1 in the chain has no previous ORA output, one of not accessed during any write operation and hence the
its inputs is always set to 0. The memory of CLB#4 is read operation on cell 3 gives an ‘X’ representing an
compared with the memory of CLB #1 in the other chain unknown state. The read operation on cell 1 during the
in the same row. The output of the ORA determines the M2 operation does not read a 1 as cell 1 does not
fault and its location. The ORA outputs two faulty signals, transitions to logic 1.

968
The fault coverage of the proposed scheme is shown in
Table 2.
Table 2: Fault Coverage.

Faulty Signal
CLB Fault Detection
F1/G1 F2/G2 F3/G3 F4/G4
0 0 0 0 No Fault in any CLB
0 0 0 1 CLB#4 Faulty
0 0 1 0 CLB#3 and CLB#4 Faulty. (Fault inserted at same address so undetected)
0 0 1 1 CLB#3 is faulty
0 1 0 0 CLB # 2 and CLB#3 Faulty. (Fault inserted at same address so undetected)
0 1 0 1 SA-0 or Up-Transient Fault or Address decoder faults in CLB # 1
0 1 1 0 CLB # 2 and CLB#4 Faulty. (Fault inserted at same address so undetected)
0 1 1 1 CLB#2 Faulty
1 0 0 0 CLB # 1 and CLB#2 Faulty (Fault inserted at same address so undetected)
1 0 0 1 SA-0 or Up-Transient fault or Address Decoder Faults in CLB # 3
1 0 1 0 CLB # 1, CLB #2, CLB#3, CLB #4 faulty.(Faults inserted at same address so undetected)
1 0 1 1 SA-0 or Up-Transient or Address Decoder fault in CLB #4
1 1 0 0 CLB # 1 and CLB#3 Faulty.(Fault inserted at same address so undetected)
1 1 0 1 SA-0 or Up-Transient fault or Address Decoder fault in CLB # 2
1 1 1 0 CLB # 1 and CLB#4 Faulty(Fault inserted at same address so undetected)
1 1 1 1 CLB#1 is faulty

Figure 7: Address decoder fault at address 0010 of G LUT (yellow circle).

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 Figure 8: Inversion coupling fault at address 0001 (yellow circle) and stuck-at 1 fault at address 0100 (red
circle) of F LUT in CLB #1.
7. Conclusion
This paper deals with testing of address decoder,
inverse coupling, transient, and stuck-at faults in
distributed SRAMs of Virtex-4 FPGAs using a modified
March X algorithm. Simulation results show the
successful testing and fault location capabilities of the
approach. Unlike previous schemes described in [5-6] and
[8], the proposed BIST scheme is time efficient and able
to detect and locate all the above mentioned faults.
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