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  • ASYNCHRONOUS TESTBENCH Module

    Diunggah oleh

    madhusudhan
    9 tayangan4 halaman
    This document contains code for asynchronous testbenches and counters including: 1) An asynchronous testbench module that initializes a clock signal toggling every 100 time units and resets an asynchronous up/down counter module after 300 time units. 2) An asynchronous decade counter module that resets to 0 after reaching the count of 9. 3) An asynchronous up counter module that increments its count on each clock pulse while an enable signal is high, and resets its count when the enable signal is low.

    Deskripsi Asli:

    Counters all VLSI

    Judul Asli

    All Counters

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    This document contains code for asynchronous testbenches and counters including: 1) An asynchronous testbench module that initializes a clock signal toggling every 100 time units and resets an asynchronous up/down counter module after 300 time units. 2) An asynchronous decade counter module that resets to 0 after reaching the count of 9. 3) An asynchronous up counter module that increments its count on each clock pulse while an enable signal is high, and resets its count when the enable signal is low.

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    © All Rights Reserved
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    9 tayangan4 halaman

    ASYNCHRONOUS TESTBENCH Module

    Diunggah oleh

    madhusudhan
    This document contains code for asynchronous testbenches and counters including: 1) An asynchronous testbench module that initializes a clock signal toggling every 100 time units and resets an asynchronous up/down counter module after 300 time units. 2) An asynchronous decade counter module that resets to 0 after reaching the count of 9. 3) An asynchronous up counter module that increments its count on each clock pulse while an enable signal is high, and resets its count when the enable signal is low.

    Hak Cipta:

    © All Rights Reserved
    Unduh sebagai DOCX, PDF, TXT atau baca online dari Scribd
    Tandai sebagai konten tidak pantas
    dari 4

    ASYNCHRONOUS TESTBENCH

    module test;
    reg rst,clk,en,up_down;
    wire [3:0] q;
    aupdown counter1(rst,clk, en,up_down,q);
    initial
    begin
    clk= 1'b0;
    forever #100 clk = ~ clk;
    end
    initial
    begin
    rst = 1'b1;#300;
    rst = 1'b0;
    en = 1'b1;
    up_down = 1'b1;#3300;
    up_down = 1'b0;#6600;
    end
    initial #6500 $finish;
    endmodule
    ASYNCHRONOUS DEC TESTBENCH
    module test;
    reg rst,clk,en;
    wire [3:0] q;
    asyndecade counter1(rst , clk , en,q);
    initial
    begin
    clk= 1'b0;
    forever #100 clk = ~ clk;
    end
    initial
    begin
    rst = 1'b1;#200;
    rst = 1'b0;
    en=1'b1;
    #3300;
    end
    initial #3300 $finish;
    endmodule
    ASYNCHRONOUS DECADE

    module asyndecade(rst,clk,en,q);
    input rst,clk,en;
    output [3:0] q;
    reg[3:0]q;
    always @ (posedge clk , rst,en)
    begin
    if (rst==1)
    q<= 4'b0000;
    else if (en==1 && q == 9)
    q <= 4'b0000;
    else
    q<=q+1;
    end
    endmodule
    ASYNCHRONOUS COUNTER UP

    module asyncnt4(rst,clk,en,q);
    input rst,clk,en;
    output [3:0]q;
    reg [3:0]q;
    always @ (posedge clk, rst,posedge en)
    begin
    if(rst==1)
    q<=4'b0000;
    else if(en==1)
    q<=q+1;
    else
    q<=4'b0000;
    end
    endmodule

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