Company DKT 212/3

LOGO DIGITAL SYSTEM 2

CHAPTER 3
Counters
 Overview

 Introduction
 Asynchronous Counter
 Synchronous Counter
 Design Synchronous Counter
 Introduction

 A counter – a group of flip-flops connected

together to perform counting operations.
 The number of flip-flops used and the way in
which they are connected determine the
number of states (modulus).
 Two broad categories according to the way they
are clocked:
– Asynchronous counter
– Synchronous counter
 ASYNCHRONOUS COUNTER

– Don’t have fixed time relationship with each

other.
– Triggering don’t occur at the same time.
– Don’t have a common clock pulse
– The clock input is always connected to LSB flip-
flop

A 2-bit asynchronous binary counter

 The Timing Diagram

– Main clock pulse only applied to FF0.

– Clock for next FF, taken from previous
complemented output (Q).
– All inputs (J, K) are high (Vcc).
The Timing Diagram
 The Binary State Sequence

0 1 0 1 0

0 0 1 1 0

CLOCK PULSE Q1 Q0
Initially 0 0
1 0 1
2 1 0
3 1 1
4 (recycles) 0 0
 3-bit asynchronous binary counter &
timing diagram (1 cycle)

Draw the output waveforms for Q0, Q1 and Q2

3-bit asynchronous binary counter &
timing diagram (1 cycle)
 The Binary State Sequence for a 3-
bit Binary Counter

CLOCK PULSE Q2 Q1 Q0
Initially 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
6 1 1 0
7 1 1 1
8 (recycles) 0 0 0
 Propagation delay

 Asynchronous counters commonly referred as ripple counter

 Effect of input clock pulse ‘ripples’ through the counter taking
some time to reach the last flip-flop due to propagation delay.
4-bit asynchronous binary counter &
timing diagram
 ASYNCHRONOUS DECADE
COUNTER

 The modulus of a counter is the number of unique

states that the counter will sequence through.
 The maximum possible number of states (max modulus)
is 2n . Where n is the number of flip-flops.
 Counter can also be designed to have a number of
states in their sequence that is less than the maximum
of 2n. The resulting sequence is called truncated
sequence.
 Counter with ten states are called decade counter.
 To obtain a truncated sequence it is necessary to force
the counter to recycle before going through all of its
possible states.
 decade counter

 Decade counter with a count sequence of zero (0000)

through nine (1001) is a BCD decade counter because
its ten-state sequence produces the BCD code.
 Required 4 flip-flop (3 insufficient because 23=8)
 BCD decade counter must recycle back to 0000 state
after 1001 state.
 One way to make the counter recycle after the count of
nine (1001) is to decode count ten (1010) with a NAND
gate and connect the output of the NAND gate to clear
(CLR) inputs of the flip-flop.
An asynchronously clocked
decade counter
 EXERCISE

Example:
Show how an asynchronous counter can be
implemented having a modulus of twelve with a
straight binary sequence from 0000 through
1011.
 EXERCISE

Solution:
Q3 Q2 Q1 Q0

0 000
: : ::
1 011
1 100

Use NAND gate to reset flip-flop 2 and 3 to 0

 SYNCHRONOUS COUNTER

In a synchronous counter all flip-flops are clocked together with

a common clock pulse. Synchronous counters overcome the
disadvantage of accumulated propagation delays, but generally
they require more circuitry to control states changes.
This 3-bit binary synchronous counter has the same count sequence as
the 3-bit asynchronous counter shown previously
HIGH
Q0

Q0Q1
J0 Q0 J1 Q1 J2 Q2

C C C

K0 K1 K2

CLK
18
 SYNCHRONOUS COUNTER
OPERATION

 A 2-bit synchronous binary counter

 The Binary State Sequence

0 1 0 1 0

0 0 1 1 0

CLOCK PULSE Q1 Q0

Initially 0 0

1 0 1

2 1 0

3 1 1

4 (recycles) 0 0
A 3-bit synchronous binary
counter
A 3-bit synchronous binary
counter
 The Binary State Sequence for
a 3-bit Binary Counter

CLOCK PULSE Q2 Q1 Q0
Initially 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
6 1 1 0
7 1 1 1
8 (recycles) 0 0 0

Q2 change state when BOTH Q1 and Q0 are HIGH

 A 4-bit synchronous binary counter
and timing diagram

Points where the AND gate outputs are HIGH are indicated by the shaded areas.
 Synchronous BCD Decade
Counter

With some additional logic, a binary counter can be

converted to a BCD synchronous decade counter. After
reaching the count 1001, the counter recycles to 0000.

This gate detects 1001, and causes FF3 to toggle on the

next clock pulse. FF0 toggles on every clock pulse.
Thus, the count starts over at 0000.

25
A 4-Bit Synchronous BCD
Decade Counter
 The Binary State Sequence for BCD
Decade Counter

CLOCK PULSE Q3 Q2 Q1 Q0
Initially 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
10 (recycles) 0 0 0 0
 DESIGN OF SYNCHRONOUS
COUNTERS

 General clocked sequential circuit

 Steps used in the design of
sequential circuit
1. Specify the counter sequence and draw a state
diagram
2. Derive a next-state table from the state diagram
3. Develop a transition table showing the flip-flop inputs
required for each transition. The transition table is
always the same for a given type of flip-flop
4. Transfer the J and K states from the transition table
to Karnaugh maps. There is a Karnaugh map for each
input of each flip-flop.
5. Group the Karnaugh map cells to generate and derive
the logic expression for each flip-flop input.
6. Implement the expressions with combinational logic,
and combine with the flip-flops to create the
counter.
State diagram for a 3-bit Gray code
counter
 Next-state table for a 3-bit Gray
code counter

Present State Next State

Q2 Q1 Q0 Q2 Q1 Q0
0 0 0 0 0 1
0 0 1 0 1 1
0 1 1 0 1 0
0 1 0 1 1 0
1 1 0 1 1 1
1 1 1 1 0 1
1 0 1 1 0 0
1 0 0 0 0 0
 Transition Table for a J-K flip-flop

Output Transitions Flip-flop Inputs

QN QN+1 J K

0  0 0 X

0  1 1 X

1  0 X 1

1  1 X 0

QN : present state

QN+1: next state

X: Don’t care
Karnaugh maps for present-state J
and K inputs
Three-bit Gray code counter
 EXAMPLE EXERCISE

 Design a counter with the irregular binary count

sequence as shown in the state diagram. Use J-K flip-
flops.
 EXAMPLE : TRANSITION TABLE

Present State Next State

Q2 Q1 Q0 Q2 Q1 Q0

0 0 1 0 1 0

0 1 0 1 0 1

1 0 1 1 1 1

1 1 1 0 0 1
 Transition Table for a J-K flip-flop

Output Transitions Flip-flop Inputs

QN QN+1 J K

0  0 0 X

0  1 1 X

1  0 X 1

1  1 X 0
EXAMPLE : K-MAP
EXAMPLE : COUNTER CIRCUIT
Example 2: State diagram for a 3-bit
up/down Gray code counter.
J and K maps. The UP/DOWN control input,
Y, is treated as a fourth variable
3-bit up/down Gray code
counter