LAB 9

Layout of 1-bit Full Adder

By
Sachin B. Kadam
15ECE1022
AIM: To design the layout of a 1-bit Full Adder

SCHEMATIC

Figure 1 (a): Truth Table of 1-bit Full Adder

Figure 1(b): 1-bit Full Adder NAND Logic

 Figure 1(c): Schematic of a 1-bit Full Adder

Procedure:
1. Rig up the given circuit diagram in the file type of schematic and plot graph to check pre layout
simulation.
2. To create the symbol remove all the input sources and replace them with corresponding input,
output and InputOutput pins.

 Create Cellview from Cellview.

 Left side pin - Input
 Right side pin - Output
 Top pin - Vdd
 Bottom pin – gnd
 A Symbol box will appear on a new window. We can change the shape of the symbol box
as desired.

3. To open Layout window

  Open schematic window.
 Now Go to LAUNCH -> Layout XL -> Create new layout

 After that Layout window will appear

 Go to Connectivity -> Generate All from source -> OK

 Press Shift+F to generate the internal view

 Make all the connections as per circuit diagram.
 Run Assura DRC to check the proper alignment and spacing of the layout design. We will have to
add the technology file when running DRC for the first time. Correct errors if any.
 After that Run LVS (Layout v/s Schematic) and check whether they match or not. Do the necessary
corrections.
 Run Quanta QRC, go to extraction and select RC to find out all the parasitic capacitance and
resistance present in the circuit.

4. Post layout Simulation

 Create a new schematic file and add an instance of the symbol of the Full adder previously
created.
 Connect input source and ground to the symbol and a make another copy of the newly
created symbol in the same file. Keep the output pins of different name to avoid the
ambiguity in the output plot.
 Now open a new file with the same name as above created file and open it as config type.
Select Schematic view and use spectre template.
 Go to the tree & table view select the first symbol and set the Instance view as schematic
and for the second symbol circuit set it to av_extracted.
 Open the Config view and perform the necessary simulations (DC & Transient) using
ADEL.

1-Bit Full Adder

The symbol for the Full Adder was designed as follows:

Figure 2: Symbol for the 1-Bit Full Adder Cellview
The testbench designed to ensure that the schematic was working correctly was as follows:

Figure 3: Testbench for 1-bit Full Adder schematic

 LAYOUT DESIGN

Figure 4: Layout Design of 1-bit Full Adder

 PARASITIC EXTRACTION

Figure 5: av_extracted file containing information about the parasitic elements in the Full Adder
 CONFIG FILE

Figure 6: Config file to observe the difference in outputs between schematic and layout designs
Transient Analysis

Figure 7(a): Transient Response of Schematic and Layout

Figure 7(b): Propagation Delay in Sum between Schematic and Layout
 Figure 7(c): Propagation Delay in Carry between Schematic and Layout From the
plots obtained above, we see that there is a slight difference between the output
due to the schematic and the layout. This is because the schematic does not
consider the effect of parasitic resistances and capacitances.

Another thing we observe is that in the transient response the output appears to spike before it
changes from high to low or vice versa. This is because of Gibbs phenomenon which is the
ringing effect at the discontinuity points. This ringing effect can be removed by using an
appropriate load capacitor.
Effect of Load Capacitor on Transient Analysis

Figure 8(a): Transient Response of Schematic and Layout with Load Capacitor
CONCLUSION

In this experiment we have successfully implemented the Layout for the 1-bit Full adder
according to the CMOS NAND logic. From the above experiment, it can be said that the
realization of a given circuit depends on its layout. This is because a certain layout design may
introduce parasitic resistances and capacitances. The Layout should be designed in such a way
to minimize the parasitics in order to obtain a response close to that of the schematic.
The increased number of parasitics is due to the use of Metal2 in the Layout design for which
design has to go to next floor.
As observed in the graphs above, a propagation delay of 1.6ps was observed in Sum and 39ps in
Carry for the worst case, giving an average propagation delay of 20.3ps.

The layout was designed with minimal use of space to constrain within an area of 7777.7 µm2.

The product of the area of this design by the square of the propagation delay,
A * tp2 = 7777.7 µm2* (20.3ps)2 = 1.577 x 10-22ms2