Contents
Efficiency Definitions
POUT
¤ Drain Efficiency: ηD =
PDC
IDS
VGS=0
Im
gm
VGS=VP
VGS VDS
2VP VP 0 0 VK VDD VDSmax
VDD − V K
κ=
VDD
gm
VGS=VP
VGS VDS
2VP VP 0 0 VK VDD VDSmax
VDS max − VK
ROPT =
Im
Class A
IDS IDS
Im Im
VGS VDS Q
2VP VP 0 0 VK VDD VDSmax 0 p 2p
VGS VDS
2p
Q
Class A – Circuit
VDD
G D
RL
S
η D = κ ⋅ 50%
G = G A (e.g. 14 dB)
η PA = κ ⋅ 48%
Class B
IDS IDS
Im Im
VGS VDS Q
2VP VP 0 0 VK VDD VDSmax 0 p 2p
VGS VDS
2p
Q
Class C
IDS IDS
Im Im
VGS VDS Q
2VP VP 0 0 VK VDD VDSmax 0 p 2p
VGS VDS
2p
Q
f0
G D
RL
S
Class B Class C
ηD = κ ⋅ 78% ηD → 100%
G = G A - 6dB (8 dB) G →1
11
Im Im
VGS VDS Q
2VP VP 0 0 VK VDD VDSmax 0 p 2p
VGS VDS
2p
Q
12
IDS IDS
Im Im
VGS VDS Q
2VP VP 0 0 VK VDD VDSmax 0 p 2p
VGS VDS
2p
Q
13
Zo(n)
0, n=1
ID Ze(n) inf, n=odd
VDS 0, n=even
RL
inf, n=even
Class F hHCA
ηD = κ ⋅100% ηD = κ ⋅100%
Im Im
VGS VDS Q
2VP VP 0 0 VK VDD VDSmax 0 p 2p
VGS VDS
2p
Q
15
G D 3f0
f0 RL
S
ηD = κ ⋅ 91%
ηPA = κ ⋅ 87%
16
Linearity Aspects
17
Linearity Aspects
¤ Class A ¤ Class AB
¤ Class B ¤ Class C
18
Linearity Aspects
19
Port 1
Z=50 Ohm Port 2
Z=50 Ohm
20
20 4000
0 500
15 3000
-1 0 10 2000
5 1000
-2 -500
Inner Gate Voltage (L, V) Inner Gate Current (R, mA)
0 0
Amp Amp
-3 -1000 -5 -1000
0 500 1000 1300 0 500 1000 1300
Time (ps) Time (ps)
21
4000 50
20 40
2000 30
10 20
0
10
-2000 0 0
0 3 6 9 12 15 0 5 10 15 20 24
Voltage (V) Power (dBm)
22
60 60 PAE[%]
40 80 PAE[%]
1dBCP
35 70
50 50
30 60
25 50
Pout Pout
IMDD
Gain 30 30
20 40 Gain
GammaIn
PAE
PAE
15 30
20 20
10 20
10 10
5 10
0 0 0 0
0 5 10 15 20 25 30 35 0 5 10 15 20 25 30 35
Pin[dBm] P in [dBm]
23
Amplifier Nonlinearity
¤ Gain and Phase depends on Input Signal
24
Amplifier Nonlinearity
¤ Higher Output Level (close to Saturation) results
in more Distortion/Nonlinearity
25
¤ Constellation Deformation
26
27
Spectral Regrowth
10
ACPR 1>60dB
ACPR 2>60dB
0
ACPR =16dB
1
ACPR 2=43dB
-10
relative power / dB
-20
-30
-40
-50
-60
-15 -10 -5 0 5 10 15
relative frequency / MHz
28
29
Constellation Deformation
¤ Input Signal ¤ Output Signal of
Nonlinear Amplifier
(with Gain- and Phase-Distortion)
30
Modeling of Nonlinearities
¤ with Memory-Effects
l Volterra Series (=„Taylor Series with Memory“)
¤ without Memory-Effects
αar α Θr 2
performance
l Saleh Model f (r ) = g (r ) =
1 + β ar 2
1 + βΘr 2
better
l Taylor Series
l Blum and Jeruchim Model
l AM/AM- and AM/PM-conversion
31
32
33
34
35
¤ Classical Method
¤ Decrease of Gain à Low Efficiency
¤ Feedback needs more Bandwidth than Signal
¤ Stability Problems at high Bandwidths
36
Distortion Feedback
37
Feedforward
38
Cartesian Feedback
baseband input
I
modulator main amp.
I RF-output
OPAs
Q
Q
local
oscillator
10
UMTS example:
original signal
I predistorted signal
Q 0
demodulator -10
relative power / dB
-20
AM/PM-correction -40
Digital Predistortion
¤ Digital Implementation of „Cartesian Feedback“
¤ Additional ADCs, DSP Power, Oversampling needed
¤ Loop can be opened à no Stability Problems
40
Analog Predistortion
41
Analog Predistortion
¤ Possible Realizations:
42
s1(t) Ks1(t)
K
K(s1(t)+s2(t))
s(t) signal =Ks(t)
separation
s2(t) Ks2(t)
K
UMTS example:
10
¤ AM/AM- and s(t)
ACPR 1 >60dB
ACPR 2 >60dB
AM/PM-correction 0 s1 (t)
ACPR 1 =18dB
ACPR 2 =29dB
relative power / dB
(accuracy!) -20
-60
-30 -20 -10 0 10 20 30
relative frequency / MHz
43
Doherty Amplifier
¤ Auxiliary amplifier supports main amplifier during saturation
¤ PAE can be kept high over a 6dB range
44
Doherty Amplifier
¤ Gain vs. Input Power ¤ Efficiency vs. Input Power
POUT
2)
1+A
(A
n
io main amp. (A1)
rat
u
fig
c on
rty aux. amp. (A2)
he
do
PIN
45
RF input signal
separation
phase information RF output
high efficiency
power amplifier
46
high efficiency
peak detector power amplifier
¤ Digital realization
l Oversampling + high D/A- amplitude information
conversion rates required digital baseband input D
supply voltage amplifier
47
-10 -10
relative power / dB
ACPR1 =51dB
ACPR2 =36dB
-20 -20
ACPR1 =53dB
ACPR2 =49dB
-30 -30
-40 -40
-50 -50
-60 -60
-30 -20 -10 0 10 20 30 -30 -20 -10 0 10 20 30
relative frequency / MHz relative frequency / MHz
48
Adaptive Bias
¤ Varying/Switching of Bias-Voltage depending on
Input Power Level
¤ Selection of Operating Point with high PAE
¤ Applicably for nearly each type of Amplifier
peak detector
bias
control
RF input RF output
high efficiency
power amplifier
49
Adaptive Bias
¤ Single tone PAE for switched ¤ Simply to implement Concept
VDD with VG kept constant ¤ Stability guaranteed
90 ¤ Possible problems:
80 l DC-DC converter with high
power added efficiency / %
70 efficiency necessary
60 l Possible Linearity Change
50
(can increase and decrease)
40
especially for HCAs
V D =3.5V
30 V D =4.5V
V D =6.5V
20
32 33 34 35 36 37 38 39 40
output power / dBm
50
Summary
¤ Digital Realization required to achieve Accuracy
51
Figure References
¤ F. Zavosh et al,
“Digital Predistortion Techniques for RF Power
Amplifiers with CDMA Applications”,
Microwave Journal, Oct. 1999
¤ Peter B. Kenington,
“High-Linearity RF Amplifier Design”,
Artech House, 2000
¤ Steve C. Cripps,
“RF Power Amplifiers for Wireless Communications”,
Artech House, 1999
52
Contact Information
( +43-1-58801-35425 ( +43-1-58801-35420
- markus.mayer@tuwien.ac.at - holger.arthaber@tuwien.ac.at
53