Synthesis

Synthesis flow
• Synthesis is the process of translating and mapping RTL code written
in HDL (such as Verilog or VHDL ) into technology specific
gate level representation
• Synthesis consists of 3 stages
• Translation
• Optimization (technology independent)
• Mapping + optimization (technology dependent)
• Tools used
• Genus from cadence
• Design compiler (DC) from Synopsys
Stages of synthesis
• Translation
• RTL code is translated to boolean format
• Optimization
• Logic restructuring : boolean equations are optimized using PoS & SoP optimization
techniques
• To reduce the no. of gates
• Gates are represented using generic cells (gtech or generic libs)
• Technology independent optimization
• Mapping
• The above generic gate verilog is mapped to the desired technology (tech libs)
• Optimization are performed to meet given design constraints
• Technology dependent optimization
Inputs/outputs for synthesis
• Inputs
• RTL (.v files)
• Technology libraries (.lib files or liberty files)
• Design constraints (SDC file)
• LEF files (only for physical aware synthesis)
• Outputs
• Netlist (Technology mapped gate verilog)
RTL
• Module definitions
module module_name (port_list);
input [msb:lsb] input_port_list;
output [msb:lsb] output_port_list;
inout [msb:lsb] inout_port_list;
... statements ...
endmodule
• Module Instantiations
• module_name instance_name_1 (port_connection_list);
Liberty file
• Liberty file is a logical library file
• It has timing, area and power information of all logic gates
• It does not contain any physical information of the logic gates, LEF is
the file having physical information
• Also consists of design rule constraints like max transition, max
capacitance & max fanout
• operating conditions and wire load models
Design constraints
• Provided as SDC file (sdc stands for synopsys design constraints)
• Used to specify the design intent, including the timing, power and area
constraints for a design.
• SDC is tcl based
• Consists of
• Clock definitions (create_clock)
• I/O constraints (set_input_delay, set_output_delay etc)
• Exceptions (multi cycle paths, false paths etc)
Liberty file syntax
• library (library_name) {
technology (cmos);
delay_model: table_lookup;
bus_naming_style : string ;
<unit declarations> # for voltage, temperature,
capacitance, timing etc.
operating_conditions(name) {
process, voltage ,temperature
}
wire load models
lookup tables
cell definitions
}
Liberty file syntax