This article has been accepted for publication in a future issue of this journal, but has not been
fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2016.2615048, IEEE
Transactions on Power Electronics
IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. XX, NO. XX, XXXX XXXX
Low-Voltage-Ride-Through (LVRT) Control of an
HVDC Transmission System Using two Modular
Multilevel DSCC Converters
Kota Oguma, and Hirofumi Akagi, Fellow, IEEE
Abstract—This paper presents an intensive discussion on a
high-voltage direct-current (HVDC) long-distance transmission
system combining two modular multilevel double-star chopper-
cells (DSCC) converters with dc power cables. Hereinafter, each
converter is referred to simply as a DSCC converter, or just
as a DSCC for more simplicity. Such an HVDC transmission
system is required to provide low-voltage-ride-through (LVRT)
capability to enhance system availability. This paper proposes
a practical LVRT control characterized by the use of power-
line communications between the two DSCC converters. The
validity and effectiveness of the LVRT control is verified not
only by simulated waveforms obtained from the software package
“PSCAD/EMTDC” but also by experimental waveforms from a
three-phase 200-V, 400-Vdc, 10-kW, 50-Hz downscaled system
with 300-meter-long dc power cables.
Keywords—high-voltage direct-current systems, low-voltage-ride-
through performance, modular multilevel DSCC converters.
I. I NTRODUCTION
H IGH-voltage direct-current (HVDC) systems are prefer-
able to high-voltage alternating-current (HVAC) systems,
in particular for long-distance power transmission. Moreover,
an HVDC system based on voltage-source converters using
IGBTs or GCTs is superior to that based on current-source
converters using light-triggered thyristors from the following
points of view [1]–[3]:
1) Reactive-power control is independent of active-power
control as long as both voltage-source converters are
operated within its volt-ampere rating.
2) Faster control performance of both active power and
reactive power makes a significant contribution to im-
proving system stability, especially under transient and
line-fault conditions.
3) The so-called “black-start capability” provides flexibil-
ity to installation and operation.
4) No commutation failure occurs, thus resulting in im-
proving system availability.
Attention has been paid to a modular multilevel cascade
converter based on double-star chopper-cells (MMCC-DSCC),
or a modular multilevel DSCC converter [4]. This converter
was originally named as a modular multilevel converter [5].
Manuscript received XXXX XX, XXXX; revised XXXX XX, XXXX. This
work was supported by Council for Science, Technology and Innovation
(CSTI), Cross-ministerial Strategic Innovation Promotion Program (SIP),
“Next-generation power electronics” (funding agency: NEDO).
The authors are with the Department of Electrical and Electronic En-
gineering, Tokyo Institute of Technology, Tokyo 152-8552, Japan (e-mail:
oguma.k@akg.ee.titech.ac.jp; akagi@ee.titech.ac.jp).
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1
The term, “MMCC-DSCC” or “modular multilevel DSCC
converter” has been introduced to distinguish it from the other
five MMCC family members without either misunderstanding
or confusion. However, this paper refers it to as a DSCC
converter or just as a DSCC for the sake of simplicity. This
converter is more suitable for HVDC systems than traditional
two-level or three-level voltage-source converters from the
following aspects:
1) Multilevel voltage waveforms with low-voltage steps
appear at the ac side of the converter, thus resulting
in requiring no ac harmonic filter.
2) The simplest three-phase line-frequency transformer
can be used for voltage matching and galvanic isolation
between the converter and the utility grid.
3) No high-voltage dc-link capacitor is required because
each chopper cell has a dc capacitor as an energy buffer.
The following distinct difference exists between a DSCC-
based HVDC transmission system and a DSCC-based back-
to-back (BTB) system. The BTB system has a “zero-meter-
long” dc link between the two DSCC converters because it is
installed at a common site [6]. As a result, the two converters
act as a single converter with a single controller, thus making
it easy to achieve real-time communications between the two
converters. On the other hand, the HVDC system has the two
converters installed not at a common site but far way each
other. Each converter has its own controller with a common
dc transmission power reference that is sent from a central or
reginal load-dispatching center with a renewal time of a few
minutes.
Recently, the so-called “low-voltage-ride-through (LVRT)”
capability has been provided to various grid codes, and it might
be applied to HVDC transmission systems in the near future.
When dc power cables are used to a long-distance HVDC
system, natural disasters such as thunder attack and strong
wind would not cause grounding faults or short circuits on the
dc link. Therefore, this paper considers voltage sags occurring
in the power system upstream of either converter. To provide
LVRT capability to an HVDC system combining two DSCC
converters with dc power cables, each DSCC converter is
required to regulate the dc component included in the capacitor
voltage of each chopper cell to its reference at, and during,
the occurrence of ac-voltage sags, as well as at the restoration
to normal conditions. The following basic proposals to LVRT
capability have been presented:
1) A bulky dc chopper circuit is installed between the two
dc poles to regulate the dc-link voltage [7], [8].
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Transactions on Power Electronics

2 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. XX, NO. XX, XXXX XXXX

2) A bulky capacitor is installed on each chopper cell to iPu

enhance energy-buffer capability [9]. vC1u
cell 1u cell 1v cell 1w
3) Three-phase ac currents of the DSCC converter suffer-
ing from a voltage sag are enhanced to keep power flow
constant [10], [11]. cell 8u cell 8v cell 8w
4) Direct optical-fiber or wireless communications be- iu
tween the two DSCC converters are used to share vuv
iZu
information on ac-voltage sags [12], [13]. vdc
The first and second proposals would be acceptable the-
oretically but not from an engineering point of view. The
third proposal would be practical although LVRT performance cell 9u vC9u cell 9v cell 9w
depends strongly on the voltage depth and duration time of
a voltage sag, as well as operating conditions. The forth cell 16u cell 16v cell 16w
proposal would be the best among the four proposals although
it would be accompanied by increased cost to achieve real-time iNu
communications. (a)
From the above literature review and its considerations, P
it would be natural that an idea of indirect communications
comes across from two different research groups at the almost
same time, independently [14], [15]. The authors of [14] have
proposed the use of existing dc power cables as a way of
achieving indirect communications. However, they have made C LZ
neither detailed description nor experimental verification of
their LVRT control. On the other hand, the authors of [15] N
have proposed a practical LVRT control based on power-line (b) (c)
communications, including experimental verification.
This paper provide an intensive discussion on the LVRT Fig. 1. Circuit configuration of a three-phase DSCC converter with 16
control, following the previous paper of [15]. In addition, chopper-cells per leg. (a) Power circuit. (b) Chopper cell. (c) Center-tapped
a three-phase 200-V, 400-Vdc, 10-kW, 50-Hz downscaled inductor.
DSCC-based HVDC system with dc power cables is designed,
constructed, and tested to verify the validity and effectiveness leg, depicted in Fig 1(c). Each chopper cell consists of a
of the LVRT control under the rated-power operation and a dc capacitor and two power devices. When the chopper-cell
low-power operation. count per leg is n, the three-phase line-to-line voltages become
The so-called “voltage droop control” has been applied orig- multilevel waveforms with 2n+1 levels. A DSCC converter
inally to high-power synchronous generators in power systems, used in a real HVDC system requires no harmonic filter at the
and then to HVDC systems [16], [17]. The LVRT control ac side because n is higher than 100. In Fig. 1(a), iPu and
discussed in this paper is similar in principles of operation iNu are the positive and negative arm currents, iu is the ac
to, but different in aim or goal from, the traditional voltage current, and iZu is the circulating current along the u-phase
droop control. In other words, the LVRT control aims at riding leg of the DSCC converter. The following definition of iZu
through voltage sags by mean of power-line communications has been made in [18], [19].
between the two DSCC converters. On the other hand, the
traditional voltage droop control for HVDC systems aims at 1
iZu = (iPu + iNu ). (1)
improving system stability in a broad sense, but does not aim 2
at riding through voltage sags. Moreover, the LVRT control The count of independent variables out of the three branch
gets quite different from the traditional voltage droop control currents iPu , iNu , and iu is not three but two because Kirch-
when an ac voltage sag occurs in the power system upstream hoff’s current law comes into existence at the u-phase ac-
of a power-receiving DSCC converter. Actually, the power- terminal of the DSCC converter or at the center tap of the
receiving DSCC converter lowers not the dc “voltage” but u-phase inductor. This paper selects the ac current and the
the dc “current” in order to send information on the voltage circulating current as two independent variables [18], [19]. As
sag from the power-receiving DSCC converter to the power- a result, the positive and negative arm currents are expressed
sending DSCC converter. This is not “voltage” droop control as the following dependent variables.
but “current” droop control. iu
iPu = − + iZu , (2)
2
II. C IRCUIT C ONFIGURATION iu
iNu = + iZu . (3)
Fig. 1(a) shows the power circuit configuration of a three- 2
phase DSCC converter. It consists of bidirectional chopper The first terms of the right-hand sides in (2) and (3) are
cells depicted in Fig 1(b), and a center-tapped inductor per related to the ac current. They are out of phase by 180◦

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SHELL et al.: BARE DEMO OF IEEETRAN.CLS FOR JOURNALS
Load-Dispatching Center
∗ ∗
qA p∗ p∗
idcA idcB
pacA pdcA pdcB
DSCC-A vdcA vdcB DSCC-B
Power
System A DC cables
Fig. 2. Basic configuration of a DSCC-based HVDC transmission system.
with each other. As a result, the magnetic fluxes formed
by the ac current cancel out each other inside the center-
tapped inductor. Therefore, the inductor presents no inductance
to the ac current, whereas it renders the inductance LZ to
the circulating current, thus making the volume much more
compact, and weight much lighter, than general two non-
coupled inductors. Note that the center-tapped inductor should
be designed so that the circulating current does not cause any
magnetic saturation.
Fig. 2 shows the circuit configuration of a DSCC-based
HVDC transmission system with dc power cables. It consists
of DSCC-A and DSCC-B that are the same in power circuit
and controller. Through this paper, the positive directions of
the dc-link current idc , the dc power pdc , and the ac power
pac are defined as those from DSCC-A or power system A
to DSCC-B or power system B, that is, from left to right, as
shown in Fig. 2.
III. VOLTAGE C ONTROL OF A LL THE C HOPPER -C ELL
C APACITORS
Voltage control of each chopper-cell capacitor is character-
ized by the so-called “hierarchical control” consisting of the
following four control layers [6], [19];
1) an overall capacitor-voltage control layer.
2) a leg-balancing control layer.
3) an arm-balancing control layer.
4) an individual-balancing control layer.
The overall capacitor-voltage control layer in the top takes
the responsibility for regulating the arithmetical-average volt-
age of all the dc capacitors within each DSCC converter to
its reference. This is achieved by adjusting the active power
flowing in, or out of, the ac side of each converter.
The leg-balancing control layer in the second top is responsi-
ble for regulating the arithmetical-average voltage of all the dc
capacitors within each leg to the arithmetical-average voltage
of all the dc capacitors within each DSCC converter. The dc
component of the circulating current in each leg is adjusted
to exchange active powers among the three legs. Note that the
sum of three circulating currents is equal to the dc current of
each DSCC converter, meeting Kirchhoff’s current law.
The arm-balancing control layer plays an important role in
eliminating the error between the arithmetic-average capacitor
voltage in the positive arm and that in the negative arm in each
leg. The ac component of the circulating current in each leg
is adjusted to exchange an active power between the positive
and negative arms. Note that the positive-arm and negative-arm
currents are out of phase by 180 degrees each other.
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Transactions on Power Electronics
3
The individual balancing control layer in the bottom takes
qB the responsibility for regulating individual capacitor voltages to
pacB the arithmetical-average voltage in each arm. This straightfor-
ward control is based on adjusting the active power formed by
the arm-side voltage of each chopper cell and the arm current.
Power
System B IV. LVRT C ONTROL AT THE R ATED -P OWER O PERATION
This section makes the following assumptions for the sake
of simplicity.
1) The dc power reference p∗ , that is common in the two
converters, is equal to the rated power P (> 0).
2) The two DSCC converters produce no power loss.
However, this section considers an ohmic power loss in the dc
power cables between DSCC-A and DSCC-B.
A. Normal Operation
A central or reginal load-dispatching center sends p∗ to
both DSCC converters. Generally speaking, DSCC-A, sitting
at the power-sending end, takes a part in regulating the dc-
link voltage vdcA to its reference, while DSCC-B, placed at
the power-receiving end, plays a role in regulating the dc-
link current idcB (= idcA ) or the dc power pdcB (≃ pdcA )
to its reference [20]. In addition, each DSCC converter has
to control an active power at the ac side, in order to achieve
power balancing between the ac side and the dc side.
B. When a Voltage Sag Occurred in Power System A
During the occurrence of a voltage sag, the dc power
reference p∗ can be assumed constant because it is renewed
every a few minutes while the duration time of the voltage
sag is almost several hundred milliseconds. Moreover, it is
assumed for the sake of simplicity that an excellent current-
minor feedback loop can regulate the three-phase ac currents
in power system A to the rated current, even during the
occurrence of the voltage sag.
First of all, it is the top priority that both DSCC converters
are required to regulate the dc component included in each
capacitor voltage to its reference, even during the occurrence of
voltage sags. This means to achieve balancing between the ac
power pac and the dc power pdc in each DSCC converter. Note
that DSCC-A, suffering from the voltage sag, quits operation
of the overall capacitor-voltage control for the purpose of
avoiding both overcurrent and overvoltage.
Next, the reason why DSCC-A should send information on
the voltage sag occurring in power system A to DSCC-B can
be discussed as follows: The voltage sag brings a serious
reduction to the active power at the ac side of DSCC-A,
p̄acA . This active-power reduction should be accompanied by
reducing pdcA (≃ pdcB ) to p̄acA , in order to achieve power
balancing in DSCC-A. On the other hand, the active power at
the ac side of DSCC-B, pacB should be reduced to pdcB , in
order to achieve power balancing in DSCC-B. To do it, DSCC-
B requires information about p̄acA at the ac side of DSCC-A.
Hence, DSCC-A should send a ratio of p̄acA with respect to
p∗ , DA , to DSCC-B. Note that DA is equal to a ratio of the
dc component of the grid d-axis voltage, v̄dA , with respect to
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4 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. XX, NO. XX, XXXX XXXX
∗
vdcA [p.u.] v̂dcA [p.u.]
1 1
0.95 0.95
Step 2
0.85 0.85
Step 1 Step 3
DA
0 0.95 1 0 0.95 1
(a) (b)
Fig. 3. Power-line communications based on voltage droop control during
the occurrence of a voltage sag in power system A. (a) Voltage-amplitude
modulation in DSCC-A. (b) Voltage-amplitude demodulation in DSCC-B.
the nominal line-to-line rms voltage VSA at the rated-power
operation as follows:
DA = p̄acA /p∗ = v̄dA /VSA .
Fig. 3 illustrates the basic concept of the power-line com-
munications during the occurrence of a voltage sag in power
system A. The proposed LVRT control based on dc-voltage
droop is characterized by taking the following steps.
Step 1 DSCC-A detects three-phase voltages at the ac side,
calculates DA , and judges the occurrence of a
voltage sag in power system A when DA < 0.951 .
This paper determines the dc-link-voltage reference
∗
vdcA as follows:
If 0.95 ≤ DA ≤ 1, then
∗ p̄acA . During the occurrence of the voltage sag, this feedback
vdcA = Vdc .
If 0 ≤ DA < 0.95, then
∗
vdcA = Vdc (0.85 + 0.1DA ) + K(v̄CA − VC∗ ).(6)
Here, Vdc is the nominal dc-link voltage, K is a
feedback gain for capacitor voltage control, v̄CA is
the arithmetic-average voltage of all the capacitors
in DSCC-A, and VC∗ is the capacitor voltage refer-
∗ reduced to p̄acB for achieving power balancing inside DSCC-
ence. The minimum per-unit value of vdcA is set
to 0.85 pu in (6), and section VI later on, not to
bring any overmodulation to DSCC-A, as shown in
Fig. 3 (a). On the other hand, the maximum per-
unit value is set to 0.95 pu, providing a margin for
making linear demodulation possible in DSCC-B, as
shown in Fig. 3 (b). However, both minimum and
maximum per-unit values may be somewhat flexible
from a practical point of view because setting both
values can be considered as a design matter.
Step 2 DSCC-B calculates an estimated per-unit value v̂dcA
from vdcB and idcB , along with a cable resistance
per-unit value Rdc as follows:
v̂dcA = vdcB + Rdc idcB .
1 While either single-phase or two-phase voltage sag occurs, vdA
includes a double line-frequency component. A moving average filter with
a sampling time of 1/(2fS ) is required to eliminate the component and to
calculate v̄dA .
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Transactions on Power Electronics
Note that moving average filters are used to remove
v̂dcA switching ripples from vdcB and idcB .
Step 3 DSCC-B judges the occurrence of the voltage sag
Rdc idcB in power system A, when v̂dcA < 0.97 pu. This
vdcB per-unit threshold-voltage value is set to 0.97 pu for
achieving reliable judgement when DA is around
0.95 pu. DSCC-B calculates an estimated value
D̂A D̂A from (6), excluding the feedback control term,
that is, the second term of the right-hand side in
(6). DSCC-B controls pdcB (≃ pdcA ) and pacB
to be proportional to D̂A , finally achieving power
balancing inside each DSCC converter as follows:
pacA = pdcA ≃ pdcB = pacB . (8)
An actual HVDC system produces a non-negligible amount
of power loss in the dc power cables. Since DSCC-A is
responsible for dc-link voltage control, the dc-cable power
(4) loss has to be supplied from each chopper-cell capacitor in
DSCC-A as long as DSCC-B regulates pdcB to p̄acA that is
sent from DSCC-A. As a result, all the capacitor voltages at
DSCC-A decrease. Although the dc-cable power loss plays an
important role in such an LVRT control, no dc-cable power
loss has been considered in [14]. Thus, the longer the duration
time of the voltage sag, the higher the possibility of the
occurrence of overmodulation. On the other hand, the LVRT
control proposed in this paper is characterized by the existence
of the feedback control term in (6). In other words, DSCC-A
achieves indirect control of pdcA by adding the arithmetic-
average value of all the capacitor voltages in DSCC-A to
(5) control mitigates effects of parameter changes on the LVRT
performance although the overall capacitor-voltage control is
out of operation.
C. When a Voltage Sag Occurred in Power System B
The occurrence of a voltage sag in power system B makes
p̄acB decrease suddenly. Therefore, pdcB (≃ pdcA ) should be
B. On the other hand, pacA should be reduced to pdcA for
achieving power balancing inside DSCC-A. To do it, DSCC-A
requires the information on p̄acB . Thus, DSCC-B sends DSCC-
A a value of DB , defined by a ratio of p̄acB , with respect to
p∗ . Note that DB results in being equal to v̄dB /VSB , that is to
a ratio of the dc component of the grid d-axis voltage, v̄dB ,
with respect to the nominal line-to-line rms voltage VSB as
follows:
DB = p̄acB /p∗ = v̄dB /VSB . (9)
Fig. 4 depicts the basic concept of the power-line commu-
nications during the occurrence of the voltage sag in power
(7) system B. The LVRT control based on dc-current droop is
characterized by taking the following steps.
Step 1 DSCC-B judges the occurrence of a voltage sag in
power system B in the same manner as that in power
system A. This paper determines the dc-link-current
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SHELL et al.: BARE DEMO OF IEEETRAN.CLS FOR JOURNALS
idcA [p.u.] idcB [p.u.]
1 1
0.95 0.95
Step 2
Step 3
D̂B
0 0
0 0.95 1 0 0.95 1
(a) (b)
Fig. 4. Power-line communications based on curret droop control during
the occurrence of a voltage sag in power system B. (a) Current-amplitude
demodulation in DSCC-A. (b) Current-amplitude modulation in DSCC-B.
reference i∗dcB as shown in Fig. 4.
If 0.95 ≤ DB ≤ 1, then
i∗dcB = p∗ /Vdc .
If 0 ≤ DB < 0.95, then
i∗dcB = (p∗ /Vdc )DB .
The dc-current droop achieves power balancing in-
side DSCC-B to hold a relation of pdcB = pacB .
Step 2 DSCC-A can take in idcB because the dc-link cur-
rent is identical between the two DSCC converters.
idcA = idcB
Step 3 Under an assumption of having completed the power
balancing of pdcB = pacB , (9) can be arranged as
follow:
DB = p̄acB /p∗ = pdcB /p∗ ≃ Vdc idcB /p∗ . (13)
Since DSCC-A and DSCC-B share information on
p∗ and Vdc , DSCC-A can calculate an estimated
value D̂B of DB from (12) and (13). DSCC-A
judges the occurrence of the voltage sag at power
system B when D̂B < 0.97 pu. Then, DSCC-A
controls pacA to be proportional to D̂B , finally,
achieving the power balancing of pacA = pdcA
inside DSCC-A .
During the occurrence of the voltage sag in power system B,
the power loss produced in the dc cables has no effect on
power balancing inside DSCC-B because all the chopper-cell
capacitors in DSCC-A discharge to compensate for the power
loss. The overall capacitor-voltage control of DSCC-A can
mitigate effects of a non-negligible voltage drop across the
dc power cables on (13). Therefore, no feedback control term
exists in (11), unlike (6).
D. Advantage and Constraint of the Power-Line Communica-
tions
The LVRT control does not need to send any information
about which converter suffers from a voltage sag, DSCC-A or
DSCC-B, to the other healthy DSCC converter by means of
the power-line communications. However, the LVRT control
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Transactions on Power Electronics
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determines which converter acts as a signal-sending converter,
on the basis of the information. In this case, a signal-sending
converter is independent of a power-sending converter. This
important determination can be explained in the following.
Like a traditional voltage-source PWM converter, the DSCC
converter has the capability of controlling its dc voltage in a
Step 1
specified range. Unlike it, the DSCC converter is allowed to
DB have the instantaneous power at the ac side, which is different
from that at the dc side, because each chopper cell is equipped
with a dc capacitor. Note that the average power at the ac side
should be equal to that at the dc side.
During the occurrence of a voltage sag in power system A,
power-sending DSCC-A, that is responsible for dc-voltage
control, lowers its dc voltage, as shown in Fig. 3. On the other
hand, power-receiving DSCC-B, that is responsible for dc-
power (or dc-current) control, detects its dc voltage, and add a
voltage drop caused by the resistance inherent in the dc power
(10) cables to the detected dc voltage. Finally, DSCC-B judges
the occurrence of the voltage sag in power system A, and
estimates the voltage depth from the detected and compensated
(11) dc voltage.
When a voltage sag occurs in power system B, power-
receiving DSCC-B lowers its dc current, as shown in Fig. 4. On
the other hand, power-sending DSCC-A detects its dc current,
judges the occurrence of the voltage sag in power system B,
and estimates the voltage depth from the detected dc current.
In order to achieve the LVRT control properly, it is required
(12)
that such a central or reginal load-dispatching center as shown
in Fig. 2 continues sending the power reference p∗ to the two
DSCC converters at the same time.
V. LVRT C ONTROL AT L OW-P OWER O PERATION
This section pays attention to LVRT control when a voltage
sag occurs in power system A. However, the LVRT control is
applicable and effective even when the voltage sag occurs in
power system B. Let the dc transmission power reference p∗ be
lower than the rated power P . The voltage sage would cause
a significant reduction of the transmission power. However,
it can be minimized by enhancing the three-phase currents at
the ac side of DSCC-A up to the rated current. Note that the
dc component of the d-axis ac-mains or grid voltage, v̄dA , is
lower than the nominal line-to-line rms voltage VSA . Therefore,
the maximum possible transmission power pmax during the
occurrence of the voltage sag is given as follow:
pmax = p∗ × (v̄dA /VSA ) × (P/p∗ ) = (v̄dA /VSA )P. (14)
A. When the Power Reference is Lower Than the Maximum
Possible Transmission Power
Enhancing the three-phase currents at the ac side of DSCC-
A allows the HVDC system to continue operation at its power
reference. Therefore, DSCC-A devotes itself to making power
balancing inside itself, whereas DSCC-B continues normal
operation as if no voltage sag occurred in power system A.
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6 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. XX, NO. XX, XXXX XXXX

∗ (= 0) ∗ (= 0) TABLE I. C IRCUIT PARAMETERS OF F IG . 1.

qA p∗ qB
Rated power P 10 kW
voltage- Nominal line-to-line rms voltage VS 200 V
sag DSCC-A DSCC-B Nominal line frequency fS 50 Hz
generator Lac
Per-leg chopper-cell count n 16
dc cables AC-link inductor Lac 2 mH (16%† )
Lac Center-tapped inductor LZ 3 mH (24%† )
Nominal dc-link voltage Vdc 400 V
Fig. 5. Experimental system of the downscaled HVDC transmission system.
DC-capacitor reference voltage VC∗ 50 V
DC capacitor C 6.6 mF
B. When the Power Reference is Higher Than the Maximum Unit capacitance constant [21] HC 40 ms at 50 V
Possible Transmission Power PWM carrier frequency fC 450 Hz
When the three-phase currents at the ac side of DSCC- Equivalent carrier frequency nfC 7.2 kHz
A are intentionally enhanced to the rated ac current, the dc Dead or blanking time 8 µs
transmission power can be boosted †: on a three-phase, 200-V, 10-kW, 50-Hz base

from (v̄dA /VSA ) p∗ to (v̄dA /VSA ) P.

TABLE II. PARAMETERS OF DC P OWER C ABLES .

Either DA defined by (6) or DB by (11) means a transmission DC-cable length 300 m

power ratio before and during the occurrence of the voltage DC-cable resistance Rdc 1 Ω (6.2%† )
sag. Therefore, when the three-phase currents at the ac side DC-cable inductance Ldc 58 µH (1.8 µs∗ )
of the DSCC converter suffering from the voltage sag are DC-cable capacitance Cdc 184 nF (1.5 µs∗ )
enhanced to the rated currents, the transmission power ratio
Dmax is given as follow: † and ∗: on a 400-Vdc, 10-kW, dc base
∗: unit inductance or capacitance constant [21]

Dmax = (v̄d /VS )P/p∗ . (15)

Replacing DA or DB with Dmax allows the HVDC system

to operate at the highest power possible under the conditions.
However, the highest power is lower than the power reference
p∗ .
VI. E XPERIMENTAL S YSTEM AND C IRCUIT S IMULATION
A. Experimental System and its Constraint
Fig. 5 shows the circuit configuration of the three-phase 200-
V, 400-Vdc, 10-kW, 50-Hz downscaled HVDC system used
in the following experiments. Fig. 6 shows the photograph
of the experimental system. Tables I and Table II summarize
the circuit parameters of each DSCC converter and those of
the dc power cables used in both experiment and simulation,
respectively. Through this section, the power (active-power)
reference was set to the rated power of p∗ = 10 kW, while the
∗ ∗
reactive-power reference was set to zero, that is, qA = qB = 0.
This experimental system shown in Fig. 5 has the following
constraint: Experiment ca be done only when voltage sags
occur in power system A. The reason is that the voltage-sag
generator used in this experiment has no capability of feeding
electric power back to the three-phase ac mains in Fig. 5 or
power system A in Fig. 2.

B. Validity of Circuit Simulation

The software package “PSCAD/EMTDC” was used for the
circuit simulation considering the followings:
1) A delay time inherent in the digital control system:
140 µs (= 1/(450 Hz × 16)),
Fig. 6. Photograph of the three-phase 200-V, 400-Vdc, 10-kW, 50-Hz
downscaled HVDC system used for experiment. 2) A dead or blanking time of each chopper cell: 8 µs,
3) An on-resistance of each MOSFET: 1 mΩ.

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2016.2615048, IEEE
Transactions on Power Electronics

SHELL et al.: BARE DEMO OF IEEETRAN.CLS FOR JOURNALS 7

[kW] 100 ms [kW] 100 ms

pdcA 10 pdcB 10
0 0
−10 −10
[V] 500 [V] 500
400 400
vdcA vdcB
300 300
200 200
[V] 500 [V] 500
vuvA vuvB
vvwA 0 vvwB 0
vwuA vwuB
−500 −500
[A] 200 [A] 200
iuA iuB
ivA 0 ivB 0
iwA iwB
−200 −200
[V] 100 [V] 100
vC1uA vC1uB
vC9uA 50 vC9uB 50
0 0
(a) DSCC-A (b) DSCC-B

Fig. 7. Simulated waveforms without LVRT control at p∗ = 10 kW before, while, and after a three-phase voltage sag with a depth of 80% and a duration
time of 100 ms occurred in power system A.

However, component tolerances of MOSFETs, a finite switch-
ing time, a lead resistance and inductance in the experimental
system, and so on were not takin into account.
This circuit simulation is characterized by using an updated
version of the previous papers [6] and [22]. Their validity
and reliability has been confirmed by the following fact that
simulated waveforms have agreed well with experimental ones.
Carefully comparing the simulated waveforms in Fig. 8 to
experimental ones in Fig. 9 in section VI-B enhances further
the validity and reliability of the circuit simulation.
VII. S IMULATION AND E XPERIMENT AT THE
R ATED -P OWER O PERATION
A. When the LVRT Control was Inactive
Fig. 7 shows simulated waveforms without LVRT control
at p∗ = 10 kW when a three-phase voltage sag with a
depth of 80% occurred and lasted for 100 ms in power
system A. No comparison is made in waveform between
simulation and experiment because it would be impossible to
do experiment under the conditions without any operation of
protection circuits.
As soon as the voltage sag occurred, the capacitor voltages
vC1uA and vC9uA , and the dc-link voltage vdcA in DSCC-
A started decreasing due to power imbalance. At the same
time, the overall capacitor-voltage control started enhancing
the three-phase currents at the ac side, iuA , iuB , and iuC . This
makes the active power at the ac side lower than the rated
power. DSCC-A, nevertheless, continued operation at the rated
power of 10 kW for 30 ms just after the voltage sag occurred.
This means that all the chopper-cell capacitors in DSCC-A
continued discharging the difference between the rated power
of 10 kW and the electric power coming from the ac mains.
At the passage of 30 ms, DSCC-A became out of control due
to overmodulation, lasting for 70 ms. At the same time, DSCC-
B also became out of control because the dc-link voltage
decreased, thus resulting in causing overmodulation. After
the voltage sag restored, an overcurrent and an overvoltage
occurred in the three-phase currents iuA , ivA , and iwA and the
capacitor voltages vC1uA and vC9uA .
Since there were no communications between the two
DSCC converters, DSCC-B did not notice that the voltage sag
occurred and lasted in power system A. As a result, DSCC-B
continued regulating all the capacitor voltages to its reference
(= 50 V) because no voltage sag occurred in power system B.
Finally, it is concluded from Fig. 7 that the HVDC system
shown in Fig. 2 cannot ride through voltage sags when no
LVRT control is applied.
B. When the LVRT Control was Active
Figs. 8 and 9 show simulated and experimental waveforms
at p∗ = 10 kW when a two-phase voltage sag with a depth
of 80% occurred and lasted for 100 ms in power system A.
The simulated waveforms look very similar to the experimen-
tal ones in detail. This fact would support the validity and
reliability of the simulated waveforms shown in Fig. 7.
As soon as the voltage sag occurred, pdcA and pdcB fell
down steeply, as shown in Figs. 8 and 9. With a non-negligible
delay time caused by moving average filters, DSCC-A judged
the occurrence of the voltage sag in power system A, and
reduced vdcA (≃ vdcB ) for achieving the power-line commu-
nications. The delay time is inherent in the moving average

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8 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. XX, NO. XX, XXXX XXXX

[kW] 100 ms [kW] 100 ms

pdcA 10 pdcB 10

0 0
[V] 500 [V] 500
vdcA 400 vdcB 400

300 300
[V] 400 [V] 400
vuvA vuvB
vvwA 0 vvwB 0
vwuA vwuB
−400 −400
[A] 60 [A] 60
iuA iuB
ivA 0 ivB 0
iwA iwB
−60 −60
[V] 75 [V] 75
vC1uA vC1uB
vC9uA 50 vC9uB 50
25 25
(a) (b)
Fig. 8. Simulated waveforms with the LVRT control at p∗
= 10 kW before, while, and after a two-phase voltage sag with a depth of 80% and a duration
time of 100 ms occurred in power system A. (a) DSCC-A. (b) DSCC-B.

[kW] 100 ms [kW] 100 ms

pdcA 10 pdcB 10

0 0
[V] 500 [V] 500
vdcA 400 vdcB 400

300 300
[V] 400 [V] 400
vuvA vuvB
vvwA 0 vvwB 0
vwuA vwuB
−400 −400
[A] 60 [A] 60
iuA iuB
ivA 0 ivB 0
iwA iwB
−60 −60
[V] 75 [V] 75
vC1uA vC1uB
vC9uA 50 vC9uB 50
25 25
(a) (b)
Fig. 9. Experimental waveforms under the same conditions as those in Fig. 8. (a) DSCC-A. (b) DSCC-B.

filters, as described in section IV. Actually, their sampling time
was designed to be 10 ms, to minimize the effect of the delay
time on LVRT control and performance.
Fig. 10 shows experimental waveforms when a three-phase
voltage sag with a depth of 80% occurred and lasted for 100 ms
in power system A. Just after the voltage sag occurred, the
capacitor voltages vC1uA and vC9uA experienced a higher fall
of voltage because the three-phase voltage sag in Fig. 10 was
more severe in power balance than the two-phase voltage sag
in Fig. 9. On the other hand, DSCC-B started lowering pdcB
(≃ pdcA ), and achieved power balancing as a result of having
controlled pdcB and pacB properly because no voltage sag

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2016.2615048, IEEE
Transactions on Power Electronics

SHELL et al.: BARE DEMO OF IEEETRAN.CLS FOR JOURNALS 9

[kW] 100 ms [kW] 100 ms

pdcA 10 pdcB 10

0 0
[V] 500 [V] 500
vdcA 400 vdcB 400

300 300
[V] 400 [V] 400
vuvA vuvB
vvwA 0 vvwB 0
vwuA vwuB
−400 −400
[A] 60 [A] 60
iuA iuB
ivA 0 ivB 0
iwA iwB
−60 −60
[V] 75 [V] 75
vC1uA vC1uB
vC9uA 50 vC9uB 50
25 25
(a) (b)
Fig. 10. Experimental waveforms with the LVRT control at p∗
= 10 kW before, while, and after a three-phase voltage sag with a depth of 80% and a
duration time of 100 ms occurred in power system A. (a) DSCC-A. (b) DSCC-B.

happened in power system B. The amplitude and frequency
of the three-phase currents at the ac side of DSCC-A were
kept constant during the voltage sag with neither overvoltage
nor overcurrent. These experimental and simulated waveforms
confirm that the HVDC system provides excellent LVRT
performance when voltage sags occurred in power system A.
As a result of achieving the LVRT control, the dc voltages of
DSCC-A and DSCC-B, vdcA and vdcB were decreasing during
the occurrence of the two-phase and three-phase voltage sags.
Nevertheless, the dc components of four capacitor voltages
vC1uA , vC9uA , vC1uB , and vC9uB were well regulated to its
reference voltage of 50 V in these experiments. This means that
all of the 192 MOSFETs in Fig. 2 continued proper switching
operation to ride through the voltage sag. It should be noticed
from Figs. 9 and 10 that the four capacitor voltages of DSCC-
B were much smaller in ac component than those of DSCC-
A because the three-phase supply currents of DSCC-B were
much smaller in amplitude than those of DSCC-A.
Figs. 11 and 12 show simulated waveforms at the rated
dc power reference of p∗ = 10 kW before, while, and after
two-phase and three-phase voltage sags with a depth of
80% occurred and lasted for 100 ms in power system B,
respectively.
As soon as DSCC-B judged the occurrence of either voltage
sag in power system B, it started reducing idc to perform
power-line communications, achieving power balancing inside
DSCC-B. As soon as DSCC-A received the information on
the voltage sag in power system B, it started reducing pacA ,
achieving power balancing inside DSCC-A. As a result, neither
overvoltage nor overcurrent occurred, showing excellent LVRT
performance.
VIII. E XPERIMENT AT L OW-P OWER O PERATION
Fig. 13 shows experimental waveforms with a dc transmis-
sion power reference of p∗ = 4 kW before, while, and after
a two-phase voltage sag with a depth of 80% occurred and
lasted for 100 ms in power system A. This power reference
is lower than 4.7 kW, that is, the maximum possible active
power calculated from (14) under the voltage-sag conditions.
Therefore, DSCC-A was able to control the three-phase cur-
rents at its ac side to be lower than the rated current during
the occurrence of the voltage sag, achieving power balancing
inside DSCC-A. Moreover, DSCC-A kept the dc power pdcA
and the dc-link voltage vdcA constant in spite of the fact that
DSCC-A were suffering from the voltage sag. On the other
hand, DSCC-B continued normal operation as if no voltage
sag occurred.
Fig. 14 shows experimental waveforms at a power reference
of p∗ = 6 kW before, while, and after a two-phase voltage
sag with a depth of 80% occurred and lasted for 100 ms in
power system A. Unless the three-phase currents at the ac side
of DSCC-A had been enhanced, the dc transmission power
during the voltage sag would have been 2.8 kW. Since the
three-phase currents at the ac side of DSCC-A were enhanced
to the rated current in Fig. 14, the dc transmission power was
boosted up to 4.7 kW.
IX. C ONCLUSION
This paper has described a high-voltage direct-current
(HVDC) transmission system combining two modular mul-
tilevel double-star chopper-cells (DSCC) converters with dc
power cables. Emphasis has been put on low-voltage-ride-
through (LVRT) capability to enhance system availability. This

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10 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. XX, NO. XX, XXXX XXXX

[kW] 100 ms [kW] 100 ms

pdcA 10 pdcB 10

0 0
[A] 30 [A] 30

idcA idcB

0 0
[V] 400 [V] 400
vuvA vuvB
vvwA 0 vvwB 0
vwuA vwuB
−400 −400
[A] 60 [A] 60
iuA iuB
ivA 0 ivB 0
iwA iwB
−60 −60
[V] 75 [V] 75
vC1uA vC1uB
vC9uA 50 vC9uB 50
25 25
(a) (b)
Fig. 11. Simulated waveforms with the LVRT control at p∗
= 10 kW before, while, and after a two-phase voltage sag with a depth of 80% and a duration
time of 100 ms occurred in power system B. (a) DSCC-A. (b) DSCC-B.

[kW] 100 ms [kW] 100 ms

pdcA 10 pdcB 10

0 0
[A] 30 [A] 30

idcA idcB

0 0
[V] 400 [V] 400
vuvA vuvB
vvwA 0 vvwB 0
vwuA vwuB
−400 −400
[A] 60 [A] 60
iuA iuB
ivA 0 ivB 0
iwA iwB
−60 −60
[V] 75 [V] 75
vC1uA vC1uB
vC9uA 50 vC9uB 50
25 25
(a) (b)
Fig. 12. Simulated waveforms with the LVRT control at p∗ = 10 kW before, while, and after a three-phase voltage sag with a depth of 80% and a duration
time of 100 ms occurred in power system B. (a) DSCC-A. (b) DSCC-B.

paper has proposed a practical LVRT control technique based
on indirect communications between the two DSCC converters.
A three-phase 200-V, 400-Vdc, 10-kW, 50-Hz downscaled
HVDC system with 300-meter-long dc power cables has been
designed, constructed, and tested to verify LVRT performance
with neither overvoltage nor overcurrent.
However, an intensive discussion on the limitations and
boundaries of the LVRT control, as well as the effect of
parameter changes on LVRT control and performance, is left
for future work. It would encourage scientists and engineers

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Transactions on Power Electronics

SHELL et al.: BARE DEMO OF IEEETRAN.CLS FOR JOURNALS 11

[kW] 100 ms [kW] 100 ms

pdcA 10 pdcB 10

0 0
[V] 500 [V] 500
vdcA 400 vdcB 400

300 300
[V] 400 [V] 400
vuvA vuvB
vvwA 0 vvwB 0
vwuA vwuB
−400 −400
[A] 60 [A] 60
iuA iuB
ivA 0 ivB 0
iwA iwB
−60 −60
[V] 75 [V] 75
vC1uA vC1uB
vC9uA 50 vC9uB 50
25 25
(a) (b)
Fig. 13. Experimental waveforms with the LVRT control at p∗
= 4 kW before, while, and after a two-phase voltage sag with a depth of 80% and a duration
time of 100 ms occurred in power system A. Note that the power reference of 4 kW is lower than the maximum possible transmission power of 4.7 kW under
the voltage-sag conditions. (a) DSCC-A. (b) DSCC-B.

[kW] 100 ms [kW] 100 ms

pdcA 10 pdcB 10

0 0
[V] 500 [V] 500
vdcA 400 vdcB 400

300 300
[V] 400 [V] 400
vuvA vuvB
vvwA 0 vvwB 0
vwuA vwuB
−400 −400
[A] 60 [A] 60
iuA iuB
ivA 0 ivB 0
iwA iwB
−60 −60
[V] 75 [V] 75
vC1uA vC1uB
vC9uA 50 vC9uB 50
25 25
(a) (b)
Fig. 14. Experimental waveforms with the LVRT control at p∗ = 6 kW before, while, and after a two-phase voltage sag with a depth of 80% and a duration
time of 100 ms occurred in power system A. Note that the power reference of 6 kW is higher than the maximum possible transmission power of 4.7 kW under
the voltage-sag condition. (a) DSCC-A. (b) DSCC-B.

in the field of power electronics and power engineering to do R EFERENCES

further research.
[1] G. Asplund, K. Eriksson, H. Jiang, J. Lindberg, R. Pålsson, and K.
Svensson, “DC transmission based on voltage source converters,” in
Proc. CIGRE SC14 Colloq. 1997, pp. 1–7.

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Transactions on Power Electronics

12 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. XX, NO. XX, XXXX XXXX

[2] N. Flourentzou, V. G. Agelidis, and G. D. Demetriades, “VSC-based source inverters,” IEEE Trans. Ind. Appl., vol. 32, no. 4, pp. 970–978,
HVDC power transmission systems: An Overview,” IEEE Trans. Power Jul./Aug. 1996.
Electron., vol. 24, no. 3, pp. 592–602, Mar. 2009. [22] F. Sasongko, K. Oguma, M. Hagiwara, and H. Akagi “Theory and
[3] G. P. Adam, K. H. Ahmed, S. J. Finney, K. Bell, and B. W. Williams, experiment on an optimal carrier frequency of a modular multilevel
“New breed of network fault-tolerant voltage-source-converter HVDC cascade converter with phase-shifted PWM,” IEEE Trans. Power Elec-
transmission system,” IEEE Trans. Power Syst., vol. 28, no. 1, pp. 335– tron., vol. 31, no. 5, pp. 3456–3471, May 2016.
346, Feb. 2012.
[4] H. Akagi, “Classification, terminology, and application of the modular
multilevel cascade converter (MMCC),” IEEE Trans. Power Electron.,
vol. 26, no. 11, pp. 3119–3130, Nov. 2011.
[5] M. Glinka and R. Marquardt, “A new ac/ac multilevel converter family,”
IEEE Trans. Ind. Electron., vol. 52, no. 3, pp. 662–669, Jun. 2005.
[6] K. Sekiguchi, P. Khamphakdi, M. Hagiwara, and H. Akagi, “A grid-
level high-power BTB (back-to-back) system using modular multilevel
cascade converters without dc-link capacitor,” IEEE Trans. Ind. Appl.,
vol. 50, no. 4, pp. 2648–2659, Jul./Aug. 2014.
[7] C. Feltes, H. Wrede, F. W. Koch, and I. Erlich, “Enhanced fault ride-
through method for wind farms connected to the grid through VSC-
based HVDC transmission,” IEEE Trans. Power Systems, vol. 24, no. 3,
pp. 1537–1546, Aug. 2009.
[8] A. Beddard and M. Barnes, “AC fault ride-through of MMC VSC-
HVDC systems,” in Proc. IEEE PEMC 2014, pp. 1–6.
[9] D. S. Sanchez and T. C. Green, “Control of a modular multilevel
converter-based HVDC transmission system,” in Proc. EPE 2011, pp. 1–
10.
[10] N. Ahmed, L. Ängquist, S. Norrga, and H. P. Nee, “Efficient modeling
of modular multilevel converters in HVDC-grid under fault conditions,”
in Proc. IEEE PES General Meeting 2014, pp. 1–5.
[11] J. W. Moon, J. W. Park, D. W. Kang, and J. M. Kim, “A control method
of HVDC-modular multilevel converter based on arm current under the
unbalanced voltage condition,” IEEE Trans. Power Delivery, vol. 30,
no. 2, pp. 529–536, Apr. 2015.
[12] G. P. Adam, K. H. Ahmed, S. J. Finney, and B. W. Williams, “AC
fault ride- through capability of a VSC-HVDC transmission systems,”
in Proc. IEEE ECCE 2010, pp. 3739–3745.
[13] X. Shi, Z. Wang, B. Liu, Y. Liu, L. M. Tolbert, and F. Wang, “Char-
acteristic investigation and control of a modular multilevel converter-
based HVDC system under single-line-to-ground fault conditions,”
IEEE Trans. Power Electron., vol. 30, no. 1, pp. 408–421, Jan. 2015.
[14] S. Cui, H. J. Lee, J. J. Jung, Y. Lee, and S. K. Sul, “EA comprehensive
ac side single line to ground fault ride through strategy of a modular
multilevel converter for HVDC system,” in Proc. IEEE ECCE 2015,
pp. 5378–5385.
[15] K. Oguma, F. Sasongko, M. Hagiwara, and H. Akagi “Low-voltage-ride-
through capability of an HVDC transmission system using two modular
multilevel cascade converters (MMCC-DSCC),” in Proc. IEEE IFEEC
2015, pp. 1–6.
[16] W. Wang and M. Barnes, “Power flow Algorithms for multi-terminal
VSC-HVDC with droop control,” IEEE Trans. Power Systems, vol. 29,
no. 4, pp. 1721–1730, Jul. 2014.
[17] E. Prieto-Araujo, A. Egea-Alvarez, S. Fekriasl, and O. Gomis-
Bellmuntand “DC voltage droop control design for multiterminal
HVDC systems considering ac and dc grid dynamics,” IEEE Trans.
Power Delivery, vol. 31, no. 2, pp. 575–585, Apr. 2016.
[18] M. Hagiwara and H. Akagi, “PWM control and experiment of modular
multilevel converters,” in Proc. IEEE PESC 2008, pp. 154–161.
[19] M. Hagiwara and H. Akagi, “Control and experiment of pulsewidth-
modulated modular multilevel converters,” IEEE Trans. Power Elec-
tron., vol. 24, no. 7, pp. 1737–1746, Jul. 2009.
[20] T. Nakajima and S. Irokawa, “A control system for HVDC transmission
by voltage sourced converters,” in Proc. IEEE PES Summer Meeting
1999, pp. 1113–1119.
[21] H. Fujita, S. Tominaga, and H. Akagi “Analysis and design of a dc
voltage-controlled static var compensator using quad-series voltage-

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