ECE 6660 Introduction To VLSI Systems Fall 2018 Test 2 Sayed Asim Ahmed

ECE 6660 Introduction to VLSI Systems
Fall 2018
Test 2
Sayed Asim Ahmed

gl0540
1 Table of Contents
1. Question 1 ................................................................................................................. 3
1.1 Example 3_1 .................................................................................................................. 3
1.2 Example 3_4 .................................................................................................................. 4
1.3 Example 4_1 .................................................................................................................. 5
1.4 Example 4_2 and Example 4_4 ....................................................................................... 6
1.5 Example 4_3 .................................................................................................................. 7
1.6 Example 4_5 .................................................................................................................. 8
1.7 Example 4_6 .................................................................................................................. 9
1.8 Example 4_7 ................................................................................................................ 10
1.9 Example 4_8 ................................................................................................................ 11
1.10 Example 4_9 ................................................................................................................ 12
1.11 Example 4_10 .............................................................................................................. 13
1.12 Example 5_1 ................................................................................................................ 14
1.13 Example 5_2 ................................................................................................................ 15
1.14 Example 5_3 ................................................................................................................ 16
1.15 Example 5_4 ................................................................................................................ 17
1.16 Example 5_5 ................................................................................................................ 18
1.17 Example 5_6 ................................................................................................................ 19
1.18 Example 5_7 ................................................................................................................ 20
1.19 Example 6_1 and 6_2 ................................................................................................... 21
1.20 Example 6_3 ................................................................................................................ 22
1.21 Example 6_4 ................................................................................................................ 23
2 Question 2 ............................................................................................................... 24
2.1 Full Adder using two half adders .................................................................................. 25
2.2 Full Adder using functional description ........................................................................ 26
2.3 Full Adder using functional description ........................................................................ 27
2.4 Comparison of the three methods ............................................................................... 28
3 Question 3 ............................................................................................................... 29
3.1 A+B’C ........................................................................................................................... 29
3.2 A’B+C ........................................................................................................................... 32
4 Conclusion ............................................................................................................... 35
1. Question 1
The objective of this question was to show the simulation of the exercise problems listed in the
Mano folder by creating a test bench for each question and then carrying out simulation using
NCLaunch to prove their proper functioning.
1.1 Example 3_1

This example was to show the functioning of simple gates. The logic being demonstrated is
Y = A.B + ~C
The truth table is shown below.
A B C X Y
0 0 0 1 1
0 0 1 0 0
0 1 0 1 1
0 1 1 0 0
1 0 0 1 1
1 0 1 0 0
1 1 0 1 1
1 1 1 1 0
Fig. 1 Truth table
The test bench was designed and then elaborated using NCLaunch and then simulated using
Cadence SimVision to obtain the following simulation result.
As can be seen, the simulations prove the truth table.

1.2 Example 3_4
This example was to showcase different Boolean operations as listed below.
X = A | (B & C) | (~B & C)

Y = = (~B & C) | (B & ~C & ~D)
The truth table for the above expression is given below.
A B C D X Y
0 0 0 0 0 0
0 0 0 1 0 0
0 0 1 0 1 1
0 0 1 1 1 1
0 1 0 0 0 1
0 1 0 1 0 0
0 1 1 0 1 0
0 1 1 1 1 0
1 0 0 0 1 0
1 0 0 1 1 0
1 0 1 0 1 1
1 0 1 1 1 1
1 1 0 0 1 1
1 1 0 1 1 0
1 1 1 0 1 0
1 1 1 1 1 0

1.3 Example 4_1
This example was to showcase the functionality of the 2-to-4 line decoder.
The truth table for which is given below.

1.4 Example 4_2 and Example 4_4
This example was to showcase the functionality of a 4 bit full adder.

1.5 Example 4_3
This example was to showcase the functionality of a 2-to-4 decoder coded in the gate level
description.

1.6 Example 4_5
This example was to showcase the functionality of the dataflow description of a 4-bit
comparator.

1.7 Example 4_6
This example was to showcase the functionality of the dataflow description of a 2-to1line
multiplexer.

1.8 Example 4_7
This example was to showcase the functionality of the behavioral description of a 2-to1line
multiplexer.

1.9 Example 4_8
This example was to showcase the functionality of the behavioral description of a 4-to1line
multiplexer.

1.10 Example 4_9
This example was to showcase the functionality of the dataflow description of a 2-to1line
multiplexer.

1.11 Example 4_10
This example was to showcase the functionality of the gatelevel description of the following
circuit.
As can be seen, the simulations prove the proper functioning of the circuit.
1.12 Example 5_1
This example was to showcase the functionality of the D-Latch.
1.13 Example 5_2
This example was to showcase the functionality of the D-Flip flop.
1.14 Example 5_3
This example was to showcase the functionality of the D-Flip flop from gates.
1.15 Example 5_4
This example was to showcase the functionality of the JK Flip Flop.
1.16 Example 5_5
This example was to showcase the functionality of the Mealy State Diagram.
This is for the circuit below.
1.17 Example 5_6
This example was to showcase the functionality of the Moore State Diagram.
1.18 Example 5_7
This example was to showcase the functionality of the structural description of a sequential
circuit.
1.19 Example 6_1 and 6_2
This example was to showcase the functionality of the behavioral description of the shift
register.
1.20 Example 6_3
This example was to showcase the functionality of the binary counter with parallel load.
1.21 Example 6_4
This example was to showcase the functionality of the ripple counter.
2 Question 2
The objective of this question was to show the simulation of 1bit full adder by means of three
different Verilog programs. And to do a comparison of the three methods and how they are
different in terms of
1) Gates used
2) Power consumption
3) Delay
The full adder is based on the following logic
The truth table and symbol for the Full Adder are also show below.
2.1 Full Adder using two half adders
To design the full adder, the following code was used:
module halfadder(S,C,x,y);
input x,y;
output S,C;
xor (S,x,y);
and (C,x,y);
endmodule
module fulladd1bit (S,C,x,y,z);

input x,y,z;
output S,C;
wire S1,D1,D2;
halfadder HA1 (S1,D1,x,y);
halfadder HA2 (S,D2,S1,z);
or g1(C,D2,D1);
endmodule
The test bench code is
module fulladd1bit_tb;
reg x,y,z;
wire S,C;
fulladd1bit fa(S,C,x,y,z);
initial
begin
x = 0; y = 0; z=0;
#100 x = 0; y = 0; z=1;
#100 x = 0; y = 1; z=0;
#100 x = 0; y = 1; z=1;
#100 x = 1; y = 0; z=0;
#100 x = 1; y = 0; z=1;
#100 x = 1; y = 1; z=0;
#100 x = 1; y = 1; z=1;
end
endmodule
The NClaunch simulation result was then obtained as follows.

2.2 Full Adder using functional description
Verilog code:
module fa_nand(a,b,cin,sum,carry);
input a,b,cin;
output carry, sum;
wire w1,w2,w3,w4,w5,w6,w7;
nand n1(w1,a,b);
nand n2(w3,a,w1);
nand n3(w2,w1,b);
nand n4(w4,w3,w2);
nand n5(w5,w4,cin);
nand n6(w6,w4,w5);
nand n7(w7,w5,cin);
nand n8(carry,w5,w1);
nand n9(sum,w6,w7);
endmodule
Test bench code:
module fulladd_tb;
reg x,y,z;
wire S,C;
full_adder fa(x,y,z,S,C);
initial
begin
x = 0; y = 0; z=0;
#100 x = 0; y = 0; z=1;
#100 x = 0; y = 1; z=0;
#100 x = 0; y = 1; z=1;
#100 x = 1; y = 0; z=0;
#100 x = 1; y = 0; z=1;
#100 x = 1; y = 1; z=0;
#100 x = 1; y = 1; z=1;
end
endmodule
NC launch simulation result:

2.3 Full Adder using functional description
Verilog code:
module fa_nand(a,b,cin,sum,carry);
input a,b,cin;
output carry, sum;
wire w1,w2,w3,w4,w5,w6,w7;
nand n1(w1,a,b);
nand n2(w3,a,w1);
nand n3(w2,w1,b);
nand n4(w4,w3,w2);
nand n5(w5,w4,cin);
nand n6(w6,w4,w5);
nand n7(w7,w5,cin);
nand n8(carry,w5,w1);
nand n9(sum,w6,w7);
endmodule
Test bench code:
module fulladd1bit_tb;
reg x,y,z;
wire S,C;
fa_nand fa(x,y,z,S,C);
initial
begin
x = 0; y = 0; z=0;
#100 x = 0; y = 0; z=1;
#100 x = 0; y = 1; z=0;
#100 x = 0; y = 1; z=1;
#100 x = 1; y = 0; z=0;
#100 x = 1; y = 0; z=1;
#100 x = 1; y = 1; z=0;
#100 x = 1; y = 1; z=1;
end
endmodule
NClaunch simulation result:

2.4 Comparison of the three methods
The number of gates used, the amount of total power consumed and the delay for signal
propagation through each of the three methods explained above is summarized in the table
below.
Power Consumption Delay

Number of gates
(nW) (ps)
1st method 8 344869.449 1317
2nd method 4 242376.771 975
3rd method 5 281400.874 850
As we can see from the table above, the lower power consumption is by the method that utilizes
the least number of gates. This is makes sense because the lower the number of gates used, the
lower is the power consumption for the entire circuit.
This fact, however, does not translate into lesser delay. As we see, the propagation delay is the
least for the third method, which shows that a circuit can be relatively complex in construction
and still have a lower propagation delay as compared to a seemingly simpler circuit.
3 Question 3
The objective of this question was to design the circuit A+B'C and A'B+C from verilog to
chip.
3.1 A+B’C
The Verilog code for the circuit is as below:
module Question_3_1 (A,B,C,x);

input A,B,C;
output x;
wire e,f;
not g2(e,B);
and g1(f,C,e);
or g3(x,A,f);
endmodule
The circuit is compiled using RC compiler and then encounter is run to arrive to the layout of
the circuit compiled in the logic.
We then launch virtuoso and create a library in which to import the Verilog file and .DEF file
that we have created.
Once we open the layout, we then use Layout XL to autoroute the circuit according to the
schematic we have drawn using encounter.
This is shown below. Once this is done, DRC is performed followed by extraction and a
comparison with the schematic using LVS.
The pad frame for the chip to be fabricated is then prepared, by copying a template pad frame
and then modifying it to add input and output pins. This is shown below. Once, this is done,
once again, DRC, extraction and LVS is done to ensure that the drawn circuitry is accurate.
Finally, the circuit for the chip to be designed is drawn in the schematic editor with all of the
internal and external inputs and outputs connected and then the layout of the padframe is edited
to add the power rails. This design is then check through DRC, extraction and LVS.
For the final step, xstream is run to export a .GDS file that can be sent over to MOSIS to be
fabricated into a chip.
3.2 A’B+C
The Verilog code for the circuit is as below:
module Question_3_2 (A,B,C,x);

input A,B,C;
output x;
wire e,f;
not g2(e,A);
and g1(f,B,e);
or g3(x,C,f);
endmodule
We then launch virtuoso and create a library in which to import the Verilog file and .DEF file
that we have created.
Once we open the layout, we then use Layout XL to autoroute the circuit according to the
schematic we have drawn using encounter.
This is shown below. Once this is done, DRC is performed followed by extraction and a
comparison with the schematic using LVS.
The pad frame for the chip to be fabricated is then prepared, by copying a template pad frame
and then modifying it to add input and output pins. This is shown below. Once, this is done,
once again, DRC, extraction and LVS is done to ensure that the drawn circuitry is accurate.
Finally, the circuit for the chip to be designed is drawn in the schematic editor with all of the
internal and external inputs and outputs connected and then the layout of the padframe is edited
to add the power rails. This design is then check through DRC, extraction and LVS.
For the final step, xstream is run to export a .GDS file that can be sent over to MOSIS to be
fabricated into a chip.
4 Conclusion
As seen from the experimental simulations in the preceding sections, the schematic and symbol
design were successfully carried out in Cadence Virtuoso. The Verilog code was compiled
using RC compiler, and then encounter was used to convert the compiled code into layout that
can be edited in virtuoso. Where the necessary changes were made to the layout to match our
expression from the question. This was then used to export a GDS file that can be sent to
MOSIS for chip fabrication.

ECE 6660 Introduction To VLSI Systems Fall 2018 Test 2 Sayed Asim Ahmed

Diunggah oleh

Informasi Dokumen

Judul Asli

Hak Cipta

Format Tersedia

Bagikan dokumen Ini

Bagikan atau Tanam Dokumen

Opsi Berbagi

Apakah menurut Anda dokumen ini bermanfaat?

Apakah konten ini tidak pantas?

Hak Cipta:

Format Tersedia

ECE 6660 Introduction To VLSI Systems Fall 2018 Test 2 Sayed Asim Ahmed

Diunggah oleh

Hak Cipta:

Format Tersedia

ECE 6660 Introduction to VLSI Systems

Sayed Asim Ahmed

1.1 Example 3_1

The truth table is shown below.

Fig. 1 Truth table

As can be seen, the simulations prove the truth table.

X = A | (B & C) | (~B & C)

The truth table for the above expression is given below.

As can be seen, the simulations prove the truth table.

The truth table for which is given below.

As can be seen, the simulations prove the truth table.

The truth table for which is given below.

As can be seen, the simulations prove the truth table.

The truth table for which is given below.

As can be seen, the simulations prove the truth table.

The truth table for which is given below.

As can be seen, the simulations prove the truth table.

The truth table for which is given below.

As can be seen, the simulations prove the truth table.

The truth table for which is given below.

As can be seen, the simulations prove the truth table.

The truth table for which is given below.

As can be seen, the simulations prove the truth table.

The truth table for which is given below.

As can be seen, the simulations prove the truth table.

This example was to showcase the functionality of the D-Latch.

The truth table for which is given below.

This example was to showcase the functionality of the D-Flip flop.

The truth table for which is given below.

The truth table for which is given below.

This example was to showcase the functionality of the JK Flip Flop.

The truth table for which is given below.

This is for the circuit below.

This is for the circuit below.

This is for the circuit below.

This is for the circuit below.

This is for the circuit below.

This example was to showcase the functionality of the ripple counter.

This is for the circuit below.

The full adder is based on the following logic

To design the full adder, the following code was used:

module fulladd1bit (S,C,x,y,z);

The test bench code is

The NClaunch simulation result was then obtained as follows.

Test bench code:

NC launch simulation result:

Test bench code:

NClaunch simulation result:

Power Consumption Delay

The Verilog code for the circuit is as below:

module Question_3_1 (A,B,C,x);

The Verilog code for the circuit is as below:

module Question_3_2 (A,B,C,x);

Anda mungkin juga menyukai