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MF1494-03

S1D15712 Series

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Rev. 1.2
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“Seiko Epson is neither licensed nor authorized to license its customers under one or more patents held by
Motif Corporation to use this integrated circuit in the manufacture of liquid crystal display modules. Such
license, however, may be obtained directly from MOTIF by writing to: Motif, Inc., c/o In Focus Systems, Inc.,
27700A SW Parkway Avenue, Wilsonville, OR 97070-9215, Attention: Vice President Corporate
Development.”
 SEIKO EPSON CORPORATION 2002

Rev. 1.2
SED1575 Series

Contents

1. DESCRIPTION .................................................................................................................................................. 1

2. FEATURES ........................................................................................................................................................ 1

3. BLOCK DIAGRAM ............................................................................................................................................. 2

4. PIN ASSIGNMENT ............................................................................................................................................ 3

5. PIN DESCRIPTION ........................................................................................................................................... 7

6. FUNCTIONAL DESCRIPTION ........................................................................................................................ 11

7. COMMAND ...................................................................................................................................................... 27

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8. ABSOLUTE MAXIMUM RATINGS .................................................................................................................. 48

9. DC CHARACTERISTICS ................................................................................................................................. 49

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10. TIMING CHARACTERISTICS ......................................................................................................................... 56

11. MPU INTERFACE (Reference Example) ........................................................................................................ 62

12. CONNECTION BETWEEN LCD DRIVERS (Reference Example) .................................................................. 63

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13. LCD PANEL WIRING (Reference Example) ................................................................................................... 64

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14. CAUTIONS ...................................................................................................................................................... 65

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–i– Rev. 1.2


S1D15712 Series

1. DESCRIPTION 2. FEATURES
The S1D15712 Series is a single chip MLS driver for • Direct RAM data display by display data RAM
dot matrix liquid crystal displays which can be directly • 4 gray-scale display
connected to the microcomputer bus. It accepts the 8- (Normally white in normal display mode)
bit parallel or serial display data from the microcomputer RAM bit data (high order and low order)
to store the data in the on-chip display data RAM, and (1,1) : gray-scale 3, black
issues liquid crystal drive signals independently of the (1,0) : gray-scale 2
microcomputer. (0,1) : gray-scale 1
The S1D15712 Series provides both 4 gray-scale display (0,0) : gray-scale 0, white
and binary display. It incorporates a display data RAM • Binary display
(81 × 256 × 2 bits). In the case of 4 gray-scale display, (Normally white display is in normal mode)
2 bits of the on-chip RAM respond to one-dot pixels, RAM bit data
while in the case of binary display, 1 bit of the on-chip “1” : On and black
RAM respond to one-dot pixels. “0” : Off and white
The S1D15712 Series features 81 common output • RAM capacity
circuits and 256 segment output circuits. A single chip 81 × 256 × 2 = 41,472 bits
provides a display of 16 characters by 5 lines with 81 × • Liquid crystal drive circuit

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256 dots (16 × 16 dots) and display of 21 characters by 81 common outputs and 256 segment outputs
6 lines by the 12 × 12 dot-character font. • High-speed 8-bit MPU interface (directly connectable

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S1D15712 Series can be used to constitute a system to to the MPUs of both 80/68 series) /serial interface
provide optimum LCD contrast throughout a wide possible

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temperature range without need for use of supplementary • A variety of command functions
parts such as the thermistor, under controls of a micro Duty set, n-line reversal, display data RAM address
computer. control, contrast control, display ON/OFF, display

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Display data RAM read/write operations do not require normal/reverse rotation, display all lighting ON/
operation clock from outside, thereby ensuring operation OFF, liquid crystal drive power supply circuit control,
with the minimum current consumption. Furthermore, display clock built-in oscillator circuit control
it incorporates a LCD-drive power supply characterized • MLS drive technology
by low power consumption and a CR oscillator circuit Built-in high precision voltage regulation function

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for display clock; therefore, the display system of a • High precision CR oscillator circuit incorporated

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handy and high-performance instrument can be realized • Low power consumption

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by use of the minimum current consumption and • Built-in temperature sensor circuit
minimum chip configuration. • Power supply
Logic power supply 1: VDD – VSS = 2.7 to 3.3 V

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Logic power supply 2: VDD – VSS = 2.7 to 5.5 V

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Liquid crystal drive power supply: V3 – VSS = 5.6 to
16.2 V
Boosting power supply: VDD2 – VSS = VDD to 5.5 V

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• Wide operation temperature range: –40 to 85°C
• CMOS process
• Shipping form : Bare chips, TCP
• Light and radiation proof measures are not taken in
designing.

Series specifications
Product name Form of shipping Chip thickness
S1D15712D01B000 Bare chip 0.625mm
S1D15712T01B*** TCP —

Rev. 1.2 EPSON 1


S1D15712 Series

3. BLOCK DIAGRAM

SEG255

COM79

COMS
COM0
SEG0
VDD2
VDD
VSS

V3
V2
V1

COMS
VC
SEG Drivers COM Drivers
MV1

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MV2

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MV3 (VSS)

Decode circuit

Display data latch circuit

in a Temperature
sensor circuit
SVD2
SV22

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CAP1+
CAP1–
Power supply circuit

FR
CAP2+ SYNC
Page address

Line address

CAP2–
I/O buffer

Display data RAM F1

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VOUT
F2
256 × 81 × 2

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CAP3+
CL
CAP4+
DOF
CAP5+
M/S

VDI

P Column address
Oscillator circuit

CLS

Bus holder Command decoder Status

MPU Interface
D6 (SCL)
WR (R/W)

D7 (SI)
TEST1

RD (E)
TEST

RES

C86
P/S
CS

D5

D4

D3

D2

D1

D0
A0

2 EPSON Rev. 1.2


S1D15712 Series

4. PIN ASSIGNMENT
4.1 Chip Assignment
170 61

171 60

D157CD0B

Die No.

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(0, 0)

S1D15712 Series

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302 1

303 412

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Size
Item Unit
X Y

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Chip thickness

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Bump pitch
Bump size PAD No.1 to 3, 5 to 14, 16, 17, 19 to 27, 29 to 60
PAD No.4, 15, 18, 28
PAD No.61 to 170, 303 to 412
6.10 ×
0.625
50 (Min.)
91.1 × 81
91.1 × 35.6
33 × 113
8.44 mm
mm
µm
µm
µm
µm
PAD No.171 to 302 113 × 33 µm
Bump height 22.5 (Typ.) µm

4.2 Alignment mark


Alignment coordinate
1 (2850.0, –4020.0) µm
2 (–2850.0, 4020.0) µm b
Mark size c a
a = 80 µm
b = 20 µm
c = 70 µm

Rev. 1.2 EPSON 3


S1D15712 Series

4.3 Pad Center Coordinates

Unit: µm
PAD Pin PAD Pin PAD Pin
X Y X Y X Y
No. Name No. Name No. Name
1 NC 2890.5 –3147 51 MV1 2890.5 2121 101 COM1 724.3 4050
2 NC –3033 52 MV2 2235 102 COM0 674.3
3 NC –2919 53 MV3 2349 103 COMS 624.4
4 VDD –2832.8 54 VDD 2463 104 NC 574.4
5 TEST1 –2746.5 55 NC 2577 105 SEG0 524.5
6 SYNC –2632.5 56 SVD2 2691 106 SEG1 474.5
7 FR –2526 57 SV22 2805 107 SEG2 424.6
8 CL –2419.5 58 NC 2919 108 SEG3 374.6
9 DOF –2313 59 NC 3033 109 SEG4 324.7
10 F1 –2206.5 60 NC 3147 110 SEG5 274.7

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11 F2 –2100 61 NC 2722.3 4050 111 SEG6 224.8
12 CS –1993.5 62 NC 2672.3 112 SEG7 174.8

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13 RES –1887 63 COM39 2622.4 113 SEG8 124.9
14 A0 –1780.5 64 COM38 2572.4 114 SEG9 74.9
15 VSS –1701.8 65 COM37 2522.5 115 SEG10 25

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16 WR,R/W –1623 66 COM36 2472.5 116 SEG11 –25
17 RD,E –1516.5 67 COM35 2422.6 117 SEG12 –74.9

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18 VDD –1437.8 68 COM34 2372.6 118 SEG13 –124.9
19 D0 –1359 69 COM33 2322.7 119 SEG14 –174.8
20 D1 –1252.5 70 COM32 2272.7 120 SEG15 –224.8
21 D2 –1146 71 COM31 2222.8 121 SEG16 –274.7
22 D3 –1039.5 72 COM30 2172.8 122 SEG17 –324.7

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23 D4 –933 73 COM29 2122.9 123 SEG18 –374.6

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24 D5 –826.5 74 COM28 2072.9 124 SEG19 –424.6

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25 D6,SCL –720 75 COM27 2023 125 SEG20 –474.5
26 D7,SI –613.5 76 COM26 1973 126 SEG21 –524.5
27 VDI –507 77 COM25 1923.1 127 SEG22 –574.4

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28 VDD –428.3 78 COM24 1873.1 128 SEG23 –624.4

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29 M/S –349.5 79 COM23 1823.2 129 SEG24 –674.3
30 CLS –243 80 COM22 1773.2 130 SEG25 –724.3
31 VSS –136.5 81 COM21 1723.3 131 SEG26 –774.2
32 TEST –30 82 COM20 1673.3 132 SEG27 –824.2

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33 C86 76.5 83 COM19 1623.4 133 SEG28 –874.1
34 P/S 183 84 COM18 1573.4 134 SEG29 –924.1
35 VDD 297 85 COM17 1523.5 135 SEG30 –974
36 VDD 411 86 COM16 1473.5 136 SEG31 –1024
37 VDD2 525 87 COM15 1423.6 137 SEG32 –1073.9
38 VOUT 639 88 COM14 1373.6 138 SEG33 –1123.9
39 CAP1+ 753 89 COM13 1323.7 139 SEG34 –1173.8
40 CAP1– 867 90 COM12 1273.7 140 SEG35 –1223.8
41 CAP3+ 981 91 COM11 1223.8 141 SEG36 –1273.7
42 CAP5+ 1095 92 COM10 1173.8 142 SEG37 –1323.7
43 VOUT 1209 93 COM9 1123.9 143 SEG38 –1373.6
44 CAP4+ 1323 94 COM8 1073.9 144 SEG39 –1423.6
45 CAP2– 1437 95 COM7 1024 145 SEG40 –1473.5
46 CAP2+ 1551 96 COM6 974 146 SEG41 –1523.5
47 V3 1665 97 COM5 924.1 147 SEG42 –1573.4
48 V2 1779 98 COM4 874.1 148 SEG43 –1623.4
49 V1 1893 99 COM3 824.2 149 SEG44 –1673.3
50 VC 2007 100 COM2 774.2 150 SEG45 –1723.3

4 EPSON Rev. 1.2


S1D15712 Series

Unit: µm
PAD Pin PAD Pin PAD Pin
X Y X Y X Y
No. Name No. Name No. Name
151 SEG46 –1773.2 4050 201 SEG92 –2880 1773.2 251 SEG142 –2880 –724.3
152 SEG47 –1823.2 202 SEG93 1723.3 252 SEG143 –774.2
153 SEG48 –1873.1 203 SEG94 1673.3 253 SEG144 –824.2
154 SEG49 –1923.1 204 SEG95 1623.4 254 SEG145 –874.1
155 SEG50 –1973 205 SEG96 1573.4 255 SEG146 –924.1
156 SEG51 –2023 206 SEG97 1523.5 256 SEG147 –974
157 SEG52 –2072.9 207 SEG98 1473.5 257 SEG148 –1024
158 SEG53 –2122.9 208 SEG99 1423.6 258 SEG149 –1073.9
159 SEG54 –2172.8 209 SEG100 1373.6 259 SEG150 –1123.9
160 SEG55 –2222.8 210 SEG101 1323.7 260 SEG151 –1173.8

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161 SEG56 –2272.7 211 SEG102 1273.7 261 SEG152 –1223.8
162 SEG57 –2322.7 212 SEG103 1223.8 262 SEG153 –1273.7

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163 SEG58 –2372.6 213 SEG104 1173.8 263 SEG154 –1323.7
164 SEG59 –2422.6 214 SEG105 1123.9 264 SEG155 –1373.6
165 SEG60 –2472.5 215 SEG106 1073.9

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265 SEG156 –1423.6
166 SEG61 –2522.5 216 SEG107 1024 266 SEG157 –1473.5
167 SEG62 –2572.4 217 SEG108 974 267 SEG158 –1523.5

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168 SEG63 –2622.4 218 SEG109 924.1 268 SEG159 –1573.4
169 NC –2672.3 219 SEG110 874.1 269 SEG160 –1623.4
170 NC –2722.3 220 SEG111 824.2 270 SEG161 –1673.3
171 NC –2880 3271.7 221 SEG112 774.2 271 SEG162 –1723.3
172 NC 3221.8 222 SEG113 724.3 272 SEG163 –1773.2

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173 SEG64 3171.8 223 SEG114 674.3 273 SEG164 –1823.2

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174 SEG65 3121.9 224 SEG115 624.4 274 SEG165 –1873.1

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175 SEG66 3071.9 225 SEG116 574.4 275 SEG166 –1923.1
176 SEG67 3022 226 SEG117 524.5 276 SEG167 –1973
177 SEG68 2972 227 SEG118 474.5 277 SEG168 –2023

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178 SEG69 2922.1 228 SEG119 424.6 278 SEG169 –2072.9

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179 SEG70 2872.1 229 SEG120 374.6 279 SEG170 –2122.9
180 SEG71 2822.2 230 SEG121 324.7 280 SEG171 –2172.8
181 SEG72 2772.2 231 SEG122 274.7 281 SEG172 –2222.8
182 SEG73 2722.3 232 SEG123 224.8

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282 SEG173 –2272.7
183 SEG74 2672.3 233 SEG124 174.8 283 SEG174 –2322.7
184 SEG75 2622.4 234 SEG125 124.9 284 SEG175 –2372.6
185 SEG76 2572.4 235 SEG126 74.9 285 SEG176 –2422.6
186 SEG77 2522.5 236 SEG127 25 286 SEG177 –2472.5
187 SEG78 2472.5 237 SEG128 –25 287 SEG178 –2522.5
188 SEG79 2422.6 238 SEG129 –74.9 288 SEG179 –2572.4
189 SEG80 2372.6 239 SEG130 –124.9 289 SEG180 –2622.4
190 SEG81 2322.7 240 SEG131 –174.8 290 SEG181 –2672.3
191 SEG82 2272.7 241 SEG132 –224.8 291 SEG182 –2722.3
192 SEG83 2222.8 242 SEG133 –274.7 292 SEG183 –2772.2
193 SEG84 2172.8 243 SEG134 –324.7 293 SEG184 –2822.2
194 SEG85 2122.9 244 SEG135 –374.6 294 SEG185 –2872.1
195 SEG86 2072.9 245 SEG136 –424.6 295 SEG186 –2922.1
196 SEG87 2023 246 SEG137 –474.5 296 SEG187 –2972
197 SEG88 1973 247 SEG138 –524.5 297 SEG188 –3022
198 SEG89 1923.1 248 SEG139 –574.4 298 SEG189 –3071.9
199 SEG90 1873.1 249 SEG140 –624.4 299 SEG190 –3121.9
200 SEG91 1823.2 250 SEG141 –674.3 300 SEG191 –3171.8

Rev. 1.2 EPSON 5


S1D15712 Series

Unit: µm
PAD Pin PAD Pin PAD Pin
X Y X Y X Y
No. Name No. Name No. Name
301 NC –2880 –3221.8 351 SEG238 –324.7 –4050 401 COM71 2172.8 –4050
302 NC –3271.7 352 SEG239 –274.7 402 COM72 2222.8
303 NC –2722.3 –4050 353 SEG240 –224.8 403 COM73 2272.7
304 NC –2672.3 354 SEG241 –174.8 404 COM74 2322.7
305 SEG192 –2622.4 355 SEG242 –124.9 405 COM75 2372.6
306 SEG193 –2572.4 356 SEG243 –74.9 406 COM76 2422.6
307 SEG194 –2522.5 357 SEG244 –25 407 COM77 2472.5
308 SEG195 –2472.5 358 SEG245 25 408 COM78 2522.5
309 SEG196 –2422.6 359 SEG246 74.9 409 COM79 2572.4
310 SEG197 –2372.6 360 SEG247 124.9 410 COMS 2622.4

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311 SEG198 –2322.7 361 SEG248 174.8 411 NC 2672.3
312 SEG199 –2272.7 362 SEG249 224.8 412 NC 2722.3

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313 SEG200 –2222.8 363 SEG250 274.7
314 SEG201 –2172.8 364 SEG251 324.7
315 SEG202 –2122.9 365 SEG252 374.6

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316 SEG203 –2072.9 366 SEG253 424.6
317 SEG204 –2023 367 SEG254 474.5

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318 SEG205 –1973 368 SEG255 524.5
319 SEG206 –1923.1 369 NC 574.4
320 SEG207 –1873.1 370 COM40 624.4
321 SEG208 –1823.2 371 COM41 674.3
322 SEG209 –1773.2 372 COM42 724.3

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323 SEG210 –1723.3 373 COM43 774.2

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324 SEG211 –1673.3 374 COM44 824.2

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325 SEG212 –1623.4 375 COM45 874.1
326 SEG213 –1573.4 376 COM46 924.1
327 SEG214 –1523.5 377 COM47 974

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328 SEG215 –1473.5 378 COM48 1024

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329 SEG216 –1423.6 379 COM49 1073.9
330 SEG217 –1373.6 380 COM50 1123.9
331 SEG218 –1323.7 381 COM51 1173.8
332 SEG219 –1273.7 382 COM52 1223.8

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333 SEG220 –1223.8 383 COM53 1273.7
334 SEG221 –1173.8 384 COM54 1323.7
335 SEG222 –1123.9 385 COM55 1373.6
336 SEG223 –1073.9 386 COM56 1423.6
337 SEG224 –1024 387 COM57 1473.5
338 SEG225 –974 388 COM58 1523.5
339 SEG226 –924.1 389 COM59 1573.4
340 SEG227 –874.1 390 COM60 1623.4
341 SEG228 –824.2 391 COM61 1673.3
342 SEG229 –774.2 392 COM62 1723.3
343 SEG230 –724.3 393 COM63 1773.2
344 SEG231 –674.3 394 COM64 1823.2
345 SEG232 –624.4 395 COM65 1873.1
346 SEG233 –574.4 396 COM66 1923.1
347 SEG234 –524.5 397 COM67 1973
348 SEG235 –474.5 398 COM68 2023
349 SEG236 –424.6 399 COM69 2072.9
350 SEG237 –374.6 400 COM70 2122.9

6 EPSON Rev. 1.2


S1D15712 Series

5. PIN DESCRIPTION
5.1 Power Pin

Number of
Pin name I/O Description pins
VDD Power Connect to system MPU power supply pin VCC. 6
supply
VSS Power Connect to the system GND. 2
supply VSS is short circuited with MV3 inside the IC chip.
VDD2 Power Boosting power supply circuit. It is necessary to maintain the 1
supply co-relation between the VDD2 and VDD as: VDD2 ≥ VDD.
VDI Power VDI pin supplies the power sent from VDD to the internal circuit for 1
operation.
Connect the capacitor between this pin and VSS. The power input
to VDI from an external power source can be also used. The input
from the external power source must satisfy the following

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relationships. 3.3 V ≥ VDI ≥ 2.7 V and VDD ≥ VDI

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V3, V2, V1, Power A liquid crystal drive multi-level power supply. The voltages 7
VC, MV1, supply determined by the liquid crystal cell are impedance-converted by (1 each)
MV2, MV3, resistive divider and operational amplifier for application.

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(=VSS) The following order must be maintained:
V3 ≥ V2 ≥ V1 ≥ VC ≥ MV1 ≥ MV2 ≥ MV3 (=VSS)

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MV3 is short circuited with VSS inside the IC chip.
Master operation: When power supply is turned on, the following
voltage is applied to each pin by the built-in power supply circuit.
V2 6/8·V3 16/20·V3 14/16·V3

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V1 5/8·V3 13/20·V3 11/16·V3
VC 4/8·V3 10/20·V3 8/16·V3

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MV1 3/8·V3 7/20·V3 5/16·V3

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MV2 2/8·V3 4/20·V3 2/16·V3

Pin name I/O


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5.2 LCD Power Supply Circuit Pin

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Number of

P
pins
CAP1+ O Pin connected to the positive side of the step-up capacitor. 1
Connect the capacitor between this pin and CAP1– pin.
CAP1– O Pin connected to the negative side of the step-up capacitor. 1
Connect the capacitor between this pin and CAP1+ pin.
CAP2+ O Pin connected to the positive side of the step-up capacitor. 1
Connect the capacitor between this pin and CAP2– pin.
CAP2– O Pin connected to the negative side of the step-up capacitor. 1
Connect the capacitor between this pin and CAP2+ pin.
VOUT O Output pin for step-up. 2
Connect the capacitor between this pin and VDD2.
CAP3+ O Pin connected to the positive side of the step-up capacitor. 1
Connect the capacitor between this pin and CAP1– pin.
CAP4+ O Pin connected to the positive side of the step-up capacitor. 1
Connect the capacitor between this pin and CAP2– pin.
CAP5+ O Pin short circuited with VOUT terminal. 1
Pin may be set to OPEN when the external power source is used
for VOUT.

Rev. 1.2 EPSON 7


S1D15712 Series

5.3 System Bus Connection Pin


Number of
Pin name I/O Description pins
D7 to D0 I/O Connects to the 8-bit or 16-bit MPU data bus via the 8-bit 8
bi-directional data bus.
(SI) When the serial interface is selected (P/S = LOW), D7 serves as the
(SCL) serial data input (SI) and D6 serves as the serial clock input (SCL),
In this case, D0 through D5 go to a high impedance state. When the
Chip select is inactive, D0 through D7 go to a high impedance state.
A0 I Normally, the least significant bit MPU address bus is connected 1
to distinguish between data and command.
A0 = HIGH : indicates that D0 to D7 are display data or command parameters.
A0 = LOW : indicates that D0 to D7 are control commands.
RES I When the RES is LOW, initialization is achieved. 1
Resetting operation is done on the level of the RES signal.
CS I A chip select signal. When CS = LOW, signals are active, 1

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and data/command input/output are enabled.

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RD I • When the 80 series MPU is connected. (active LOW) 1
(E) A pin for connection of the RD signal of the 80 series MPU.
When this signal is LOW, the data bus of the

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S1D15712 Series is in the output state.
• When the 68 series MPU is connected. (active HIGH)

in
Serves as a 68 series MPU enable clock input pin.
WR I • When the 80 series MPU is connected. (active LOW) 1
(R/W) A pin for connection of the WR signal of the 80 series MPU.
Signals on the data bus are latched at the leading edge of the
WR signal.

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• Serves as a read/write control signal input pin when the 68 series

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MPU is connected. (active HIGH)

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R/W = HIGH : Read
R/W = LOW : Write

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C86 I A MPU interface switching pin. 1
C86 = HIGH : 68 series MPU interface

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C86 = LOW : 80 series MPU interface
P/S I Parallel data input/serial data input select pin 1
P/S = HIGH : Parallel data input

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P/S = LOW : Serial data input
The following Table shows the summary:
P/S Data/Command Data Read/Write Serial clock
HIGH A0 D0 to D7 RD, WR
LOW A0 SI (D7) Write only SCL (D6)
When P/S = LOW, D0 to D5 are high impedance.
D0 to D5 can be HIGH, LOW or open.
RD(E) and WR(R/W) are locked to HIGH or LOW.
The serial data input does not allow the RAM display data to be read.

8 EPSON Rev. 1.2


S1D15712 Series

Number of
Pin name I/O Description pins
CLS I A pin used to select Enable/Disable state of the built-in oscillator 1
circuit for display clock.
CLS = HIGH : Built-in oscillator circuit Enabled
CLS = LOW : Built-in oscillator circuit Disabled (External input)
When CLS is LOW, display clock is input from the CL pin. When
the S1D15712 Series is used in the master/slave mode,
each CLS pins must be set to the same level.
Display clock Master Slave
Built-in oscillator circuit used HIGH HIGH
External input LOW LOW

M/S I A pin used to select the master/slave operation for


S1D15712 Series. 1
Liquid crystal display system is synchronized when the master

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operation outputs the timing signal required for liquid crystal

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display, while the slave operation inputs the timing signal required
for liquid crystal display.
M/S = HIGH : Master operation

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M/S = LOW : Slave operation
The following Table shows the relation in conformance to the M/S and CLS:

in
Oscillation Power FR, DOF,
M/S CLS CL
circuit circuit F1, F2, SYNC
HIGH Enabled Enabled Output Output
HIGH
LOW Disabled Enabled Input Output

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HIGH Disabled Disabled Input Input
LOW
LOW Disabled Disabled Input Input
The slave power supply circuit can also operate, but do not use it.
CL I/O Display clock input/output pin. 1

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The following Table shows the relation in conformance to the M/S and CLS state:

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M/S CLS CL
HIGH Output
HIGH
LOW Input

P
HIGH Input
LOW
LOW Input

When you want to use the S1D15712 Series in the master/slave


mode, connect each CL pin.
FR I/O A liquid crystal alternating current input/output pin. 1
M/S = HIGH : Output
M/S = LOW : Input
When you want to use the S1D15712 Series in the master/slave
mode, connect each FR pin.
F1, F2, I/O A liquid crystal sync signal input/output pin. 3
SYNC M/S = HIGH : Output (1 each)
M/S = LOW : Input
When you want to use the S1D15712 Series in the master/slave
mode, connect each F1, F2 and SYNC pins.
DOF I/O A liquid crystal blanking control pin. 1
M/S = HIGH : Output
M/S = LOW : Input
When you want to use the S1D15712 Series in the master/slave
mode, connect each DOF pin.

Rev. 1.2 EPSON 9


S1D15712 Series

5.4 Liquid crystal drive pin


Number of
Pin name I/O Description pins
SEG0 to O Liquid crystal segment drive output pins. One of the V2, V1, VC, 256
SEG255 MV1, and MV2 levels is selected by a combination of the display
RAM content and FR/F1/F2 signals.
COM0 to O Liquid crystal common drive output pins. One of the V3, VC, 80
COM79 MV3 (VSS) levels is selected by a combination of the scan data
and FR/F1/F2 signals.
COMS O COM output pins for Icon line. These pins outputted the same 2
signal. Set to OPEN not used. When COMS is used for the
master/ slave configuration, the same signal is output to both the
master and slave.

5.5 Thermal sensor pins

y
Number of
Pin name I/O Description pins
SVD2
SV22

5.6 Test pins


O
O
Analog voltage output pin for thermal sensor.
Thermal sensor test pin. Set to OPEN.

a r 1
1

in
Number of
Pin name I/O Description pins
TEST I IC chip test pin. Fix these pins LOW. 1

m
TEST1 I IC chip test pin. Fix the pin HIGH. 1

e l i
• When VDD is used at between 2.7 to 3.3 V, Short-circuit between VDD and VDI pins.

When TEST1 is set to HIGH, current consumption is increased by approximately 10 µA, because the VDI generation
circuit becomes ON.

r
When TEST1 is set to LOW, the VDI generation circuit becomes OFF.
When VDD and VDI pins are short-circuited, TEST1 can be set to LOW.
The circuits in this IC are operated by using the VDI voltage as power supply voltage that is generated within the IC.

P
The ON/OFF control of the VDI voltage generation circuit can be done by set up of the TEST1 pin.
When TEST1 is used after changing from LOW to HIGH, initialization by resetting (setting RES to LOW) is required.

10 EPSON Rev. 1.2


S1D15712 Series

6. FUNCTIONAL DESCRIPTION
6.1 MPU Interface
6.1.1 Selection of Interface Type
S1D15712 Series allows data to be sent via the 8-bit bi-directional data buses (D7 to D0) or serial data input (SI). By
setting the polarity of the P/S pin to HIGH or LOW, you can select either 8-bit parallel data input or serial data input,
as shown in Table 6.1.

Table 6.1
P/S CS A0 RD WR C86 D7 D6 D5 to D0
HIGH : Parallel input CS A0 RD WR C86 D7 D6 D5 to D0
LOW : Serial input CS A0 — — — SI SCL (HZ)
—: Fixed to HIGH or LOW HZ: High impedance state
6.1.2 parallel interface
When the parallel interface is selected (P/S = HIGH), direction connection to the MPU bus of either 80 series MPU or

y
68 series MPU is performed by setting the 86 pin to either HIGH or LOW, as shown in Table 6.2.

Table 6.2
P/S
HIGH : 68 series MPU bus
CS
CS
A0
A0
RD
E
WR
R/W

a
D7 to D0
D7 to D0 r
in
LOW : 80 series MPU bus CS A0 RD WR D7 to D0

The data bus signals are identified by a combination of A0, RD (E), and WR (R/W) signals as shown in Table 6.3.

m
Table 6.3

i
Common 68 series 80 series

l
Function
A0 R/W RD WR
1 1 0 1 Display data read, status read
1
0
0
0

r
1
1

e 0
0
Display data write, status write
Command write

6.1.3 Serial interface

P
When the serial interface is selected (P/S =LOW), the chip is active (CS = LOW), and reception of serial data input (SI)
and serial clock input (SCL) is enabled. Serial interface comprises a 8-bit shift register and 3-bit counter. The serial
data are latched by the rising edge of serial clock signals in the order of D7, D6, .... and D0 starting from the serial data
input pin. On the rising edge of 8th serial clock signal, they are converted into 8-bit parallel data to be processed.
Whether serial data input is a display data or command is identified by A0 input. A0 = HIGH indicates display data,
while A0 = LOW shows command data. The A0 input is read and identified at every 8 × n-th rising edge of the serial
clock after the chip has turned active.
Fig. 6.1 shows the serial interface signal chart.

Rev. 1.2 EPSON 11


S1D15712 Series

CS

SI D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2

SCL
1 2 3 4 5 6 7 8 9 10 11 12 13 14
A0

Fig. 6.1

* When the chip is inactive, the counter is reset to the initials state.
* Reading is not performed in the case of serial interface.
* For the SCL signal, a sufficient care must be taken against terminal reflection of the wiring and external noise.
Recommend to use an actual equipment to verify the operation.

y
6.1.4 Chip Selection

r
The S1D15712 Series has chip select pin. MPU interface or serial interface is enabled only when CS = LOW.
When the chip select pin is inactive, D0 to D5 are in the state of high impedance, while A0, RD and WR inputs are
disabled. When serial interface is selected, the shift register and counter are reset.

6.1.5 Access to display data RAM and internal register

in
does not required waiting time; hence, high-speed data transfer is allowed.
a
Access to S1D15712 Series viewed from the MPU side is enabled only if the cycle time requirements are kept. This

Furthermore, at the time of data transfer with the MPU, S1D15712 Series provides a kind of inter-LSI pipe line
processing via the bus holder accompanying the internal data bus.
For example, when data is written to the display data RAM by the MPU, the data is once held by the bus holder. It is

m
written to the display data RAM before the next data write cycle comes.

i
On the other hand, when the MPU reads the content of the display data RAM, it is read in the first data read cycle

l
(dummy), and the data is held in the bus holder. Then it is read onto on the system bus from the bus holder in the next
data read cycle. Restrictions are imposed on the display data RAM read sequence. When the address has been set,
specified address data is not output to the Read command immediately after that. The specified address data is output

e
in the second data reading. This must be carefully noted. Therefore, one dummy read operation is mandatory

r
subsequent to address setting or write cycle. Fig. 6.2 illustrates this relationship.

12 EPSON Rev. 1.2


S1D15712 Series

Write

A0
WR
MPU

Latch
DATA White N N+1 N+2
Command
Internal timing

BUS Holder N N+1 N+2

Write Signal

Read

A0

WR

y
MPU

RD

DATA Read
Command
Dumy

a
n

r n+1
Internal timing

in
Read Signal

Column Address Preset N Increment N+1 N+2


Bus Holder Read command code n n+1 n+2

m
Dummy Read Data Read Data Read

e l i Fig. 6.2

6.2 Display data RAM


6.2.1 Display Data RAM

P r
This is a RAM to store the display dot data, and comprises 81 × 256 × 2 bits. Access to the desired bit is enabled by
specifying the page address and column address. When the 4 gray-scale is selected by the Display Mode command,
display data input for gray-scale display are processed as a two-bit pair. Combination is as follows:

(MSB, LSB) = (D1,D0), (D3,D2), (DS,D4), (D7,D6)

When the RAM bit data is gray-scale 1 and 2, gray-scale display is realized according to the parameter of the Gray-scale
Pattern Set command.
RAM bit data (high order and low order)
(1,1) : gray-scale 3 Black (when display is in normal mode)
(1,0) : gray-scale 2
(0,1) : gray-scale 1
(0,0) : gray-scale 0 White (when display is in normal mode)

When binary display is selected by the Display Mode command, the RAM 1 bit built in the one-dot pixel responds to
it. When the RAM bit data is “1”, the display is black. If it is “0”, the display is given in white.
RAM bit data
“1” : Light On Black (when display is in normal mode)
“0” : Light Off White (when display is in normal mode)

Rev. 1.2 EPSON 13


S1D15712 Series

Display data D7 to D0 from the MPU correspond to LCD common direction, as shown in Fig. 6.3 and 6.4. Therefore,
less restrictions when multi-chip usage.
Furthermore, read/write operations from the MPU to the RAM are carried out via the input/output buffer. The read
operation from Display data RAM is designed as an independent operation. Accordingly, even if the MPU accesses
the RAM asynchronously during LCD display, no adverse effect is given to display.

(D1,D0) (0,0) (1,1) (1,1) (0,0) COM0


(D3,D2) (1,1) (0,0) (0,0) (0,0) COM1
(D5,D4) (0,0) (1,0) (0,1) (0,0) COM2
(D7,D6) (0,0) (0,0) (0,0) (0,0) COM3

Display data RAM LCD

Fig. 6.3 4 gray-scale

D0 0 1 1 1 0 COM0

r y
a
D1 1 0 0 0 0 COM1
D2 0 0 0 0 0 COM2

in
D3 0 1 1 1 0 COM3
D4 1 0 0 0 0 COM4

Display data RAM LCD

l i m Fig. 6.4 Binary

e
6.2.2 Gray-scale display

r
When the 4 gray-scale is selected by the Display Mode command, gray-scale is represented by the FRM control carried
out according to the gray-scale data written in the display data RAM.
Of the 4 gray-scale, 2 gray-scale of halftones (gray-scale 2 and 1) has its level of contrast specified by the Gray-scale

P
Set command. Gray-scale can be selected from 5 levels of contrast.

6.2.3 Page address circuit/column address circuit


The address of the display data RAM to be accessed is specified by the Page Address Set command and Column Address
Set command, as shown in Fig. 6.5 and Fig. 6.6.
For Address incremental direction, either the column direction or page direction can be selected by the Address
Direction command. Whichever direction is chosen, increment is carried out by positive one (+1) after write or read
operation.
When the column direction is selected for address increment, the column address is increased by +1 for every write or
read operation. After the column address has accessed up to FFH, the page address is incremented by +1 and the column
address shifts to 0H.
When the page direction is selected for address increment, the page address is increased with the column address locked
in position. When the page address has accessed up to Page 20, the column address is incremented by +1, and the page
address goes to Page 0.
Whichever direction is selected for address increment, the page address goes back to Page 0 and the column address
to 0H after access up to the column address FFH of page address Page 20.
As shown in Fig. 6.4, relationship between the display data RAM column address and segment output can be reversed
by the Column Address Set Direction command. This will reduce restrictions on IC layout during LCD module
assembling.
Page 20 is a RAM domain only for indicators, and when display data D0 · D1 chooses two values after four-gradation
being chosen by the display mode command, only D0 of its display data is effective.

14 EPSON Rev. 1.2


S1D15712 Series

Table 6.4
SEG output SEG0 SEG255
ADC “0” 0(H)→ Column Address →FF(H)
(D0) “1” FF(H)← Column Address ←0(H)

6.2.4 Line address circuit


The line address circuit specifies the line address corresponding to COM output when the contents of the display data
RAM is displayed, as shown in Fig. 6.5 and 6.6. Normally, the top line of the display (COM0 output in the case of normal
rotation of the common output status and COM79 output in the case of reverse rotation) is specified by the Display Start
Line Address Set command. The display area starts from the specified display start line address to cover the area
corresponding to the lines specified by the DUTY Set command in the direction where the line address increments.
If the display start line address set command is used for dynamic modification of the line address, screen scroll and page
change are enabled.

6.2.5 Display data latch circuit

y
The display data latch circuit is a latch to temporarily latch the display data output from then display data RAM to the
liquid crystal drive circuit. Display normal/reverse, display ON/OFF, and display all lighting ON/OFF commands

r
control the data in this latch, without the data in the display data RAM being controlled.

in a
l i m
r e
P

Rev. 1.2 EPSON 15


S1D15712 Series

4 gray-scale display Line Common COM


Page Address Output state:
Data
D4 D3 D2 D1 D0 Address Normal rotation Output
When the display start line is set to 11H

D1,D0 00H COM0


D3,D2 01H COM1
0 0 0 0 0 Page 0
D5,D4 02H COM2
D7,D6 03H COM3
D1,D0 04H COM4
D3,D2 05H COM4
0 0 0 0 1 Page 1
D5,D4 06H COM6
D7,D6 07H COM7
D1,D0 08H COM8

80 lines
D3,D2 09H COM9
0 0 0 1 0 Page 2
D5,D4 0AH COM10
D7,D6 0BH COM11
D1,D0 0CH COM12
D3,D2 0DH COM13
0 0 0 1 1 Page 3

y
D5,D4 0EH COM14
D7,D6 0FH COM15

r
D1,D0 10H COM16
D3,D2 11H COM17
0 0 1 0 0 Page 4

a
D5,D4 12H COM18
D7,D6 13H COM19
D1,D0 14H COM20

in
D3,D2 15H COM21
0 0 1 0 1 Page 5
D5,D4 16H Start COM22
D7,D6 17H COM23

1 0 0 1 0
D1,D0
D3,D2
D5,D4

l i m Page 18
48H
49H
4AH
COM72
COM73
COM74

e
D7,D6 4BH COM75

r
D1,D0 4CH COM76
D3,D2 4DH COM77
1 0 0 1 1 Page 19
D5,D4 4EH COM78
D7,D6 COM79

P
4FH
1 0 1 0 0 D1,D0 Page 20 COMS
Address
Column
SEG252 03 FC
SEG253 02 FD
SEG251 04 FB

SEG254 01 FE

D0 D0
SEG255 00 FF
SEG250 05 FA
SEG0 FF 00
SEG1 FE 01
SEG2 FD 02
SEG3 FC 03
SEG4 FB 04
SEG5 FA 05

ADC

Accesses to line 81
1

independent from the


LCD

display start line


Out

address.

Fig. 6.5 4 gray-scale

16 EPSON Rev. 1.2


S1D15712 Series

Binary display
Common
Page Address Line output state: COM
Data Address Output
D4 D3 D2 D1 D0 When the display start line is set to 06CH Normal mode

D0 00H COM0
D1 01H COM1
D2 02H COM2
D3 03H COM3
0 0 0 0 0 D4 Page 0 04H COM4
D5 05H COM5
D6 06H COM6
D7 07H COM7
Start
D0 08H COM8
D1 09H COM9
D2 0AH COM10
D3 0BH COM11
0 0 0 0 1 D4 Page 1 0CH COM12
D5 0DH COM13
D6 0EH COM14
D7 0FH COM15
D0 10H COM16
D1 11H COM17

80 lines
D2 12H COM18

y
0 0 0 1 0 D3 Page 2 13H COM19
D4 14H COM20

r
D5 15H COM21
D6 16H COM22

.........

.........
D7
.........

.........

a
D0
D1 49H COM73
D2 4AH COM74
D3 4BH COM75

in
0 1 0 0 1 D4 Page 9 4CH COM76
D5 4DH COM77
D6 4EH COM78
D7 4FH COM79
D0 50H
D1 51H
D2 52H

m
0 1 0 1 0 D3 Page 10 53H

i
D4 54H

l
D5 55H
D6 56H
.........

D7
.........

.........

D0

e
D1 99H
D2 9AH

r
D3 9BH
1 0 0 1 1 D4 Page 19 9CH
D5 9DH
D6 9EH

P
D7 9FH
1 0 1 0 0 D0 Page 20 COMS
Address
Column
FC
FD
FA
FB

FE

D0 D0
FF
SEG0 FF 00
SEG1 FE 01
SEG2 FD 02
SEG3 FC 03
SEG4 FB 04
SEG5 FA 05

1 0

ADC
05
04
03
02
01
00

Accesses to line 81
SEG250
SEG251
SEG252
SEG253
SEG254
SEG255

independent from the


LCD
Out

display start line


address.

Fig. 6.6 Binary display

Rev. 1.2 EPSON 17


S1D15712 Series

6.3 Oscillator circuit


A display clock is generated by the CR oscillator. The oscillator circuit is enabled only when M/S = HIGH and CLS
= HIGH. Oscillation starts after input of the built-in oscillator circuit ON command input.
When CLS = LOW, oscillation stops, and display clock is input from the CL pin.

6.4 Display timing generation circuit


Timing signals are generated from the display clock to the line address circuit and display data latch circuit.
Synchronized with display clock, display data is latched in display data latch circuit, and is output to the segment drive
output pin. Reading of the display data into the LCD drive circuit is completely independent of access from the MPU
to the display data RAM. Accordingly, asynchronous access to the display data RAM during LCD display does not give
any adverse effect; like as flicker.
Furthermore, the display clock generates internal common timing, liquid crystal alternating signal(FR), field start signal
(SYNC) and drive pattern signal (Fl and F2).
The FR normally generates 2-frame alternating drive system drive waveform to the liquid crystal drive circuit. The
n-line reverse alternating drive waveform is generated for each 4 × (a+1) line by setting data on the n–line reverse drive
register. When there is a display quality problem including crosstalk,the problem may be solved using the n-line reverse
alternating drive.

y
Execute liquid crystal display to determine the number of lines “n” for alternation.

r
When you want to use the S1D15712 Series in multi-chip configuration, supply display timing signal (FR, SYNC, F1,
F2, CL, DOF) to the slave side from the master side. Table 6.5 shows the statuses of FR, SYNC, F1, F2, CL, DOF.

Table 6.5
Operating mode
Master (M/S = HIGH) Built-in oscillator circuit enabled (CLS = HIGH)
Built-in oscillator circuit disabled (CLS = LOW)
Slave (M/S = LOW) Built-in oscillator circuit enabled (CLS = HIGH)
Built-in oscillator circuit disabled (CLS = LOW)
in a CL
Output
Input
Input
Input
FR,SYNC, F1, F2, DOF
Output
Output
Input
Input

6.5 Liquid crystal drive circuit


6.5.1 SEG Drivers

l i m
e
This is a SEG output circuit. It selects the five values of V2, V1, VC, MV1 and MV2 using the driver control signal

r
determined by the decoder, and output them.

6.5.2 COM Drivers

P
This is a COM output circuit. It selects three values of V3, VC and MV3(VSS) using the driver control signal determined
by the decoder, and output them.
S1D15712 Series allows the COM output scanning direction to be set by the common output status select command.
(See Table 6.6). This will reduce restrictions on IC layout during LCD module assembling.

6.5.3 COMS
It is a COM output circuit for microcomputer lines, and three values of V3, VC and MV3 (VSS) are output after being
chosen with the driver control signal determined by the decoder. These can be output to the timing just before one screen
is changed, independent of DUTY selection command and display start line selection command.

Table 6.6
Status Direction of COM scanning
Normal COM 0 → COM79 → COMS
Reverse COM79 → COM 0 → COMS

18 EPSON Rev. 1.2


S1D15712 Series

6.6 Power supply circuit


This is a power supply circuit to generate voltage required for liquid crystal drive, and is characterized by a low power
consumption. It consists of a step-up circuit, voltage regulating circuit and liquid crystal drive voltage generating
circuit, and is enabled only during master operation. The power supply circuit uses the power control set command to
provide an on/off control of step-up circuit, voltage regulating circuit and liquid crystal drive potential generating
circuit. This allows a combined use of the external power supply and part of built-in power supply functions. Table
6.7 shows functions controlled by the 3-bit data of the control set command, and Table 6.8 shows reference
combinations. Also, by use of the magnification of amplification changing over command, it is possible to select the
amplifying magnification from five different steps. The power supply circuit is enabled only during master operation.

Table 6.7 Control by 5-bit data of the control set command


Item State
“1” “0”
D2 Step-cut circuit control bit ON OFF

y
D1 Voltage regulator circuit (V3 regulator circuit) control bit ON OFF
D0 LCD driving potential generating circuit (LCDV circuit) control bit ON OFF

Table 6.8 Reference combination


Circuits used D2 D1 D0 Step-up VC regulator

a LCDV r
Eternal input

in
circuit circuit circuit power supply
1 Use of all built-in 1 1 1 “1” “1” “1” –
power supplies
2 V3 regulating circuit and 0 1 1 × “0” “1” “1” VOUT

m
LCDV circuit only

i
3 LCDV circuit only 0 0 1 × “0” × “0” “1” V3

l
4 External power supply only 0 0 0 × “0” × “0” × “0” V 3 , V 2 , V 1 , VC ,
MV1, MV2

e
* Any combinations other than the above are not available.
In case of 2, the V3 voltage is generated from VOUT. Set VOUT ≥ V3+0.2 V.

P r

Rev. 1.2 EPSON 19


S1D15712 Series

6.6.1 Amplification circuit


By use of the amplification circuit being built into the S1D15712 Series, it is possible to make amplification of the
electric potential between VDD2–VSS onto quintuple amplification, quadruple amplification, triple amplification or
double amplification. Also, by use of the relevant command, it is possible to select either one from the quintuple
amplification, quadruple amplification, triple amplification, double amplification and equal amplification.

1 When using the quintuple-boosting, connect the capacitor C1 between CAP1+ <–> CAP1–, between CAP2+ <–>
CAP2–, between CAP3+ <–> CAP1–, between CAP4+ <–> CAP2– and between VDD2 <–> VOUT before use.
2 When using the quadruple-boosting, connect the capacitor C1 between CAP1+ <–> CAP1–, between CAP2+ <–>
CAP2–, between CAP3+ <–> CAP1– and between VDD2 <–> VOUT and short-circuit the CAP4+ pin and the VOUT pin
before use.
3 When using the triple-boosting, connect the capacitor C1 between CAP1+ <–> CAP1–, between CAP2+ <–> CAP2–
and between VDD2 <–> VOUT and short-circuit the CAP4+ pin, CAP3+ pin and the VOUT pin before use.
4 When using the double-boosting, connect the capacitor C1 between CAP1+ <–> CAP1– and between VDD2 <–>
VOUT, open the CAP2– pin and short-circuit the CAP4+ pin, CAP3+ pin, CAP2+ pin and the VOUT pin before use.

C1
VDD2
C1
VDD2
C1
VDD2

r y
C1
VDD2

a
+ VOUT + VOUT + VOUT + VOUT

+ CAP1+ + CAP1+ + CAP1+ + CAP1+


C1 C1 C1 C1

in
S1D15712 Series

S1D15712 Series

S1D15712 Series

S1D15712 Series
CAP1– CAP1– CAP1– CAP1–
C1 C1
+ +
CAP3+ CAP3+ CAP3+ CAP3+

+ CAP4+ CAP4+ CAP4+ CAP4+

m
C1

i
CAP2– CAP2– CAP2– OPEN CAP2–
C1 C1 C1

l
+ CAP2+ + CAP2+ + CAP2+ CAP2+

e
1 Quintuple-boosting 2 Quadruple-boosting 3 Triple-boosting 4 Double-boosting

VOUT = 5 × VDD2 = 15V


r
Fig. 6.7.1 below shows the electric potential relations when making respective amplifications.

P VOUT = 4 × VDD2 = 12V VOUT = 3 × VDD2 = 12V


VOUT = 2 × VDD2 = 10V

VDD2 = 5V
VDD2 = 4V
VDD2 = 3V VDD2 = 3V

VSS = 0V VSS = 0V VSS = 0V VSS = 0V


Electric potential relations Electric potential relations Electric potential relations Electric potential relations
when making the quintuple when making the quadruple when making the triple when making the double
amplification amplification amplification amplification

Fig. 6.7.1

* Set the voltage range of the VDD2 so that the voltage of the VOUT pin may not exceed the absolute maximum rating.

20 EPSON Rev. 1.2


S1D15712 Series

6.6.2 Voltage Regulating Circuit


VOUT generated from the step-up circuit or VOUT input from the outside produces liquid crystal drive voltage VC via
the voltage regulating circuit. The voltage regulating circuit is controlled by liquid crystal drive voltage change
command and electronic volume.
The S1D15712 Series has a high precision constant voltage source, and incorporates 8-step liquid crystal drive voltage
change command and 128-step electronic volume functions. This makes it possible to provide a high precision liquid
crystal drive voltage regulation only by the command without adding any external parts.

• Electronic volume

α of Table 6.10 indicates an electronic volume command value. It takes one of 128 states when the data is set in the
7-bit electronic volume register.
Table 6.9 shows the value of α by setting the data in the electronic volume register.

Table 6.9

y
D6 D5 D4 D3 D2 D1 D0 α Voltage VC

r
0 0 0 0 0 0 0 0 Small
0 0 0 0 0 0 1 1 ↑
0 0 0 0 0 1 0 2

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
0
1
125
126
127

in

Largea
m
• Liquid crystal drive voltage selection

i
The liquid drive voltage range can be selected from 8 states by the liquid crystal drive voltage select command using

l
the 3-bit crystal drive voltage select command register. The V3 voltage output ranges in Table 6.10 are Typ. values at
25˚C. The V3 voltage output range varies with the temperature depending on the temperature gradient set by the Set
Temperature gradient command.

e
Table 6.10

D2
0
0
0
D1
0
0
1
D0
0
1
0 P r VC voltage output range
5.6 to 7.0V
6.3 to 7.8V
7.1 to 8.9V
Example)
When the V3 voltage output range is set as (D2,
D1, D0) = (0, 1, 1).
At 35˚C with the temperature gradient setting –
0 1 1 8.0 to 10.0V 0.06% / ˚C,
1 0 0 9.2 to 11.4V 8 V + 8 V × {(35–25) × (–0.06/100)} = 7.952 V
10 V + 10 V × {(35-25) × (–0.06/100)} = 9.94 V
1 0 1 10.3 to 12.8V The calculated V3 voltage output range is between
1 1 0 11.7 to 14.5V 7.952 and 9.94 V.
1 1 1 12.8 to 16.0V

Rev. 1.2 EPSON 21


S1D15712 Series

Equation A-1 shows the theoretical value of V3 at 25˚C, over which the
actual value has an error (Max. ± 3% at 25˚C).

Equation A-1
Unit [V]
LCD voltage selection α = 0 to 127
D2 D1 D0 V3 (Max.) V3
0 0 0 7.0 5.576+0.0109 × α
0 0 1 7.8 6.256+0.0122 × α
0 1 0 8.9 7.125+0.0139 × α
0 1 1 10.0 8.016+0.0156 × α
1 0 0 11.4 9.161+0.0178 × α
1 0 1 12.8 10.26+0.0200 × α
1 1 0 14.5 11.659+0.0227 × α
12.825+0.0250 × α

y
1 1 1 16.0

r
16

14

12

in a
m
10

i
V3

e l
r
6

P
4

0
32 64 96 127

Value of electronic volume α

Figure 6.8

22 EPSON Rev. 1.2


S1D15712 Series

6.6.3 Liquid crystal drive voltage generation circuit


Voltages V3 is converted by resistive divider to produce V2, V1, VC, MV1 and MV2 voltages. V2, V1, VC, MV1 and
MV2 voltages are impedance-converted by the voltage follower, and is supplied to the liquid crystal drive circuit.
A bias ratio is chosen by the bias set command.

Table 6.11 LCD bias set command register contents


D1 D0 D1 D0 D1 D0
0 0 0 1 1 0
V2 6/8·V3 16/20·V3 14/16·V3
V1 5/8·V3 13/20·V3 11/16·V3
VC 4/8·V3 10/20·V3 8/16·V3
MV1 3/8·V3 7/20·V3 5/16·V3
MV2 2/8·V3 4/20·V3 2/16·V3

r y
in a
l i m
r e
P

Rev. 1.2 EPSON 23


S1D15712 Series

Examples of the peripheral circuits of the power circuit

1 When using all the built-in power supply


When using the quintuple-boosting (C: 12 units) When using the quadruple-boosting (C: 13 units)
(VDD = VDDI = 2.7 to 3.2 V)

CAP5+ CAP5+
+ VOUT + VOUT
C1 C1
VDD2 VDD2
+ CAP1+ + CAP1+
C1 C1
C1 CAP1– CAP1–
VDD + C1 +
+ CAP3+ + CAP3+ VDD
C1 C1
VSS
S1D15712 Series

S1D15712 Series
VSS
+ CAP4+ CAP4+
C1 +

y
CAP2– CAP2–
C1 C1 +
+ CAP2+ VDD2 CAP2+ VDD2
C1

r
VSS VSS

+ V3 + V3

a
+ V2 VDI + V2
C3 × 6 + V1 C3 × 6 + V1 VDI +
VSS C1
+ VC + VC VSS

in
+ MV1 + MV1
+ MV2 + MV2
MV3(VSS) MV3(VSS)

When using the triple-boosting (C: 12 units)

e il m When using the double-boosting (C: 11 units)

C1

C1
+

+
CAP5+
VOUT

P
VDD2

CAP1+
CAP1–
CAP3+
r VDD +
C1
C1

C1
+

+
CAP5+
VOUT
VDD2

CAP1+
CAP1–
CAP3+ VDD +
C1
S1D15712 Series

S1D15712 Series

VSS VSS

CAP4+ CAP4+
CAP2– CAP2–
C1 + +
+ CAP2+ VDD2 CAP2+ VDD2
C1 C1
VSS VSS

+ V3 + V3
+ V2 + V2
C3 × 6 + V1 VDI + C3 × 6 + V1 VDI +
C1 C1
+ VC VSS + VC VSS
+ MV1 + MV1
+ MV2 + MV2
MV3(VSS) MV3(VSS)

24 EPSON Rev. 1.2


S1D15712 Series

2 V3 adjusting circuit and LCDV circuit 3 LCDV circuit only


VOUT external input (C: 9 units) V3 external input (C: 8 units)

+ CAP5+ CAP5+
VOUT VOUT VOUT
C1 VDD2 VDD2

CAP1+ CAP1+
CAP1– CAP1–
CAP3+ VDD + CAP3+ VDD +
C1 C1
S1D15712 Series VSS VSS

S1D15712 Series
CAP4+ CAP4+
CAP2– CAP2–
CAP2+ VDD2 CAP2+ VDD2
VSS VSS
+
+ V3 V3 V3

y
+ V2 + V2 VDI +
C3 × 6 + V1 VDI + + V1 C1
C1

r
VSS C3 × 6 + VSS
+ VC VC
+ MV1 + MV1
+ MV2 + MV2

a
MV3(VSS) MV3(VSS)

4 External power supply only


External input (C: 2 unit)
in
5 Example of a connection of the smoothing capacitor
for the LC drive.

il m
For quintuple-boosting (C:12 pieces) (VDD = VDI =
2.7 to 3.2 V)

This connection can be also used for the circuits shown


in P.24 and P.25. See P24 and P25 for connections other

e
than that of the smoothing capacitor.

CAP5+
VOUT
VDD2

P
CAP1+
CAP1–
CAP3+ VDD
VSS
r +
C1
C2

C2
C2
+

+
CAP5+
VOUT
VDD2

CAP1+
CAP1–
CAP3+ VDD
VSS
+
C1
S1D15712 Series

S1D15712 Series

CAP4+ + CAP4+
C2
CAP2– CAP2–
C2
CAP2+ VDD2 + CAP2+ VDD2
VSS VSS
C3 × 6
V3 + V3
V2 + + V2
External VDI VDI
V1 C1 + V1
Power VSS VSS
VC + VC
Supply MV1 + MV1
MV2 + MV2
MV3(VSS) MV3(VSS)

Rev. 1.2 EPSON 25


S1D15712 Series

Examples of common reference settings


Item Settings Unit
C1 1.0 to 4.7 µF
C2 1.0 to 4.7
C3 0.47 to 1.0

Optimum values of C1, C2 and C3 above vary depending on the LCD panel to be driver. Above values should be referenced
as information only. It is recommended to check how patterns with hish-load are displayed before finalizins the values.
The optimum values for above-mentioned Cl, C2 and C3 vary according to the LCD panel to drive. Use the above-
mentioned values as references. Actually verify the display of a pattern with big load to make a decision.

6.6.4 Temperature gradient select circuit


This is a circuit to select the temperature gradient characteristics of the liquid crystal drive power supply voltage.
Temperature gradient characteristics can be selected from eight states by the Temperature Gradient command.
Selection of temperature gradient characteristics conforming to the temperature characteristics of the liquid crystal to
be used makes it possible to configure a system without providing an external element for temperature characteristics

y
compensation.

6.7 Thermal Sensor Circuit

a r
The S1D15712 Series IC has the built-in thermal sensor circuit equipped with the pin to output the analog voltage, which
represents the TBD V/˚C (Typ.) temperature gradient. The suitable tone LCD display is enabled in a wide temperature
range by inputting the electronic control resistor value sent from the MPU for the thermal sensor output value to control

in
the LCD drive voltage V3. To achieve higher precision LC drive voltage control, we recommend creating the system
that absorbs the variation of the output voltage by sending sampled output voltages at a certain temperature to the MPU
to receive and store the processed and returned voltage from the MPU as reference voltages.
If an excessive load is put on the S1D15712 Series IC (such as high-speed writing in the display RAM), the power
fluctuation in the IC may cause inaccurate outputs for temperature. Therefore, read the output from the thermal sensor

m
in the state that does not put the heavy load on the S1D15712 Series IC.

6.8 Reset circuit

1. Display : OFF

e l
The following shows the initially set state:
i
When the RES input becomes LOW, this LSI is set to the initialized state.

20. LCD bias set register : (D1, D0) = (0, 0)

r
2. Display : normal mode 21. Electronic volume register : (D6, D5, D4, D3, D2,
3. Display all lighting : OFF D1, D0) = (0, 0, 0, 0, 0, 0, 0)
4. Common output status : normal 22. Discharge : ON (only for when RES = LOW)

P
5. Display start line : Set to 1st line 23. Power save : ON
6. Page address : Set to 0 page 24. Temperature gradient resistor : (D2, D1, D0) = (0,
7. Column address : Set to 0 address 0, 0) (–0.06/°C)
8. Display data input direction : Column direction 25. Register data in the serial interface : Clear
9. Column address direction : forward 26. Thermal sensor OFF.
10. n-line a.c. reverse drive : OFF (reverse drive for 27. MLS drive selection register: (D3) = (0) (non-
each frame) distributed drive)
11. n-line reverse drive register : (D4, D3, D2, D1, D0)
= (0, 0, 0, 0, 0) When power is turned on, initialization by the RES pin
12. Display mode : 4 gray-scale display is necessary. After initialization by the RES pin, each
13. Gray-scale pattern register : (D7, D6, D5, D4, D3, input pin must be controlled correctly.
D2, D1, D0) = (*, 1, 0, 1, *, 0, 1, 0) Furthermore, when control signals from the MPU have
14. DUTY register : (D4, D3, D2, D1, D0) = (1, 0, 0, 1, a high impedance, the excessive current may flow to the
1) (1/81duty) IC.
Start spot (block) register : (D4, D3, D2, D1, D0) = After VDD is applied, measures should be taken to
(0, 0, 0, 0, 0) (COM0) ensure that the input pin does not have a high impedance.
15. Read modify write : OFF The S1D15712 Series discharges the electric charge of
16. Built-in oscillation circuit : stop VOUT and liquid crystal drive voltage (V3,V2, V1, VC,
17. Oscillation frequency register : (D3, D2, D1,D0) = MV1, MV2) at the level of RES pin = LOW. When
(0, 0, 0, 0) liquid crystal drive external power supply is used,
18. Power control register : (D2, D1, D0) = (0, 0, 0) external power supply should not be supplied during the
19. LCD drive voltage selection resister : (D2, D1, D0) period of RES = LOW to prevent external power supply
= (0,0,0) and VDD from being short circuited.

26 EPSON Rev. 1.2


S1D15712 Series

7. COMMAND
The S1D15712 Series identifies data bus signals by a combination of A0, RD(E) and WR(R/W). Interpretation and
execution of the command are executed by the internal timing alone which is independent of the external clock. This
allows high-speed processing.
The 80 series MPU interface allows the command to be started by entering the low pulse in the RD pin during reading
and by entering the low pulse in the WR pin during writing.
The 68 series MPU interface allows a read state to occur by entering HIGH in the R/W pin, and permits a write state
to occur by entering LOW. It also allows the command to be started by entering the high pulse in the pin E. (For timing,
see the description of “10. Timing characteristics”).

Accordingly, the 68 series MPU interface is different from 80 series MPU interface in that RD(E) is “1(H)” in the case
of display data/read shown in the Command Description and Command Table. The following describes the commands,
based on the example of the 80 series MPU interface:
When the serial interface is selected, enter data sequentially starting from D7.

Command Description

(1) Display ON/OFF


This command sets the display ON/OFF.

r y
a
E R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 Output level
0 1 0 1 0 1 0 1 1 1 0 Display OFF

in
1 Display ON

(2) Display Normal/Reverse

m
This command allows the display ON/OFF state to be reversed, without having to rewrite the contents of the display

i
data RAM. In this case, contents of the display data RAM are maintained.

A0
E
RD
R/W
WR D7 D6

e l
D5 D4 D3 D2 D1 D0 Setting

r
0 1 0 1 0 1 0 0 1 1 0 RAM data = HIGH
LCD ON Voltage
(normal)

P
1 RAM data = LOW
LCD ON Voltage
(reverse)

Rev. 1.2 EPSON 27


S1D15712 Series

(3) Display All Lighting ON/OFF


This command forces all the displays to be turned on independently of the contents of the display data RAM. In this
case, the contents of the display data RAM are maintained. Fully white display can also be made by a combination of
the Display Reverse command.

E R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 Setting
0 1 0 1 0 1 0 0 1 0 0 Normal display status
1 Display all lighting

(4) Common Output Status Select


This command allows the scanning direction of the COM output pin to be selected. For details, see the description of
“6.5.2 COM Drivers” in the Function Description.
E R/W

y
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 Selected state
COM0 → COM79 → COMS

r
0 1 0 1 1 0 0 0 1 0 0 Normal
1 Reverse COM79 → COM0 → COMS

(5) Display Start Line set

6.5 and 6.6.

in a
The parameter following this command specifies the display start line address of the display data RAM shown in Fig.

The display area is indicated in the direction where line address numbers are incremented, starting from the specified
line address. If a dynamic change of the line address is made by this command, smooth scrolling in the longitudinal
direction and page breaking are enabled. For details, see the description of “6.2.4 Line address circuit” in the Function

il m
Description.

E R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0

e
0 1 0 1 0 0 0 1 0 1 0 Mode setting

r
1 1 0 P7 P6 P5 P4 P3 P2 P1 P0 Register setting 1
(only binary display required)

28 EPSON Rev. 1.2


S1D15712 Series

• Display Start Line Set command parameter


(i) When the display mode is a 4 gray-scale mode:
The one-byte parameter is used to specify the address.
Line
P7 P6 P5 P4 P3 P2 P1 P0 address
0 0 0 0 0 0 0 0 00H
0 0 0 0 0 0 0 1 01H
↓ ↓
0 1 0 0 1 1 1 0 4EH
0 1 0 0 1 1 1 1 4FH
Set to the line address 00H at the time of resetting.

(ii) When the display mode is binary:


P7

0
P6

0
P5

0
P4

0
P3

0
P2

0
P1

r y P0
P8
0
Line
address
00H

0
0
0

0
0
0

0
0
0

0
0
0

in
0
0 a0 0

1
1
Set to line address 000H at the time of resetting.
0

1
1
1

0
1
01H

9EH
9FH

• Line address setting sequence

l i m
r e Set Line Address Mode

P
Set Line Address Register
Reset Line Address Mode
No
Change Completed?
Yes

Fig. 7.1

Rev. 1.2 EPSON 29


S1D15712 Series

(6) Page Address Set


This command specifies the page address corresponding to row address when MPU access to the display data RAM
shown in Fig. 6.5 and 6.6. For details, see the description of “6.2.3 Page address circuit” in the Function Description.

E R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 Page address
0 1 0 1 0 1 1 0 0 0 1 Command
1 1 0 * * * P4 P3 P2 P1 P0 Page address setting
*: denote invalid bits.
P4 P3 P2 P1 P0 Page address
0 0 0 0 0 Page 0
0 0 0 0 1 Page 1
↓ ↓
1 1 1 1 1 Page 18
0
1
0
0
0
1
0
0
0
0

r y
Page 19
Page 20

(7) Column Address Set

“6.2.3 Column address circuit” in the Function Description.

A0
E
RD
R/W
WR D7 D6 D5 D4 D3 D2
a
This command sets the display data RAM column address given in Fig. 6.5 and 6.6. For details, see the description of

in D1 D0

m
0 1 0 0 0 0 1 0 0 1 1
1 1 0 P7

P7
P6

P6

e
P5

l
P5i P4

P4
P3

P3
P2

P2
P1

P1
P0

P0
Column
address

r
0 0 0 0 0 0 0 0 00H
0 0 0 0 0 0 0 1 01H

P
0 0 0 0 0 0 1 0 02H
↓ ↓
1 1 1 1 1 1 1 0 FEH
1 1 1 1 1 1 1 1 FFH

(8) Display Data Write


This command allows the 8-bit data to be written to the address specified by the display data RAM. After writing,
column address or page address is automatically incremented +1 by the Display Data Input Direction Select command.
This enables the MPU to write the display data continuously.

E R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
0 1 0 0 0 0 1 1 1 0 1
1 1 0 Write Data

30 EPSON Rev. 1.2


S1D15712 Series

(9) Display Data Read


This command allows the 8-bit data to be read from the address specified by the display data RAM. After reading,
column address or page address is automatically incremented +1 by the Display Data Input Direction select command.
This enables the MPU to read multiple word data continuously.
It should be noted that one dummy reading is essential immediately after the column address or page address has been
set. For details, see the description of “6.1.5 Access to display data RAM and internal register” in the Function
Description. When the serial interface is used, display data cannot be read.

E R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
0 1 0 0 0 0 1 1 1 0 0
1 0 1 Read Data

(10) Display Data Input Direction Select


This command sets the direction where the display RAM address number is automatically incremented. For details,

y
see the description of “6.2.3 Column address circuit” in the Function Description.

A0
0
E
RD
1
R/W
WR
0
D7
1
D6
0
D5
0
D4
0
D3
0
D2
1

a
D1
0
D0
0
1 r
Direction
Column
Page

(11) Column Address Set Direction

in
This command can reverse the relationship between the display RAM data column address and segment driver output
shown in Fig. 6.5 and 6.6. So you can reverse the sequence of segment driver output pins using this command. When

m
the display data is written or read, the column address is incremented by (+1) according to the column address given

i
in Fig. 6.4 and 6.5. For details, see the description of “6.2.3 Column address circuit” in the Function Description.

A0
E
RD
R/W
WR D7 D6

e l
D5 D4 D3 D2 D1 D0 Setting

r
0 1 0 1 0 1 0 0 0 0 0 Normal
1 Reverse

WR
P
(12) n-line Inversion Drive Register Set
This command sets the liquid crystal alternating drive reverse line count in the register to start line reverse driving
operation. The line count to be set is 4 to 76 (19 states for each 4 lines. For details, see the description of “6.4 Display
timing generation circuit” in the Function Description.

A0
E
RD
R/W
D7 D6 D5 D4 D3 D2 D1 D0 Reverse line count
0 1 0 0 0 1 1 0 1 1 0 Command
1 1 0 * * * P4 P3 P2 P1 P0 Reverse line count
*: denote invalid bits.
P4 P3 P2 P1 P0 Reverse line count
0 0 0 0 0 4 (1 × 4)
0 0 0 0 1 8 (2 × 4)
↓ ↓
1 0 0 0 1 72 (18 × 4)
1 0 0 1 0 76 (19 × 4)

Rev. 1.2 EPSON 31


S1D15712 Series

(13) n-line ON/OFF


This command provides ON/OFF control of n-line inverting drive.

E R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 n-line
0 1 0 1 1 1 0 0 1 0 0 OFF
1 ON

(14) Display Mode


This command sets the display mode. 4 gray-scale and binary display each have a different RAM configuration.
For details, see the description of “6.2.1 Display Data RAM” in the Function Description.

E R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 Display mode
0 1 0 0 1 1 0 0 1 1 0 Command

y
1 1 0 * * * * * * P1 P0 Display mode

r
*: denote invalid bits.
P1 P0 Display mode

a
0 0 4gray-scale
0 1 Binary value

in
Set to 4 gray-scale (D1, D0) = (0, 0) at the time of resetting.

(15) Gray-scale Pattern Set

m
This command sets the level of gray-scale.

A0
0
1
E
RD
1
1
R/W
WR
0
0
D7
0
*
D6
0
P6

e l
D5
1
P5i D4
1
P4
D3
1
*
D2
0
P2
D1
0
P1
D0
1
P0
Gray-scale pattern
Command
Selection of

r
gray-scale level
* (P6, P5, P4) : Selects the level of gray-scale bit (1, 0)
* (P2, P1, P0) : Selects the level of gray-scale bit (0, 1)
Gray-scale bit (1, 0)

Gray-scale bit (0, 1)


P –


P6
0
0

P6
P5
0
1

P5
P4

0
1
0

P4


P2



P2
P1



P1
P0

P0
Level of gray-scale
White


Black

Level of gray-scale
– – – – – 0 0 1 White
– – – – – 0 1 0
↓ ↓
– – – – – 1 1 0 Black

32 EPSON Rev. 1.2


S1D15712 Series

(16) Duty Set Command


Liquid crystal drive at a lower power consumption is ensured by using this command to change the duty. Use of this
command also allows display at a desired position on the panel (continuous COM pins on a 4-line basis).
This command is used with a pair of the duty set parameter and start point (block) parameter, so be sure to set both
parameters so that one of them will immediately follow the other.

E R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 Selected state
0 1 0 0 1 1 0 1 1 0 1 Duty set command
1 1 0 * * * P14 P13 P12 P11 P10 Duty set
1 1 0 * * * P24 P23 P22 P21 P20 Start point set
*: denote invalid bits.

• Duty set
Duty can be set in the range from 1/5 duty to 1/81 duty by 4 steps.

y
Set to 1/81 duty after resetting.

r
P14 P13 P12 P11 P10 Duty set
0 0 0 0 0 1/5 duty set

a
0 0 0 0 1 1/9 duty set
↓ ↓

in
1 0 0 1 0 1/77 duty set
1 0 0 1 1 1/81 duty set

• Start point (block) register set parameter

il m
Use this parameter to set 5-bit data in the start point (block) register. Then one of 20 start point blocks will be determined.
* Use the Display Start Line Set command (6) for display scroll. Do not use this command for display scroll.

P24 P23 P22 P21 P20 Start piont setting

e
0 0 0 0 0 0 (COM0 to 3)

r
0 0 0 0 1 1 (COM4 to 7)
0 0 0 1 0 2 (COM8 to 11)
↓ ↓

P
1 0 0 1 0 18 (COM72 to 75)
1 0 0 1 1 19 (COM76 to 79)
Set to 0 block (D7 to D0: ***00000) at the time of resetting

* Voltage optimum to liquid crystal drive is changed when the duty is changed. Use the electronic volume and set the
voltage to get the optimum display.

• Duty command setup example


1. Duty 1/49 When 1 (COM4 to COM7) is specified as the start point (block)
Display area COM4 to COM51, COMS
2. Duty 1/65 When 16 (COM64 to COM67) is specified as the start point (block)
Display area COM64 to COM79 and COM0 to COM47, COMS

* If the COM pin is not shared by the master and slave in the master/slave 2-chip operation (for vertical drive such as
SEG256, COM81+COM81), the same duty must be used on the master and slave.

Rev. 1.2 EPSON 33


S1D15712 Series

(17) Read Modify Write


This command is paired with end command for use. If this command is entered, the column address is not changed by
the Display Data Read command. It can be incremented +1 by the Display Data Read command alone. This state s
retained until the End command is input. If the End command is input, the column address goes back to the address
when the Read Modify Write command is input. This function reduces the MPU loads when changing the data repeated
in the specific display area such as blinking cursor.

E R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
0 1 0 1 1 1 0 0 0 0 0

* A command other than display data Read/Write command can be used in the Read Modify Write mode. However,
you cannot use the column address set command.

• Sequence for cursor display

Page Address Set

r y
Column Address Set

Read Modify Write

in a
il m
Dummy Read

Data Read
Data Manipulation

e
Data Write

r
No
Change Completed?
Yes

P
End

Fig. 7.2

34 EPSON Rev. 1.2


S1D15712 Series

(18) End
This command releases the read modify write mode and gets column address back to the initial address of the mode.

E R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
0 1 0 1 1 1 0 1 1 1 0

Return

Column address N N+1 N+2 N+3 ••• N+m N

Set read-modify-write mode End

Fig. 7.3

y
(19) Built-in Oscillator Circuit ON/OFF

r
This command starts the built-in oscillator circuit operation. It is enabled only in the master operation mode (M/S =
HIGH) when built-in oscillator circuit is valid (CLS = HIGH).
When the built-in power supply is used, the Oscillator Circuit ON command must be executed before the Power Control

a
Set command. (See the description of “(21) power control command”). If the built-in oscillator circuit is turned off
when the built-in power supply is used, display failure may occur.

in
E R/W Built-in oscillator
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 circuit
0 1 0 1 0 1 0 1 0 1 0 OFF
1 ON

l i m
r e
P

Rev. 1.2 EPSON 35


S1D15712 Series

(20) Built-in Oscillator Circuit Frequency Select


This command sets the built-in oscillator circuit frequency. The frequency can be selected whether the built-in oscillator
circuit is turned on or off.
E R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 fOSC kHz fCL kHz
0 1 0 0 1 0 1 1 1 1 1 Command Command
1 1 0 * * * * P3 P2 P1 P0 Oscillation CL frequency
frequency

Oscillation frequency fOSC kHz CL frequency


P3 P2 P1 P0 1/81 Duty 1/65 Duty 1/49 Duty 1/33 Duty fCL kHz
0 0 0 0 198 245 321 463 400
0 0 0 1 164 202 265 382 330
0 0 1 0 144 178 232 335 290

y
0 0 1 1 127 156 204 295 255

r
0 1 0 0 117 144 189 273 236
0 1 0 1 105 130 170 246 213

a
0 1 1 0 97 120 156 226 195
0 1 1 1 90 111 145 209 181

in
1 0 0 0 86 106 138 200 173
1 0 0 1 79 98 128 185 160
1 0 1 0 75 93 122 176 152
1 0 1 1 70 87 114 164 142

m
1 1 0 0 68 84 109 158 136

i
1 1 0 1 64 79 103 149 129
1
1
1
1
1
1
0
1
61
58

e l 76
72
99
94
143
136
124
117
(D7 to D0: ****0000) is set after resetting.

P r
* The above-mentioned value is a Typ. value at 25°C. There is a tolerance of ±8% at 25°C.
Values for fFR represent the frame frequency, not the fFR signal frequency.

36 EPSON Rev. 1.2


S1D15712 Series

(21) Power Control Set


This command sets the built-in power supply circuit function. For details, see the description of “6.6 Power supply
circuit” in the Function Description.

E R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 Selected state
0 1 0 0 0 1 0 0 1 0 1 Command
1 1 0 0 0 0 0 0 P2 P1 P0 Register set

P2 P1 P0
Selected state
0 Step-up: OFF
1 Step-up: ON
0 VC: OFF
1 VC: ON
0 LCD voltage: OFF

y
1 LCD voltage: ON

r
LCD voltage: V3, V2, V1, MV1, MV2

in a
An internal clock is required to operate the built-in power supply circuit. During the operation of the built-in power
supply circuit, be sure that the internal clock is present inside.
If the built-in oscillator circuit is used, execute the built-in oscillator circuit ON command before the power control

m
set command. If an external oscillator circuit is used, operate the external oscillator circuit before the power control

i
set command.

l
If the internal clock is cut off during the operation of the built-in power supply circuit, display failure may occur. To
avoid this, do not cut it off.
In the slave operation mode, only the parameters (D7 to D0 : *****000) can be used with the power control set

e
command. Do not use any other parameter.

P r Built-in oscillator ON

Power Control Set


External oscillator input

A built-in oscillator used An external oscillator used

Fig. 7.4

Rev. 1.2 EPSON 37


S1D15712 Series

(22) Liquid Crystal Drive Voltage Select


The liquid crystal drive voltage range issued from the liquid crystal drive voltage regulating circuit is selected from 3
states by this command. V3 voltage output ranges are Typ. values at 25˚C.

E R/W V3 voltage
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 output range
0 1 0 0 0 1 0 1 0 1 1 Command
1 1 0 * * * * * P2 P1 P0 Register
*: denote invalid bits.

V3 voltage
P2 P1 P0 output range
0 0 0 5.6 to 7.0V
0 0 1 6.3 to 7.8V
0 1 0 7.1 to 8.9V

y
0 1 1 8.0 to 10.0V

r
1 0 0 9.2 to 11.4V
1 0 1 10.3 to 12.8V

a
1 1 0 11.7 to 14.5V
1 1 1 12.8 to 16.0V

in
(D2, D1, D0)=(0, 0, 0) is set after performing reset.

l i m
r e
P

38 EPSON Rev. 1.2


S1D15712 Series

(23) LCD Bias Set


With this command, the bias ratio of voltage required for a liquid crystal drive is chosen.
E R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 Bias ratio
0 1 0 1 0 1 0 0 0 1 0 Command
1 1 0 0 0 0 0 0 0 P1 P0 Register set

P1 P0 Bias ratio
0 0 1/8
0 1 1/6.7
1 0 1/5.3
(D1, D0) = (0, 0) are set up after reset.

(24) Electronic Volume

r y
This command controls liquid crystal drive voltage V3 issued from the built-in liquid crystal power supply voltage
regulating circuit, and adjusts the liquid crystal display density. For details, see the description of “6.6.2 Voltage

a
Regulating Circuit” in the Function Description.

in
E R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
0 1 0 1 0 0 0 0 0 0 1 Command
1 1 0 * P6 P5 P4 P3 P2 P1 P0 Register

m
*: denote invalid bits.

• Electronic Volume Register Set

l i
When a 7-bit data to the electronic volume register is set by this command, liquid crystal drive voltage V3 assumes one

e
state out of voltage values in 128 states.
After this command is input, and the electronic volume register is set, the electronic volume mode is reset.

P r P6
0
0
0

1
P5
0
0
0

1
P4
0
0
0

1

P3
0
0
0

1
P2
0
0
0

1
P1
0
0
1

1
P0
0
1
0

0
VC
Smaller

1 1 1 1 1 1 1 Larger
*: denote invalid bits.

• Electronic volume register set sequence

Set Electronic Volume Mode

Set Electronic Volume Register


Reset Electronic Volume Mode
No
Change Completed?
Yes

Fig. 7.5

Rev. 1.2 EPSON 39


S1D15712 Series

(25) Discharge ON/OFF


This command discharges the capacitors connected to the power supply circuit. This command is used when the system
power of this IC (S1D15712 Series) is turned off, and the duty is changed. See the description of (3) Power Supply OFF
and (4) Changing the Duty in the Instruction Setup: Reference.

E R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 Setting
0 1 0 1 1 1 0 1 0 1 0 Discharge OFF
1 Discharge ON

* If this command is executed when the external power supply is used, a large current may flow to damage the IC. If
external power supply is used to drive liquid crystal, be sure to turn off the external power supply before executing
this command.

(26) Power Saving


This command establishes the power save mode, thereby ensuring a substantial reduction of current consumption.

A0
E
RD
R/W
WR D7 D6 D5 D4 D3 D2 D1 D0

r y
Power save mode

a
0 1 0 1 0 1 0 1 0 0 0 OFF
1 ON

in
In the power save mode, display data and operation before power saving are maintained. Access to the display data
RAM from the MPU is also possible. The current consumption is reduced to the value close to static current if all
operations of the LCD display system are stopped and there is no access from the MPU.

m
In the power save mode, the following occurs:

i
Stop of oscillator circuit

l
Stop of LCD power supply circuit
Stop of all liquid crystal drive circuit (VSS level output is issued as the segment and common driver output).

e
The power save OFF command releases the power save mode. The system goes back to the state before the power save

r
mode.

* When the external power supply is used, it is recommended to stop the external power supply circuit function when

P
the power save mode is started. For example, when each level of the liquid crystal drive voltage is given from the
external resistive divider circuit, it is recommended to add a circuit to cut off the current flowing to the resistive
divider circuit when power save function is started. The S1D15712 Series has a liquid crystal display blanking
control control pin DOF, and the level goes LOW when power save function is started. You can use the DOF output
to stop the external power supply circuit function.

40 EPSON Rev. 1.2


S1D15712 Series

(27) Temperature Gradient Set


The 3-bit data of this command is used to set the temperature gradient characteristics of the liquid crystal drive voltage
output from the built-in power supply circuit from eight states to one state. The temperature gradient of the liquid crystal
drive voltage can be set according to the liquid crystal temperature gradient to be used. This eliminates the need of a
temperature characteristics regulating circuit to be installed outside this IC (S1D15712 Series).

E R/W Temperature
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 gradient [%/°C]
0 1 0 0 1 0 0 1 1 1 0 Command
1 1 0 * * * * * P2 P1 P0 Register
*: denote invalid bits.

Temperature
P2 P1 P0 gradient [%/°C]
0 0 0 –0.06

y
0 0 1 –0.08

r
0 1 0 –0.10
0 1 1 –0.11

a
1 0 0 –0.13
1 0 1 –0.15

in
1 1 0 –0.17
1 1 1 –0.18
(D7 to D0: *****000) is set after resetting. *: denote invalid bits.

(28) Status Read

l i m
This command reads out the temperature gradient select bit set on the register.

e
E R/W Temperature
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 gradient [%/°C]
0
1
1
0
0
1

P r 1
*
0
*
0
*
0
*
1
*
1
P2

P2
1
P1

P1
0
P0

P0
Command
Register
*: denote invalid bits.

Temperature
gradient [%/°C]
0 0 0 –0.06
0 0 1 –0.08
0 1 0 –0.10
0 1 1 –0.11
1 0 0 –0.13
1 0 1 –0.15
1 1 0 –0.17
1 1 1 –0.18

Rev. 1.2 EPSON 41


S1D15712 Series

(29) Thermal sensor ON/OFF


The ON/OFF of the thermal sensor is set by this command.

E R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 Setting
0 1 0 0 1 1 0 1 0 0 0 Thermal sensor OFF
1 Thermal sensor ON
The thermal sensor is set to OFF after performing reset.

When the built-in thermal sensor is used, this command is used to set the thermal sensor to ON. The thermal sensor
setting to ON when it is not used, has no problem except for occurrence of approximately 10 µA current consumption.

(30) MLS drive selection


This is the command for the MLS drive selection. It switches between the distributed drive and the non-distributed
drive.

y
E R/W

r
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 MLS drive
0 1 0 1 1 1 0 0 1 1 1 Command

a
1 1 0 * * * 0 M3 0 1 1 Register
* represents an invalid bit.

in
M4 M3 M2 M1 M0 MLS drive
0 0 0 1 1 Distributed drive
1 Non-distributed drive
The non-distributed drive is selected after performing reset.

l i m
The distributed drive and non-distributed drive are the liquid crystal drive method unique to the MLS drive.
The S1D15712 Series ICs perform the 4-line MLS drive, that outputs the selected voltage for the period as much as four
times of the period (for 81-line display, 4/(81+3) of 1 frame) used for one line display in the normal display (for 81-

e
line display, 1/81 of 1 frame).
In the non-distributed drive, the selected signals for 4 lines are output 4 times consecutively. This drive method is

r
recommended for displays that are changed frequently.
In the distributed drive, the selected signals are output 4 times during the Gamma frame period. In this drive method,
the frame frequency can be decreased. This drive method is recommended when the current consumption should be

P
reduced. This method is not suitable to display moving pictures because the moving picture may blink in this method.
Select the drive type after checking the actual display.

(31) NOP
This is a Non-Operation command.

E R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
0 1 0 1 1 1 0 0 0 1 1

Note: S1D15712 Series maintains the operation status due to the command. However, when exposed to excessive
external noise, internal status may be changed. This makes it necessary to take some measures which reduces
noise generation in terms of installation or system configuration, or which protects the system against adverse
effect of noise. To cope with sudden noise, it is recommended to refresh the operation status on a periodic basis.

42 EPSON Rev. 1.2


S1D15712 Series

Table 7.1 Table of commands in SED15E0 series


Command code
Command A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 Function
(1) Display ON/OFF 0 1 0 1 0 1 0 1 1 1 0 LCD display ON/OFF control.
1 0: OFF, 1: ON
(2) Display Normal 0 1 0 1 0 1 0 0 1 1 0 LCD display normal/reverse
/Reverse 1 0: Normal, 1: Reverse
(3) Display All Lighting 0 1 0 1 0 1 0 0 1 0 0 Display All Lighting
ON/OFF 1 0: Normal display, 1: All ON
(4) Common Output 0 1 0 1 1 0 0 0 1 0 0 Selects COM output scan direction.
Status Select 1 0: Normal, 1: Reverse
(5) Display Start Line Set 0 1 0 1 0 0 0 1 0 1 0 Sets display start line.
1 1 0 Display start line address
(6) Page Address Set 0 1 0 1 0 1 1 0 0 0 1 Sets the display RAM page address.
* * Page address
(7) Column Address Set 0 1 0 0 0 0 1 0 0 1 1 Sets the display RAM column
1 1 0 Column Address Set address.

y
(8) Display Data Write 0 1 0 0 0 0 1 1 1 0 1 Writes data to the display RAM.

r
1 1 0 Writes data
(9) Display Data Read 0 1 0 0 0 0 1 1 1 0 0 Reads data to the display RAM.
1 0 1 Reads data

a
(10) Display Data Input 0 1 0 1 0 0 0 0 1 0 0 Display RAM data input direction
Direction Select 1 0: Column direction 1: Page direction
(11) Column Address Set 0 1 0 1 0 1 0 0 0 0 0 Compatible with display RAM

in
Direction 1 address SEG output
0: Normal 1: Reverse
(12) n-line inversion Drive 0 1 0 0 0 1 1 0 1 1 0 Line invert drive.
Register Set 1 1 0 * * * Invert line count Sets the line count.
(13) n-line ON/OFF 0 1 0 1 1 1 0 0 1 0 0 Resets the line invert drive.

m
0: n-line OFF 1: n-line ON

i
(14) Display Mode 0 1 0 0 1 1 0 0 1 1 0 00: 4 gray-scale, 01: binary

l
1 1 0 * * * * * * Mode
(15) Gray-scale Pattern Set 0 1 0 0 0 1 1 1 0 0 1 Selects the contrast of gray-scale
1 1 0 Gray-scale pattern bit (1,0) (0,1).

e
(16) Duty Set Command 0 1 0 0 1 1 0 1 1 0 1
Duty Set

r
* * Duty count
Static spot (block) set * * Static spot (block)
(17) Read Modify Write 0 1 0 1 1 1 0 0 0 0 0 Increments the column address.
Increments +1 in the write mode.

P
Does not increment in the read mode.
(18) End 0 1 0 1 1 1 0 1 1 1 0 Resets read modify write functions.
(19) Built-in Oscillator 0 1 0 1 0 1 0 1 0 1 0 Built-in oscillator circuit operation
Circuit ON/OFF 1 0: OFF, 1: ON
(20) Built-in Oscillator 0 1 0 0 1 0 1 1 1 1 1
Circuit Frequency Select 1 1 0 * * * * Frequency
(21) Power Control Set 0 1 0 0 0 1 0 0 1 0 1 Selects built-in power supply
1 1 0 * * * * * Operation state operation state.
(22) Liquid Crystal Drive 0 1 0 0 0 1 0 1 0 1 1
Voltage Select 1 1 0 * * * * * * V3 range
(23) LCD bias set 0 1 0 1 0 1 0 0 0 1 0 Bias ratio select
1 1 0 * * * * * * bias
(24) Electronic Volume 0 1 0 1 0 0 0 0 0 0 1
Mode Set
Electronic Volume 1 1 0 * Electronic volume V3 output voltage is set to the
Register Set electronic volume register. 128 states
(25) Discharge ON/OFF 0 1 0 1 1 1 0 1 0 1 0 Discharges Power supply circuit
1 connection capacitor.
0: OFF (normal), 1: ON
(26) Power Save ON/OFF 0 1 0 1 0 1 0 1 0 0 0 Power Save 0: OFF, 1: ON
1
(27) Temperature 0 1 0 0 1 0 0 1 1 1 0 Sets to 8 steps.
Gradient Select 1 1 0 * * * * * Temperature gradient

Rev. 1.2 EPSON 43


S1D15712 Series

Command code
Command A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 Function
(28) Stator Read 0 1 0 1 0 0 0 1 1 1 0 Issues the temperature gradient
1 0 1 * * * * *Temperature gradient select bit.
(29) Thermal sensor 0 1 0 0 1 1 0 1 0 0 0 Thermal sensor
ON/OFF 1 0: OFF (normal), 1: ON
(30) MLS drive selection 0 1 0 1 1 1 0 0 1 1 1 MLS drive selection
1 1 0 * * * 0 MLS 0 1 1 * represents an invalid bit.
(31) NOP 0 1 0 1 1 1 0 0 0 1 1 Non-operation command

r y
in a
l i m
r e
P

44 EPSON Rev. 1.2


S1D15712 Series

Instruction Setup Example (Reference)


(1) Initial setup

VDD - VSS, VDD2 - VSS power turns on when RES terminal = LOW.

Stable power supply

Release the reset state. (RES terminal = HIGH) *1

Function setup by command entry (set by users)


(11) Column address set direction
(4) Common output status select
(2) Display normal/reverse
(3) Display all lighting ON/OFF
(14) Display mode set
(16) Set the duty

y
(22) LCD voltage select

r
(24) Electronic volume
(27) Temperature gradient set

(When the n-line invert drive is not used)

a
Function setup by command entry (set by users)
(12) n-line invert drive register set

in
(13) n-line ON/OFF

(When the external oscillator circuit is used)


Function setup by command entry (set by users)
(20) Built-in oscillator circuit frequency select Enter the external clock

il m
(19) Built-in oscillator circuit ON/OFF

(When the external LCD power supply circuit is used)


Function setup by command entry (set by users)
External LCD power supply entry
(23) LCD bias set

e
(21) Power control set

P r Initialization completed

Note: *1 DDRAM contents are not determined even in the initialized state after resetting. See “6.7 Reset Circuit”
in the “6. Function Description”.
* Numerals in the command parenthesis correspond to the numerals of the items in Command Description.

Rev. 1.2 EPSON 45


S1D15712 Series

(2) Data display


End of initialization

Function setup by command entry (set by users)


(5) Display start line set
(10) Display data input direction select
(6) Page address set
(7) Column address set

Function setup by command entry (set by users)


(8) Display data write

Function setup by command entry (set by users)


(1) Display ON/OFF command

y
End of data display

r
Note: * DDRAM contents are not determined after end of initialization. Write data to all the DDRAM used for
display. See “9. Display data write” in the “7. Command Description”.

(3) Power OFF

A desired state

in a
m
Function setup by command entry (set by users)

i
(26) Power save ON

l
(When an external LCD power supply circuit is used)

External LCD power supply OFF

e
(When the built-in power supply circuit is used)
Function setup by command entry (set by users)

r
(25) Discharge ON

P
Reset state (RES terminal = LOW)

Set the time (tL) between entry into the reset state and turning off of
VDD, VDD2 -VSS power supply liquid crystal drive potential
(MV1,VC,V1,V2) so that it is longer than the time (tH) where it is reduced
below the threshold value of the LCD panel.

VDD2 - VSS, VDD - VSS power supply OFF

Note: * This IC controls the circuit of the liquid crystal drive power supply system using the VDD, VDD2–VSS power
supply circuit. If the VDD, VDD2–VSS power supply is cut off with voltage remaining in the liquid crystal
drive power supply system, voltage not controlled will be issued from the SEG and COM pins, and this may
result in display failure. To avoid this, follow the above-mentioned power off sequence.

46 EPSON Rev. 1.2


S1D15712 Series

(4) How to change the duty

A desired state

Function setup by command entry (set by users)


(1) Displya OFF

Function setup by command entry (set by users)


(26) Power save ON

Function setup by command entry (set by users)


(25) Discharge ON

y
Function setup by command entry (set by users)

r
(24) Electronic volume
(20) Built-in oscillator circuit frequency select Secure an interval of

a
(16) Duty set 30ms or more between
When the n-line reversing command is used : discharge ON to
discharge OFF .

in
(12) n-line reverse drive register set

Function setup by command entry (set by users)

m
(25) Discharge OFF

l i
Function setup by command entry (set by users)
(26) Power save OFF

e
Note:

P r End of duty change

* Execution of the above sequence causes display to be turned off temporarily (for the time from Power
Saving command ON to Power Saving command OFF plus 200 ms (frame frequency 60Hz) upon switching
of the duty. Temporary display failure may occur if Duty Change command is executed during liquid
crystal display without executing the above-mentioned setup example. Follow the setup example when the
duty is changed as discussed above.

(5) Refresh
It is recommended that the operating modes and display contents be refreshed periodically to prevent the effect of
unexpected noise.

A desired state

Set all commands to the ready state


(Including default state setting.)

Refreshing of DRAM

Rev. 1.2 EPSON 47


S1D15712 Series

8. ABSOLUTE MAXIMUM RATINGS


Table 8.1 VSS = 0V unless otherwise specified.
Item Symbol Specified value Unit
Power voltage (1) VDD –0.3 to +6.0 V
Power voltage (2) VDD2 –0.3 to +6.0
Power voltage (3)(requires external input) VDI –0.3 to +3.6
Power voltage (4) V3, VOUT –0.3 to +18.0
Power voltage (5) V 2, V1, V C, –0.3 to V3
MV1, MV2
Input voltage VIN –0.3 to VDD+0.3
Output voltage VO –0.3 to VDD+0.3
Operating temperature TOPR –40 to +85 °C
Storage temperature bare chip TSTR –55 to +125

VOUT

r y
a
V3

in
VDD2
V2, V1, VC, MV1, MV2
VCC VDD

GND VSS

System (MPU) side

l i m S1D15712 side

Fig. 8.1

r e
Notes: 1. VoltagesV 3 , V 2 , V 1 , V C , MV 1 and MV 2 (V SS ) must always meet the conditions of
V3≥V2≥V1≥VC≥MV1≥MV2 (VSS).
2. Voltage VOUT must always meet the conditions of VOUT≥VDD2 and VOUT≥VC.

P
3. If the LSI has been used in excess of the absolute maximum rating, it may be subjected to permanent
breakdown. So in the normal operation, the LSI is preferred to be used under the condition of electrical
characteristics. If this condition is not met, LSI operation error may occur and LSI reliability may be
deteriorated.

48 EPSON Rev. 1.2


S1D15712 Series

9. DC CHARACTERISTICS
VSS = 0V, VDD = 5.0 V ± 10% and Ta = –40 to +85°C unless otherwise specified.

Table 9.1
Specified value Applicable
Item Symbol Conditions Min. Typ. Max. Unit pin
Operating voltage (1) Operation enabled VDD — 2.7 — 5.5 V VDD *1
Operating voltage (2) Operation enabled VDD2 — VDD — 5.5 VDD2
Operating voltage (3) Operation recommended VDI requires external input 2.7 — 3.3 VOUT
Operating voltage (4) Operation enabled VOUT — VDD2 — 16.2 VOUT
Operating voltage (5) Operation enabled V3 — 5.6 — 16.2 V3 *2
High-level input voltage VIHC VDD=2.7V to 5.5V 0.8×VDD — VDD *3
Low-level input voltage VILC VSS — 0.2×VDD *3
High-level output voltage VOHC VDD=2.7V IOH=–0.25µA 0.8×VDD — VDD *4

y
Low-level output voltage VOLC to 5.5V IOL=0.25µA VSS — 0.2×VDD *4

r
Input leak current ILI VIN=VDD or VSS –1.0 — 1.0 µA *5
Output leak current ILO –3.0 — 3.0 *6

a
LCD driver ON resistance RON Ta=25°C V3=7.2V — 10 20 kΩ SEGn
V3=14.0V — 5 10 COMn *7
µA

in
Static current consumption IDDQ Ta=25°C VDD=3.0V — 0.3 5 VDD *8
I3Q V3=16.0V — 5 20 V3
Input pin capacity CIN Ta=25°C, f=1MHz — 8 16 pF —
Oscillation Built-in oscillation fOSC Ta=25°C 368 400 432 kHz *9
frequency Max. frequency

[Asterisked references]
*1.

l i m
Does not guarantee if there is an abrupt voltage variation during MPU access.

e
*2. For VDD2 and V3 system operating voltage range, see Fig. 9.6.
Applicable when the external power supply is used.

r
*3. A0, D0 to D5, D6(SCL), D7(SI), RD(E), WR(R/W), CS, CLS, CL, FR, F1, F2, SYNC, M/S, C86, P/S, DOF, RES,
TEST and TEST1 pins
*4. D0 to D7, FR, DOF, CL, F1, F2 and SYNC pins

P
*5. A0, RD(E), WR(R/W), CS, CLS, M/S, C86, P/S, RES, TEST and TEST 1 pins
*6. Applicable when D0 to D5, D6(SCL), D7(S1), CL, FR, DOF, F1, F2 and SYNC pins have a high impedance.
*7. Indicates the resistance when 0.1V voltage is applied between the output pin SEGn or COMn and each power
supply (V2, V1, VC, MV1, MV2).
RON =0.1V/∆I (where ∆I denotes current when 0.1V is applied when power is on).
*8. Current values when TEST1 = LOW.
*9. For the relationship between oscillation frequency and frame frequency, see Table 9.9. The standard values of
the external input item are recommended ones.

Rev. 1.2 EPSON 49


S1D15712 Series

Table 9.2
Specified value Applicable
Item Symbol Conditions Min. Typ. Max. Unit pin
Input voltage VDD2 When making doubleamplification 2.7 — 5.5 V VDD2
Built-in power circuit

VDD2 When making triple amplification 2.7 — 5.3


VDD2 When making quadruple amplification 2.7 — 4.0
VDD2 When making quintuple amplification 2.7 — 3.2
Amplified output VOUT — — — 16.2 VOUT
voltage
Voltage adjusting V3 — 5.6 — 16.2 V3 *10
circuit operating
voltage

y
Dynamic current consumption value (1)

r
While the indication operation is in progress and when the built-in power supply is being turned on:
The current value being consumed by the whole IC including the built-in power supply.

a
Indication mode: 4 gradations, fFR = 144Hz, VDD = VDD2, No line reversion, 1/8 bias

Table 9.3 Indications: All white indications *12

in
Symbol: ISS(1)
1/81 Duty 1/65 Duty
VDD Boosting V3 voltage Typ. Min. Typ. Min. Unit Remark
5V Triple 14V 215 358 191 318 µA *11

m
10V 210 350 187 312
3V Quintuple
Quadruple
14V
10V

e l i 236
177
393
295
210
158
350
263

r
Table 9.4 Indications: Heavy load indications *13
Symbol: ISS(1)

P
1/81 Duty 1/65 Duty
VDD Boosting V3 voltage Typ. Min. Typ. Min. Unit Remark
5V Triple 14V 400 666 345 575 µA *11
10V 306 510 270 450
3V Quintuple 14V 875 1458 691 1151
Quadruple 10V 329 548 284 473

[* marked section: Refer to page 51.]

50 EPSON Rev. 1.2


S1D15712 Series

Display mode in binary at fFR = (75Hz), VDD = VDD2, No line reversion, 1/8 bias

Table 9.5 Display: entirely in white *12 Code: ISS(1)


1/81 Duty 1/65 Duty
VDD Boosting V2 Voltage Unit Remarks
Typ. Max. Typ. Max.
5V Triple 14V 168 280 154 257 µA *11
10V 163 272 150 250
3V Quintuple 14V 166 277 151 252
Quadruple 10V 137 228 127 212

Table 9.6 Display: Heavy load display *13 Code: ISS(1)


1/81 Duty 1/65 Duty
VDD Boosting V2 Voltage Unit Remarks
Typ. Max. Typ. Max.

y
5V Triple 14V 276 460 343 405 µA *11

r
10V 227 378 201 335
3V Quintuple 14V 464 773 380 633

a
Quadruple 10V 215 358 188 313

in
Current consumption under power saving mode (1): VSS = 0V, VDD = 5.0 V, TEST1 = HIGH, Ta = 25°C

Table 9.7
Specified value

m
Item Symbol Condition Unit Remarks
Min. Typ. Max.

i
Sleep state IDDS1 — — 15.0 30.0 µA —

e l
Current consumption under power saving mode (2): VSS = 0V, VDD = VDI = 3.0 V, TEST1 = LOW, Ta = 25°C

r
Table 9.8
Specified value
Item Symbol Condition Unit Remarks

P
Min. Typ. Max.
Sleep state IDD2 — — 0.3 5.0 µA —

[Asterisked references]
*10. The V3 voltage regulating circuit should be adjusted within the electronic volume operation range.
*11. Indicates the current consumed by a single IC when display is on. Use the electronic volume for voltage
regulation. Also use the internal oscillator circuit. The current due to LCD panel capacity and wiring capacity
is not included. Applicable when there is access from the MPU.
*12. ALL WHITE occurs when the normally white LCD panel is used. ALL BLACK occurs when the normally black
LCD panel is used.
*13. Heavy load indicates the load where the maximum current is consumed as a display pattern.

Rev. 1.2 EPSON 51


S1D15712 Series

[Reference Data 1]
• Dynamic current consumption during displaying the LCD using the built-in power supply
VDD = VDD2 = 3.0 V, fFR = 144Hz, Built-in oscillator circuit, 4 gray-scale display, 1/8 bias

1000

3V, quintuple-boosting,
V3 =14 V, heavy load
[µA]

3V, quadruple-boosting,
V3 =10 V, heavy load
500

3V, quintuple-boosting,
IDD

V3 =14 V, white display

r y
3V, quadruple-boosting,

a
0 V3 =10 V, white display
33 65 81

in
1/DUTY

Fig. 9.1

il m
VDD = VDD2 = 5.0 V, fFR = 144Hz, Built-in oscillator circuit, 4 gray-scale display, 1/8 bias

500

5V, triple-boosting,

e
V3 =14 V, heavy load

r
[µA]

5V, triple-boosting,
V3 =10 V, heavy load

250

P 5V, triple-boosting,
V3 =14 V, white display

5V, triple-boosting,
IDD

V3 =10 V, white display

0
33 65 81

1/DUTY

Fig. 9.2

52 EPSON Rev. 1.2


S1D15712 Series

[Reference Data 2]
• Dynamic current consumption during displaying the LCD using the built-in power supply
VDD = VDD2 = 3.0 V, fFR = 75Hz, Built-in oscillator circuit, binary display, 1/8 bias

500

3V, quintuple-boosting,
V3 =14 V, heavy load
[µA]

3V, quadruple-boosting,
V3 =10 V, heavy load
250
3V, quintuple-boosting,
V3 =14 V, white display
IDD

r y
3V, quadruple-boosting,
V3 =10 V, white display

a
0
65 81

in
1/DUTY

Fig. 9.3

m
VDD = VDD2 = 3.0 V, fFR = 75Hz, Built-in oscillator circuit, binary display, 1/8 bias

500

e l i
r
[µA]

5V, triple-boosting,
V3 = 14 V, heavy load

P
5V, triple-boosting,
250
V3 = 10 V, heavy load

5V, triple-boosting,
V3 = 14 V, white display
IDD

5V, triple-boosting,
V3 = 10 V, white display

0
65 81

1/DUTY

Fig. 9.4

Rev. 1.2 EPSON 53


S1D15712 Series

[Reference Data 3]
• Dynamic current consumption (3)-2 during access

10
Fig. 9.5 shows the current
consumption duringwriting
the checker patterns constantly
at fCYC.
[mA]

When access is not done,


ISS (1) only is consumed.

Condition: VDD=VDD2=5.0 V,
1
triple-boosting, V3=14V
IDD

0.1

r y
0.001 0.01
fCYC
0.1
[MHz]
1

Fig. 9.5
2

in a
m
[Reference Data 4]

i
• Operating voltage range for the VDD2 series and the V3 series

20.0

e l
r
16.0
15.0

P
[V]

10.0
V3

5.6
5.0

2.7 5.5
0
0 2 4 6 8
VDD2 [V]
Fig. 9.6

54 EPSON Rev. 1.2


S1D15712 Series

• Relationship between oscillation frequency fOSC, display clock frequency fCL and liquid crystal frame fFR

Table 9.9
Item fCL fFR
Built-in oscillator See p.36 fCL / {(n+3) × 24}
circuit used
Built-in oscillator circuit External input (fCL) fCL / {(n+3) × 24}
not used

(fFR indicates the cycle of rewriting one screen; it does not indicate FR signal cycle.)

Thermal sensor characteristics (under development)


Item Symbol Condition Standard value Unit Applicable pin
Min. Typ. Max.
Output voltage VSVD2 –35˚C TBD 1.475 TBD V SVD2

y
25˚C TBD 1.200 TBD

r
80˚C TBD 0.935 TBD
Output voltage VGRA TBD TBD –4.70 TBD mV/˚C SVD2
temperature gradient
Output voltage linearity
Output voltage set up time
Operating current
∆VL
tSEN
ISEN
TBD
25˚C
25˚C
–1.5
TBD


in
TBD
a 1.5

TBD
%
mS
µA
SVD2
SVD2
VDD

l i m
r e
P

Rev. 1.2 EPSON 55


S1D15712 Series

10. TIMING CHARACTERISTICS


(1) System path read/write characteristics 1 (80 system MPU)

A0

tAW8 tAH8

CS

tCYC8, tCYC8C
*1
tCCLR, tCCLW

WR, RD
tCCHR, tCCHW

y
CS
tCCLRC, tCCLWC

r
tCCHRC, tCCHWC
*2 tf tr

WR, RD

D0 to D7
(Write)
tDS8

in a tDH8, tDH8C

m
tACC8 tOH8

i
D0 to D7

l
(Read)

e
Fig. 10.1

P r

56 EPSON Rev. 1.2


S1D15712 Series

Table 10.1

[VDD = 2.7V to 5.5V, Ta = –40 to +85°C]


Specified value
Item Signal Symbol Condition Unit
Min. Max.
Address hold time A0 tAH8 0 — ns
Address setup time tAW8 0 —
System write cycle time WR tWCYC8 500 —
System write cycle time CS tWCYC8C 700 —
System read cycle time RD tRCYC8 7000 —
System read cycle time CS tRCYC8C 7000 —
Control LOW-pulse width (WR) WR tCCLW 60 —
Control LOW-pulse width (CS) CS tCCLWC 200 —
Control LOW-pulse width (RD) RD tCCLR 3000 —
Control LOW-pulse width (CS) CS tCCLRC 3000 —
Control HIGH-pulse width (WR) WR tCCHW 60 —

y
Control HIGH-pulse width (CS) CS tCCHWC 200 —

r
Control HIGH-pulse width (RD) RD tCCHR 60 —
Control HIGH-pulse width (CS) CS tCCHRC 200 —

a
Data setup time D0 to D7 tDS8 200 —
Data hold time (WR) tDH8 15 —
Data hold time (CS) tDH8C 30 —

in
RD access time tACC8 CL=100pF — 3500
Output disable time tOH8 500 2000
*1. This is in case of making the access by WR and RD, setting the CS = LOW.

m
*2. This is in case of making the access by CS, setting the WR, RD = LOW.

i
*3. Input signal rise and fall time (tr, tf) must not exceed 15 ns. When the system cycle time is used at a high speed,
it is specified by (tr + tf) ≤ (tCYC8 – tCCLW – tCCHW) or (tr + tf) ≤ (tCYC8 – tCCLR – tCCHR).

l
*4. Timing is entirely specified with reference to 20% or 80% of VDD.
*5. tCCLW and tCCLR are specified in terms of the overlapped period when CS is at LOW level and WR and RD are at

e
LOW level.

P r

Rev. 1.2 EPSON 57


S1D15712 Series

(2) System path read/write characteristics 2 (68 system MPU)


A0
R/W
tAW6 tAH6

CS

tCYC6, tCYC6C
*1
tEWHR, tEWHW

E
tEWLR, tEWLW
CS tEWHRC, tEWHWC
tEWLRC, tEWLWC

y
*2
tf tr

D0 to D7
tDS6

a r
tDH6, fDH6C

in
(Write)

tACC6 tOH6
D0 to D7
(Read)

l i m Fig. 10.2

r e
P

58 EPSON Rev. 1.2


S1D15712 Series

Table 10.2

[VDD = 2.7V to 5.5V, Ta = –40 to +85°C]


Specified value
Item Signal Symbol Condition Unit
Min. Max.
Address hold time A0 tAH6 0 — ns
Address setup time tAW6 0 —
System write cycle time E tWCYC6 500 —
System write cycle time CS tWCYC6C 700 —
System read cycle time E tRCYC6 7000 —
System read cycle time CS tRCYC6C 7000 —
Data setup time D0 to D7 tDS6 200 —
Data hold time (E) tDH6 30 —
Data hold time (CS) tDH6C 30 —
Access time tACC6 CL=100pF — 3500

y
Output disable time tOH6 500 2000
Enable HIGH-pulse width Read E tEWHR 3000 —

r
Read CS tEWHRC 3000 —
Write E tEWHW 60 —

a
Write CS tEWHWC 200 —
Enable LOW-pulse width Read E tEWLR 70 —
tEWLRC

in
Read CS 200 —
Write E tEWLW 70 —
Write CS tEWLWC 200 —
*1 This is in case of making the access by E, setting the CS = LOW.
*2 This is in case of making the access by CS, setting the E = HIGH.

m
*3 The rise time and the fall time (tr & tf) of the input signals should be set to 15ns or less. When it is necessary to

i
use the system cycle time at high speed, the rise time and the fall time should be so set to conform

l
to (tr+tf) ≤ (tCVC6-tEWLW-tEWHW) or (tr+tf) ≤ (tCYC6-tEWLR-tEWHR).
*4 All the timing should basically be set to 20% and 80% of the “VDD”.
*5 tEWLW, tEWLR should be set to the overlapping zone where the CS is on the LOW level and where the E is on the
HIGH level.

r e
P

Rev. 1.2 EPSON 59


S1D15712 Series

(3) Serial interface


CS tCSS tCSH

tSAS tSAH

A0

tSCYC
tSLW
SCL
tSHW
tf
tr

y
tSDS tSDH

SI

Figure 10.3

a r
Table 10.3

in
m
[VDD = 2.7V to 5.5V, Ta = –40 to +85°C]

Parameter

Serial clock period


SCL HIGH pulse width

e l i Signal

SCL
Symbol

tSCYC
tSHW
Condition


Specified value
Min.
250
100
Max.


Unit

ns

r
SCL LOW pulse width tSLW 100 —
Address setup time A0 tSAS — 150 —
Address hold time tSAH 150 —
Data setup time
Data hold time
CS-SCL time
P SI

CS
tSDS
tSDH
tCSS
tCSH
*1. Input signal rise and fall time (tr, tf) must not exceed 15 ns.
*2. Timing is entirely specified with reference to 20% or 80% of VDD.


200
100
150
150



60 EPSON Rev. 1.2


S1D15712 Series

(4) Display control output timing


CL
(OUT)

tDFR

FR

tDF1,F2

F1, F2

tDSYNC
SYNC

Fig. 10.4

Table 10.4

r y
a
[VDD = 2.7V to 5.5V, Ta = –40 to +85°C]
Specified value
Parameter Signal Symbol Condition Unit

in
Min. Typ. Max.
FR delay time FR tDFR CL = 50pF — 60 200 ns
F1, F2 delay time F1, F2 tDF1, tF2 — 60 200 ns
SYNC delay time SYNC tDSYNC — 60 200 ns

m
*1. Valid only in master operation

i
*2. Timing is entirely specified with reference to 20% or 80% of VDD.

(5) Reset input timing

e l
RES

Internal state

P r tRW

During resetting
tR

End of resetting

Fig. 10.5

Table 10.5
[VDD = 2.7V to 5.5V, Ta = –40 to +85°C]
Specified value
Parameter Signal Symbol Condition Unit
Min. Typ. Max.
Reset time — tR — — — 1 µs
Reset LOW pulse width RES tRW 1 — —

*1. Timing is entirely specified with reference to 20% or 80% of VDD.

Rev. 1.2 EPSON 61


S1D15712 Series

11. MPU INTERFACE (Reference Example)


The S1D15712 Series can be connected to the 80 series MPU and 68 series MPU. Use of a serial interface allows
operation with a smaller number of signal lines.
You can expand the display area using the S1D15712 Series as a multi-chip. In this case, the IC to be accesses can be
selected individually by the chip select signal. After initialization by the RES pin, each input terminal of the S1D15712
Series must be placed under normal control.

(1) 80 series MPU

VDD

VCC VDD2 VDD


A0 A0 C86

S1D15712 Series
A1 to A7 CS
IORQ Decoder
MPU

D0 to D7 D0 to D7

y
RD RD
WR WR

r
RES RES P/S
GND VSS
RESET

a
VSS

Fig. 11.1

in
(2) 68 series MPU

VDD

VCC VDD2 VDD

il m
A0 A0 C86
S1D5712 Series

A1 to A15 CS
VMA Decoder
MPU

D0 to D7 D0 to D7

e
E E

r
R/W R/W
RES RES P/S
GND VSS
RESET

P
VSS

Fig. 11.2
(3) Serial interface
VDD

VCC VDD2 VDD


A0 A0 C86 VDD or VSS
S1D15712 Series

CS1
A1 to A7 Decoder CS2
MPU

Port 1 SI
Port 2 SCL
RES RES P/S
GND VSS
RESET
VSS

Fig. 11.3

62 EPSON Rev. 1.2


S1D15712 Series

12. CONNECTION BETWEEN LCD DRIVERS (Reference Example)


You can easily expand the liquid crystal display area using the S1D15712 Series as a multi-chip. In this case, use the
same model (S1D15712/S1D15712) as the master and slave systems.

S1D15712 (Master) S1D15712 (Slave)

VDD

VSS VDD
M/S M/S

CL CL
FR FR
DOF DOF
F1 F1

y
F2 F2
SYNC SYNC

CLS
V3
V2
V1

a
V3
V2
V1
CLS

r
in
VC VC
MV1 MV1
(VSS) MV2 MV2 (VSS)
(VSS) MV3 MV3 (VSS)

m
Fig. 12 Master/slave connection example

e l i
P r

Rev. 1.2 EPSON 63


S1D15712 Series

13. LCD PANEL WIRING (Reference Example)


You can easily expand the liquid crystal display area using the S1D15712 Series as a multi-chip. In the case of multi-
chip configuration, use the same models.

(1) Single chip configuration example

256 × 81 Dots

COM SEG COM

S1D15712 Series

y
Master

a
Fig. 13.1 Single chip configuration example

(2) Double chip configuration example r


in
m
512 × 81 Dots

COM

e l
SEGi SEG COM

P r S1D15712 Series
Master
S1D15712 Series

Fig. 13.2 Double chip configuration example


Slave

64 EPSON Rev. 1.2


S1D15712 Series

14. CAUTIONS
Cautions must be exercised on the following points when using this Development Specification:
1. This Development Specification is subject to change for engineering improvement.
2. This Development Specification does not guarantee execution of the industrial proprietary rights or other rights, or
grant a license. Examples of applications described in This Development Specification are intended for your
understanding of the Product. We are not responsible for any circuit problem or the like arising from the use of them.
3. Reproduction or copy of any part or whole of this Development Specification without permission of our company,
or use thereof for other business purposes is strictly prohibited.

For the use of the semi-conductor,cautions must be exercised on the following points:

[Cautions against Light]


The semiconductor will be subject to changes in characteristics when light is applied. If this IC is exposed to light,
operation error may occur. To protect the IC against light, the following points should be noted regarding the substrate
or product where this IC is mounted:
(1) Designing and mounting must be provided to get a structure which ensures a sufficient resistance of the IC to
light in practical use.

y
(2) In the inspection process, environmental configuration must be provided to ensure a sufficient resistance of the
IC to light.

r
(3) Means must be taken to ensure resistance to light on all the surfaces, backs and sides of the IC

in a
l i m
r e
P

Rev. 1.2 EPSON 65