PROJECT

This video talks about the state of the 2017 advanced package. The first speaker first

talked about the impact of the market on advanced packaging. I talked about five

kinds of moves that we should do. So the speaker also talked about two ways to

improve advanced packaging, scaling and functional routes. Scaling should be carried

on, I think the scaling here refers to continue to shrink the size of the product. Let

advanced packaging achieve half-package or even no package. High-density products

can make the performance of the product even more improved. In order to integrate

more functions in the package, many companies are looking for a higher density 3D

chip package. The 3D interconnect breaks the current chip package mainly in the x

and y directions, adding a z-direction package. Short signal paths, due to reduced

signal loss, lower transmission power requirements, and greatly improved

performance. But functional and system-level features are becoming more and more

important for product differentiation. The outlook for the future brings the Internet of

Things, including the industrial Internet of Things, the semiconductor industry's

semiconductorization, 5G interconnection, augmented reality/virtual reality, and

artificial intelligence. In this regard, I think the more important is the power

consumption and cost. The Internet of Things has been developing for a long time,

and many technologies are very mature. But whether many new industries can bring

prospects to the semiconductor industry, there are too many uncertainties and

opportunities.
The speaker also mentioned that there are very complete interconnects and packages

are fixed to the customer like Yole or there are more advanced technologies to survive

in the market. Later he also talked about some competition in recent years. He talked

about the competition of three advanced packaging in technology. We can see that

with the development of technology, many packaging technologies that have not been

mixed before gradually expand their fields. The integration degree has been upgraded

from PCB and carrier board to high-level wafer integration methods such as thin film

process or 2.5D interposer. In terms of industry chain, the competition between the

carrier board and the packaging and testing plant and even the fab will be faced, but

the carrier has always been an important partner of the packaging and testing plant,

and therefore even if the customer is interested in high-integration packaging, will the

packaging and testing plant with the flip-chip packaging capacity be willing to

abandon the long-established flip chip packaging technology. Is it possible to

purchase a large number of thin film processes to develop fan-out packaging

technology by investing in capital costs? Or is there both a meridian production

capacity and a carrier plant for high-density carrier board development? I think the

latter is more likely, because the latter are both available, and no matter how the

market changes, they will find a way out.

The speaker then talked about the industry chain. In the industry chain, we can see that

some companies have more than 10nm accuracy, so it is necessary to reduce the scaling

to a lower standard, because if the accuracy does not meet the market requirements. , it

will bring a lot of losses. It is better to put these funds on the study of functional. The
adjustment of the semiconductor supply chain is to prepare for future uncertainties and

seek other value streams. M&A in the market has occurred in order to provide a more

complete and diversified supply mix while achieving the goal of controlling costs and

potential losses. Finally, the prospects for advanced packaging are very good, and they

all occupy a very important ratio. In the future, I think there will be a relatively large

development in these three areas. 1.SiP system-level packaging, the Internet of Things

will be the main driving force for future semiconductor growth. Since the Internet of

Things is more lightweight and shorter than mobile phones, it is necessary to package

all chips with different processes and functions in 3D and other ways to reduce the size

and improve system integration. 2. FO-WLP fan-out wafer-level package, FO-WLP has

the characteristics of ultra-thin, high I/O pin number, etc. The product has the

advantages of small size, low cost, good heat dissipation, excellent electrical property

and high reliability.

The second speaker introduced advanced packaging technology in two ways. One is the

application process and the system-in-packages. First we can see a comparison of the

three technologies, especially the tsmc technology used by the third Apple mobile

phone. The substrate of the package and in copper to remove now all of the steps are

realized of the wafer level. The main advantage of this "fan-out" fan-out package chip

is that it can bring a more compact motherboard and antenna design, so that no more

space can be reserved for the battery, and the body can be changed. More slim. If

combined with the first speaker, this is very satisfying market demand. The chip gets

smaller, giving more room for the battery and other parts. Single-chip fan-out package,
the main application is the baseband processor, power management, RF transceiver and

other chips, it will have a stable market in the future. Another mainstream is the high-

density fan-out package, which is mainly for processors with a large number of I/O pins,

such as application processors and memory. However, it needs to be equipped with

more new integration technologies, so there is still some uncertainty in development.

But the future growth potential is huge.

In the second part, he talked about the contrast between fan-out technology and other

technologies. In fact, it is very obvious, reducing the size by nearly 60%. Later, I talked

about various modules. We can all clearly see that system in package is now a very

mature technology. Whether it's wifi, Bluetooth, battery modules, etc., it's very good

and the cost is getting less and less. In general, SIP maximizes system performance,

avoids re-packaging, shortens development cycles, reduces costs, and increases

integration. Compared with SoC, SIP has the characteristics of high flexibility, high

integration, short design cycle, low development cost and easy access. SIP technology

can be applied to various fields of the information industry, but the most distinctive

research and application at present is the physical layer circuit in wireless

communication. But it is also flawed. 1. Increasingly thin wafers will cause problems

for automated equipment. The wafer becomes too fragile and therefore more fragile. 2.

The cost of the more mature packaging industry is higher. SiP generally uses a multi-

layered BT substrate as the carrier of the package, plus the testing cost of various

component assembly, chip package and the entire package product. From the

perspective of package manufacturing, the cost is indeed higher than that of the
packaged single-chip SoC product. So for the future of sip, there will be many

opportunities, but how to develop is still a big challenge. Under the trend of the Internet

of Things, it is inevitable to combine various mobile devices, wearable devices,

transportation, medical care, and home networks in tandem. Multi-functional

heterogeneous chip integration estimates will have huge demand, and low power

consumption will also be an important trend.