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Code: 9A04306 1

B.Tech II Year I Semester (R09) Regular & Supplementary Examinations December/January 2013/14
DIGITAL LOGIC DESIGN
(Computer Science and Engineering)
Time: 3 hours Max Marks: 70
Answer any FIVE questions
All questions carry equal marks
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1 (a) Convert the following numbers:
(i) (41. 6875)10 to hexadecimal number.
(ii) (11001101. 0101)2 to base -8 and base 4.
(iii) (4567)8 to base 10.
(b) Add and multiply the following numbers without converting them to decimal:
(i) Binary numbers 1011 and 101.
(ii) Hexadecimal numbers 2E and 34.

2 Simply the following Boolean expressions to minimum number of literals:


(a) 𝐴𝐴� 𝐶𝐶̅ + 𝐴𝐴𝐴𝐴𝐴𝐴 + 𝐴𝐴 𝐶𝐶̅ .
(b) (𝐴𝐴̅ + 𝐶𝐶)(𝐴𝐴̅ + 𝐶𝐶̅ )(𝐴𝐴 + 𝐵𝐵 + 𝐶𝐶̅ 𝐷𝐷).
(c) 𝐴𝐴𝐴𝐴𝐴𝐴 + 𝐴𝐴̅ 𝐵𝐵 + 𝐴𝐴𝐴𝐴𝐶𝐶̅ .
(d) (𝐵𝐵𝐶𝐶̅ + 𝐴𝐴̅𝐷𝐷)(𝐴𝐴 � �)
𝐵𝐵 + 𝐶𝐶𝐷𝐷
(e) ��������� ���������
̅
(𝐴𝐴 + 𝐵𝐵 ) (𝐴𝐴 + 𝐵𝐵� )

3 (a) Simplify and implement the following SOP using NOR gates f(A, B, C, D) = ∑𝑚𝑚 (0, 1, 4, 5, 10, 11, 14, 15).
(b) Reduce the following function using K-map technique f (A, B, C, D) = 𝜋𝜋𝑚𝑚 (0, 2, 3, 8, 9, 12, 13, 15).

4 (a) Implement BCD to 7-segment decoder for common anode using 4:16 decoder.
(b) Implement the following Boolean function using 8:1 multiplexers F(A, B, C, D) = 𝐴𝐴� 𝐵𝐵𝐷𝐷
� + 𝐴𝐴𝐴𝐴𝐴𝐴 + 𝐵𝐵� 𝐶𝐶𝐶𝐶 +
� ̅
𝐴𝐴 𝐶𝐶 𝐷𝐷.

5 (a) Draw the circuit diagram of clocked D-flip flop with NAND gates and explain its operation using truth table.
Give its timing diagram.
(b) Draw the logic diagram of a JK – flip flop and explain.

6 (a) Explain synchronous and ripple counters. Compare their merits and demerits.
(b) Design Mod-10 counter using T-Flip flop.

7 (a) Give the comparison between PROM, PLA and PAL.


(b) A combinational circuit is defined by the functions
𝐹𝐹1 (𝐴𝐴, 𝐵𝐵, 𝐶𝐶) = ∑(3, 5, 6,7)
𝐹𝐹2 (𝐴𝐴, 𝐵𝐵, 𝐶𝐶) = ∑(0, 2, 4, 7)
Implement the circuit with a PLA having three inputs, four product terms and two outputs.

8 (a) Explain the salient features of ASM chart.


(b) Draw the ASM chart for weighing machine and explain.

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Code: 9A04306
2
B.Tech II Year I Semester (R09) Regular & Supplementary Examinations December/January 2013/14
DIGITAL LOGIC DESIGN
(Computer Science and Engineering)
Time: 3 hours Max Marks: 70
Answer any FIVE questions
All questions carry equal marks
*****
1 (a) Subtract (111001)2 from (101011) using i’s complement.
(b) Convert the following numbers:
(i) (2 C6B. F2)16 to octal. (ii) (26153. 7406)8 to binary (iii) (1001001. 011)2 to decimal.

2 (a) Simplify the following Boolean expressions to minimum number of literals:


(i) 𝐴𝐴̅ 𝐵𝐵� + 𝐴𝐴𝐴𝐴𝐴𝐴 + 𝐴𝐴 𝐶𝐶̅ . (ii) (𝐴𝐴̅ + 𝐶𝐶) (𝐴𝐴̅ + 𝐶𝐶̅ ) (A+B+𝐶𝐶̅ 𝐷𝐷). (iii) (𝑥𝑥
�������
+ 𝑦𝑦) (𝑥𝑥̅ + 𝑦𝑦�). (iv) 𝑥𝑥𝑥𝑥 + 𝑥𝑥 (𝑤𝑤𝑤𝑤 − 𝑤𝑤𝑧𝑧̅).
(b) Simplify the following Boolean function in SOP form 𝐹𝐹(𝑤𝑤, 𝑥𝑥, 𝑦𝑦, 𝑧𝑧) = 𝑥𝑥𝑦𝑦�𝑧𝑧 + 𝑥𝑥̅ 𝑦𝑦�𝑧𝑧 + 𝑤𝑤 �𝑥𝑥𝑥𝑥 + 𝑤𝑤𝑥𝑥̅ 𝑦𝑦 + 𝑤𝑤𝑤𝑤𝑤𝑤.

3 (a) Reduce the following function using K-map in SOP form 𝐹𝐹(𝑤𝑤, 𝑥𝑥, 𝑦𝑦, 𝑧𝑧) =∑(0, 1, 2, 4, 5, 8, 9, 12, 13, 14).
(b) Simplify the Boolean function using K-map.
𝐹𝐹(𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) = 𝐴𝐴̅ 𝐵𝐵
� 𝐶𝐶̅ + 𝐵𝐵� 𝐶𝐶𝐷𝐷
� + 𝐴𝐴̅ 𝐵𝐵 𝐶𝐶 𝐷𝐷
� + 𝐴𝐴𝐵𝐵� 𝐶𝐶̅ Implement with NAND gates.

4 (a) Design and implement a 4-bit combinational circuit of binary to gray code.
(b) Implement the full adder with a decoder and two OR-gates.

5 (a) Determine a minimal state table equivalent to the state table given below.
PS NS Z
J1 J2
1 2, 0 4, 1
2 7, 0 1, 0
3 4, 0 2, 1
4 7, 0 1, 0
5 4, 0 1, 1
6 5, 1 6, 1
7 4, 1 4, 1
(b) Design a sequential circuit specified by the state diagram in figure using JK-flip flop.

oo
1 1
1

o
o 1
o
6 (a) Design a 4-bit binary synchronous counter with D-flip flop.
(b) Design a converter with the following repeated binary sequence: 0, 1, 2, 4, 6. Use D-flip flops.

7 Implement the following using PLA:


(a) 𝐴𝐴(𝑥𝑥, 𝑦𝑦, 𝑧𝑧) = ∑𝑚𝑚(1, 2, 4, 6), 𝐵𝐵(𝑥𝑥, 𝑦𝑦, 𝑧𝑧) = ∑𝑚𝑚 (0, 1, 6,7), 𝐶𝐶(𝑥𝑥, 𝑦𝑦, 𝑧𝑧) = ∑𝑚𝑚 (2, 6).
(b) Obtain the 15-bit hamming code word for the 11-bit data word 11001001010.

8 (a) Obtain the ASM chart for the following state transactions if 𝑥𝑥 = 0, control goes from state 𝑇𝑇1 to state 𝑇𝑇2 . If 𝑛𝑛 = 1 generate
a conditional operation and go from 𝑇𝑇1 𝑡𝑡𝑡𝑡 𝑇𝑇2 .
(b) How do you indicate moore outputs and Melay outputs in an ASM?

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Code: 9A04306 3
B.Tech II Year I Semester (R09) Regular & Supplementary Examinations December/January 2013/14
DIGITAL LOGIC DESIGN
(Computer Science and Engineering)
Time: 3 hours Max Marks: 70
Answer any FIVE questions
All questions carry equal marks
*****
1 (a) Convert the following numbers in decimal:
(i) (10110. 0101)2 (ii) (16. 5)16 (iii) (26. 24)8.
(b) Perform (15)10- (28)10 in complement representation.
(c) Find the 16’s complements of AF3B and convert AF3B to binary.

2 (a) Convert the following to the other canonical form:


(i) F(x, y, z) = ∑(1, 3, 7) (ii) F (A, B, C, D) = 𝜋𝜋(0, 1, 2, 3, 4, 6,12).
(b) State and prove the following theorems:
(i) Demorgan’s theorem. (ii) Conserver theorem. (iii) Shanon’s expansion and reduction theorem.

3 (a) Simplify the following Boolean function for minimal POS form using K-map:
𝐹𝐹 (𝑤𝑤, 𝑥𝑥, 𝑦𝑦, 𝑧𝑧) = 𝜋𝜋 (4, 5, 6, 7, 8, 12) + 𝑑𝑑 (1, 2, 3, 9, 11, 14) implement with NOR gates.
(b) Reduce the following function using K-map in SOP form.
F(w, x, y, z) = ∑(0, 1, 2, 4, 5, 6, 8, 9, 12, 13, 14).

4 (a) Realize the following Boolean expression using a 8 × 1 multiplexer:


𝑌𝑌 = 𝐴𝐴̅ 𝐵𝐵�𝐶𝐶 + 𝐴𝐴̅ 𝐵𝐵 𝐶𝐶̅ + 𝐴𝐴 𝐵𝐵� 𝐶𝐶 + 𝐴𝐴𝐴𝐴𝐴𝐴.
(b) Construct a 5 – to – 32 line decoder with four 3-to-8 line decoders with enable and a 2 – to -4 line decoder. Use block
diagrams for the components.

5 A sequential circuit with two D-flip flops, A and B, two inputs 𝑥𝑥 𝑎𝑎𝑎𝑎𝑎𝑎 𝑦𝑦, and one output z, is specified by the following
next state and output equations:
𝐴𝐴 (𝑡𝑡 + 1) = 𝑥𝑥1 𝑦𝑦 + 𝑥𝑥𝑥𝑥
𝐵𝐵(𝑡𝑡 + 1) = 𝑥𝑥1 𝐵𝐵 + 𝑥𝑥𝑥𝑥
𝑧𝑧 = 𝐵𝐵.
(a) Draw the logic diagram of the circuit.
(b) List the state table for the sequential circuit.
(c) Draw the corresponding state diagram.

6 (a) Design a serial 2’s complementor with a shift register and a flip –flop. The binary number is shifted out from one side
and its 2’s complement shifted in to the other side of the shift register.
(b) Show that a BCD ripple counter can be constructed using a 4-bit binary ripple converter with asynchronous clear and
a NAND gate that detects the occurrence of count 1010.

7 (a) Tabulate the truth table for an 8 × 4 ROM that implements the Boolean functions:
𝐴𝐴 (𝑥𝑥, 𝑦𝑦, 𝑧𝑧) = ∑(1, 2, 4, 6), 𝐵𝐵(𝑥𝑥, 𝑦𝑦, 𝑧𝑧) = ∑(0, 1, 6, 7), 𝐶𝐶 (𝑥𝑥, 𝑦𝑦, 𝑧𝑧) = ∑(2,6), 𝐷𝐷 (𝑥𝑥, 𝑦𝑦, 𝑧𝑧) = ∑(1, 2, 3, 5, 7).
Considering now the ROM as a memory, specify the memory contents at addresses 1 and 4.
(b) Tabulate the PLA programming table for the four Boolean functions listed in above problem.

8 (a) Draw an ASM chart and stage table for a 2-bit up-down can be having mode control input, M= 1: up counting , M = 0
down counting: The circuit should generate an output ‘1’ whenever count becomes minimum or maximum.
(b) Draw the ASM chart for weighing machine and explain.
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Code: 9A04306 4
B.Tech II Year I Semester (R09) Regular & Supplementary Examinations December/January 2013/14
DIGITAL LOGIC DESIGN
(Computer Science and Engineering)
Time: 3 hours Max Marks: 70
Answer any FIVE questions
All questions carry equal marks
*****
1 (a) The state of a 12-bit register is 100010010111. What is its content if it represents:
(i) Three decimal digits in BCD. (ii) Three decimal digits in the excess -3 code.
(iii) Three decimal digits in the 8421 code. (iv) A binary number.
(b) Convert decimal 9126 to both BCD and ASCII codes. For ASCII, an add parity bit is to be appended at
the left.

2 (a) Given the Boolean function 𝐹𝐹 = 𝑥𝑥𝑥𝑥 + 𝑥𝑥 1 𝑦𝑦1 + 𝑦𝑦1 𝑧𝑧:


(i) Implement it with AND. OR and inverter gates. (ii) Implement it with OR and inverter gates.
(iii) Implement it with AND and inverter gates.
(b) Obtain the dual of the following Boolean expressions:
(i) A𝐵𝐵� 𝐶𝐶 + 𝐴𝐴𝐵𝐵� 𝐷𝐷 + 𝐴𝐴� 𝐵𝐵� (ii) 𝐴𝐴� 𝐵𝐵� 𝐶𝐶̅ + 𝐴𝐴𝐴𝐴𝐶𝐶̅ + 𝐴𝐴� 𝐵𝐵� 𝐶𝐶� 𝐷𝐷.

3 (a) Simplify the following Boolean function by using a Quline-McCluskey method:


𝐹𝐹 (𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) = ∑𝑚𝑚 (0, 2, 3, 6, 7, 8, 10, 12, 13).
(b) Find the reduced SOP form of the following function F (A, B, C, D) = ∑m (1, 3, 7, 11, 15) + ∑d (0, 2, 4).

4 (a) Design and implement a 4-bit combinational circuit of binary to gray code.
(b) Implement the full adder with a decoder and two OR-gates.

5 A sequential circuit has two JK flip-flops A and B two inputs 𝑥𝑥 𝑎𝑎𝑎𝑎𝑎𝑎 𝑦𝑦, and one output ‘2’. The flip flops
input equations and circuit output equation are
𝐽𝐽𝐴𝐴 = 𝐵𝐵𝐵𝐵+𝐵𝐵1 𝑌𝑌1 𝐾𝐾𝐴𝐴 = 𝐵𝐵1 𝑥𝑥 𝑌𝑌1
1
𝐽𝐽𝐵𝐵 = 𝐴𝐴 𝑥𝑥 𝐾𝐾𝐵𝐵 = 𝐴𝐴 + 𝑥𝑥𝑌𝑌1 .
(a) Draw the logic diagram of the circuit.
(b) Tabulate the state table.
(c) Derive the state equations for A and B.

6 (a) Design a counter with the following repeated binary sequence: 0, 1, 2, 3, 4, 5, 6. Use JK-flip flops.
(b) What is the difference between serial and parallel transfer? Explain how to converter serial data to
parallel and parallel data to serial. What type of register is needed?

7 (a) Design a combinational circuit using a ROM. The circuit accepts a 3- bit number and generates an
output binary number equal to the square of the input number.
(b) Implement the following two Boolean functions with a PLA:
𝐹𝐹1 (𝐴𝐴, 𝐵𝐵, 𝐶𝐶) = ∑(0, 1, 2, 4), 𝐹𝐹2 (𝐴𝐴, 𝐵𝐵, 𝐶𝐶) = ∑(0, 5, 6, 7).

8 (a) Explain how the ASM chart differs from a conventional flow chart. Show the difference in interpretation
using one example.
(b) Obtain ASM chart for the following state transitions if 𝑥𝑥 = 0. Control goes from state 𝑇𝑇1 to state 𝑇𝑇2 , if
𝑛𝑛 = 1 generate a conditional operation and go from 𝑇𝑇1 𝑡𝑡𝑡𝑡 𝑇𝑇2 .

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