Menka Sukhwani, V. B.

Chandratre, Megha Thomas,

C. K. Pithawa
Centre for Micro-Electronics, Electronics Division
Bhabha Atomic Research Centre
Mumbai, India

Vangmayee Sharda,
AITTM, Amity University, Noida
 Introduction
 ANUSMRITI ASIC Required Specifications
 Analog Memory Concept and Architectures
 ANUSMRITI ASIC Architecture
 ANUSMRITI ASIC Design Blocks
 ANUSMRITI ASIC Operation
 Design Trade-offs & Calibration
 Simulation Results
 Test Results
 Conclusion
 Electronics Division, BARC involved in design and
development of “Full custom mixed mode CMOS ASICs”
for
 Instrumentation requirements of the Department
 National and International High Energy Physics Experiments
like Indian Neutrino Observatory (INO), CERN-CMS

 “ANUSMRITI” ASIC designed for requirements of

 „Astrophysics Experiments on Cosmic Ray Shower‟ at NRL,
BARC
 „Pulse profile analysis‟ in Laser/Accelerator based
experiments at RRCAT, Indore
 „Charge over threshold‟ measurement in INO experiment.
 Sampling Rate: 500 MHz
 Memory Depth: 128-bin; 256 ns
 Sampling Rate ensured by Reference Delay locked loop
 Dynamic Range: 2 V
 Readout rate: 1 MHz
 Power consumption: 400 mW
 Technology: 0.7 um mixed CMOS
 Die area: 5 mm by 3.5 mm
 Package: CLCC-44
 Switched capacitor circuit to sample and store the
instantaneous value of analog input signal
 Stored samples can be read and digitized later at
lower speed
 Eliminates the need of high speed ADC and DAQ
where continuous digitization is not requited
 Pulse profile recording applications :
Radar, ultrasonic, astronomy, High energy physics
experiments, High speed transient digitization in lab
instruments
 V
V

Analog Memory
Sin Sout
0 t
0 t Vin
Ci

Sr ADC
Sw
SENSOR/ AMPLIFIER/ Vref
DETECTOR SHAPER

ANALOG
Reset Calibration
MEMORY Read
Write Matrix
Logic Logic
Calibrated
Slow Read Digital output
Clock
 Shift Register based Read Logic
Read
Clock Rn
1st cell R1 nth cell
Min Mout
Input Bus

Input
Mw1 Mwn
Common output
Mr1 Mrn buffer

Cn Vref
C1 +
Read Bus
Signal Path -
Vref Output
W1 Wn Mreset
Trigger

Ext Vctr Write Logic

Ref: Stuart Kleinfelder, “Advanced transient waveform digitizers” in Proceedings of the Particle
Astrophysics Instrumentation Conference, (2003) pp 316-326
 Shift Register based Read Logic
Read Clock
R1 nth cell Rn
1st cell

Input +
Mw1 Mwn
Read Bus Read Bus

Differential Mr1
Cn Mrn
Input
C1
Vref Vref
Individual cell Buffer
Input -

W1 Wn
Stop
Write Logic
Ext Vctr

Ref: Stefan Ritt, “Design and Performance of the 5 GHz Waveform Digitizing Chip DRS3”, IEEE Nuclear
Science Symposium Conference Record, pp- 2485 – 2488, 2007.
 Shift Register based Read Logic
Read
Clock R1 nth cell Rn
1st cell

Input +
Mw1 Mwn
Read Bus Read Bus

Mr1 Cn Mrn
C1
Vref Vref
Input -
W1 Wn
Stop Write Logic
Vctr
Reference DLL
Wref Phase
Detector &
Charge Pump

Aref
Ref: Stefan Ritt, “Design and Performance of the 6 GHz Waveform Digitizing Chip DRS4”, IEEE Nuclear
Science Symposium Conference Record, 2008.
 Shift Register based Read Logic
Read Clock
R1 Dummy cell R128
1st cell 128th cell
Min Input Bus Mout

Input
C1d C1 C128d C128 Common output
Mr1 Mr128 buffer
Signal
Return Path Vref
Mwd1 Mwd128 Mw128 +
Read Bus
Mw1 - Output
Vref
Mreset
W1 W128
Trigger Write Logic

Reference Vctr
DLL
Wref Write
Servo Logic
Feedback
Contol

Aref
 Comin

Min Read logic Comout

Vin R1 R128
Mout

Vref
Mr1 Mr128
C1 C128 Memout
Cd1 Cd128 +
Op-amp
Mw1 Mw128 _
Mwd1 Mwd128

Memory block Comreset

Vref
Rbus Mreset
W1 W128
Write logic
 Write Logic Aref

Delay Chain of 128 Current Starved Inverters

Wref Wrefn
Servo Vctr
Write Feedback
trigger Control
Current starved
Inverter
VDD w1 w2 w3 w127 w128

VDD
M1
Vctr
Wrefn
Rgnd
M2 M4
Phi Vctr
Win
Wout
Rvdd
Aref
M3 M5

VSS VSS
 Reference Write Patterns
(a) Wref

Wref_d
td
Aref
Phi
Vctr
Servo Capacitor Charges
(b) Wref

Wref_d
td
Aref

Phi

Vctr
Servo Capacitor Discharges
 Read Logic
Two Phase Shift R1 R2 R128

Register

Phien
Phis1b
Phis2b

Phirin
Phis2
Phis1

Phis2
Two Phase Clock Phis2b
generator
Phis1b
Phisr
Phis1
DGND
 ANALOG MEMORY CORE
128 CELL

WRITE REFERENCE GENERATION LOGIC OUTPUT AMPLIFIER

 Write Phase

Min Mout
Vin Input Bus

Ci Vref
+
Mem_out
Read Bus _
Mri
Mwi
Vref
Mreset
 Read Phase
Min
Vin Mout

Ci
Vref
+
Mem_out
_
Mwi Mri
Vref

Mreset
Memory output not exact replica of the
input signal
Input signal Charge Injection
dependent from write
Pedestal Voltage, transistor during
Analog Bandwidth & turnoff
Switching Time Memory
Cell Offset
Non-
Non-unity
Linearity &
Cell Gain
Distortion

Calibration
& Parasitic
Correction Capacitances
 The Calibration Matrix Comprises calibration constants for
◦ Gain (Ka)
◦ Offset (Koff)
◦ Linearity (Kl)

 Simpler Calibration Matrix requires

“Uniformity in the memory cell transfer characteristics across
the memory depth”

 Non-uniformity across the memory depth depends upon

 Memory Architecture : to minimize input signal dependent cell
transfer characteristics
 Mismatch among the cell parameters : Sampling capacitance
(Ci), write transistor width (W) & length (L)
 Non-Linearity & Distortion
 Memory Cell Analog Bandwidth =
f(Sampling capacitor, Write transistor ON resistance)
Vin

Smaller Cell Capacitor Ci

Wider write Transistor
W/L
 Switching Time when Constant (Vref)
VGS < Vth Switched Voltage
Vref VH
i. e. VH – Va < Vth VL

Independent of Write Transistor in

Input Signal Signal Return Path
 Memory Cell Offsets
Vin
Due to Charge injection from Write
Transistor during turn-off Ci
Cov
Two Components
VH
Qch VL
Channel Charge Injection
& W/L
Write Signal Feed-Through via Overlap Capacitor

Pedestal Voltage: Vped = Vch + Vov Vref

Constant Switched Voltage Vref  Input independent Vped

 Memory Cell Offsets
Mismatch among cell parameters : Ci , W & L

Dominates Under fast turn-off conditions

Considering cell parameter mismatch

Smaller write Transistor Larger Cell Capacitor

Trade-off between
Analog Bandwidth &
δVped
 Calibration Constants
Memory cell output in presence of offset Voff and non-unity
gain Ai,
Voi = Ai Vin + Voffi

Two Reference voltages  Vcal1 ; Vcal2

Gain Calibration Constant  Kai = (Voi1 – Voi2)/(Vcal1- Vcal1)

Offset Calibration Constant  Koffi = Vcal1-Ka Voi1

Calibration

Vsig = Kai Voi + Koffi

W1 W5
W32 W64 W96 W128

Analog Input
Rise Time : 5ns
Fall Time : 30ns

256 ns
Memory Output : Read at 1 MHz

128 us
  Tested for designed specification using

 Input buffer capable of

driving 64pF input
capacitive load of
ANUSMRITI ASIC.
 CPLD for the Read
patterns at 1 MHz
 Write patterns generated
on-chip using 40 MHz
external clock.
Error Voltage variation across Memory Depth < 2.5% FS
0.05

0.03
Error voltage (V)

0.01

0 20 40 60 80 100 120 140

-0.01
Memory Cell No.

-0.03

-0.05
Memory cell gain variation across Memory Depth < 2.5% FS
1.02

1.015
Memory Cell Gain

1.01

1.005

0.995

0.99

0.985

0.98
0 20 40 60 80 100 120 140
Memory Cell No.
Memory cell Linearity plot across dynamic range
4

y = 0.9969x + 0.0091
3.5
R² = 0.9998
Output Voltage (V)

2.5

1.5

1
1 1.5 2 2.5 3 3.5 4

Input Voltage (V)

Analog Memory output for an input sinusoid of 8.78 MHz

3.1

2.9
Output Voltage (V)

2.7

2.5

2.3

2.1

1.9

1.7

1.5
0 50 100 150 200 250
Time (n sec)
 500MHz, 128-bin Analog Memory ASIC “ANUSMRITI”
designed and tested successfully
 Pre-cursor to the design of 2 GHz, 1024-bin, Multi-
channel Analog Memory ASIC
 Implementation of “Analog Ring Sampler” mode &
enhanced Readout
 Design of wideband input buffer capable of driving
large capacitive load

Envisaged future application

Frequency conversion in RF communication ...
Dr. S. Banerjee, Chairman, Atomic Energy Commission; Former Director,
BARC
Dr. R. K. Sinha, Director, BARC
Shri G. P. Srivastva, Director, E&I Group, BARC
Shri R. K. Patil, Associate Director, E&I Group, BARC
Shri C. N. Norhona, Former Zonal Manager(W), Electronics Corporation of
India Ltd., Mumbai
Shri D S Kulkarni, Zonal Manager (W), Electronics Corporation of India
Ltd., Mumbai
Shri R V Raut, Technical Manager, Electronics Corporation of India Ltd.,
Mumbai
Semiconductor Complex Ltd., Chandigarh
Bharat Electronics Ltd., Bangaluru
And
CMEMS Team