8288 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 64, NO.

10, OCTOBER 2017

Parasitic Inductance and Capacitance-Assisted

Active Gate Driving Technique to Minimize
Switching Loss of SiC MOSFET
Parthasarathy Nayak, Student Member, IEEE, and Kamalesh Hatua, Member, IEEE

Abstract—High di/dt and dv/dt of SiC MOSFET cause a
considerable amount of overshoot in device voltage and
current during switching transients in the presence of in-
verter layout parasitic inductance and load parasitic ca-
pacitance. The excessive overshoots in device voltage and
current cause failure of the device. Moreover, these un-
controlled overshoots increase the switching loss in the
inverter. It is difficult to reduce parasitic inductance beyond
a certain point. This paper proposes an active gate driving
technique, which allows inverter to operate with moderate
amount of layout parasitic inductance and load parasitic
capacitance. The proposed technique dramatically reduces
switching loss of the SiC MOSFET with the help of existing
parasitic elements. The proposed switching loss reduction
technique is termed as quasi zero switching. The developed
active gate driver has been tested in a double pulse test
setup and a 10 kW two-level voltage source inverter driving
an induction motor.
Index Terms—Active gate driver, double pulse (DP) test,
induction motor drive, SiC MOSFET, switching loss.
I. INTRODUCTION
DEALLY, SiC MOSFET can switch much faster and the
I overall switching loss can be reduced to a large extent. But
the parasitic inductance present in the inverter layout and par-
asitic capacitance of the load pose a significant hindrance to
this benefit. Device voltage and current experience overshoot
and oscillations due to the formation of different L–C networks
between parasitic inductance, device and load capacitances
[1]–[3]. This overshoot and oscillation result in undesired
stress in the device and increase overall switching loss. The
switching behavior of SiC MOSFET is similar to Si MOSFET.
Literature has extensively studied the switching characteristics
of Si MOSFET and Si IGBT [4]–[7]. Even though the switching
behavior remains the same, SiC MOSFET exhibit few aberrant
switching characteristics due to very high di/dt and dv/dt in
the presence of parasitic elements in the circuit [2]. In this pa-
per, two of these aberrant characteristics are exploited to reduce
Manuscript received November 29, 2016; revised February 22, 2017
and April 3, 2017; accepted April 18, 2017. Date of publication June
2, 2017; date of current version September 11, 2017. (Corresponding
author: Parthasarathy Nayak.)
The authors are with the Department of Electrical Engineering, In-
dian Institute of Technology Madras, Chennai 600036, India (e-mail:
parthasarathy.nayak.2015@ieee.org; kamalesh@ee.iitm.ac.in).
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TIE.2017.2711512
0278-0046 © 2017 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications standards/publications/rights/index.html for more information.
overall switching loss of the device and to increase the flexibility
of inverter layout design.
A fall in device voltage is observed when device current rises
during turn-on switching instant. This reduction is due to the
voltage developed across the parasitic inductance during device
current transition. The magnitude of this voltage drop across
the device is proportional to the amount of parasitic inductance
present in the commutation circuit and di/dt of the device cur-
rent [4]–[6]. In the case of IGBT, the drop is not significant as
di/dt of the device is comparatively slower. However, consid-
erable amount of voltage drop across the device occurs in case
of SiC MOSFET due to very high di/dt for the same amount
of parasitic inductance [2]. In this paper, the di/dt of the device
is controlled in such a way that device current rises without any
significant voltage across the device. This switching condition
leads to minimal turn-on switching loss. However, a complete
voltage drop across the device is sometimes difficult to achieve.
This controlled turn-on process is termed as quasi zero voltage
(QZV) turn-on.
Similarly, a reduction in device current is observed when
device voltage rises during turn-off switching instant due to a
significant amount of parasitic capacitance of the load. Similar
to QZV turn-on, the turn-off switching loss can be minimized
if dv/dt of the device voltage is controlled appropriately. This
controlled turn-off switching process is termed as quasi zero
current (QZC) turn-off.
The proposed switching loss reduction methods (QZV and
QZC) are termed as quasi zero switching (QZS). The maximum
benefits of QZV process can be explored with moderate amount
of parasitic inductance in the converter layout which is in the
range of 100 to 300 nH. It is interesting to note that the maximum
di/dt and dv/dt of the device are still within its limit during
QZS.
It is possible to achieve desired QZS response with controlled
overshoots and oscillations by controlling the gate current of the
SiC MOSFET. Gate current control mechanisms during every
switching transient are popularly known as active gate driving
(AGD).
There are AGD mechanisms reported in the literature to im-
prove device voltage and current profiles. Multistage gate resis-
tance control concepts have been proposed in [8]–[15] to realize
optimized turn-on and turn-off performance. In [16] and [17],
the gate voltage is modulated to control device dv/dt. A sen-
sorless gate driver with feed forward control for the turn-off
NAYAK AND HATUA: PARASITIC INDUCTANCE AND CAPACITANCE-ASSISTED ACTIVE GATE DRIVING TECHNIQUE TO MINIMIZE
Fig. 1. Schematic representation of double pulse test circuit.
switching dynamics is proposed in [18] and [19] to minimize
dv/dt and di/dt. Recently, there has been research in driving
the SiC MOSFET through GaAs based optically triggered power
transistors to reduce device voltage and current overshoots [20].
This paper proposes a unique method of reducing switch-
ing loss (QZS) by combining the beneficial aspects of having
higher parasitic elements in the circuit with an AGD technique.
The proposed method offers enough flexibility to design SiC
MOSFET-based inverter with higher parasitic inductances at a
lesser switching loss. The QZS technique has been tested in a
double pulse (DP) test setup and also implemented in a 10 kW
two-level voltage source inverter (VSI) driving an induction
motor.
This paper is organized as follows. Section II reports the
theory of the proposed QZS technique. Switching energy
distribution during every switching transient is explained in
Section III. The proposed AGD methodology is reported in
Section IV. Experimental results obtained from the DP test and
a 10 kW VSI are discussed in Section V. Section VI concludes
the paper.
II. THEORY OF QZS TECHNIQUE
The proposed QZS technique is explained in a standard
inductive load clamped DP test circuit as shown in Fig. 1.
An ideal DP test circuit consists of device under test (DUT)
(SiC MOSFET), a freewheeling diode (Df ), and a load induc-
tor (Lload ). But in every practical circuit, parasitic inductance
in the inverter layout (Lp ), interwinding parasitic capacitance
(Cl ) of the load inductor, and reverse biased capacitance (Cf )
of Df are present. A parasitic inductance (Lf ) also exists in
series with the freewheeling diode (Df ). Lp denotes the total
parasitic inductance present in the power circuit. It includes in-
ductances offered by the lead terminals of the device and the
bus bar. Apart from these parasitic elements, SiC MOSFET has
internal gate-source capacitance (Cg s ), gate-drain capacitance
8289
Fig. 2. Turn-on switching characteristics of SiC MOSFET.
(Cg d ) and drain-source capacitance (Cds ). Gate resistance is
noted as Rg .
A. Quasi Zero Voltage Switching (QZV)
Fig. 2 shows a turn-on switching waveform in the presence
of parasitic inductance Lp . The total switching duration of SiC
MOSFET can be divided into four stages. They are turn-on delay
time (Tdon ), device current rise time (Tir ), device voltage fall
time (Tv f ), and gate voltage rise time (Tv g sr ) [21].
It is required to reduce the area under device voltage (vds )
and device current (id ) waveform to reduce the switching loss
in the device. It is interesting to notice that there is a drop in
vds during Tir duration. This drop in vds results due to the
voltage developed across the parasitic inductance (Lp ) during
the device current rise time (Tir ). The drop in vds is governed
2 3
by (1). Generally, Lf Cl d vdtd s2 (t) and Cl Lp Lf d dt
i d (t)
3 terms are
di d (t)
small compared to (Lp + Lf ) dt term for lower value of
Cl . Therefore, the device voltage can be rewritten as (2). The
detailed derivation of (1) is provided in the Appendix
did (t) d2 vds (t)
vds (t) = Vdc − (Lp + Lf ) − Lf Cl
dt dt2
d3 id (t)
− Cl Lp Lf (1)
dt3
did (t)
vds (t) = Vdc − (Lp + Lf ) . (2)
dt
The device voltage (vds ) can be dropped instantaneously
near to zero by appropriately controlling di/dt of the device.
This drop in device voltage results in very less turn-on loss
(QZV switching) (see Fig. 2 ). For example, a voltage drop of
400 V is observed for a parasitic inductance of 200 nH at an
average di/dt of 2 kA/µsec in case of SiC MOSFET.
8290 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 64, NO. 10, OCTOBER 2017
Fig. 3. Turn-off switching characteristics of SiC MOSFET.
The di/dt can be increased by reducing the gate resistance.
However, very high di/dt will cause overshoot and oscillations
in device current during voltage fall duration (Tv f ) due to the
formation of L–C network between Lp , Cf , and Cl [4]. There-
fore, successful implementation of QZV switching along with
a reduced device current overshoot are possible if di/dt is very
high during Tir interval and it is comparatively slower during
Tv f interval. It is achieved with the proposed AGD technique
by appropriate selection of gate resistances for different stages
of turn-on switching interval.
B. Quasi Zero Current Switching (QZC)
Fig. 3 depicts a typical turn-off switching instant of
SiC MOSFET in the presence of parasitic capacitance (Cl ).
The turn-off switching duration of SiC MOSFET can also be
divided into four stages as turn-off delay period (Tdof f ), device
voltage rise period (Tv r ), device current fall period (Tif ), and
gate voltage fall period (Tv g sf ) [21].
The device remains in the on-state during turn-off delay dura-
tion (Tdof f ). Df blocks the dc bus voltage (Vdc ). In this interval,
Cl does not experience any change in voltage across it. During
device voltage rise interval (Tv r ) device voltage rises. As a
consequence, Cl experiences a change in voltage. This voltage
change causes a capacitive current to flow through it. Due to
that some of the load current is bypassed to the Cl resulting
a reduction in the magnitude of device current. Device current
is expressed by (3) during Tv r interval. When Lp is very low,
2
i d (t)
Lp Cl d dt 2 term becomes negligible compared to Cl dv ddts (t) and
the device current can be rewritten as (4). The detailed derivation
of (3) is provided in the Appendix
dvds (t) d2 id (t)
id (t) = Il − Cl + Lp Cl (3)
dt dt2
dvds (t)
id (t) = Il − Cl . (4)
dt
In this circuit conditions, device current can be dropped in-
stantaneously to a very low value by appropriately controlling
dv/dt for a fixed value of Cl and it can result in very less
turn-off loss (see Fig. 3). This turn-off switching loss reduc-
tion mechanism is termed as QZC switching. For example, the
device current can be reduced by 16 A during Tv r interval at
a Cl of 400 pF if the dv/dt is increased to 40 kV/µsec for
SiC MOSFET.
Similar to turn-on switching instant, the dv/dt can be in-
creased by reducing the gate resistance. However, high dv/dt
causes very high voltage overshoot across the device due to the
coupling between Lp and Cds [4]. Therefore, it is required to
have a very high dv/dt during Tv r interval and a slower dv/dt
during current fall interval (Tif ). It is implemented by the pro-
posed AGD by selecting different values of gate resistances at
different sub intervals during turn-off switching transient.
III. ENERGY DISTRIBUTION IN THE SWITCHING CIRCUIT
The proposed QZS technique highly depends on the magni-
tude of parasitic elements present in the switching circuit. These
parasitic elements dissipate their stored energy during turn-off
switching instant. Therefore, the question arises that whether
it is beneficial to allow a moderately higher amount of para-
sitic elements in the circuit. This section presents a quantitative
analysis on energy distribution during switching transients.
During turn-on switching transient, both Lp and Cl store en-
ergies. They dissipate these energies in the switching circuit
during turn-off duration. The magnitude of the energies stored
in Cl (Ecl ) and Lp (Elp ) during turn-on transient can be cal-
culated as 12 Cl vds2
and 12 Lp i2d , respectively. The proposed QZS
technique can only be advantageous if the sum total of energy
(EQ Z S n et ) dissipated by the reactive elements (Ecl + Elp ) in
turn-off transient and the QZS technique (EQ Z V + EQ Z C ) at a
moderately higher parasitic elements is much smaller compared
to the switching loss observed by the conventional gate driv-
ing (EC G D ) at minimum parasitic elements. Table I provides
information regarding different energies present in the system
along with the switching loss observed by the CGD and the
QZS technique. The switching loss information tabulated for
CGD (EC G D ) is obtained at Lp of 50 nH and Cl of 50 pF.
Whereas the switching loss reported for QZS (EQ Z S n et ) is
achieved at a moderately higher magnitude of parasitic elements
(Lp = 300 nH and Cl = 400 pF). The data are collected from
DP testing of the device at a dc bus voltage of 600 V.
It can be inferred from Table I that EC G D is 1220 µJ for a
device current of 30 A. Whereas achieved net switching loss by
QZS technique (EQ Z S n et ) is 400 µJ. It shows that there is a
saving (Esav e ) of 820 µJ (reduction by 67 %) by the proposed
QZS technique. Hence, it can be concluded that the proposed
QZS technique is able to reduce switching loss coexisting with
moderately higher amount of parasitic elements.
It is important to note here that the actual switching loss in the
device is relatively different from the measured switching loss
discussed in this section. It is due to the charging and discharg-
ing of device output capacitance (Coss = Cg d + Cds ) during
device voltage transition. During turn-on switching transient,
NAYAK AND HATUA: PARASITIC INDUCTANCE AND CAPACITANCE-ASSISTED ACTIVE GATE DRIVING TECHNIQUE TO MINIMIZE 8291

TABLE I
SWITCHING LOSS DISTRIBUTION BY CGD AND QZS TECHNIQUE

L p = 50 nH, C l = 50 pF L p = 300 nH, C l = 400 pF

i d (A) E o n (µJ) E o f f (µJ) E C G D (µJ) E l p (µJ) E c l (µJ) E Q Z V (µJ) E Q Z C (µJ) E Q Z S n e t (µJ) E s a v e (µJ )

10 540 548 1088 15 72 80 80 247 841

20 558 560 1118 60 72 82 90 304 814
30 600 620 1220 135 72 95 98 400 820

E C G D = Total switching loss by CGD at minimum parasitic elements (L p = 50 nH and C l = 50 pF), E Q Z V = Switching loss by QZV switching,
E Q Z C = Switching loss by QZC switching, E Q Z S n e t = Sum total of E l p , E c l , E Q Z V and E Q Z C and E s a v e = Difference between E C G D and
EQ Z S n e t .

Fig. 4. Block diagram representation of different units of the proposed active gate driver and the picture of the developed active gate driver. Where
(1) CPLD, (2) comparator and reference generator unit, (3) sensing unit, (4) turn-on unit, (5) turn-off unit, (6) digital isolator, (7) signal conditioning
unit.

the Coss discharges through the channel. This discharge current
increases the actual turn-on loss. Whereas during turn-off in-
stant, a part of the device current is used to charge the Coss . As
a result, the actual channel current reduces. This reduced chan-
nel current further reduces the turn-off switching loss. However,
this switching loss variation is very small compared to the actual
switching loss in the device. It can be calculated theoretically as
1 2
2 Coss vds . For the DUT, this part of the switching loss during
turn-on switching instant is 32 µJ at a vds of 600 V and Coss
of 175 pF. It is very less compared to the turn-on switching loss
caused due to the device current (600 µJ at a id of 30 A).
IV. AGD TECHNIQUE
The proposed QZS technique is implemented through an ac-
tive gate driver [22]. The developed gate driver controls the rate
of rise of device current and voltage by dynamically controlling
the gate current. It ensures reduced switching loss along with
reduced device voltage and current overshoot in the presence of
moderately higher amount of parasitic elements.
A. Operation of the Active Gate Driver
Different units of the developed active gate driver is depicted
in Fig. 4. The major challenge in designing an active gate driver
for SiC MOSFET is that it demands a very high speed con-
trol action. Therefore, the control algorithm is implemented us-
ing a high-speed complex programmable logic device (CPLD)
(EPM1270T144C5N from Altera MAX II) operating at a clock
frequency of 200 MHz. The CPLD receives the gate signal from
the signal conditioning unit through a digital isolator. The driver
controls the gate current by modulating the gate resistances in
four stages. The four stages during turn-on switching transient
are denoted as S1 to S4 and the four stages for the turn-off
switching transient is represented as S5 to S8 . Identification of
different stages for AGD are carried out by the device voltage
and current sensing unit, comparator unit and reference genera-
tor unit collectively.
1) Device Voltage and Current Sensing Unit: De-
vice voltage is sensed through a voltage divider network
(Ra and Rb ) connected across the device as shown in Fig. 4.
Noninductive resistors are selected and they are appropriately
placed in the PCB, such that they have minimum coupling capac-
itance. Generally, device current (id ) is sensed through voltage
developed across kelvin inductor of the device during current
transitions [23]. This approach is highly dependent on di/dt of
the device current. In this AGD, it is proposed to connect a non-
inductive low value (1 mΩ) resistor (Rsh ) in series with DUT to
sense the device current. Voltage developed across Rsh during
id transitions at turn-on and turn-off switching transients are
amplified to get exact device current information (is ). A wide
band (3.9 GHz), ultra low noise, voltage-feedback operational
amplifier (OPA847) is selected for better response.
2) Comparator Unit: Comparator unit decides the dura-
tions of each distinct four stages during both turn-on and turn-off
switching transients. It compares reference signals and sensed
device voltage (vs ) and current signal (is ) as shown in Fig. 5. In
order to effectively detect different control signals, appropriate
reference threshold voltages have been selected. The reference
voltages are kept fixed by resistive voltage divider networks for
8292 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 64, NO. 10, OCTOBER 2017
Fig. 5. Operation of comparator unit of the proposed active gate driver.
DP test of the device at constant load current. However, these
voltages are varied in a sinusoidal fashion in phase with load
current for induction motor drive application. The sinusoidal
variation of reference voltages are explained in subsequent
sections.
There are two sets of comparator circuit in the developed
AGD. Turn-on comparator unit has two reference signals to
compare sensed device current (is ). These reference signals are
denoted as R1 and R2 . These two signals correspond to 10%
of the device current and the maximum device current, respec-
tively. Their respective outputs are C1 and C2 . Similarly, there is
another reference signal to compare sensed device voltage (vs )
named as R3 . R3 corresponds to the 85% drop in device voltage
magnitude. Its output is termed as V1 . From the beginning of
turn-on gate pulse till 10% rise in device current is considered
to be turn-on delay period (Tdon ). This stage is denoted as S1 .
From the 10% to the maximum device current is considered
as current rise period (Tir ). This stage is shown as S2 . From
the end of S2 till 85% drop in device voltage is treated as device
voltage fall time (Tv f ). This stage is represented as S3 . The
rest of the turn-on duration is denoted as S4 . Comparator output
goes high if sensed signal exceeds the reference signal. Output
states of turn-on comparators are shown in Fig. 5(a). These out-
put signals are sent to CPLD to decide durations of stage S1 to
stage S4 .
Similar technique is also implemented in turn-off compara-
tor unit. In this case, two reference signals (R4 and R6 ) are
compared with sensed device voltage (vs ) and one reference
signal (R5 ) is compared with sensed device current (is ). Their
outputs are V2 , V3 , and C3 , respectively. Turn-off comparator
also operates as described for turn-on comparator unit. As per
output states of the turn-off comparator unit, CPLD decides du-
rations of stage S5 to stage S8 . A high-speed comparator IC
(MAX962/SO) is used to minimize propagation delay.
B. Control Mechanism
The control algorithm is implemented in a CPLD from
ALTERA MAXII series. It is operated at a clock frequency
TABLE II
TURN-ON CONTROL MECHANISM
Active Resistors
Stage pMOSFETs in on state Resistors Values (R g o n )
S1 D 1 and D 3 R 1 and R 3 2 and 4 Ω
S2 D 1 and D 2 R 1 and R 2 2 and 10 Ω
S3 D2 R2 10 Ω
S4 D 2 and D 3 R 2 and R 3 10 and 4 Ω
(CLK) of 200 MHz. CPLD decides durations of control stages
(stage S1 to stage S8 ) considering the outputs of the comparator
unit. It generates control signals (M1 to M6 ) to select appro-
priate gate resistances at both turn-on and turn-off switching
instants through a buffer stage as shown in Fig. 4. Buffer stage
is required to drive the switching MOSFETs present in the turn-
on and turn-off units.
1) Turn-on Control Mechanism: Turn-on control unit
consists of three pMOSFETs (D1 , D2 , and D3 ) with their re-
spective series resistances (R1 , R2 , and R3 ). The source terminal
of D1 is connected to a voltage V + (VD 1 ). Its magnitude is al-
ways greater than 20 V (maximum up to 30 V) and it is derived
from an external closed-loop power supply. The power supply
voltage is controlled in such a way that at every turn-on instant,
voltage drop across the device (SiC MOSFET) is nearly zero.
Whereas the source terminal of D2 and D3 are connected to a
fixed 20 V. The selected series resistances (R1 , R2 , and R3 ) are
2, 10, and 4 Ω, respectively. Appropriate pMOSFET combina-
tions are chosen during every stage in such a way that equivalent
turn-on gate resistance is applied to the DUT. Table II provides
detailed switching sequence of pMOSFETs and the turn-on gate
resistance (Rg on ) during different switching subintervals.
Both D1 and D3 are in the on-state during S1 subinterval. As
a consequence, very low gate resistance is offered. A very high
value of gate current is injected as VD 1 is at a voltage greater
than 20 V. It reduces S1 duration to a large extent. At the onset
of S1 , D3 is turned OFF and D2 is turned ON. In this case, gate
current slightly reduces due to a comparatively higher value of
R2 which controls the di/dt and drop in vds . The achieved di/dt
ensures QZV switching operation with the help of layout par-
asitic inductance (Lp ). At the end of S2 duration, gate voltage
reaches miller plateau voltage, and the device voltage decreases
from the already reduced device voltage in the previous subin-
terval. In this stage, device current overshoots and oscillates.
To arrest this overshoot, D1 is turned OFF and only D2 is in
on-state with a very high gate resistance (R2 ). This high value
of R2 slows down the switching speed. Once the device voltage
reaches zero, D3 is again turned ON to expedite the charging
process of gate capacitance and finally the gate voltage settles
at 20 V (recommended maximum limit) in a quicker fashion in
S4 duration.
The proposed AGD technique quickly charges the gate ca-
pacitance during S1 and S2 duration with a higher gate volt-
age and lower Rg on . However, it restricts the overshoot in
device current during subsequent subintervals by controlling the
Rg on at a fixed gate voltage. As the VD 1 (greater than 20 V) is
NAYAK AND HATUA: PARASITIC INDUCTANCE AND CAPACITANCE-ASSISTED ACTIVE GATE DRIVING TECHNIQUE TO MINIMIZE 8293

TABLE III
TURN-OFF CONTROL MECHANISM

Active Resistors

Stage nMOSFETs in on state Resistors Values (R g o f f )

S5 D 4 and D 6 R 4 and R 6 2 and 4 Ω

S6 D 4 and D 5 R 4 and R 5 2 and 10 Ω
S7 D5 R5 10 Ω
S8 D 5 and D 6 R 5 and R 6 10 and 4 Ω

active only in first two stages (S1 and S2 ), the gate voltage never
exceeds the maximum gate voltage (typically 20 V). Whereas it Fig. 6. CGD test result for turn-on switching transient. Scale
: v d s = 200 V/div, id = 10 A/div, Time = 50 nsec/div.
injects higher gate current to increase di/dt.
2) Turn-Off Control Mechanism: Turn-off control
mechanism is also implemented in four stages. The turn-off
control unit consisting of three nMOSFETs (D4 , D5 , and D6 )
with their respective series resistances (R4 , R5 , and R6 ). The
source terminal of D4 is connected to a voltage (VD 4 ) which
is greater than −5 V (maximum up to −12 V). It is derived
from a closed-loop power supply. Similar to turn-on case, the
higher negative voltage (more than −5 V) ensures the device
current to drop nearly zero. Whereas the source terminals of
D5 and D6 are connected to fixed −5 V. The selected series
resistances (R4 , R5 , and R6 ) are 2, 10, and 4 Ω, respectively.
Table III provides detailed switching sequence of nMOSFETs
and the equivalent turn-off gate resistance (Rg of f ) during dif-
Fig. 7. QZV test result with AGD for turn-on switching transient. Scale
ferent switching subintervals. : v d s = 200 V/div, id = 10 A/div, Time = 50 nsec/div.
The operation of turn-off unit can be explained in a similar
fashion as that of turn-on unit. Gate capacitance is discharged
quickly by a gate voltage greater than −5 V during S5 and The experimental result observed by the CGD with a positive
S6 interval to have very high dv/dt. This high dv/dt ensures gate voltage of 20 V and gate resistance of 10 Ω is depicted in
QZC switching with the help of Cl . In subsequent intervals, Fig. 6. The di/dt is found to be 600 A/µsec. As a consequence,
the device voltage overshoot is restricted by a higher value of device voltage drops by 175 V resulting in turn-on switching
gate resistance with a fixed gate voltage of −5 V. The gate loss of 550 µJ. In this test condition, device current overshoots
voltage never drops below the maximum allowable negative by 50% due to moderately higher parasitic inductance in the
gate voltage (typically −5 V) as VD 4 (greater than −5 V) is layout.
active only in first two stages (S5 and S6 ). An improved switching response achieved by the proposed
QZV technique along with AGD is depicted in Fig. 7 at the
V. EXPERIMENTAL RESULTS same test condition. The di/dt is increased in first two stages to
ensure a large drop in device voltage. It can be noticed that the
The QZS performance of the developed active gate driver is
di/dt of device current is 2 kA/µsec and the device voltage has
evaluated in a DP test bed as well as in a 10 kW SiC MOSFET-
dropped by 580 V. As a consequence, turn-on loss is reduced
based two-level VSI driving an induction motor. The device
to 80 µJ (reduction by 85%). It is achieved by connecting the
switching is controlled in four stages by the on-board CPLD
source terminal of D1 (VD 1 ) to 30 V. A large gate current is
and the driving units as discussed in Section IV.
injected to charge the gate input capacitance quickly as D1
is active during first two stages. Later, the device switching
A. Response of the QZS in a DP Test Setup
process is slowed down by disconnecting D1 and modulating
The DUT for the DP testing is a 1200 V, 35 A SiC MOSFET gate resistance by D2 and D3 alone. The overshoot in id is
(SCH2080KE) from ROHM Semiconductor. Experiments are limited to 30%. The values of resistances R1 , R2 , and R3 are 2,
conducted at a Vdc of 600 V and a id of 20 A at different values 15, and 4 Ω, respectively.
of Lp and Cl . 2) Evaluation of QZC Technique: The QZC switch-
1) Evaluation of QZV Technique: The reported test re- ing is implemented by controlling dv/dt of the device voltage
sults are obtained at a parasitic inductance of 300 nH. The di/dt during turn-off switching transient with the assistance of para-
of the device is controlled by adjusting the magnitude of VD 1 sitic capacitance (Cl ). The dv/dt is controlled by appropriately
as discussed in Section IV. Whereas source terminal voltages of changing the magnitude of VD 4 . The experimental result ob-
D2 and D3 are kept at 20 V. served by CGD with a fixed negative gate voltage of −5 V and
8294
Fig. 8. CGD test result for turn-off switching transient. Scale
: v d s = 152 V/div, id = 10 A/div, Time = 100 nsec/div.
Fig. 9. QZC test result with AGD for turn-off switching transient. Scale
: v d s = 152 V/div, id = 10 A/div, Time = 50 nsec/div.
gate resistance of 10 Ω is depicted in Fig. 8. The dv/dt of de-
vice voltage is 15 kV/µsec. In this case, device current drops
by 5 A resulting in a turn-off switching loss of 530 µJ. These
results are achieved at a load parasitic capacitance of 300 pF.
An improved switching response achieved by increasing dv/dt
to 40 kV/µsec is shown in Fig. 9. It is obtained by increasing
VD 4 to −12 V during Tdof f and Tv r intervals. The increased
dv/dt causes a 13 A drop in id and reduces the turn-off loss to
120 µJ (reduction by 77%). At the onset of Tv r duration, device
switching is slowed down by disconnecting D4 and modulating
gate resistance by D5 and D6 alone. It arrests device voltage
overshoot to 15%. The values of resistances R4 , R5 , and R6 are
2, 15, and 4 Ω, respectively.
B. Response of QZS in a 10 kW VSI
A 10 kW SiC MOSFET-based two-level VSI has been devel-
oped in the laboratory. The inverter is switched at a switching
frequency of 20 kHz. The dc bus is maintained at 450 V. The
dc bus is designed with copper wires instead of sandwiched
bus bar technique to accommodate moderately higher parasitic
inductance (300 nH). The induction motor has an interwinding
capacitance (Cl ) of 10 nF. The test waveforms are shown for a
load current of 10 A. The induction motor is driven in a V/F
mode.
IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 64, NO. 10, OCTOBER 2017
Fig. 10. Sinusoidal reference voltage waveform. Scale : v r e f = 2 V/div,
Time = 10 msec/div.
Fig. 11. CGD test result for turn-on switching transient. Scale
: v d s = 152 V/div, id = 5 A/div, Time = 50 nsec/div.
In the case of motor drive application, the load current varies
sinusoidally. Therefore, it is necessary to vary the reference
voltage signal in a sinusoidal fashion with the load current for
accurate selection of different stages. The developed AGD re-
ceives the sinusoidal current from an external current sensor and
it is provided to the signal conditioning unit shown in Fig. 4.
The ADC present in the signal conditioning unit converts the
analog load current into digital data. It is sent to the CPLD
through the digital isolator. CPLD generates pulse width modu-
lation (PWM) signal by comparing the load current information
with an internally generated triangular carrier signal. This PWM
signal is given to an R–C filter to generate sinusoidally vary-
ing reference voltage (vr ef ) as depicted in Fig. 10. Though the
R–C filter introduces a small phase shift, it does not affect the
performance of comparator unit as the frequency of the load
current is low (50 Hz). This mechanism ensures accurate detec-
tion of different stages for different magnitudes of load current.
However, the reference voltages required to compare the device
voltage is kept fixed as the dc bus voltage is constant. As the
load current is small and motor parasitic capacitance is large in
the present experimental test setup, the effectiveness of varying
current reference in the experimental results is less visible. This
technique will be more effective for larger magnitude of current.
1) Evaluation of QZV Technique: Fig. 11 shows a turn-
on switching instant by conventional gate driver (CGD) at an
Rg of 10 Ω. It can be observed that device voltage drops by
NAYAK AND HATUA: PARASITIC INDUCTANCE AND CAPACITANCE-ASSISTED ACTIVE GATE DRIVING TECHNIQUE TO MINIMIZE
Fig. 12. QZV test result with AGD for turn-on switching transient. Scale
: v d s = 152 V/div, id = 5 A/div, Time = 50 nsec/div.
Fig. 13. CGD test result for turn-off switching transient. Scale
: v d s = 152 V/div, id = 5 A/div, Time = 50 nsec/div.
150 V. In this case, di/dt of the device current is 500 A/µsec
and turn-on switching loss is 202 µJ for a load current of 10 A.
It is interesting to notice that the drop in device voltage and
di/dt of the device current is comparatively smaller than the
DP test results. It is because Cl is very high (10 nF) in the
case of induction motor load. A very high value of Cl affects
the di/dt and dv/dt of the device (1). Unlike DP test waveforms,
the drop in vds is governed by (1).
A turn-on switching transient achieved by the QZV technique
is shown in Fig. 12. In this case, VD 1 is at 25 V. Due to higher in-
jected gate current, device voltage drops by 300 V. The achieved
di/dt of device current is 1 kA/µsec and turn-on loss is found to
be 110 µJ. A high value of Cl restricts the increase in di/dt. As
a consequence, device voltage does not fall to a very low value
like DP test waveforms. However, the turn-on loss is reduced
by 50% from the CGD technique. The values of resistances R4 ,
R5 , and R6 are 2, 15, and 4 Ω, respectively.
2) Evaluation of QZC Technique: Turn-off test wave-
forms obtained by the CGD technique with an induction motor
load is depicted in Fig. 13. The turn-off switching loss is found
to be 150 µJ with a 2 A drop in device current at a dv/dt
of 5 kV/µsec. Fig. 14 depicts a turn-off switching transient
achieved by the proposed QZC technique. In this case, VD 4 is
at −8 V. Due to higher extracted gate current, device current
drops by 10 A at a dv/dt of 15 kV/µsec. Turn-off loss is found
to be 80 µJ. Similar to turn-on switching waveforms, a higher
8295
Fig. 14. QZC test result with AGD for turn-off switching transient. Scale:
v d s = 152 V/div, id = 5 A/div, Time = 50 nsec/div.
Fig. 15. Experimental test setup and busbar layout of the 10 kW VSI.
value of Cl affects dv/dt of the device drastically (3). However,
the turn-off switching loss is reduced by 45%. The experimental
test setup is depicted in Fig. 15.
C. Discussion
The proposed QZS technique is able to reduce switching loss
in the device to a large extent with the help of existing parasitic
elements in the system. Table IV compares the switching loss
information achieved by CGD and QZS technique at different
values of Lp and Cl . The tabulated switching loss information
for Cl of 50 to 400 pF is obtained from the DP testing of the
device. DP test is conducted at a Vdc of 600 V and id of 20 A.
Whereas test results tabulated for Cl of 10 nF is obtained from
the 10 kW inverter driving induction motor. The inverter is
tested at a Vdc of 450 V and id of 10 A. The total switching
loss obtained at a Lp of 300 nH and Cl of 400 pF by the CGD
and QZS technique are 1118 and 172 µJ, respectively, in the DP
testing of the device. It can be noticed that there is a drastic 84%
reduction in switching loss by the QZS technique. Similarly,
switching loss in the 10 kW inverter by the CGD and QZS
technique is 352 and 190 µJ, respectively. In this case, reduction
in switching loss is 46%. The energy saving in case of induction
motor application is lesser compared to the DP testing due to
the presence of higher parasitic capacitance (Cl ). High value of
Cl limits the di/dt and dv/dt (1), (3). However, for grid tied
inverter applications, line inductors can be designed with very
low parasitic capacitance. In those applications, energy savings
by the proposed QZS technique will be much higher. From
the above discussion, it can be concluded that the proposed
8296 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 64, NO. 10, OCTOBER 2017

TABLE IV
PERFORMANCE COMPARISON BETWEEN CGD AND QZS TECHNIQUE

L p = 150 nH L p = 300 nH

E C G D (µJ) E Q Z S (µJ) E C G D (µJ) E Q Z S (µJ)

Eo n Eo f f EC G D EQ Z V EQ Z C EQ Z S Eo n Eo f f EC G D EQ Z V EQ Z C EQ Z S

Cl = 50 pF 568 380 948 120 152 272 541 485 1026 75 150 225
Cl = 150 pF 570 405 975 122 138 260 545 510 1055 80 135 215
Cl = 300 pF 580 420 1000 125 125 250 550 530 1080 80 120 200
Cl = 400 pF 585 445 1030 128 95 223 558 560 1118 82 90 172
Cl = 10 nF (Results for C l =10 nF are obtained at V d c =450 V, i d =10 A) 202 150 352 110 80 190

range of 10–15 kW at a parasitic inductance of 300 nH and a

capacitance of 10 nF. However, the range of operation can be
extended for a lower load parasitic capacitance as they limit
dv/dt and di/dt. It is evident from the DP test results.
Under low load condition, the switching loss is dominated by
the capacitive discharge current from Coss for both CGD and
AGD. In this condition, the CGDs do not reduce the switching
loss caused due to low load current. Whereas the proposed QZS
technique ensures that the part of switching loss due to the load
current is zero. It reduces the overall switching loss compared
to the CGDs. The increase in di/dt and dv/dt also increase the
injected common mode (CM) current into the control circuit. It
degrades EMI performance of the converter. These CM noise
Fig. 16. Turn-on switching loss by the CGD and QZV technique. can be restricted by placing CM chokes at the gate driver end
[24], [25].
The core of the proposed technique lays on the detection of
different stages. They are obtained by sensing device current
and voltage. The reference for the current comparator is varied
as per the load current. Whereas the reference for the voltage
comparator is kept fixed. The proposed technique can be adopted
for the converters where the dc bus voltage is constant. However,
this technique can be extended to all types of converters by
replacing the fixed reference for the device voltage comparator
circuit to a variable reference similar to the current comparator
circuit.

VI. CONCLUSION

Fig. 17. Turn-off switching loss by the CGD and QZC technique.
QZS technique can be very effective for a Cl in the range of
200–600 pF and for an Lp of 200–350 nH.
Effectiveness of the proposed QZS technique also depends on
the operating conditions (dc bus voltage and load current) and
amount of parasitic elements present in the switching circuit. It
can be analyzed in the context of induction motor application
under study. Figs. 16 and 17 depict the comparison of the switch-
ing loss observed by CGD and QZS technique at different load
currents. It can be noticed that the achieved switching loss by
the proposed QZS technique is very low compared to the CGD.
However, the switching loss by the QZS technique gradually
increases beyond 20 A at a dc bus voltage of 450 V. Therefore,
the proposed technique is very effective for the inverter in the
SiC MOSFET exhibits very high di/dt and dv/dt. Due to
that, a drop in device voltage and current is experienced dur-
ing switching transients in the presence of parasitic elements
in the circuit. They reduce switching loss in the device. How-
ever, device voltage and current overshoot increase manifold
and they generate stress in the device. Therefore, users prefer to
reduce parasitic elements. This paper proposed a unique QZS
technique to reduce switching loss along with an AGD mech-
anism. It enables users to coexist with a moderate amount of
parasitic inductance in the inverter layout and load parasitic
capacitance simultaneously reducing switching loss. The pro-
posed QZS technique has been implemented by a CPLD-based
active gate driver. It’s performance is evaluated in a DP test
setup as well as in a 10 kW VSI driving an induction motor.
More than 50% reduction in switching loss has been achieved
by the proposed QZS mechanism compared to the CGD.
NAYAK AND HATUA: PARASITIC INDUCTANCE AND CAPACITANCE-ASSISTED ACTIVE GATE DRIVING TECHNIQUE TO MINIMIZE 8297

APPENDIX [6] S. Hazra et al. “High switching performance of 1700-V, 50-A SiC power
MOSFET over Si IGBT/BiMOSFET for advanced power conversion ap-
A. Effects of Parasitic Inductance and Parasitic plications,” IEEE Trans. Power Electron., vol. 31, no. 7, pp. 4742–4754,
Capacitance on the Device Voltage During Turn-On Jul. 2016.
[7] M. Rodriguez, A. Rodriguez, P. F. Miaja, D. G. Lamar, and J. S. Zuniga,
The following equations have been derived from the switch- “An insight into the switching process of power MOSFETs: An improved
analytical losses model,” IEEE Trans. Power Electron., vol. 25, no. 6,
ing circuit shown in Fig. 1. Equation (A.1) can be written ap- pp. 1626–1640, Jan. 2010.
plying KVL in the power loop. During device current transi- [8] A Tripathi, K. Mainali, S. Madhusoodhanan, A. Yadav, K. Vechalapu, and
tion, Df continues to conduct till device current reaches load S. Bhattacharya, “A MV intelligent gate driver for 15kV SiC IGBT and
10kV SiC MOSFET,” in Proc. IEEE Appl. Power Electron. Conf. Expo.,
current. In this condition, the voltage across Cl (vd ) can be 2016, pp. 2076–2082.
written by (A.2). Equation (A.3) is obtained applying KCL. [9] Y. Mao, Z. Miao, C. M. Wang, and K. D. T. Ngo, “Passive balancing
Equations (A.1)–(A.3) can be used to find icd (A.5) and device of peak currents between paralleled MOSFETs with unequal threshold
voltages,” IEEE Trans. Power Electron., vol. 32, no. 5, pp. 3273–3277,
voltage (vds ) during current rise duration (A.6) May 2017.
[10] V. John, B. S. Suh, and T. A. Lipo, “High performance active gate drive for
vds (t) = Vdc + vd (t) − vlp (t) (A.1) high power IGBTs,” IEEE Trans. Ind. Appl., vol. 35, no. 5, pp. 1108–1117,
Sep./Oct. 1999.
dif (t)
vd (t) = Lf (A.2) [11] Z. Wang, X. Shi, L. M. Tolbert, F. Wang, and B. J. Blalock, “A di/dt
dt feedback-based active gate driver for smart switching and fast overcurrent
protection of IGBT modules,” IEEE Trans. Power Electron., vol. 29, no. 7,
if (t) = Il − id (t) − icd (t) (A.3) pp. 3720–3732, Jul. 2014.
[12] Z. Wang et al.“A high temperature silicon carbide MOSFET
did (t) dicd (t) power module with integrated silicon-on-insulator-based gate drive,”
vds (t) = Vdc − (Lp + Lf ) − Lf (A.4) IEEE Trans. Power Electron., vol. 30, no. 3, pp. 1432–1445,
dt dt
Mar. 2015.
dvds (t) d2 id (t) [13] A. Kadavelugu, S. Bhattacharya, S. H. Ryu, D. Grider, S. Leslie, and
icd (t) = Cl + Cl Lp (A.5) K. Hatua, “Understanding dv/dt of 15 kV SiC N-IGBT and its control
dt dt2 using active gate driver,” in Proc. Energy Convers. Congr. Expo., Sep.
did (t) d2 vds (t) 2014, pp. 2213–2220.
vds (t) = Vdc − (Lp + Lf ) − Lf Cl [14] H. Riazmontazer, A. Rahnamaee, A. Mojab, S. Mehrnami, S. K.
dt dt2 Mazumder, and M. Zefran, “Closed-loop control of switching transition
d3 id (t) of SiC MOSFETs,” in Proc. IEEE Appl. Power Electron. Conf. Expo.,
− Cl Lp Lf . (A.6) 2015, pp. 782–788.
dt3 [15] D. Peftitsis and J. Rabkowski, “Gate and base drivers for silicon carbide
power transistors: An overview,” IEEE Trans. Power Electron., vol. 31,
B. Effects of Parasitic Inductance and Parasitic no. 10, pp. 7194–7213, Oct. 2016.
Capacitance on the Device Current During Turn-Off [16] N. Idir, R. Bausiere, and J. J. Franchaud, “Active gate voltage con-
trol of turn-on di/dt and turn-off dv/dt in insulated gate transis-
At the beginning of the turn-off switching transient, Df re- tors,” IEEE Trans. Power Electron., vol. 21, no. 4, pp. 849–855, Jul.
2006.
mains reverse biased. Therefore, if is zero (B.1). Similar to turn- [17] L. Dulau, S. Pontarollo, A. Boimond, J. F. Garnier, N. Giraudo, and
on instant, (B.2) can be obtained using KVL in power loop. By O. Terrasse, “A new gate driver integrated circuit for IGBT devices
solving (B.1)–(B.3), device current (id ) can be obtained (B.4) with advanced protections,” IEEE Trans. Power Electron., vol. 21, no. 1,
pp. 38–44, Jan. 2006.
if (t) = 0 (B.1) [18] P. J. Grbovic, “An IGBT gate driver for feed-forward control of turn-on
losses and reverse recovery current,” IEEE Trans. Power Electron., vol. 23,
vd (t) = Vdc − vlp (t) − vds (B.2) no. 2, pp. 643–652, Mar. 2008.
[19] P. J. Grbovic, F. Gruson, N. Idir, and P. L. Moigne, “Turn-on performance
dvds (t) d2 id (t) of reverse blocking IGBT (RB IGBT) and optimization using advanced
icd (t) = −Cl − Cl Lp (B.3) gate driver,” IEEE Trans. Power Electron., vol. 25, no. 4, pp. 970–980,
dt dt2 Apr. 2010.
[20] H. Riazmontazer and S. K. Mazumder, “Optically switched-drive-based
id (t) = Il − icd (t) − if (t). (B.4) unified independent dv/dt and di/dt control for turn-off transition of power
MOSFETs,” IEEE Trans. Power Electron., vol. 30, no. 4, pp. 2338–2349,
REFERENCES Apr. 2015.
[21] B. J. Baliga, Fundamentals of Power Semiconductor Devices. New York,
[1] Z. Chen, D. Boroyevich, and R. Burgos, “Experimental parametric study NY, USA: Springer, 2008.
of the parasitic inductance on MOSFET switching characteristics,” in [22] P. Nayak and K. Hatua, “Active gate driving technique for a 1200 V SiC
Proc. Int. Power Electron. Conf., 2010, pp. 164–169. MOSFET to minimize detrimental effects of parasitic inductance in the
[2] P. Nayak, M. V. Krishna, K. Vasudevakrishna, and K. Hatua, “Study of converter layout,” in Proc. IEEE Energy Convers. Congr. Expo., 2016,
effects of parasitic inductances and device capacitances on 1200 V, 35 A pp. 1–8.
SiC MOSFET based voltage source inverter design,” in Proc. IEEE Int. [23] Z. Wang, X. Shi, L. M. Tolbert, and B. J. Blalock, “Switching per-
Conf. Power Electron., Drives Energy Syst., pp. 1–6, Dec. 2014. formance improvement of IGBT modules using an active gate driver,”
[3] Y. Shen, J. Jiang, Y. Xiong, Y. Deng, X. He, and Z. Zeng,“Parasitic in Proc. 28th Annu. Appl. Power Electron. Conf. Expo., Mar. 2013,
inductances effects on the switching loss measutement of power semi- pp. 1266–1273.
conductor devices,” in Proc. IEEE Int. Symp. Ind. Electron., 2006, vol. 2, [24] T. Kim, D. Feng, M. Jang, and V. G. Agelidis, “Common mode
pp. 847–852. noise analysis for cascaded boost converter with silicon carbide de-
[4] J. Wang, H. S. Chung, and R. T. Li, “Characterization and experimental vices,” IEEE Trans. Power Electron., vol. 32, no. 3, pp. 1917–1926,
assessment of the effects of parasitic elements on the MOSFET switching Mar. 2017.
performance,” IEEE Trans. Power Electron., vol. 28, no. 1, pp. 573–590, [25] S. Hazra, S. Madhusoodhanan, G. K. Moghaddam, K. Hatua, and
Jan. 2013. S. Bhattacharya, “Design considerations and performance evaluation
[5] Y. Xiao, H. Shah, T. P. Chow, and R. J. Gutmann, “Analytical modeling and of 1200-V 100-A SiC MOSFET-based two-level voltage source con-
experimental evaluation of interconnect parasitic inductance on MOSFET verter,” IEEE Trans. Ind. Appl., vol. 52, no. 5, pp. 4257–4268,
switching haracteristics,” Proc. IEEE Appl. Power Electron. Conf. Expo., Sep./Oct. 2016.
2004, vol. 1, pp. 516–521.
8298 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 64, NO. 10, OCTOBER 2017
Parthasarathy Nayak (S’15) received the
B.Tech. degree in electrical and electronic en-
gineering from Biju Patnaik University of Tech-
nology, Rourkela, India, in 2011, and the
M.S. degree in electrical engineering from In-
dian Institute of Technology Madras, Chen-
nai, India, in 2016. Since 2016, he has been
working toward the Ph.D. degree in the field
of application of wide band gap devices and
power converter design at the Power Electron-
ics, Microgrids and Subsea Electrical Systems
Center, University of Houston, Houston, TX, USA.
From 2011 to 2013, he was an Operation and Maintenance Engineer
with the Monnet Power Company Ltd., India. His research interests in-
clude gate driver design for SiC MOSFET, high power density converter
design, ac–dc power conversion, and multilevel converter topologies.
Kamalesh Hatua (M’16) received the B.E.
degree in electrical and electronic engineer-
ing from Karnataka Regional Engineering Col-
lege, Surathkal, India, in 2000, the M.Sc. and
Ph.D. degrees, both in electrical engineering,
from the Indian Institute of Science Bangalore,
Bangalore, India, in 2004 and 2011, respectively.
He was with Bharat Earth Movers Ltd.,
Mysore, India, during 2000–2001. He was in-
volved in the development of computerized
transmission controller for dumpers. He was also
with the Honeywell Technology Solutions Laboratory, Bangalore, for
the development of inverter for aerospace applications during 2004–
2005. He has extensively worked for aerospace grade inverter develop-
ment, EMI/EMC-related issues, and their mitigation techniques. After the
Ph.D. degree, he was a Postdoctoral Research Fellow with Future Re-
newable Electrical Energy Delivery and Management Center, North
Carolina State University Raleigh, for the development of SiC device-
based solid-state transformer during 2010–2012. He is currently an As-
sistant Professor in the Department of Electrical Engineering, Indian
Institute of Technology Madras, Chennai, India. His area of research in-
terests include medium-voltage electric drives, polyphase induction mo-
tor drive, solid-state transformer, power electronics application in power
system, design of high-efficient power converters using upcoming SiC
power switches, and DSP- and FPGA-based controller design for power
electronics application.