CMOS Electrical Characteristics

Power-delay product
¾Figure of merit to determine
•Power-delay product quality of a digital gate
¾Power-delay product PDP:
•Latch-up measures the energy of the
•Hot carriers gate [W.s=J]

•Electromigration
•Sheet resistance
¾PDP stands for the average
•Parasitic capacitances energy consumed per
switching event

CMOS CMOS

Power-delay product Latch-up

¾Assuming that the gate is switched at its maximum
possible rate fmax Pav ¾MOS technology contains intrinsic bipolar transistors
PDP =
tp=(tpHL+tpLH)/2 2 f max ¾in CMOS processes, combination of wells and
substrates results in parasitic n-p-n-p structures.
¾In high frequencies, power dissipation dominated by
capacitive load CL
¾ignoring contributions of static and direct-path currents:

¾The design goal is to minimize PDP, in order to get low

power in high frequencies
¾Thus it is important to decrease VDD but it is extremely
important to decrease the load capacitance CL

CMOS CMOS

1
 Latch-up Hot carriers
¾Triggering these SCR-like devices ⇒ short circuit ¾ Small dimension MOSFET
between VDD and VSS suffers from hot-carrier effect
¾Consequence: destruction of the chip, or at best ¾ High velocity electrons leave
system failure (can solved by power-down) the silicon and tunnel into the
gate oxide
¾To avoid latch-up: ¾ Electrons trapped in oxide
9Keep low temperatures and low VDD (temperature change threshold voltage VT:
increases bipolar gain and leak currents ) ƒ NMOS: VTN ⇑
ƒ PMOS: |VTP| ⇓

9Decrease Rnwell and Rpsubs ⇒ well and substrate ¾ Can cause permanent dammage
to the device
contacts close to the source of NMOS/PMOS
¾ Sensible to Temperature and VDD

CMOS CMOS

Electromigration Electromigration example

● Metal wire can tolerate only a certain amount of

current density.
● Direct current for a long time causes ion
movement breaking the wire over time.
● Contacts are more vulnerable to
electromigration as the current tends to run
through the perimeter.
● Possible solutions:
» Make wire cross section wider⇒increase width/depth
(reduce current density)
A contact (via) broken up due
» Use of copper instead of Al (heavier ions) A wire broken off due to electromigration
to electromigration
These figures are derived from Digital integrated circuit – a design perspective, J. Rabaey Prentice Hall

CMOS CMOS

2
 Current limits Sheet resistance RS
● Resistivity of materials are given
● Electromigration in ohms/square (Ω/□)
● Easier way to compute resistance
● Power density: heating due to Joule effect due to uniform depth of
conducting/semiconducting layers
● To calculate the resistance of a
● Respect max current densities to each layer line:
(specified by the technology design rules) » Divide the line in squares
» Multiply the number of squares by
the given value of RS in Ω/□

CMOS CMOS

Delay in the Presence of (Long)

Parasitic capacitances Interconnect Wires
● Conducting lines over substrate or
crossing forms parasitic capacitances
● Can be very important for long lines
● Increase power dissipated and PDP tpHL = f(R on.CL)
= 0.69 R onCL

● To calculate the capacitance of two

crossing lines: ln(0.5)

» Calculate the total crossing area

» Multiply by the given value of C per
area in µF/µm2

CMOS CMOS