MOS Inverters: Switching Characterstics and Interconnect Effects

SWITCHING CHARACTERSTICS OF CMOS AND

DELAY – TIME CALCULATIONS

1. INTRODUCTION
In this topic we are going learn about the dynamic (time-domain) behavior of the inverter
circuits. The switching characteristics of digital integrated circuits and, in particular, of inverter
circuits, essentially determine the overall operating speed of digital systems.
Consider the cascade connection of two CMOS inverter circuits shown Fig:6.1. The parasitic
capacitances associated with each MOSFET are illustrated individually. Here, the capacitances
Cgs and Cgs are primarily due to gate overlap with diffusion, while Cdb and Csb are voltage-
dependent junction capacitances. The capacitance component Cg is due to the thin-oxide
capacitance over the gate area. In addition, we also consider the lumped interconnect capacitance
Cint, which represents the parasitic capacitance contribution of the metal or polysilicon
connection between the two inverters.

It is assumed that a pulse waveform is applied to the input of the first-stage inverter. We wish to
analyze the time-domain behavior of the first-stage output, Vout. The problem of analyzing the
output voltage waveform is fairly complicated, even for this relatively simple circuit, because a
number of nonlinear, voltage-dependent capacitances are involved.

Fig:6.1 Cascaded Inverters

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MOS Inverters: Switching Characterstics and Interconnect Effects

To simplify the problem, we first combine the capacitances seen in Fig:1 into an equivalent
lumped linear capacitance, connected between the output node of the inverter and the ground.
This combined capacitance at the output node will be called the load capacitance, Cload.

Cload = Cgd,. + Cgdp + Cdb,,n + Cdbp + Cint + Cg (6.1)

Note that some of the parasitic capacitance components shown in Fig:6.1 do not appear in this
lumped capacitance expression.
In particular, Csbn and Csbp have no effect on the transient behavior of the circuit since the
source-to-substrate voltages of both transistors are always equal to zero. The capacitances Cgsn
and Cgsp are also not included in equation (6.1) because they are connected between the input
node and the ground (or the power supply).The capacitance terms Cdbn and Cdbp in Fig:6.1 are
the equivalent junction capacitances calculated for a particular output voltage transition.

The first-stage CMOS inverter is shown with the single lumped output load capacitance Cload in
Fig:6.2. Now, the problem of analyzing the switching behavior can be handled more easily. In
fact, the question of inverter transient response is reduced to finding the charge-up and charge-
down times of a single capacitance which is charged and discharged through one transistor. The
delay times calculated using Cload may slightly overestimate the actual inverter delay, but this is
not considered a significant deficiency in a first-order approximation.

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MOS Inverters: Switching Characterstics and Interconnect Effects

2. Delay-Time Definitions
The input and output voltage waveforms of a typical inverter circuit are shown in Fig. 6.3. The
propagation delay times TpHL and TpLH determine the input-to-output signal delay during the
high-to-low and low-to-high transitions of the output, respectively. By definition, TpHL is the
time delay between the V50%-transition of the rising input voltage and the V50 -transition of the
falling output voltage. Similarly, TpLH is defined as the time delay between the V50% -
transition of the falling input voltage and the V50%-transition of the rising output voltage.

To simplify the analysis and the derivation of delay expressions, the input voltage waveform is
usually assumed to be an ideal step pulse with zero rise and fall times. Under this assumption,
TpHL becomes the time required for the output voltage to fall from VOH to the V10% level,
and TpLH becomes the time required for the output voltage to rise from VOL to the V50% level.
The voltage point V50% is defined as follows.

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MOS Inverters: Switching Characterstics and Interconnect Effects

V50% = VOL + 1/2(VOH VOL)=1/2( VOL + VOH) (6.2)

Thus, the propagation delay times TpHL and TpLH are found from Fig. 6.3 as

TpHL = t1 - to
TpLH = t3 - t2 (6.3)

The average propagation delay Tp of the inverter characterizes the average time required for the
input signal to propagate through the inverter.

Tp = ( TpHL + TpLH)/2 (6.4)

We will refer to Fig. 6.4 for the definition of output voltage rise and fall times. The rise time
Trise is defined here as the time required for the output voltage to rise from the V10% level to
Vg90% level. Similarly, the fall time Tfall is defined here as the time required for the output
voltage to drop from the V90% level to Vl0% level. The voltage levels Vl0% and V90% are
defined as

V10% = VOL +0.1 (VOH - VOL) (6.5)

V90% = VOL +0.9(VOH – VOL) (6.6)

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MOS Inverters: Switching Characterstics and Interconnect Effects

Thus, the output rise and fall times are found from Fig. 6.4 as follows.
Tfall = tB- tA
Trise =tD-tC (6.7)

Note that other delay definitions using 20% and 80% voltage levels have also been used.

3. Calculation of Delay Times

The simplest approach for calculating the propagation delay times TpHL and TpLH is based on
estimating the average capacitance current during charge down and charge up, respectively. If
the capacitance current during an output transition is approximated by a constant average current
Iavg the delay times are found as

Note that the average current during high-to-low transition can be calculated by using the current
values at the beginning and the end of the transition.
While the average-current method is relatively simple and requires minimal calculation, it
neglects the variations of the capacitance current between the beginning and end points of the
transition. Therefore, we do not expect the average-current method to provide a very accurate
estimate of the delay times. Still, this approach can provide rough, first-order estimates of the
charge-up and charge-down delay times.

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MOS Inverters: Switching Characterstics and Interconnect Effects

The propagation delay times can be found more accurately by solving the state equation of the
output node in the time domain. The differential equation associated with the output node is
given below. Note that the capacitance current is also a function of the output voltage.

Cload (dVout/dVin) = iC= iDp - iDn (6.12)

First, we consider the rising-input case for a CMOS inverter. Initially, the output Voltage is
assumed to be equal to VOH. When the input voltage switches from low (VOL) to high (VOH),
the nMOS transistor is turned on and it starts to discharge the load capacitance. At the same time,
the pMOS transistor is switched off thus,

The circuit given in Fig. 6.2 can now be reduced to a single nMOS transistor and a capacitor, as
shown in Fig. 6.5. The differential equation describing the discharge event is then

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MOS Inverters: Switching Characterstics and Interconnect Effects

Note that in other types of inverter circuits, such as the resistive-load inverter or the depletion-
load inverter, the load device continues to conduct a nonzero current when the input is switched
from low to high. However, the load current is usually negligible in comparison to the driver
current. Therefore, (6.14) can be used to calculate the charge down time not only in CMOS
inverters, but also in almost all common types of inverter circuits.

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MOS Inverters: Switching Characterstics and Interconnect Effects

The, input and output voltage waveforms during this high-to-low transition are illustrated in Fig.

6.6. When the nMOS transistor starts conducting, it initially operates in the saturation region.
When the output voltage falls below (VDD - VT), the nMOS transistor starts to conduct in the
linear region. These two operating regions are also shown in Fig. 6.6. First, consider the nMOS
transistor operating in saturation.
Since the saturation current is practically independent of the output voltage (neglecting channel-
length modulation), the solution of (6.14) in the time interval between to and tl' can be found as

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MOS Inverters: Switching Characterstics and Interconnect Effects

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MOS Inverters: Switching Characterstics and Interconnect Effects

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MOS Inverters: Switching Characterstics and Interconnect Effects

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MOS Inverters: Switching Characterstics and Interconnect Effects

All of the delay time derivations in this section were made under the simplifying assumption that
the input signal waveform is a step pulse with zero rise and fall times. Now, we consider the case
where the input voltage waveform is not an ideal (step) pulse waveform, but has finite rise and
fall times. The exact calculation of the output voltage delay times is more complicated under this
more realistic assumption, since both the nMOS transistor and the pMOS transistor conduct
current during the charge-up and charge-down events. To simplify the estimation of the actual
propagation delays, we can utilize the propagation delay times calculated under the step-input
assumption, using the following empirical expressions:

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MOS Inverters: Switching Characterstics and Interconnect Effects

Here, TpHL(step input) and TpLH(step input) denote the propagation delay time values
calculated assuming a step pulse input waveform at the input, i.e., using (6.22b) and (6.23b).
While the expressions given above are purely empirical, they provide a simple estimation of how
much the propagation delays are increased as a result of non-zero input rise and fall times.

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