by
Laboratory Manual
Issued with Labs 1, 2, 3, 4
Last Updated: September 21, 2018
McMaster University
Department of Electrical and Computer Engineering
Faculty of Engineering
Hamilton, Ontario, Canada
Set in LATEX 2ε .
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ii
Abstract
The Laboratory Manual, which complements the course’s textbook and notes, defines
the scope, content, timing and academic standards in the laboratory component of
the Computer Engineering Logic Design (2DI4) course. Guidelines are included that
provide information on the expected form and content of the laboratory reports.
Although care has been taken to make the Manual reasonably accurate and helpful,
it should be stressed that no document can cover all the situations encountered in
engineering work.
iii
Contents
Abstract iii
Contents iv
List of Figures 1
1 Overview 3
1.1 Calendar Description of the Course . . . . . . . . . . . . . . . . . . . 3
1.2 Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.3 Laboratory Schedule . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
iv
2.7 Note Regarding Pre-Lab/Lab Format . . . . . . . . . . . . . . . . . . 16
2.8 Submission Requirements . . . . . . . . . . . . . . . . . . . . . . . . 16
2.9 TA Grading Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
v
5.4 Integrated Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
5.5 Experiment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
5.5.1 The Versatile Flip-Flop: JK . . . . . . . . . . . . . . . . . . . 39
5.5.2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
5.5.3 Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
5.5.4 EPROM: Erasable Programmable Read Only Memory . . . . 44
5.6 Submission Requirements . . . . . . . . . . . . . . . . . . . . . . . . 46
5.7 TA Grading Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
vi
List of Tables
vii
List of Figures
5.1 The JK FF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
5.2 A Shift Register Implementation . . . . . . . . . . . . . . . . . . . . . 41
5.3 A Shift Register Implementation in Schematic Capture . . . . . . . . 41
5.4 A Circular Shift Register Implementation . . . . . . . . . . . . . . . . 42
5.5 A Circular Shift Register Implementation in Schematic Capture . . . 42
5.6 A Synchronous Up-Counter Implementation . . . . . . . . . . . . . . 43
5.7 A Synchronous Up-Counter Implementation in Schematic Capture . . 43
5.8 An EPROM Circuit Implementation . . . . . . . . . . . . . . . . . . 45
1
2
Overview
Binary numbers and codes; Boolean algebra; combinational circuit design; elec-
trical properties of logic circuits; sequential circuit design; computer arithmetic; pro-
grammable logic; CPU organization and design
Three lecture hours, one tutorial, one lab every other week; first term
3
Chapter 1. Overview 4
1.2 Evaluation
The final mark in the Digital Logic Design (2DI4) course consists of the components
listed in the 2DI4 course outline. The laboratory component of the course mark is
determined as specified in table 1.1.
Laboratory exercises may offer bonus mark(s) for extra and/or advanced work
by the student. The bonus mark(s) will only apply to lab reports that make a
clear attempt to meet all non-bonus criteria (including pre-lab). For example, by
not attempting to answer a question from the Laboratory Prelab section, the bonus
mark(s) will not be considered in evaluation of the exercise. It should also be noted,
although the bonuses may make it possible to achieve greater than 100% in the
laboratory component of CoE 2DI4, the maximum grade assigned to the laboratory
component will not be greater than 100%.
It should be stressed that due to high course enrolment, students shall not be
admitted to other laboratory sessions than those assigned.
Please enter and exit the lab punctually and pay close attention to the time
limits your TAs give you for submitting your lab exercises. Failure to have your lab
execution checked because the lab time expired may result in a 0 for the lab - TAs are
instructed to not accept/review work that is late.. Failure to exit the lab punctually
may result in being assigned an automatic zero for the entire lab exercise.
Chapter 2
2.1 Objective
To introduce fundamental concepts of digital logic gates and laboratory techniques.
(a) AND,
(b) OR,
(c) NAND,
(d) NOR,
(e) XNOR, and
(f) XOR.
2. In the context of 2DI4, define the term “Logical equivalence” and provide an
example [2].
6
Chapter 2. Laboratory #1: Logic Gates 7
Obtain the data sheets for each of the above TTL devices. Familiarize yourself
with their logical and electrical characteristics and bring a copy to your lab session.
2.4 Experiment
Read the following experiment and study the circuits as shown. Pre-filling your re-
port with the necessary truth tables and structuring your report such that you only
need record experimental output will allow you to focus on the experiment(s).
(a)
(b)
(c)
(d)
(e)
6. The output of the 2-input XOR gate is HI when its inputs are different and LO
otherwise. Verify the truth table for the XOR gate and explain how it could
also be considered to be a ”controllable inverter”.
(a)
7. Parity bits are commonly used to detect errors in serial communications and
memory access. A binary number is said to have odd parity if the number of
1’s contained in it is odd; it has even parity when the number of 1’s is even.
This may be detected using an XOR gate circuit such as the one shown. Build
the following circuit to verify that the output FP arity is HI when the parity of
Chapter 2. Laboratory #1: Logic Gates 12
the input word wxyz is odd and LO otherwise. Draw the corresponding truth
table.
(a)
Note: this idea is readily extended to produce a circuit that compares the
magnitude of input numbers. For example the SN74LS85 takes two 4-bit inputs
A and B, and produces three outputs that indicate A = B, A > B or A < B.
(a)
Pulse Generator
9. Build the circuit as shown below. For the input apply 100Hz square wave
(carefully verifying that it is 5V peak-to-peak with 2.5V DC offset using
the oscilloscope) to the clock input. Display the input signal on channel 1 of the
oscilloscope. Display the output signal (Fdelay ) on channel 2 of the oscilloscope
and explain the result. For your report you can carefully draw or photograph
the two wave forms and clearly label the axis, oscilloscope channels, pulse Fdelay
(channel 2) relative to the edges of the input waveform (channel 1), and the
total pulse delay. Before disconnecting this circuit, ensure you have noted the
Discussion requirement in section 2.5.
Milestone 4: TA to check 9b. [15 marks]
(a) Provide a clear sketch of both clock input and Fdelay . Label your axes.
(b) Comparing these two waveforms, what would you estimate for the tdelay .
(c) Vary the number of inverters in the circuit and state the effect.
(d) Replace the NAND gate in this circuit with an XOR gate and explain the
observed output.
Chapter 2. Laboratory #1: Logic Gates 14
Oscillator
10. Connect a series of 4 inverters plus a NAND gate (as shown below) and display
the output Foscillator on the oscilloscope. An odd number of inversions back-
to-back will produce an oscillator with a period equal to twice the delay of the
inverter chain.
Milestone 5: TA to check 10b. [15 marks]
(a) Measure and clearly state the time for 1/2 of one cycle of this circuit using
the automatic measurement functions of the oscilloscope.
(b) How does this measured time compare to parameters tP LH and tP HL from
the sn74LS00 data sheet? State tP LH and tP HL .
Chapter 2. Laboratory #1: Logic Gates 15
1. 3
2. 4e
3. 5
4. 9b
5. 10b
1. At the beginning of each lab you are to have your Pre-Lab checked for com-
pletion by a TA.
2. Your lab report has a cover page clearly indicating the lab title, date, each
member’s name, and student number.
5. One member has uploaded the lab report to Avenue (ensuring both have a
copy for future reference).
Chapter 2. Laboratory #1: Logic Gates 18
Deductions
Final Score
Chapter 3
3.1 Objective
To introduce fundamental concepts of combinational logic and circuit design.
2. Define the term encoder and provide an example of where one would be used
in a digital system (not a software system/application).[2 marks]
3. Define the term decoder and provide an example of where one would be used
in a digital system (not a software system/application).[2 marks]
4. Define the term binary coded decimal and provide an example of where one
would be used in a digital system.[2 marks]
5. Minimize the following Boolean function and draw the circuit diagram (use
logic symbols) using only NAND gates (HINT: DeMorgan’s Theorem is re-
quired here).
19
Chapter 3. Laboratory #2: Combinational Logic 20
P
F (a, b, c, d) = (0, 2, 5, 7, 8, 10, 13, 15)
Obtain the data sheets for each of the above TTL devices. Familiarize yourself
with their logical and electrical characteristics and bring a copy to your lab session.
3.4 Experiment
Read the following experiment and study the circuits as shown.
Chapter 3. Laboratory #2: Combinational Logic 21
REQUIRED: Pre-filling your report with the necessary truth tables, ta-
bles, circuit diagrams, etc. and structuring your report such that you
only need record experimental observations will allow you to focus on the
experiment(s). Failing to do this will result in an incomplete lab.
3. The fundamental circuit for computation is the half adder. Figure 3.2 illustrates
the half-adder combinational logic circuit. The output S is the sum of inputs
A and B, where Cout represents a carry out. Build this circuit and verify the
truth table. Use switches for inputs and LEDs for output(s).
A better approach is to form the sum and carry out in a parallel arrangement,
such as the arrangement of the 74LS283. The 74LS283 is a 4-bit parallel adder
with internal carry look-ahead. Review the data sheet for this IC and note the
internal configuration of gates.
Chapter 3. Laboratory #2: Combinational Logic 24
Verify the operation of the 74LS283 by wiring the IC and completing the table
below. Use switches for inputs and LEDs for output(s). Clearly record the
output as unsigned and as signed 2’s complement.
6. A parallel adder may be used to add or subtract 4-bit numbers. Given the
following arrangement , when S=0 the output is A+B. When S=1, the output
is A-B. Construct and verify this circuit. Explain the operation (hint: what
are S and the XORs doing?).
Note that this adder/subtractor may be used to take the 2’s complement of an
input B by setting A=0000 and S=1. Verify this for several test cases. This
feature will be used in a following circuit so do not disconnect this circuit.
Milestone 3: TA to check 6
Chapter 3. Laboratory #2: Combinational Logic 25
7. The seven-segment display is an easy and very common way to display decimal
numbers from binary codes. Each segment of the display is lit by pulling
the input to the display LO. The 74LS47 BCD to 7-segment encoder will
drive the display with the correct current-limiting requirements. NEVER
CONNECT THE DISPLAY INPUTS TO GROUND OR +5V - YOU
WILL DESTROY THE DEVICE. Connect the circuit as shown below
and leave this circuit connected for use in a following circuit. However, before
proceeding you should connect the 4 BCD inputs to 4 sequential toggle switches
Chapter 3. Laboratory #2: Combinational Logic 26
8. Connect the output of the adder/subtractor circuit from section 3.4.6 to the
input of of the 74LS47 BCD to 7-segment encoder circuit from section 3.4.7.
Milestone 4: TA to check 8
1. At the beginning of each lab you are to have your Pre-Lab submitted no later
than 2:45pm.
2. Your lab report has a cover page clearly indicating the lab title, date, each
member’s name, and student number.
5. One report uploaded per 2-member team. Please ensuring both team members
have a copy for future reference.
Chapter 3. Laboratory #2: Combinational Logic 29
Deductions
Final Score
Chapter 4
4.1 Objective
To introduce fundamental concepts of combinational logic and circuit design. To
demonstrate the use of a commercial Programmable Logic Device (PLD) design
package for schematic and Verilog entry. To introduce the design process for combi-
national logic in a Complex Programmable Logic Device (CPLD) device.
4.2 Resources
You will need the following resources to complete this lab:
1. Software: Quartus II Web Edition versions 9.0 (available in lab and can be
downloaded free from Altera)
2. Reference: ftp://ftp.altera.com/up/pub/Altera_Material/9.0/Tutorials/
Verilog/
3. Introduction: ftp://ftp.altera.com/up/pub/Altera_Material/9.0/Tutorials/
Verilog/Quartus_II_Introduction.pdf
30
Chapter 4. Laboratory #3: Programmable Logic 31
Obtain the data sheets for each of the above devices. Familiarize yourself with
their logical and electrical characteristics and bring a copy to your lab session.
4.5 Experiment
Read the following experiment and study the circuits as shown.
REQUIRED: Pre-filling your report with the necessary truth tables, ta-
bles, circuit diagrams, etc. and structuring your report such that you
only need record experimental observations will allow you to focus on the
Chapter 4. Laboratory #3: Programmable Logic 32
1. Verify the function table for the sn74LS138 is a 3-to-8 line decoder from Table
4.6 of your textbook (Truth Table of a Three-toEight-Line Decoder). Use
switches for X, Y, Z selects and LEDs for the outputs. Refer to the data sheet
for handling the enable pins.
Referring to your textbook, find the truth table and logic expression for a full
adder (see Table 4.4). “Program” this full-adder circuit such that F1 represents
the sum (S) and F2 represents the carry (C). Mark every connected row-column
intersection with an X. Build the circuit and verify operation. (hint: consider
how DeMorgan’s can help here).
Milestone 2: TA to check 2
point. Using Quartus II define a 3-to-8 Line Decoder, compile your model and load
it on to the CPLD. For inputs connect wires from toggle switches to CPLD inputs.
For outputs connect CPLD outputs to LEDs.
For your report, include a screen capture of your modelling – ensure all team
member names and student numbers appear in the comments of the Verilog model
text.
1. At the beginning of each lab you are to have your Pre-Lab submitted no later
than 2:45pm.
Chapter 4. Laboratory #3: Programmable Logic 35
2. Your lab report has a cover page clearly indicating the lab title, date, each
member’s name, and student number.
5. One report uploaded per 2-member team. Please ensuring both team members
have a copy for future reference.
Chapter 4. Laboratory #3: Programmable Logic 36
Deductions
Final Score
Chapter 5
5.1 Objective
To apply the design process for combinational logic in a Complex Programmable
Logic Device (CPLD) device. To study the behaviour and application of sequential
circuits.
5.2 Resources
You will need the following resources to complete this lab:
1. Software: Quartus II Web Edition versions 9.0 (available in lab and can be
downloaded free from Altera)
2. Reference: ftp://ftp.altera.com/up/pub/Altera_Material/9.0/Tutorials/
Verilog/
3. Introduction: ftp://ftp.altera.com/up/pub/Altera_Material/9.0/Tutorials/
Verilog/Quartus_II_Introduction.pdf
37
Chapter 5. Laboratory #4: Programmable & Sequential Logic 38
Obtain the data sheets for each of the above devices. Familiarize yourself with
their logical and electrical characteristics and bring a copy to your lab session.
Chapter 5. Laboratory #4: Programmable & Sequential Logic 39
5.5 Experiment
Read the following experiment and study the circuits as shown.
REQUIRED: Pre-filling your report with the necessary truth tables, ta-
bles, circuit diagrams, etc. and structuring your report such that you
only need record experimental observations will allow you to focus on the
experiment(s). Failing to do this will result in an incomplete lab.
1. Verify the behaviour of the JK flip-flop by wiring up the IC and compare against
the characteristic table (inputs are toggle switches, output LEDs). Make note
of the following: i) is this device rising edge, falling edge, or a level trigger, ii)
what does the preset do, and iii) what does the clear do?
Chapter 5. Laboratory #4: Programmable & Sequential Logic 40
2. Modify your circuit from part-1 by using a single input toggle switch connected
to J and K. Compare to the characteristic table of a T flip-flop.
3. Modify your circuit from part-1 by using a single input toggle switch connected
to J with an inverter from J to K. Compare to the characteristic table of a D
flip-flop.
5.5.2 Registers
A register is a group of n flip-flops operating together to represent an n-bit binary
number. Each flip-flop represents a single bit. The simplest form of a register is used
to capture its input(s) and hold the value (e.g., the D flip-flop) in response to the
write command (a clock pulse). A common application in using registers is to shift
their content by one bit left or right. A left shift, moving all bits one position to the
left, has the effect of multiplying the content value by 2. Conversely, a right shift
has the effect of dividing the content value by 2.
For the implementation of these registers, please design the circuit using schematic
capture in the Quartus II IDE. Load each circuit onto the MAX3000 chip and test
with toggles switches and LEDs. Note that switches 12 15 are de-bounced.
1. There are a number of way to connect flip-flops in series to create shift registers.
Figure 5.2 illustrates a simple left-to-right shift register. Note it is constructed
using JK’s in such a way they operate like D flip-flops. Implement the cir-
cuit as shown in the HDL and load onto the CPLD. Tie your preset values
HI and experiment with this circuit sing a very low clock frequency supplied
by the physical bench top function generator (Alternatively you could use a
toggle switch to simulate the clock). Observe the register bit output patterns
(Q3 Q2 Q1 Q0 ) on LEDs. Remember to also use the toggle switches to input the
clear and serial data signals. If the HDL model of the flip-flop does not provide
a Q’ output then implement one using an inverter off of Q.
2. Modify your Shift Register circuit as shown in figure 5.4 to implement a circular
shift capability by connecting the Q0 output back to the input through an OR
gate. You will also find this implementation referred to as a ring counter.
Milestone 1: TA to check Circular Shift register operation
Chapter 5. Laboratory #4: Programmable & Sequential Logic 41
5.5.3 Counters
As we have a focus on synchronous sequential logic, you will only be required to build
a synchronous counter. However, the student is should be aware that there exist
Chapter 5. Laboratory #4: Programmable & Sequential Logic 42
many asynchronous counter designs which can cause difficulties due to intermediate
false outputs caused by time delays. Using HDL implement the synchronous counter
from figure 5.6. The counter from figure 5.6 is a better design because all flip-flops
Chapter 5. Laboratory #4: Programmable & Sequential Logic 43
receive a common clock pulse. Verify the timing and operation using the timing
diagram provided, Note: count enable can freeze the clock count, and clock transition
occur on rising edge.
Increase the clock frequency to 100KHz and record the frequency at each output.
Chapter 5. Laboratory #4: Programmable & Sequential Logic 44
The 2732A contains the binary to BCD conversion look-up table (LUT). A binary
Chapter 5. Laboratory #4: Programmable & Sequential Logic 45
number is applied to the address inputs (A0 – A7 ) and the equivalent BCD number is
read from the output. Given we have 8 output lines we can store 00-99 BCD values
for which we will require 7 bits (A0 – A6 ). The first 100 locations from address 0000
0000 0000 to 0000 0110 0011 of the EPROM are used for the binary-to-BCD LUT.
Verify the operation of the device and the conversion.
Milestone 3: TA to check EPROM Binary-to-BCD operation
Access time for peripheral digital devices is always a concern to the digital de-
signer. When the CE and OE lines are tied LO, the one way to calculate this
EPROM’s access time tACC is the delay between i) the application of an address
input, and ii) the appearance of stable data input outputs. Configure the EPROM
circuit as shown in figure 5.9 and observe the output from pin O1 on the oscilloscope.
Using this waveform, estimate the actual tACC for the 2732A EPROM. Sketch and
explain your observations.
1. At the beginning of each lab you are to have your Pre-Lab submitted no later
than 2:45pm.
2. Your lab report has a cover page clearly indicating the lab title, date, each
member’s name, and student number.
5. One report uploaded per 2-member team. Please ensuring both team members
have a copy for future reference.
Deductions
Final Score