1100
6, NOVEMBER 2012
Optimized Design of a 32-nm CNFET-Based
Low-Power Ultrawideband CCII
Ale Imran, Member, IEEE, Mohd. Hasan, Member, IEEE, Aminul Islam, Member, IEEE,
and Shuja Ahmad Abbasi, Senior Member, IEEE
Abstract—CMOS technology faces significant challenges like
tunneling effect, random dopant fluctuation, and line edge rough-
ness at channel lengths below 45 nm. Carbon nanotube-based elec-
tronics seems to be a better prospect for extending the saturating
Moore’s law because of its higher mobility, scalability, and better
channel electrostatics. This paper presents an optimum design of
a wide bandwidth, high-performance carbon nanotube field-effect
transistor (CNFET) realization of a dual-output second-generation
current conveyor (CCII±) at a 32-nm technology node. The per-
formance of the CCII module has been thoroughly investigated
in terms of number of carbon nanotubes (CNTs), the diameter of
CNT and inter-CNT pitch. The parameters of individual CNFET
are then modified to further improve the performance. The per-
formance of the optimum CNFET (ITOPT)-based CCII is then
compared with CMOS at different supply voltages. It has been
found that CNFET-based CCII provides excellent high-frequency
response and also consumes lower power at scaled supply voltage
compared with its CMOS counterpart.
Index Terms—Carbon nanotube (CNT), carbon nanotube field-
effect transistor (CNFET), current conveyor, current mode circuits,
nanoelectronics.
I. INTRODUCTION
HE last decade has witnessed tremendous growth in the
T field of current-mode (CM) analog-signal processing. In
CM operation, the circuit response is described in terms of cur-
rent rather than voltage. The use of current, rather than voltage
as the active variable in the whole circuit (or in part), offers an
elegant solution for various circuit- and system-based problems.
Generally, CM circuits exhibit better high-frequency response,
have simpler architecture, provide better dynamic range, and
operate at lower voltages than their voltage-mode counterparts.
Another important reason for the fast development in CM cir-
cuits is the recent availability of attractive integrated devices like
Manuscript received September 29, 2011; accepted July 12, 2012. Date of
publication August 8, 2012; date of current version November 16, 2012. This
work was supported by the Comprehensive National Plan for Science, Technol-
ogy and Innovation, King Saud University, Riyadh, Saudi Arabia, under Grant
09-ELE854-0. The review of this paper was arranged by Associate Editor S. D.
Cotofana.
A. Imran and M. Hasan are with the Department of Electronics Engi-
neering, Aligarh Muslim University, Aligarh 202002, India (e-mail: aleimran.
amu@gmail.com; mohd.hasan@amu.ac.in).
A. Islam is with the Department of Electronics and Communication Engi-
neering, Birla Institute of Technology, Mesra, Ranchi 835215, India (e-mail:
aminulislam@bitmesra.ac.in).
S. A. Abbasi is with the Department of Electrical Engineering, King Saud
University, Riyadh 11421, Saudi Arabia (e-mail: abbasi@ksu.edu.sa).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TNANO.2012.2212248
1536-125X/$31.00 © 2012 IEEE
IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 11, NO.
current feedback amplifier (CFA), current differencing buffered
amplifier (CDBA), current differencing transconductance am-
plifier (CDTA) for an analog circuit design. However, among all
CM devices, a dual-output second-generation current conveyor
(CCII±) by far is the most popular one. A current conveyor is
basically a CM device that conveys (transfers) current with unity
gain from an input port to an output port. It is widely considered
as the op amp equivalent in CM analog signal processing and
finds wide range of applications in realizing amplifiers, differ-
entiators, impedance converters, integrators, filters, oscillators,
etc. [1]–[4]. The performance of the current conveyor is charac-
terized by its voltage and current following behaviors.
In the past many decades, CMOS technology has played an
instrumental role in driving the world economics and scaling
down of size has been the fundamental strategy for improving
the performance of the device. However, ITRS suggests that by
2016, the gate length of the MOSFET will be less than 10 nm
and at these nanoscale regimes both the fundamental limits and
the technological challenges are going to be encountered [5]. In
addition to that problems like process variations, extreme short-
channel effects, leakage current, high field effect, lithographic
limits and quantum confinement effect will have significant im-
pact on the MOSFET’s functioning. Therefore, it is extremely
imperative to find new, molecular-scale devices that could com-
plement the existing silicon platform by providing it with new
capabilities or that might even replace existing silicon CMOS
technology and allow device scaling to continue to the atomic
scale [6].
It is a well-known fact that the last few years have witnessed
significant increase in nanoelectronics research, where many
possibilities are appearing in the form of various device struc-
tures such as multigate field-effect transistor (FET), FinFET,
nanowire FET, etc., to name a few. However, among all these,
carbon nanotubes (CNTs) is generally considered to be the most
promising nanostructured material for realizing nanoelectronic
transistors because of its ballistic transport capability, very nar-
row diameter of the order of few nm, possible engineering of
electronic properties and high current carrying capacity [7].
A carbon nanotube field-effect transistor (CNFET) is a three-
terminal device which consists of a semiconducting nanotube
bridging two contacts (source and drain) and acting as a carrier
channel, which is turned ON or OFF electrostatically via the
third contact, i.e., gate. It was first fabricated in 1998 and since
then it has come a long way.
A CNFET has the potential of taking over in the post silicon
era due to its exceptional electrical and structural characteristics,
such as quasi 1-D (ballistic) transport of electrons (and equally
IMRAN et al.: OPTIMIZED DESIGN OF A 32-nm CNFET-BASED LOW-POWER ULTRAWIDEBAND CCII 1101

likely for holes), higher drive current (three to four times than
MOSFETs), large transconductance (four times), low intrinsic
capacitance, near ideal subthreshold slope, high temperature
resilience and strong covalent bonding [8]. Moreover, the device
structure and the operating principle of CNFET are quite similar
to the existing CMOS and it can also be fabricated by utilizing
the existing CMOS infrastructure.
Significant research work has already been carried out in Fig. 1. General structure of CCII±.
the digital domain using the emerging CNFET technology.
Full adders, multiplexers, memory (SRAM), LUTs, etc., imple-
mented using CNFET, are available in the literature [9]–[12].
However, the design of analog modules like OTA, current con-
veyor, etc. in CNFET technology still remains an unexplored
territory. This paper presents the design of a high-performance
dual-output current conveyor module and investigates its design
metrics at 32-nm technology node. It is to be noted that to the
best of our knowledge, no previous work has been reported in
the literature on the performance of a CNFET-based current
conveyor. This paper makes the following contributions.
1) In view of the aforesaid requirement of circuits operat-
ing in an ultrawideband range of frequencies, a CCII±
module is designed to achieve high performance (in terms
of current, voltage bandwidth and the input/output resis-
tances) using a CNFET optimized in terms of number of
CNTs, inter-CNT pitch and the diameter of CNT. The per-
formance of the optimized CNFET-based CCII is further Fig. 2. CCII± implementation using a translinear loop.
improved by altering parameters of an individual CNFET
(ITOPT).
2) The performance of ITOPT CCII is then compared with equations of the dual output current conveyor can be represented
CMOS at different supply voltages. as follows:
The rest of the paper is organized as follows. A brief introduc-
tion of CCII± is given in Section II, followed by an overview
of CNFET design parameters and equations in Section III. IY = 0 (1)
Section IV and V discuss in detail the design and performance VX = VY (2)
analysis of CNFET-based CCII. In Section VI, the parameters
of individual CNFET are altered to further improve the per- IZ = ±IX (3)
formance of CNFET-based CCII, and then, its performance is
compared with the existing bulk CMOS-based CCII. It is then where VX and VY are the voltages at ports X and Y, respectively.
followed by conclusion in Section VII. IX and IY are the currents entering ports X and Y. Moreover,
IZ+ is the positive-type output current and IZ− is the negative-
type output current. Ideally, a current conveyor should satisfy
II. CURRENT CONVEYOR the following attributes.
The first-generation current conveyor (CCI) was introduced 1) Infinite input impedance (RIN ) at port Y.
way back in 1968 by Sedra and Smith [13]. In 1970, the same 2) Zero input impedance (RX ) at port X for current inputs.
duo modified the architecture of CCI and came up with a novel 3) Infinite output impedance (ROUT ) at port Z.
type of current conveyor, which is now known as the second- 4) Unity current transfer gain between ports X and Z.
generation current conveyor (CCII) [14]. It is an attractive build- 5) Unity voltage transfer gain between ports Y and X.
ing block for voltage and CM circuits with great functional 6) Infinite bandwidth.
versatility. It is widely used for implementing various functions Current and voltage bandwidths along with the input and
in analog signal processing, such as amplifiers, integrators, dif- output port resistances of the CCII have been chosen as the pa-
ferentiators, oscillators, filters, etc. rameters for the assessment of its performance using the emerg-
CCII is basically a CM device, which conveys current, with ing CNFET technology at a 32-nm technology node. However,
unity gain, from the input port to the output port. It has reliable various configurations of CCII± based on silicon CMOS and
frequency response and is popularly used for high frequency bipolar technologies exist in the literature.
applications. The block diagram representation of CCII± and However, the one chosen in this paper for carrying out the
its internal transistor implementation are shown in Figs. 1 and 2 design and performance optimization with CNFET technology
respectively [15]. Using the standard notation, the characteristic exhibits excellent high-frequency response.
1102
Fig. 3. Top view of a CNFET.
III. CARBON NANOTUBE FET
As silicon CMOS technology reaches its scaling limit, the
development of alternative technologies that could improve
the performance of the device/circuit is of utmost importance.
Nanotechnology-based fabrication is expected to offer the ex-
tra density and potential performance to take electronic circuits
to the next level. Among all the nanoscale electronic devices
investigated till date, CNT FET seems to have the brightest
prospect due to its excellent electronic properties [16]. Most of
the traditional fundamental problems like extreme short channel
effects, leakage currents, high field effects, lithographic limits,
and quantum confinement effect associated with silicon CMOS
are overcome in a CNFET [17]. A CNFET can be scaled down to
10-nm channel length and 4-nm channel width, thus enhancing
throughput in terms of speed. Besides that a majority of issues
related to the fabrication process of CNFET has been solved and
the future looks promising [18]–[21].
A CNFET is obtained by replacing the channel of a conven-
tional MOSFET by an array of semiconducting CNTs as shown
in Fig. 3. CNTs are long, thin allotropic cylinders of carbon,
discovered by Ijima [22]. They are composed of a single shell
namely single-walled CNT (SWCNT). SWCNTs are quasi—
1-D molecular structures and can be formed by folding graphite
layers into a cylinder. It is because of this—1-D structure of
SWCNT that CNFETs provide better electrostatic control over
the channel as compared to 2-D (e.g., silicon on insulator) and
3-D (bulk CMOS) devices [23]. The properties of SWCNT de-
pend on the chirality (n1 , n2 ). The SWCNT is considered to be
metallic if n1 = n2 or (n1 –n2 ) is a multiple of “3,” otherwise
it is a semiconductor. The diameter of the CNT (DCNT ) and
its threshold voltage (Vth ) is calculated with the assistance of
chirality vector as follows:
a(n21 + n22 1/2
+ n1 n2 )
DCNT = (4)
π For carrying out simulation of CNFET-based CCII± at a
aVπ
Vth =√ (5)
3 qDCNT
where q = electronic charge, a = 2.49 Å is the lattice constant
and Vπ = 3.033 eV is the carbon π–π bond energy [24], [25].
The operating principle of CNFET is similar to a traditional
MOSFET. As in other FETs, the CNFET too relies on one of its
three terminals, i.e., the gate, to modulate the carrier concentra-
IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 11, NO. 6, NOVEMBER 2012
tion in the device channel by applying a field perpendicular to
the charge flow between the two other contacts, i.e., source and
drain. The number of semiconducting SWCNTs required in the
channel region depends on the current drive requirement. The
carrier transport between the n+ /p+ source and drain regions
takes place through these narrow CNTs and utilizes its ballistic
transport property. Ballistic transport means that the mean free
path for a charge carrier is longer than the device dimensions.
Thus, the charge carriers do not collide, reducing resistance to
negligible levels, resulting in higher mobility as compared to the
bulk MOSFETs [26]. On the basis of device operation mecha-
nism, the CNFET can be categorized into Schottky-barrier con-
trolled FET (SB-CNFET) or MOSFET-like FET. In this work,
MOSFET-like FETs are employed which exhibits unipolar be-
havior by suppressing either the electron (pFET) or hole (nFET)
transport with heavily doped source/drain.
Generally, while designing a circuit in the conventional sil-
icon CMOS technology, a PMOS/NMOS ratio of 2–4 is used,
in order to match the p- and n-type devices. However, no such
constraint exists in CNFET technology. In a CNFET, a ratio of
“1” could easily be used for PCNFET/NCNFET because both
“p” and “n” types of a CNFET have similar current-driving
capabilities with the same transistor geometries.
Moreover, unlike CMOS, where the widths and lengths of
the transistor are adjusted to change the PMOS/NMOS ratio,
a CNFET-based current conveyor is designed in terms of the
following optimal structural parameters.
1) Number of CNTs (N): It is important to determine the
number of CNTs to be used in an array in order to en-
sure sufficient current supply for driving fixed capacitive
loads as a single-nanotube-based transistor does not pro-
vide competitive performance over CMOS.
2) Inter-CNT Pitch (S): It is defined as the distance between
the center of two adjacent lying CNTs in the channel.
It is denoted by “S” and is one of the important factors
affecting the performance of the CNFET.
3) Diameter of CNT (DCNT ): It should be chosen very care-
fully because it directly affects the threshold voltage of
the device.
The design equations relating to the diameter of the CNT
(DCNT ), number of CNTs in the channel (N) and inter-CNT
pitch
 (S) with the width of the CNFET (W) and the energy gap
( g ) are given as follows:
W = (N − 1) ∗ S + DCNT (6)

= 0.84 eV/DCNT . (7)
g
32-nm technology node, we have used the Stanford CNFET
model [24]. This model has been experimentally validated and
designed for the unipolar MOSFET-like CNFET and takes into
consideration the device parasitics and non-idealities including
channel length dependence of current drive, source–drain series
resistance, source–drain contact resistance, effect of the source–
drain extension region, inter-CNT charge screening effect,
etc. along with accurate predictions of dynamic and transient
IMRAN et al.: OPTIMIZED DESIGN OF A 32-nm CNFET-BASED LOW-POWER ULTRAWIDEBAND CCII 1103

TABLE I
TECHNOLOGY PARAMETERS OF A CNFET

performance with more than 90% accuracy [27], [28]. Some

of the important device and technology parameters related to a
CNFET are given in Table I. Fig. 4. Number of CNTs versus 3-dB bandwidth.

IV. CNFET-BASED CURRENT CONVEYOR

A second-generation current conveyor is designed using a
CNFET, optimized in terms of uniformly spaced and perfectly
aligned CNTs, inter-CNT pitch, and the diameter of CNT. A
typical CNFET fabricated with Pd source/drain contacts and Al
gate contact is used in the simulation [29]. Intrinsic device ca-
pacitance (∼2–5 aF/nanotube), overlap, and fringe capacitances
(∼0.1 fF/nanotube) along with a capacitive load of 1fF are con-
sidered for a 32-nm CNFET device. To begin with, the circuit
is properly biased with power supply being kept constant at
±0.9 V and the value of current source Io , set to 10 μA in order
to establish a current in the circuit. The performance evaluation
is carried out on the basis of five key characteristics of a CCII Fig. 5. Number of CNTs versus resistance at port X.
namely current bandwidth, voltage bandwidth, input port resis-
tance X, input port resistance Y, and output port resistance Z.
The next sections investigate the effect of key parameters of the
CNFET on the performance of CCII.

A. Optimum Number of CNTs (N)

It is important to ascertain the number of CNTs to be used
in the channel so that sufficient current could be supplied for
driving load, as a single-CNT-based transistor cannot provide an
edge in performance over traditional CMOS [30]. The variation
of the performance parameters of CCII± with the number of
CNTs is shown in Figs. 4–6. It can be deduced from Fig. 4 that
with the increase in number of CNTs, the bandwidth increases
somewhat linearly, which allows for the use of larger number of Fig. 6. Number of CNT versus port resistance.
tubes to get best performance as expected. This is due to the fact
that parallel CNTs improve the driving capability of the device,
thus resulting in a significant increase in the transconductance (RX ) with the number of CNTs is depicted in Fig. 5. It can easily
[31]. be inferred that as the number of CNTs is increased, the value of
The small signal analysis of the port resistances of the device RX gradually decreases. This happens because with the increase
is performed in order to seek their dependence on the transistor in the number of CNTs, the value of transconductance increases
geometries. The small signal analysis at input port X of the and as per (8), RX decreases. Thus, increasing the number of
proposed circuit is depicted in Fig. 7. We can deduce from these CNTs is a good option for reducing RX . The same approach is
that the theoretical expression of RX is given by [32] followed for input port resistance Y and output port resistance
1 Z. The small signal analysis of the port resistances, i.e., RY and
RX = (8) RZ yields the following results:
gm 2 + gm 4
−1
where gm 2 and gm 4 are the transconductances of transistors M2 gm 1 + ro9
RY = −1 (9)
and M4, respectively. The variation of input port resistance X gm 3 + ro11
1104 IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 11, NO. 6, NOVEMBER 2012

Fig. 8. Inter-CNT pitch versus 3-dB bandwidth.

Fig. 7. Small signal analysis at port X.

r06 (1 − gm 6 /4αIo0.5 β 0.5 )

RZ = (10)
r07 (1 − gm 7 /4αIo0.5 β 0.5 )
where gm n and ron represent the transconductance and output
resistance of the nth transistor. Io is the value of the current
source that has been kept constant throughout the analysis at
10 μm, in order to establish a current in the circuit, and α and
β represent the values of current and voltage gain. The results
incorporating the variations in input port resistance Y (RY ) and
output port resistance Z (RZ ) with increasing number of CNTs
is shown in Fig. 6. It is to be noted that “Z” is an output current
Fig. 9. Inter-CNT pitch versus resistance at port X.
port, and for proper cascading of the device, it is preferable
to have high output resistance. However, it has been observed
that as the number CNTs in an array increases, and the value
of output port resistance Z (RZ ) decreases, thus presenting a
tradeoff with other parameters involved. Moreover, the power
dissipation goes up with the number of CNTs in the channel of
the device, thus putting an upper limit on the number of CNTs to
be incorporated in the channel. Hence, the number of CNTs to be
used is determined by the tradeoff involved between bandwidth,
input port resistances on one side and power and output port
resistances on the other. Nevertheless, looking at the overall
performance merits obtained sufficient number of tubes must
be chosen. Based on the simulation results, the optimum value
of number of tubes comes out to be 9, which has been used for
further simulation purposes.
Fig. 10. Inter-CNT pitch versus port resistance.

B. Optimum Inter-CNT Pitch (S)

current per tube ITUBE gets reduced for lower pitch because of
The effect of varying the inter-CNT pitch on the performance
the inter-CNT screening effect. Furthermore, it is observed that
of CCII is now investigated. It is worth noting that the CNFET
resistances at Ports X, Y, and Z decrease in a similar manner
model used for simulation purposes assumes that because of the
on increasing the inter-CNT pitch. Hence, compact packing of
screening phenomenon, the CNTs lying at the corner, conducts
CNTs deteriorates the overall performance. From the plots of
in a better fashion compared to the CNTs lying in-between.
Figs. 8–10, we conclude that the optimum choice of inter-CNT
Analytical results indicate that both the 3-dB current and voltage
pitch comes out to be 16 nm.
bandwidths improve slightly with the increase in inter-CNT
pitch as shown in Fig. 8. The observed variations is due to the
C. Optimum Diameter of CNT (DCNT )
fact that the capacitance from the gate to each CNT channel
(Cgc ) decreases, as the CNTs are brought closer because every The diameter of an SWCNT is a measure of its electronic
nanotube can mirror a small amount of charge [33]. Hence, the properties. An SWCNT is obtained by selective axial folding of
IMRAN et al.: OPTIMIZED DESIGN OF A 32-nm CNFET-BASED LOW-POWER ULTRAWIDEBAND CCII
Fig. 11. CNT diameter versus 3-dB bandwidth.
Fig. 12. CNT diameter versus resistance at port X.
a single layer of graphite called graphene. The diameter of CNT
(DCNT ), its bandgap energy Eg and the threshold voltage of the
device (Vth ) are closely related as given by
0.84 eV
Eg = (11)
DCNT
Eg
Vth = (12)
2e
where “e” is the electronic charge. The diameter of a CNT is in
fact one of the most important design parameters because it not
only affect the source/drain series resistance but also the thresh-
old voltage of CNFET. For optimum values of “N” and “S”, we
next consider the effect of variation in the CNT diameter on the
circuit performance. Analytical results suggest that with the in-
crease in the diameter of the nanotube as shown in Figs. 11–13,
there is a significant improvement in the frequency response of
a CNFET-based current conveyor. The trend could be well jus-
tified because on increasing the diameter, the gate–to-channel
capacitance along with the fringe capacitance decrease appre-
ciably on account of enhanced screening between the adjacent
CNT channels [34]. Moreover, the transconductance also goes
up with the reduction in the threshold voltage with the increase
in diameter of the CNT.
The variation in input and output port resistances with the
CNT diameter is depicted in Figs. 12 and 13, respectively. Re-
sults indicate that the resistance at port X decreases, moving
1105
Fig. 13. CNT diameter versus port resistance.
towards its ideal value of zero, as the diameter is increased.
This happens because the bang gap decreases with the increase
in diameter. As a result, a large number of charge carriers are
able to overcome the energy barrier, thus strengthening the cur-
rent flow, resulting in a higher value of transconductance. As
clearly indicated by (8), the expression of resistance at port X
is inversely proportional to the transconductance. However, it
is to be noted that for larger values of CNT diameter, the cur-
rent tends to saturate because of large screening and scattering
effect.
Finally, Fig. 13 shows that deterioration is observed in re-
sistances at ports Y and Z as the CNT diameter is increased.
Therefore, opting for a suitable value of diameter is extremely
difficult; rather a compromise between conflicting requirements
and a tradeoff is involved between the 3-dB bandwidth and the
port resistances. The optimum diameter value is hence chosen to
be 1.5 nm corresponding to chiral vector (19, 0). The simulation
results of CNFET-based CCII± obtained by using the optimized
CNFET transistor parameters are discussed in the next section.
V. PERFORMANCE OF CNFET-BASED CCII±
We begin with the evaluation of static and dynamic charac-
teristics of the current conveyor. The dc input–output current
characteristics of the current conveyor between terminals X and
Z+ and X and Z– are plotted in Fig. 14. The input current applied
to the X terminal, i.e., IIN , is swept from 100 to –100 μA, and
the characteristics obtained, follows the linear curve, in accor-
dance with the theory satisfying the basic equations, i.e., IZ =
IX and IZ = –IX . The voltage transfer characteristic between
ports Y and X is illustrated in Fig. 15. Now, as expected, an ex-
cellent voltage following action can be seen over a wide range
in accordance with the theory of a current conveyor satisfying
the relation VX = VY . Next, the frequency characterization of
the current conveyor is presented. Fig. 16 shows the frequency
response of voltage gain between terminals Y and X of the cur-
rent conveyor. It is to be noted that the static voltage gain close
to unity is obtained.
In addition to that a CNFET-based module provides a
high voltage cut-off frequency. A voltage bandwidth exceed-
ing 20 GHz is obtained by using optimum values of CNFET
1106
Fig. 14. Current input–output characteristics at 32 nm.
Fig. 15. Voltage transfer characteristics at 32 nm.
Fig. 16. Frequency response of voltage gain at 32 nm.
parameters. Fig. 17 shows the small signal current gain char-
acteristics between terminals Z± and X. The CNFET module,
besides giving a high voltage cut-off frequency, also provides
remarkably high 3-dB current bandwidth. It should be noted
that current bandwidth exceeding 25 GHz is obtained, keeping
the static current gain close to unity.
Finally, the resistances involved at the input and output ports
of the device are investigated. The resistance at port X (RX )
is plotted for a control current of 10 uA against the frequency
as shown in Fig. 18 with port Y grounded. It is observed that
RX has a value of 1.45 kΩ for frequencies below 4 GHz and it
decreases at high frequencies. The resistance at port Y (RY ) is
plotted under the same condition in Fig. 19. Ideally, the resis-
tance expected at port Y is infinite, since it draws no current,
i.e., IY = 0. However, the value obtained through the HSPICE
simulation is 153.4 kΩ, which though not very high, but is satis-
factory. The variation of resistance RZ with frequency is shown
IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 11, NO. 6, NOVEMBER 2012
Fig. 17. Frequency response of current gain at 32 nm.
Fig. 18. Resistance R X against frequency at 32 nm.
Fig. 19. Resistance R Y against frequency at 32 nm.
in Fig. 20 and it shows a value of approximately 362 kΩ, which
decreases at higher frequencies. The optimized design param-
eters and the corresponding performance characteristics of the
CNFET-based current conveyor is summarized in Table II.
VI. OPTIMIZED CNFET-BASED CCII± (ITOPT)
Simulation results obtained after several iterations clearly
indicate that a CNFET-based current conveyor is an excel-
lent prospect for designing high-performance analog circuits.
Various analog modules like multifunctional filters, amplifiers,
multiphase oscillators, etc., now could easily be designed for
ultrawideband range of frequencies by using a CNFET-based
CCII± module. However, in this section, an attempt is made
IMRAN et al.: OPTIMIZED DESIGN OF A 32-nm CNFET-BASED LOW-POWER ULTRAWIDEBAND CCII
Fig. 20. Resistance R Z against frequency at 32 nm.
TABLE II
DESIGN PARAMETERS AND PERFORMANCE CHARACTERISTICS
to explore the possibility of further improving the performance
by optimizing parameters of individual transistors of current
conveyors (ITOPT-individual transistor optimization).
The designed module, shown in Fig. 2, uses a mixed translin-
ear loop (transistors M1–M4) as the input cell. Two current
mirrors (transistors M9, M10 and M11, M13) allow the mixed
loop to be dc biased by the current Io . The input cell presents a
high input impedance at the input port Y and a low impedance
at port X. This cell acts as a voltage follower. The output Z
that copies the current flowing through port X is realized in the
conventional manner using two complementary mirrors.
Now, as already discussed in the previous sections, the num-
ber of CNTs along with the pitch and diameter plays a prominent
role in designing of a CNFET-based circuit. However, among
these, the changes in diameter are crucial because even minor
changes can lead to much improved current drive and higher
power dissipations. Since the designed CNFET CCII± module
has not so high port Y resistance values, the diameters of the
corresponding transistors affecting its value, i.e., transistors M1
and M3 are increased in order to achieve higher transconduc-
tance values for the best possible RY . Nevertheless, it needs to
be noted that transistors M1, M2, M3 and M4 form a translinear
loop and changes in M1–M3 will lead to alterations in M2–M4.
The parameters of various transistors in the designed module
(ITOPT) are given in Table III.
1107
TABLE III
PARAMETERS OF AN ITOPT CNFET CCII± MODULE
TABLE IV
PERFORMANCE COMPARISON OF CNFET-BASED CCII REALIZATIONS
The ITOPT designed CNFET CCII± module provides im-
proved resistance at port Y, as its value increases 1.5 folds from
153 to 231 kΩ. The resistance at port X also follows suite and
its value decreases to 0.93 kΩ from 1.45 kΩ, exhibiting another
improved parameter; however, the resistance at port Z decreases
from 362 to 304 kΩ, presenting the tradeoff involved. Slight im-
provement is also observed over the preceding design in the
case of frequency response, but at the cost of higher power dis-
sipation as illustrated in Table IV. In order to get a fair idea,
where the design obtained by selectively choosing parameters
of individual CNFET of CCII± module (ITOPT) stands with
respect to the state-of-the-art CMOS CCII±, the 32-nm cus-
tomized model parameters used for the simulation purpose of
the CMOS CCII± module are generated from a specific tool
known as “Nano CMOS” [35].
Although CMOS-designed CCII shows good high-frequency
response in deep submicrometer but still its performance is much
inferior to the CNFET-based realization. It is also important to
investigate the performance of the two designs at a scaled sup-
ply voltage. Therefore, the supply voltage for both CNFET and
CMOS-based modules has been varied from 0.9–0.7 V in order
to see its effect on the module’s performance. It can be inferred
from Table V that for both technologies, with the decrease in
supply voltage from 0.9 to 0.7 V, there is a significant deteri-
oration in the 3-dB bandwidth. This happens because of much
lower driving current and hence transconductance. However, it
is to be noted that, even at a lower supply voltage of 0.7 V, the
CNFET-based module provides better performance compared to
bulk CMOS. Hence, the supply voltage scaling of CNFET-based
CCII can be carried out from 0.9 to 0.7 V for achieving slightly
better performance in all key parameters along with lower power
consumption. Hence, an ITOPT CNFET-designed module could
1108
TABLE V
PERFORMANCE COMPARISON OF ITOPT CNFET DESIGN WITH BULK CMOS
be utilized for low power high performance analog circuits in
the microwave range of frequencies.
VII. CONCLUSION
This paper has successfully presented the design of a CNFET-
based dual output current conveyor at 32-nm technology node
that is based on optimum parameters of CNFET. The perfor-
mance of CNFET-based CCII is further improved by optimizing
parameters of individual CNFET giving rise to ITOPT. ITOPT
provides excellent voltage and current bandwidths along with
good port resistances, thus making it a viable proposition for
ultrawideband systems. The overall design and analysis clearly
indicates that a CNFET can significantly achieve better perfor-
mance than CMOS even at a scaled supply voltage of 0.7 V with
the added advantage of lower power consumption.
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IMRAN et al.: OPTIMIZED DESIGN OF A 32-nm CNFET-BASED LOW-POWER ULTRAWIDEBAND CCII
Ale Imran (S’10–M’11) received the B.Tech.
(Hons.) and M.Tech (Hons.) degrees in electronics
engineering with major in electronic circuits and sys-
tem design from Aligarh Muslim University (AMU),
Aligarh, India, in 2007 and 2010 respectively.
He has been currently a Lecturer in the Department
of Electronics Engineering, Aligarh Muslim Univer-
sity (AMU) since 2008. He is the author or coauthor
of more than 20 research papers in reputed journals
and conference proceedings. His current research in-
terests include simulation studies of circuits employ-
ing technologies beyond CMOS (that include emerging technologies such as
fin-shaped FETs, carbon-nanotube FETs, etc.)
Mr. Imran is a member of The Institution of Electronics and Telecommuni-
cation Engineers (IETE).
Mohd. Hasan (M’10) received the B.Tech. degree
in electronics engineering from Aligarh Muslim Uni-
versity, Aligarh, India, in 1990, the M.Tech. degree
in integrated electronics and circuits from the Indian
Institute of Technology Delhi, New Delhi, India, and
the Ph.D. degree in low-power architectures for multi-
carrier systems, under a Commonwealth Scholarship,
from the University of Edinburgh, Edinburgh, U.K.,
in 2004.
He has been currently a Full Professor at AMU
since 2005. From 2008 to 2009, he was a Visiting
Postdoctoral Researcher on a project funded by the prestigious Royal Academy
of Engineering, U.K., on low-power field programmable gate array (FPGA)
architecture with the School of Engineering, University of Edinburgh. He is the
author of more than 123 research papers in reputed journals and conference
proceedings. He received both the best International journal paper and interna-
tional conference paper awards. His research interests include low-power VLSI
design, nanoelectronics, batteryless electronics along with spintronics.
1109
Aminul Islam (M’10) received the B.Tech. degree in
computer engineering from The Institution of Engi-
neers (India), Kolkata, India, in 2001 and the M.Tech.
degree in electronics and communication engineering
from the Birla Institute of Technology (BIT) (Deemed
University), Mesra, Ranchi, India, in 2006. He is cur-
rently working toward the Ph.D. degree in the field of
very large scale integrated (VLSI) design at the De-
partment of Electronics Engineering, Aligarh Muslim
University, Aligarh, India.
Since November 2006, he has been in the De-
partment of Electronics and Communication Engineering, BIT, where he is
currently an Assistant Professor. He is the author or coauthor of more than 37
research papers in reputed journals and conference proceedings. His research
interests include VLSI/computer-aided design for classical CMOS, nonclassical
CMOS, and non-CMOS technologies (that include emerging technologies such
as fin-shaped FETs, carbon-nanotube FETs, nanowire FETs and tunnel FETs),
robust design of ultralow-power nanoscale circuit for portable computing and
wireless communications, and spin transfer torque–magnetic tunnel junction
(STT–MTJ)-based logic and memory design.
Shuja Ahmad Abbasi (M’80–SM’98) was born at
Amroha, India, in 1950. He received B.Sc. (Eng.) and
M.Sc. (Eng.) degrees in electrical engineering from
Aligarh Muslim University (AMU), Aligarh, India,
in 1970 and 1972, respectively, with first position in
the University. He received the Ph.D. degree in mi-
croelectronics from the University of Southampton,
Southampton, U.K., in 1980.
He joined the Department of Electrical Engineer-
ing at Aligarh Muslim University, Aligarh, India, in
1971, as an Assistant Professor, and was promoted to
the positions of Associate Professor and Professor in 1982 and 1986, respec-
tively. He shifted to the newly created Department of Electronics Engineering
at AMU as a Professor in 1988. He served as the Chairman of the Depart-
ment of Electronics Engineering, AMU, from 1996 to 1999. He held many
Academic/ Administrative positions in the past at AMU and outside. He joined
as a Professor of Electronics Engineering at the College of Engineering, King
Saud University, Riyadh, Saudi Arabia, in 1999. He has more than 100 research
publications to his credit so far. He has completed many client funded projects
from various organizations. His current interests include Nanoelectronics, VLSI
design and technology.
Dr. Abbasi is a Fellow of the Institution Electronics and Telecommunication
Engineers (IETE).