I/O Buffer, Latch up, ESD and Layout

Debashis Mandal
Advanced VLSI Design Laboratory,
Indian Institute of Technology Kharagpur
 I/O Buffer

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 Why I/O Buffers ?

¾ Properly drive different loads

¾ Get clean (less noisy) signal from incoming noisy signal
¾ Provide proper interface between ICs with different signal
levels
¾ Isolate internal circuit from external effects
¾ Translate incoming/outgoing signal level to the required
internal/external signal level

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 Types of I/O Buffers

¾ Depending on the direction of signal flow

9 Input buffer
9 Output buffer
9 Bidirectional (IO) buffer
¾ Other types of buffers
9 Level shifter
9 Schmitt trigger circuit
9 Unity gain buffer
9 Push pull buffer

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 Latch up

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 What is latch up

¾ Latch up is a typical problem but its occurrence in most of

the time is unpredictable in any CMOS or Bi-CMOS process
¾ External transients above supply or below ground cause
more latch up
¾ Latch up problem occurs due to the SCR (Silicon Controlled
Rectifier) phenomenon in the lateral pnp and npn parasitic
transistors of the MOSes
¾ Effect: Uncontrolled huge current flow from VDD to GND
¾ This state will continue until the power supply is removed

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 Latch up problem
Vdd
Gn Gp
Bn Sn Dn Dp Sp Bp

p+ n+ n+ p+ p+ n+
pnp
Vss npn
Rnwell
Rsub

n-well
p-substrate

Rsub Dp Vdd

Dn
Rnwell
Vss
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 Latch up problem (cont’d)
Vdd
Gn Gp
Bn Sn Dn Dp Sp Bp

p+ n+ n+ p+ p+ n+
pnp
Vss npn
Rnwell
Rsub

E n-well
p-substrate

Rsub Dp Vdd

Dn
Rnwell
Vss
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 How to minimize latch up problem
¾ Use guard rings to remove the latch up problem
9 N+ ring for PMOS and connect it to Vdd
9 P+ ring for NMOS and connect it to gnd
¾ Keep spacing between NMOS and PMOS
¾ Reducing Rsub and Rnwell
9 Minimizing spacing between source and bulk
9 Increasing the substrate and nwell doping density
9 Using more number of source, substrate and nwell contacts
¾ Wider guard ring provides low resistive paths to minority
carriers
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 Electro Static Discharge
(ESD)

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 What is ESD

¾ As you are probably aware, you have to be very careful

when handling MOS circuits, to be sure that you are properly
grounded. Why?
9 because you do not transfer any static electricity to the chip.
¾ Almost any form of fiction can generate static electricity.
Even human body has static electricity.
¾ ESD can occur when charges stored in machines or human
body are discharged to the chip on contact or by static
induction.

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 What is ESD (cont’d)
¾ Ex: Assume a static charge transfer of about 0.1 micro-
Coulombs ( 10−7C) upon static electricity discharge between
a human/machine and a chip. Is this charge enough to do any
harm?
¾ Remember the formula: Q=CV. Now C~84fF for W=10μm,
L=1μm NMOS in 0.18μm CMOS process, which gives
V=1.2MV. Electric field in the gate oxide (tox=42Ao) is
about 3x1012 V/cm. Gate oxide breaks. This problem is
called electrostatic discharge (ESD) and is one of the major
concerns of IC manufacturers.
¾ Protecting against ESD is still very much a ”black art” and is
something that people are still studying quite a bit.

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 Different models for ESD testing

1MΩ 1.5kΩ 1MΩ

Vesd 100pF DUT Vesd 200pF DUT

Human body model (HBM) Machine model (MM)

1.5GΩ
DUT
Discharging
Vesd Probe

Charged device model (CDM)

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 LAYOUT

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 MOSFET Structure

G
S D
Poly Oxide

n+ Leff n+

Ldrawn

p-substrate

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 Substrate Connection
B S G D
S G D
B

p+ n+ n+ n+ p+ p+

n-substrate
p-substrate

G G
B S D D S B

p+ n+ n+ p+ p+ n+

n-well
p-substrate

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 Cross section of an Inverter

Oxide layer (spun on glass)

Metal 2

Metal 1
oxide

nwell

substrate

N+ implant P+ implant

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 Passive devices

Resistors:
RND
Resistance marker
N+ Composite
Metal 1

salex

rho ~ 45 ohm/ in 0.18µm CMOS process

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 Passive devices (cont’d)

Resistors:
RPD
Resistance marker
P+
Metal 1 Composite

salex

nwell
rho ~ 79 ohm/ in 0.18µm CMOS process

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 Passive devices (cont’d)

Resistors:
RNP

Resistance marker
N+ Poly
Metal 1

salex

rho ~ 137 ohm/ in 0.18µm CMOS process

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 Passive devices (cont’d)

Resistors:
1) RPP
Resistance marker
P+ Poly
Metal 1

salex

rho ~ 175 ohm/ in 0.18µm CMOS process

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 Passive devices (cont’d)

Capacitor:
CPP (over the substrate) :

Upper plate Lower plate

Field Oxide (FOX)
poly

oxide

substrate

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 Passive devices (cont’d)

Capacitor:
CPP (over the Nwell) :

Upper plate Lower plate

Field Oxide (FOX)
poly

oxide

nwell

substrate

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 Passive devices (cont’d)

Capacitor:
Accumulation capacitor :

Upper plate
Lower plate
oxide poly

nwell

substrate

N+ implant

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 PMOS in Nwell

NWELL POLY

P+ Composite
Metal 1

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 NMOS

POLY

N+ Composite
Metal 1

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 Guard ring

POLY

N+ Composite
Metal 1

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 Things to remember
¾ All the modules of the chip should be properly connected to
Vdd and Gnd
¾ Vdd and Gnd metal should be wider to reduce resistive loss
¾ Try to avoid same Vdd and Gnd line for a noisy and
sensitive blocks
¾ Keep sufficient spacing between noisy blocks and sensitive
blocks
¾ Two high frequency carrying pins should not be side by side
¾ Use ground pin to avoid magnetic coupling between two
pins
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 Matching of the devices

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 Why Special attention on Matching ?

¾ A large variety of analog circuits rely on matching of

transistors. Circuits like differential pair rely on gate to
source voltage matching while current mirrors rely on
current matching.
¾ Most integrated resistors and capacitors have a tolerance of
about 20% to 30%. But ratio of two similar components can
be controlled to a tolerance of even 0.1% by proper
matching of the components.

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 Reasons of Mismatch
Mismatch in integrated circuits are generally of two types :
¾Random mismatches due to microscopic fluctuations in
dimensions, doping, oxide thickness and other parameters that
influence component values.
¾Systematic mismatches which are caused by:
9 Process biases
9 Mechanical stress
9 Temperature gradients
9 Diffusion interactions, Polysilicon etch rates etc.

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 How does mismatch affect the performance of the
circuit ?

™ Current Mirror

I1 = ½ μnCox W (VGS-Vt1)2 I1 I2
L 1
M1 M2

I2 = ½ μnCox W (VGS-Vt2)2
L 2

Mismatch in the current depend upon

¾ Mismatch in the (W/L) values of the transistors.
¾ Mismatch in the threshold values of the transistors which
increases as the overdrive voltage ( VGS-Vt) is reduced.

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 How does mismatch affect the performance of the
circuit ? (cont’d )

™ Input Offset Voltage of Differential pair

Offset voltage depends upon:

¾Threshold voltage mismatch of the transistors . This depends
upon the layout and it can be reduced by careful layout.
¾Offset scales with the overdrive voltage and is related to
mismatch in the load elements and mismatch in the W/L
values.

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 Rules for MOS transistor matching

¾ Place transistors in close proximity.

¾ Orient transistors in the same direction.
¾ Keep the layout of the transistors as compact as possible
¾ Whenever possible use common centroid layouts.
¾ Place transistors well away from the power devices.
¾ For current matching keep overdrive voltage large.
¾ For voltage matching keep overdrive voltage large.

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 Rules for resistor and capacitor matching
¾ Threshold voltage mismatch of the transistors . This
depends upon the layout and it can be reduced by careful
layout.
¾ Construct matched resistors of same type.
¾ Make matched resistors of the same width.
¾ Orient matched resistors in the same direction.
¾ Place matched resistors in close proximity.
¾ Place the matched resistors in such a way that there
centroids coincide ie interdigitate arrayed resistors.
¾ Place dummies on either end of the resistor array.
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 Common Centroid Layout
¾ Gradient-induced mismatches can be minimized by
reducing the distance between the centroids of the matched
devices. The layouts which actually reduce the distance
between centroids of the matched pair to zero are called
common centroid layouts.

A B B A
D SS DD SS D

Common Centroid Layout of two MOS

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 Common Centroid Layout (cont’d)
¾ Interdigitation can also be done in 2 dimensions

DASSBD DASSBDDBSSAD
DBSSAD
DBSSADDASSBD

Common Centroid Layout for Resistors

R1 R2 R2 R1

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 Layout of a matched transistors

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 Layout of Matched Resistors

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 Fully Custom IC Design Flow

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 Design Rule Check (DRC)

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 Design Rule Check (DRC) (cont’d)

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 Layout vs. Schematic (LVS)

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 Layout Passives
and their model

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 Resistance

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 Diffusion resistance

N+ Diffusion (RND)

Equivalent Model

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 Diffusion resistance (cont’d)

P+ Diffusion (RPD)

Equivalent Model

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 Poly resistance (RPP)

Equivalent Model

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 Choice of resistors

¾ Parasitic effect ,

¾ Process variation,

¾ Temperature variation,

¾ Operating frequency, Q factor( for bypass and decoupling case)

¾ Area constraint of design

¾ AC simulation, Temperature variation and process corner

simulation

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 Capacitance

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 Poly to Poly resistor

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 Accumulation Cap

There are many others capacitors :COMB cap, Interdigtized Cap, MOS Varactor cap

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 Interconnection

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 Interconnection (cont’d)

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