Radio

SOBA Server: RTP Streaming Audio over Ethernet
Final Project Report ver. 1.0
Warriors:
Avraham Shinnar as1619@columbia.edu

Benjamin Dweck bjd2102@columbia.edu
Oliver Irwin omi3@columbia.edu
Sean White sw2061@columbia.edu
“...no pain no tears”

– ASIX AX88796L Ethernet controller documentation
May 10, 2005

CONTENTS CONTENTS
Contents
1 Overview 3
2 System Design 3
2.1 General design and layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.2 Audio Codec . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.2.1 Audio Control Peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2.2 Audio Sample Peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.3 Ethernet Codec . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.4 Microblaze . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.5 RTP Packet Structure and Construction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.6 RTP Client . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3 Process 11
4 Lessons Learned and Advice for Future Projects 11
5 Acknowledgements 12
A Code listing 13
A.1 C Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
A.1.1 ether.h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
A.1.2 ether.c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
A.1.3 main.c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
A.2 clkgen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
A.2.1 data/clkgen v2 1 0.pao . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
A.2.2 data/clkgen v2 1 0.mpd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
A.2.3 hdl/verilog/clkgen.v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
A.3 Audio Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
A.3.1 data/opb audio cntlr v2 1 0.pao . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
A.3.2 data/opb audio cntlr v2 1 0.mpd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
A.3.3 data/opb audio cntlr.vhd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
A.4 Audio Sampler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
A.4.1 data/opb audio sampler v2 1 0.pao . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
A.4.2 data/opb audio sampler v2 1 0.mpd . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
A.4.3 hdl/vhdl/opb audio sampler v2 1 0.vhd . . . . . . . . . . . . . . . . . . . . . . . . . . 37
A.5 opb ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
A.5.1 data/opb ethernet v2 1 0.pao . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
A.5.2 data/opb ethernet v2 1 0.mpd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
A.5.3 hdl/vhdl/memoryctrl.vhd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
A.5.4 hdl/vhdl/opb ethernet.vhd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
A.5.5 hdl/vhdl/pad io.vhd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
A.5.6 hdl/vhdl/opb ethernet.vhd.old . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
A.6 misc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
A.6.1 Makefile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
A.6.2 system.mhs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
A.6.3 system.mss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
A.6.4 data/system.ucf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
2
2 SYSTEM DESIGN LIST OF FIGURES
List of Figures
1 System Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2 Audio Controller Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3 Audio Controller Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4 Audio Sampler Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
5 Audio Sampler Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
6 Ethernet Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
7 Ethernet Timing Diagram (for Read Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1 Overview
This document describes the design of our system, development process, and advice for future project groups
that want to develop similar systems. A full listing of our source code is included as Appendix A
The SOBA server is a streaming audio server based on the XESS XSB-300E FPGA board. We imple-
mented it using IP’s included in the Xilinx EDK 6.1 in addition to our own IP’s, and some C code. The
system encodes analog audio input into 16-bit samples and streams the digitized audio out the ethernet port
in RTP packets, ready to be played in real time by an RTP client.
The system is comprised of three primary subsystems: the audio codec, the microblaze, and the ethernet
controller. Each is described in further detail in the following sections.
2 System Design
2.1 General design and layout
Figure 1 shows a general block diagram for our system.
The system accepts line level audio via the AKM AK4565 audio codec where the signal is converted
from analog to 16-bit signed digital samples. The samples are fetched from the audio codec by our audio
sampler peripheral which generates an interrupt each time a complete sample arrives. The 32-bit Microblaze
soft processor then transmits the sample from the audio sampler to the ethernet peripheral via the on-
board peripheral bus (OPB). The ethernet peripheral places the samples in the ASIX AX88796L Ethernet
controller’s onboard RAM as the payload of a preloaded real-time transport protocol (RTP) packet. As each
packet’s payload is filled, it is transmitted onto the IP network as a UDP packet. An RTP client on the
machine at the destination IP address receives the packets and plays the streaming audio in real time.
In addition the components mentioned above, we also designed, implemented and tested an audio control
peripheral discussed below which is not included in our final design.
Address Space on the OPB Bus
Ethernet Controller: 0x00800000 – 0x00FFFFFF
Audio Sampler: 0x10000100 – 0x100001FF
UART: 0xFEFF0100 – 0xFEFF01FF
Interrupt Controller: 0xFFFF0000 – 0xFFFF00FF
2.2 Audio Codec

The AKM AK4565 Audio Codec has two separate intefaces: (1) a control interface used to configure the codec
and (2) a transceiver interface used to send and recieve audio samples. The control interface is connected
to the FPGA via the off-FPGA shared peripheral bus while the transceiver interface is connected to the
FPGA via separate signal lines. We implemented two separate OPB peripherals to use the two interfaces.
In our final design we did not include the audio control peripheral because the ethernet controller also uses
the off-FPGA shared peripheral bus and our design did not require the audio control peripheral (we relied
on the default codec values).
3
2.2 Audio Codec 2 SYSTEM DESIGN
Clock Signal
FPGA
Clock
Generator
ASIX
Ethernet AX88796L
Peripheral Ethernet
Controller
Microblaze
Audio
Controller
Interrupt
Interrupt
Controller UART
Controller
Audio
Sampler
OPB
Controller
UART
AKM AK4565
Audio Codec
Figure 1: System Block Diagram

2 SYSTEM DESIGN 2.3 Ethernet Codec
2.2.1 Audio Control Peripheral
Figure 2: Audio Controller Timing Diagram
The timing diagram for the audio control signals is shown Figure 2. Our audio control peripheral,
shown in Figure 3, takes read/write requests from the Microblaze on the OPB bus and translates them into
read/write requests to specific registers in the audio codec. The audio control peripheral is allocated a byte’s
worth of address space on the OPB bus. The lowest address byte designates the addressed register on the
audio codec.
2.2.2 Audio Sample Peripheral

The timing diagram for the audio transceiver signals is shown in Figure 4. Our audio sampler peripheral is
only capable of reading samples from the codec and cannot transmit them to the codec as our design requires
only receiving samples. Upon receiving a sample, the peripheral raises the interrupt signal which is connected
to the interrupt controller. The interrupt controller then raises the interrupt line on the Microblaze which
calls the BSP’s general interrupt handler which, in turn, calls our audio sample interrupt handler. The
handler fetches the sample from the audio sample peripheral at its address on the OPB bus. This location
is read-only.
The block diagram for the audio sampler peripheral is shown in Figure 5. It generates the appropriate
clocks for the audio codec from the OPB clock and continually shifts in bits from the codec, raising an
interrupt each time it receives a complete sample.
2.3 Ethernet Codec

To use the ASIX AX88796L Ethernet controller, we created a peripheral based on the JAYCam design which
included a memory controller, pads for i/o, and the ethernet controller itself. Usage consists of initializing
the chip, filling the on-board SRAM with a packet skeleton, filling the payload, and initiating transmission.
We also created a diagnostic program to verify that we could read and write registers on the chip.
The memory control maintains the state machine that manages signals to the Ethernet chip. The PAD
I/O component is responsible for boosting the current of the lines that leave the FPGA on the PB so that
they can drive chips on the shared PB. The Ethernet component incorporates the memory controller and
5
2.3 Ethernet Codec 2 SYSTEM DESIGN
OPB_CLK
OPB_DBus(25)
OPB_DBus(27)
OPB_DBus(29)
OPB_DBus(31)
OPB_ABus(29)
OPB_ABus(31)
AU_CDTO
OPB_DBus(24)
OPB_DBus(26)
OPB_DBus(28)
OPB_DBus(30)
OPB_ABus(28)
OPB_ABus(30)
OPB_RNW
'1'
'0'
'1'
Clock Divider 15 14 . . . (int_au_cdti_buff) ... 3 2 1 0
(Clock / 12)
int_au_cclk
shift_in reg
shift_out
cdto_buff
reg
cdti_buff
count_rst
Clock
Counter
cdti_load
int_au_cdti
int_au_cclk_count
MUX '0'
output enable
FSM
int_au_csn
AU_CDTI_ AU_CSN_ AU_CCLK

IOBUFF IOBUFF _IOBUFF
AU_CDTI AU_CSN AU_CCLK Sln_DBus
Figure 3: Audio Controller Block Diagram

Figure 4: Audio Sampler Timing Diagram
OPB_CLK
AU_SDTO0 OPB_RST
au_sdto0_ OPB_cloc
IObuff k_counter
OPB_clk_count
0 1 2 3 4 5 6 7 8 9 ...
au_sdti_ shift_rcv
obuff (32 bit shift reg)
OPB_clk_count(9) lrck
OPB_clk_count(4) bclk
mclk
[0:31]
OPB_SELECT
OPB_clk_count(1)
OPB_RST
OPB_ABUS Compar
ator
C_BASEADDR
int_selected
latch_sample
send_
interrupt au_mcl au_bclk au_lrck
k_obuff
[0:31]
_obuff _obuff
enable
enable
OPB_RST
FSM
gate_aus_
dbus_output
[0:31]
AU_BCLK
Interrupt
AU_SDTI AUS_DATA AU_MCLK AU_LRCK
Figure 5: Audio Sampler Block Diagram
7
2.3 Ethernet Codec 2 SYSTEM DESIGN
PAD I/O while maintaining the logic for managing the OPB peripheral selection and setting address line
activity as well as data line direction based on OPB signals.
The timing diagram (Figure 7)and block diagram (Figure 6) for the Ethernet component are shown
below. Our timing follows the timing diagram except we add an extra cycle between taking the chip select
active and taking the IOWR active.
OPB_RST
SIn_xferAck
OPB_RNW
OPB_RNW
FSM
OPB_Select
CS
Comparator
[31:21]
OPB_ABUS
IORW
IORD
[9:0]
Ether_CS
BHE
AEN
[0:9] PB_A PB_D
[15:0] [0:15] [0:15] SIn_DBus

OPB_DBus
Figure 6: Ethernet Block Diagram
As described in the design document, we implemented diagnostic functionality so we could verify our
ability to read and write registers on the Ethernet Chip and generally check the health of the chip. In
particular, there are certain registers that have default values that can be checked to verify accurate reading
of registers. See the diagnostics function in ether.c (Section A.1.2)
Our initialization process also closely followed our design document. The following steps were taken:
1. Write 21h to Command Register to abort current DMA operations.

2. Wait 2 milliseconds (timout for inter-frame gap timer)
3. Write 01h to Data Control Register to enable 16-bit word transfers.
4. Write 00h to both Remote Byte Count Registers to zero out DMA counter.
5. Write 00h to Interrupt Mask Register to mask interrupts.
6. Write ffh to Interrupt Status Register to clear interrupt flags
7. Write 20h to Receive Configuration Register to put NIC in monitor mode
8. Write 02h to Transmit Configuration Register to put NIC in loop-back mode
9. Set RX Start and Stop, Boundary, and TX start page.
10. Reset interrupt mask and flags.
11. Write 22h to Command Register to start NIC
12. Write 00h to Transmit Configuration Register to set normal transmit operation
Writing to registers involved writing directly to the memory location of the register based on OPB
mapping. Writing data to the on-chip RAM required a remote DMA write which involved first setting the
target address and then the target byte count in appropriate registers. Once this was done, the data was
placed on the dataport a word at a time.
8
OPB_CLK
OPB_Select
OPB_ABUS
OPB_RNW
PB_LB
PB_UB
PB_A
CS_N
OE
WE
IDLE Selected Read Read2 Done
Figure 7: Ethernet Timing Diagram (for Read Only)
9
2.4 Microblaze 2 SYSTEM DESIGN
2.4 Microblaze
Our Microblaze code is used to initialize chips, interrupts, and stuff the default data into packet headers.
Our code size was shrunk below the Microblaze 4K limit so we were able to keep all of our code on BRAM.
2.5 RTP Packet Structure and Construction

The packets sent via ethernet are RTP packets which are UDP/IP packets with an additional set of headers
for streaming media. We write most of the IP, UDP, and RTP header data once to the Ethernet chip’s
on-board RAM during initialization and only update the payload, sequence number, and time stamp. We
have code for updating the UDP checksum as well but decided not to use it to reduce the amount of code
in the system.
The header structure is shown in Table 1.
0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30
MAC hdr Ethernet destination address

Ethernet destination address Ethernet source address
Ethernet source address
Length / Type Blank (no bits here)
ip hdr Version IHL TOS Total Length
ip v ip hl ip tos ip len
Identification Flags Fragment Offset
ip id (see below) ip off
Time to Live Protocol Header Checksum
ip ttl ip proto ip sum
Source Address
ip src
Destination Address
ip dst
udp hdr Source Port Destination Port
udp sport udp dport
Length Checksum
udp ulen udp sum
rtp hdr ver P X CC M PT Sequence Number
Timestamp
SSRC
Table 1: Header Structure for packets. Includes actual bit/byte values in many cases.
To view packets that we sent over Ethernet, we used Ethereal, an excellent network packet sniffing tool
which can be found at http://www.ethereal.com/. To test reception of UDP packets, we used netcat
on Linux. To test reception of RTP packets, we used rtpdump which can be found at http://www.cs.
columbia.edu/IRT/software/rtptools/
2.6 RTP Client

We used a number of different ways to receive our RTP packets and play them. Initially, we used rtpdump
and then played the audio using CoolEdit 2000. Once we were confident of the audio working, we moved to
mplayer as our regular RTP client.
mplayer -rawaudio on:channels=2:samplesize=2:bitrate=48100 rtp://128.59.144.169:3042
10
4 LESSONS LEARNED AND ADVICE FOR FUTURE PROJECTS
3 Process
We started off by splitting up the work into two main components. Avi and Sean worked on the Ethernet
peripheral and BJ and Oliver worked on the audio peripheral. We experienced significant difficulties devel-
oping our Ethernet peripheral from scratch and ended up basing our vhdl off the JAYCam project’s Ethernet
peripheral. Once the Ethernet peripheral was sending packets and the audio peripheral was digitizing audio,
the two components were combined into a single system that utilized the Microblaze for control. Avi and
Sean did the initial integration and then the team as a whole worked in shifts to get the client receiving
audio and to verify proper packet construction.
4 Lessons Learned and Advice for Future Projects

Sean Initially, we wanted to create a pure hardware system that had no Microblaze and passed audio data
directly from the audio peripheral to the Ethernet peripheral. However, time constraints and difficulties
with the ethernet codec lead us to reduce our requirements such that the Microblaze became necessary
for managing the initialization of peripherals and the passing of data between peripherals. I certainly
learned that getting the Ethernet to work properly was more difficult than I thought. I’ll keep this in
mind when I next scope out an embedded systems project.
Some additional lessons learned:
Understand how the whole build system works. Take the time to read the docs and figure out what each
file means and how it gets constructed. It’ll save you time later on when you’re trying to understand
why a pin doesn’t get connected.
Before writing any code, start out with pencil and paper. Write out your block diagrams and wave
forms first and double check them twice. It helps you plan out how you’ll pass data, which bits to
pass, and how to structure your FSM. It also helps you communicate with other team members and
anyone trying to provide advice about the project.
Compare your expected waveforms to reality: use the oscilloscope. We couldn’t understand why we
had problems with our Ethernet communication until we actually looked at the pins on the codec
chip and saw that they weren’t doing what we thought they were doing. Make sure your oscilloscope
handles high frequencies so you don’t miss anything.
Don’t forget the jumpers for Ethernet projects or any other strange hardware requirements. The board
we used required two jumpers in place before the ethernet chip would read our waveforms correctly.
Most of the boards in the lab don’t have them in place so make sure you have the hardware configured
correctly.
Symphony provides a great free VHDL simulation tool for Linux and Windows. Use it to see if your
waveforms are acting the way you expect them to act.
Do not believe data sheets if you can help it. Treat them as possible suggestions but don’t trust them.
Watch your code size if you intend to put everything in BRAM. Our code grew larger than the
allocated code space and we didn’t realize it so only part of our code for the Microblaze was actually
being executed. Strange behavior comes of this.
Avi Hardware is evil!!!

BJ This project gave me a good opportunity to learn VHDL. After spending weeks coding up the audio
hardware and testing and debugging the VHDL, I feel very comfortable with VHDL. I also feel that
I have a better idea of the timing issues involved in hardware and how to work with them. I have
previously studied low-level programming and different hardware protocols but I have never before
implemented my own hardware interface and controlled it with software. I now feel that I would be
comfortable designing my own embedded system which was not the case before I took this course. My
wife baught me a Virtex-4 based Xilinx board for my birthday last week so I hope to work on many
fun embedded projects in the future!
11
5 ACKNOWLEDGEMENTS
Oliver The greatest thing I learned in embedded system was grand scheme of organization and implementation
of an embedded system. VHDL was new to me before this class and now I feel I have a good handle on
how a project needs to be coded, debugged, re-coded, debugged, again and again. I found it interesting
to think about how fsm design allows settings to happen concurrently in the same clock signal. VHDL
is a marriage between code and clock that exists on a level that I can only compare to gate level
layout in VLSI. My work this semester was mostly accomplished by understanding the operation audio
codec and proofreading VHDL code. I also tested pins of the board with the oscilloscope to debug and
test codec output. This was the best way to initially see if our codec was operating reasonably. My
understanding of UDP and TCP has also been born from this class, and I now understand the basic
handling of headers and checksums.
5 Acknowledgements
Many thanks to Marcio Buss, Stephen Edwards, Josh Weinberg and JAYCam, Raj, and Christian for their
advice.
12
A CODE LISTING
A Code listing
A.1 C Source
A.1.1 ether.h
/∗−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
# CSEE 4 8 4 0 Embedded System Design
#
# SOBA S e r v e r
#
# Team W a r r i o r s : Avraham Sh in n a r as1619@columbia . edu
# Benjamin Dweck bjd2102@columbia . edu
# Oliver Irwin omi3@columbia . edu
# Sean White sw2061@columbia . edu
#
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−∗/
#include ” x i o . h”
#include ” x b a s i c t y p e s . h”
#define d p r i n t p r i n t
#i f n d e f BYTE
#define BYTE unsigned char
#endif
#i f n d e f WORD
#define WORD unsigned short
#endif
// d e f i n e the s i z e of a packet
#define MAC HEADER SIZE 1 4

#define IP HEADER SIZE 2 0
#define UDP HEADER SIZE 8
#define RTP HEADER SIZE 1 2
#define HEADER SIZE ( MAC HEADER SIZE+IP HEADER SIZE+UDP HEADER SIZE+RTP HEADER SIZE)
#define IP LENGTH ( PACKET SIZE−MAC HEADER SIZE)

#define UDP LENGTH ( IP LENGTH−IP HEADER SIZE )
#define IP CHECKSUM OFFSET 2 4

#define UDP CHECKSUM OFFSET 4 0
#define RTP SEQNUM OFFSET 4 4
#define RTP TIMESTAMP OFFSET 4 6
#define DATA CHUNK SIZE 1 6

#define DATA CHUNKS IN PACKET 9 0
#define PAYLOAD SIZE ( DATA CHUNKS IN PACKET∗DATA CHUNK SIZE)

#define PACKET SIZE ( PAYLOAD SIZE+HEADER SIZE)
#define PACKET BUFFERS 1
13
A.1 C Source A CODE LISTING
/ / NE2000 d e f i n i t i o n s
#define NIC BASE ( 0 x00A00400 ) / / Base I /O a d d r e s s o f t h e NIC c a r d
#define DATAPORT ( 0 x10 ∗ 2 )
#define NE RESET ( 0 x 1 f ∗ 2 )
/ / NIC page0 r e g i s t e r o f f s e t s
#define CMDR ( 0 x00 ∗ 2 ) / / command r e g i s t e r f o r r e a d & w r i t e
#define PSTART ( 0 x01 ∗ 2 ) / / page s t a r t r e g i s t e r f or w r i t e
#define PSTOP ( 0 x02 ∗ 2 ) / / page s t o p r e g i s t e r f o r w r i t e
#define BNRY ( 0 x03 ∗ 2 ) / / boundary r e g f or rd and wr
#define TPSR ( 0 x04 ∗ 2 ) / / tx s t a r t page s t a r t r e g f o r wr
#define TBCR0 ( 0 x05 ∗ 2 ) / / tx byte count 0 r e g f or wr
#define TBCR1 ( 0 x06 ∗ 2 ) / / tx byte count 1 r e g fo r wr
#define ISR ( 0 x07 ∗ 2 ) / / i n t e r r u p t s t a t u s r e g f or rd and wr
#define RSAR0 ( 0 x08 ∗ 2 ) / / low byte o f remote s t a r t addr
#define RSAR1 ( 0 x09 ∗ 2 ) / / h i byte o f remote s t a r t addr
#define RBCR0 ( 0 x0A ∗ 2 ) / / remote byte count r e g 0 fo r wr
#define RBCR1 ( 0 x0B ∗ 2 ) / / remote byte count r e g 1 fo r wr
#define RCR ( 0 x0C ∗ 2 ) / / rx c o n f i g u r a t i o n r e g f or wr
#define TCR ( 0 x0D ∗ 2 ) / / tx c o n f i g u r a t i o n r e g f or wr
#define DCR ( 0 x0E ∗ 2 ) / / data c o n f i g u r a t i o n r e g f o r wr
#define IMR ( 0 x0F ∗ 2 ) / / i n t e r r u p t mask r e g f or wr
/ / NIC page 1 r e g i s t e r o f f s e t s
#define PAR0 ( 0 x01 ∗ 2 ) / / p h y s i c a l addr r e g 0 f or rd and wr
#define CURR ( 0 x07 ∗ 2 ) / / c u r r e n t page r e g fo r rd and wr
#define MAR0 ( 0 x08 ∗ 2 ) / / m u l t i c a s t addr r e g 0 f or rd and WR
/ / B u f f e r Length and F i e l d D e f i n i t i o n Info

#define TXSTART 0 x41 // Tx b u f f e r s t a r t page
#define TXPAGES 8 // Pages f o r Tx b u f f e r
#define RXSTART (TXSTART+TXPAGES) / / Rx b u f f e r s t a r t page
#define RXSTOP 0 x7e // Rx b u f f e r end page fo r word mode
#define BASE ADDR (XPAR ETHERNET PERIPHERAL BASEADDR+0x400 )

/ / macros for r e a d i n g and w r i t t i n g r e g i s t e r s
#define o u t n i c ( addr , data ) XIo Out16 (NIC BASE+addr , data )
#define i n n i c ( addr ) ( X I o I n 1 6 (NIC BASE+addr ) )
#define PACKET END ADDRESS PACKET START ADDRESS+PACKET SIZE

#define PACKET START ADDRESS (TXSTART << 8)
#define PAYLOAD START ADDRESS PACKET START ADDRESS+HEADER SIZE ;

#define UDP CHECKSUM ADDRESS PACKET START ADDRESS+UDP CHECKSUM OFFSET
#define RTP SEQNUM ADDRESS PACKET START ADDRESS+RTP SEQNUM OFFSET
/∗ function prototypes , external i n t e r f a c e . ∗ /

BYTE i n i t ( ) ;
BYTE o u t p u t s a m p l e (WORD ∗ sample ) ;
int d i a g n o s t i c s ( ) ;
14
A CODE LISTING A.1 C Source
void w a i t ( int mult ) ;
/ ∗ s y m b o l i c names f o r v a r i o u s r e g i s t e r b i t s ∗ /
#define ISR PTX 0 x02 / / p a c k e t t r a n s m i t t e d with no error

#define ISR RXE 0 x04 / / r e c i e v e error
#define ISR RDC 0 x40 / / Remote DMA S u c c e s s f u l
#define CR STOP 0 x01

#define CR START 0 x02
#define CR TXP 0 x04
#define CR READ 0 x08
#define CR WRITE 0 x10
#define CR ABORT 0 x20
#define CR COMPLETE 0 x20
#define CR PAGE0 0 x00
#define CR PAGE1 0 x40
A.1.2 ether.c
/∗−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
#
# SOBA S e r v e r
#
# Team W a r r i o r s : Avraham S h i n n a r as1619@columbia . edu
#
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−∗/
#include ” e t h e r . h”
#include ” x p a r a m e t e r s . h”
#include ” x i n t c l . h”
/∗ function prototypes , i n t e r n a l helpers ∗/

s t a t i c BYTE send (WORD ∗ data , WORD addr , WORD dmalen ) ;
s t a t i c BYTE t r a n s m i t (WORD s e n d l e n ) ;
/ ∗ n o t e t h a t a t one p o i n t we had l o t s more f u n c t i o n s . t h e code

i n d i c a t e s where they were . Many o f them were f l a t t e n e d f o r code
s p a c e r e a s o n s ( t h e c o m p i l e r had some i n l i n i n g i s s u e s , p o s s i b l y due
t o out smashing t h e s t a c k ) . ∗ /
/ ∗ s t a t i c data ∗ /
/ ∗ s t o r e d w i t h o ut t h e one ’ s complement ∗ /
/ ∗ n o t e : i p checksum can a c t u a l l y be c o n s t a n t ! ! ∗ /
/ ∗ a l l t h e pseudo h e a d e r s and most o f t h e h e a d e r s on t h e udp checksum
can be c a l c u l a t e d i n advance . we j u s t need t o ask e t h e r e a l what i t
15
should be : ) . s i n c e time stamp and s e q u e n c e number a r e i n c r e m e n t s ,

we can j u s t add ( with c a r r i e s ) t h e s e i n c r e m e n t s t o t h e new i n i t i a l
values each new p a c k e t . s o a l l we need i s t h e update s t u f f i n append . ∗ /
/∗ s t a t i c u n s i g n e d l o n g udp checksum ; ∗ /
/ ∗ t h e r e a l n o t e : udp checksum can a c t u a l l y be ( and now i s ) 0 . This

means t h a t i t i s i g n o r e d . We o r i g i n a l l y wrote code t o c a l c u l a t e a
p r o p e r udp checksum ( i t i s s t i l l i n t h e code , j u s t commented out ) .
we l a t e r commented i t out and d e c i d e d t o u s e 0 due t o code s p a c e
l i m i t a t i o n s . ( t h i s a l s o a l l o w e d us t o put back i n d i a g n o s t i c s ) .
n o t e t o f u t u r e p e o p l e : smashing your s t a c k i s a bad i d e a .

∗/
s t a t i c WORD c u r p a y l o a d a d d r ;
struct {
WORD padding ;
WORD sequence number ;
unsigned long time stamp ;
} dynamic data ;
/∗ # d e f i n e UDP INIT CHECKSUM ( ˜ ( (WORD) ( 0 xaa78 ) ) ) ; ∗ /

/∗ # d e f i n e UDP INIT CHECKSUM ( ˜ ( (WORD) ( 0 xb15d ) ) ) ; ∗ /
s t a t i c BYTE h e a d e r [ HEADER SIZE ] = {

/∗ c r e a t e the s t a t i c portion of the packets ∗/
/ ∗ MAC h e a d e r ( 1 4 b y t e s ) ∗ /
/∗ D e s t i n a t i o n MAC a d d r e s s ( 6 b y t e s ) : f i x e d ∗ /
/ ∗ 0 − 5 ∗ 0 x00 , 0 x0C , 0 xF1 , 0 x73 , 0 x4C , 0 x9C ,
∗/
/ ∗ Micro4 MAC ∗ /
0 x00 , 0 x07 , 0 xE9 , 0 x43 , 0 x8A , 0 x38 ,
/∗ S o u r c e MAC a d d r e s s ( 6 b y t e s ) : f i x e d ∗ /
/ ∗ 6 ∗ / 0 x00 ,
/ ∗ 7 ∗ / 0 x0D ,
/ ∗ 8 ∗ / 0 x60 ,
/ ∗ 9 ∗ / 0 x7F ,
/ ∗ 1 0 ∗ / 0xF9 ,
/ ∗ 1 1 ∗ / 0xAF ,
/∗ Length ( 2 b y t e s ) : f i x e d ∗ /
/ ∗ used a s a type ∗/
/ ∗ 1 2 ∗ / 0 x08 ,
/ ∗ 1 3 ∗ / 0 x00 ,
/ ∗ IP h e a d e r ( 2 0 b y t e s ) ∗ /
/∗ Version ( 4 b i t s ) : f i x e d ∗/
/∗ IHL ( 4 b i t s ) : f i x e d ∗ /
/ ∗ 1 4 ∗ / 0 x45 ,
/∗ TOS ( 1 byte ) : f i x e d ∗ /
/ ∗ 1 5 ∗ / 0 x00 ,
/∗ T o t a l Length ( 2 b y t e s ) : f i x e d ∗ /
/ ∗ 1 6 ∗ / IP LENGTH>>8,
/ ∗ 1 7 ∗ / IP LENGTH & ( 0 x f f ) ,
/∗ I d e n t i f i c a t i o n ( 2 bytes ) : fixe d ∗/
16
/ ∗ 1 8 ∗ / 0 x00 ,
/ ∗ 1 9 ∗ / 0 x00 ,
/∗ Flags ( 3 b i t s ) : f i x e d ∗/
/∗ Fragment O f f s e t ( 1 3 b i t s ) : f i x e d ∗ /
/ ∗ 2 0 ∗ / 0 x00 ,
/ ∗ 2 1 ∗ / 0 x00 ,
/∗ TTL ( 1 byte ) : f i x e d ∗ /
/ ∗ f o r now , t h i s s h o u l d d i e on c o n t a c t ∗/
/ ∗ 2 2 ∗ / 0 x04 ,
/∗ P r o t o c o l ( 1 byte ) : f i x e d ∗ /
/ ∗ UDP=17 ∗/
/ ∗ 2 3 ∗ / 0 x11 ,
/∗ Header Checksum ( 2 b y t e s ) : updated . s e e u p d a t e i p c h e c k s u m ∗ /
/ / Micro4
0x8A , 0 x63 ,
/∗ S o u r c e IP ( 4 b y t e s ) : f i x e d ∗ /
/ ∗ 2 6 ∗ / 0 x80 ,
/ ∗ 2 7 ∗ / 0 x3B ,
/ ∗ 2 8 ∗ / 0 x95 ,
/ ∗ 2 9 ∗ / 0 xA2 ,
/∗ D e s t i n a t i o n IP ( 4 b y t e s ) : f i x e d ∗ /
/ / Micro4
128,59,144,169,
// / ∗ 3 0 ∗ / 1 2 8 ,
// / ∗ 3 1 ∗ / 5 9 ,
// / ∗ 3 2 ∗ / 1 4 4 ,
// / ∗ 3 3 ∗ / 1 6 8 ,
/ ∗ UDP h e a d e r ( 6 Bytes ) ∗ /
/∗ S o u r c e Port ( 2 b y t e s ) : f i x e d ∗ /
/ ∗ 3 4 ∗ / 0 x0B ,
/ ∗ 3 5 ∗ / 0 xE2 ,
/∗ D e s t i n a t i o n Port ( 2 b y t e s ) : f i x e d ∗ /
/∗ in decimal : 3 0 4 2 ∗ /
/ ∗ 3 6 ∗ / 0 x0B ,
/ ∗ 3 7 ∗ / 0 xE2 ,
/∗ Length ( 2 b y t e s ) : f i x e d ∗ /
/ ∗ 3 8 ∗ / UDP LENGTH>>8,
/ ∗ 3 9 ∗ / UDP LENGTH & 0 x f f ,
/∗ Checksum ( 2 b y t e s ) : updated ∗ /
/∗ 40 ∗/ 0 ,
/∗ 41 ∗/ 0 ,
/ ∗ RTP h e a d e r ( 1 2 b y t e s ) ∗ /
/∗ Version ( 2 b i t s ) : f i x e d ∗/
/∗ 10 ∗/
/∗ Padding ( 1 b i t ) : f i x e d ∗ /
/∗ 0 ∗/
/∗ Extension ( 1 b i t ) : f i x e d ∗/
/∗ 0 ∗/
/∗ CSRC count ( 4 b i t s ) : f i x e d ∗ /
/∗ 0 ∗/
/ ∗ 4 2 ∗ / 0 x80 ,
/∗ Marker b i t ( 1 b i t ) : f i x e d ∗ /
/∗ 0 ∗/
17
/∗ Payload type ( 7 b i t s ) : f i x e d ∗ /
/ ∗ L16 = 1 0 ( 2 c h a n n e l ( ( s e e
h t t p : / /www. n e t w o r k s o r c e r y . com/ enp / p r o t o c o l / r t p . htm ) ∗ /
/ ∗ 4 3 ∗ / 0 x0a ,
/∗ Sequence number ( 1 6 b i t s ) : updated ∗ /
/ ∗ 4 4 ∗ / 0 x00 ,
/ ∗ 4 5 ∗ / 0 x00 ,
/∗ Time stamp ( 3 2 b i t s ) : updated ∗ /
/ ∗ 4 6 ∗ / 0 x00 ,
/ ∗ 4 7 ∗ / 0 x00 ,
/ ∗ 4 8 ∗ / 0 x00 ,
/ ∗ 4 9 ∗ / 0 x00 ,
/∗ SSRC ( 3 2 b i t s ) : f i x e d ∗ /
/ ∗ s h o u l d be a random v a l u e : I don ’ t t h i n k t h i s i s what i s meant : )
−− s i n c e we don ’ t change our s o u r c e t r a n s p o r t a d d r e s s and don ’ t
h a n d l e m u l t i p l e s y n c h r o n i z a t i o n s o u r c e w i t h i n t h e same RTP
c h a n n e l , t h i s s h o u l d not be a problem . ∗ /
/ ∗ 5 0 ∗ / 0 x42 ,
/ ∗ 5 1 ∗ / 0 x42 ,
/ ∗ 5 2 ∗ / 0 x42 ,
/ ∗ 5 3 ∗ / 0 x42
/∗ CSRC l i s t ( 0 b i t s ) : f i x e d ∗ /
/ ∗ we a r e e v i l and don ’ t g i v e p r o p e r a t t r i b u t i o n t o s o u r c e s . ∗ /
};
/ ∗ a s i m p l e w a i t f u n c t i o n t h a t burns c l o c k c y c l e s . ∗ /
void w a i t ( int mult ) {
v o l a t i l e int j = 0 , i =1000000;
f o r ( ; i > 0; −− i ) {
f o r ( ; mult > 0; −− mult ) {
/ / a smart c o m p i l e r with a g g r e s i v e i n l i n e r s h o u l d u n r o l l t h i s
++j ;
}
}
}
/∗
INITIALIZATION
∗/
/ ∗ D i a g n o s t i c s based on page 3 1 o f t h e E t h e r n e t C o n t r o l l e r manual

Write on two p a g e s f i r s t and then r e a d t o a v o i d b e i n g f o o l e d by
data l a t c h e d i n both w r i t e and r e a d .
∗/
int d i a g n o s t i c s ( ) {
/ / o u t n i c (CMDR, 0 x21 ) ; / / s t o p AX88796
wait ( 1 0 ) ;
o u t n i c (CMDR, 0 x61 ) ;
o u t n i c (PSTART, 0 x4E ) ;
18
o u t n i c (CMDR, 0 x21 ) ;
o u t n i c (PSTOP , 0 x3E ) ;
o u t n i c (CMDR, 0 x61 ) ;
i f ( i n n i c (PSTART) ! = 0 x4e )
return 1 ;
o u t n i c (CMDR, 0 x21 ) ; / / switch t o page 0

i f ( i n n i c (PSTOP) ! = 0 x3e )
return 2 ;
i f ( i n n i c ( 0 x16 ∗ 2 ) ! = 0 x15 )
return 3 ;
i f ( i n n i c ( 0 x12 ∗ 2 ) ! = 0 x0c )
return 4 ;
i f ( i n n i c ( 0 x13 ∗ 2 ) ! = 0 x12 )
return 5 ;
return 0 ;
}
/ ∗ i n i t i a l i z e s t h e e t h e r n e t c a r d and our data s t r u c t u r e s . s e t s up t h e

s t a t i c p a r t o f t h e p a c k e t h e a d e r i n memory . ∗ /
BYTE i n i t ( ) {
int r e t ;
o u t n i c (NE RESET , i n n i c (NE RESET ) ) ; / / t r i g g e r a r e s e t

wait ( 2 ) ;
i f ( ( i n n i c ( ISR ) & 0 x80 ) = = 0 ) / / Report i f f a i l e d
{
p r i n t ( ” E t h e r n e t c a r d f a i l e d t o r e s e t ! \ r \n” ) ;
p r i n t ( ” E t h e r n e t NIC not p r e s e n t o r not i n i t i a l i z i n g c o r r e c t l y \ r \n” ) ;
return 1 ;
}
else
{
d p r i n t ( ” E t h e r n e t c a r d r e s e t s u c c e s s f u l ! \ r \n” ) ;
/∗ e t h e r r e s e t ( ) ; ∗ / / ∗ Reset E t h e r n e t c a r d , ∗ /
/ ∗ Write 2 1 h t o Command R e g i s t e r t o a b o r t c u r r e n t DMA o p e r a t i o n s . ∗ /

o u t n i c (CMDR, 0 x21 ) ;
/ ∗ Wait 2 m i l l i s e c o n d s ( timout f o r i n t e r−frame gap t i m e r ) ∗ /
wait ( 1 0 ) ;
/ ∗ Write 0 1 h t o Data C o n t r o l R e g i s t e r t o e n a b l e 16− b i t word t r a n s f e r s . ∗ /
o u t n i c (DCR, 0 x01 ) ;
/ ∗ Write 0 0 h t o both Remote Byte Count R e g i s t e r s t o z e r o out DMA c o u n t e r . ∗ /
o u t n i c (RBCR0 , 0 x00 ) ;
o u t n i c (RBCR1 , 0 x00 ) ;
/ ∗ Write 0 0 h t o I n t e r r u p t Mask R e g i s t e r t o mask i n t e r r u p t s . ∗ /
o u t n i c (IMR , 0 x00 ) ;
/ ∗ Write f f h t o I n t e r r u p t S t a t u s R e g i s t e r t o c l e a r i n t e r r u p t f l a g s ∗ /
19
o u t n i c ( ISR , 0 x f f ) ;
/ ∗ Write 2 0 h t o R e c e i v e C o n f i g u r a t i o n R e g i s t e r t o put NIC i n monitor mode ∗ /
o u t n i c (RCR, 0 x20 ) ;
/ ∗ Write 0 2 h t o Transmit C o n f i g u r a t i o n R e g i s t e r t o put NIC i n l o o p−back mode ∗ /
o u t n i c (TCR, 0 x02 ) ;
/ ∗ S e t RX S t a r t and Stop , Boundary , and TX s t a r t page . ∗ /
o u t n i c (PSTART , RXSTART) ;
o u t n i c (PSTOP , RXSTOP) ;
o u t n i c (BNRY, ( BYTE) (RXSTOP− 1 ) ) ;
o u t n i c (TPSR , TXSTART) ;
/ ∗ Reset i n t e r r u p t mask and f l a g s . ∗ /
o u t n i c ( ISR , 0 xFF ) ; // c l e a r i nt e rr u pt status register
o u t n i c (IMR , 0 x00 ) ; / / Mask c o m p l e t i o n i r q
/ ∗ Write 2 2 h t o Command R e g i s t e r t o s t a r t NIC ∗ /
o u t n i c (CMDR, 0 x22 ) ;
/ ∗ Write 0 0 h t o Transmit C o n f i g u r a t i o n R e g i s t e r t o s e t normal t r a n s m i t o p e r a t i o n ∗ /
o u t n i c (TCR, 0 x00 ) ;
d p r i n t ( ” E t h e r n e t c a r d i n t i a l i z a t i o n c o m p l e t e ! \ r \n” ) ;
}
/∗ i n i t p a c k e t s e t u p ( ) ; ∗ /
dynamic data . sequence number = 0 ;
dynamic data . time stamp = 0 ;
/∗ udp checksum = UDP INIT CHECKSUM ; ∗ /

c u r p a y l o a d a d d r = PAYLOAD START ADDRESS;
/ ∗ now l e t s i n i t i a l i z e t h e b u f f e r s . ∗ /
return send ( (WORD ∗ ) h e a d e r , PACKET START ADDRESS , 5 4 ) ; / / HEADER SIZE ) ;
}
/∗ a c t u a l l y transmits a ( f i l l e d in ) packet . ∗ /
s t a t i c BYTE t r a n s m i t (WORD s e n d l e n )
{
int j ;
o u t n i c (TPSR , TXSTART) ; / / s e t Transmit Page S t a r t R e g i s t e r
o u t n i c (TBCR0 , ( s e n d l e n&0 x f f ) ) ; / / s e t Transmit Byte Count
o u t n i c (TBCR1 , ( s e n d l e n >>8));
o u t n i c (CMDR, CR COMPLETE| CR TXP ) ; / / s t a r t t r a n s m i s s i o n

j =1000;
while ( j −−>0 && !( i n n i c ( ISR ) & ISR PTX ) ) ;
i f ( ! j ){
return 1 ;
}
o u t n i c ( ISR , 0 xFF ) ;
return 0 ;
}
20
/ ∗ low l e v e l f u n c t i o n t h a t d o e s dma t o send data t o c a r d . ∗ /

/ ∗ based on code from Josh ’ s group . ∗ /
s t a t i c BYTE send (WORD ∗ data , WORD addr , WORD dmalen ) {
int i , j , h ;
WORD c o u n t e r ;
WORD word ;
c o u n t e r = dmalen>>1;
o u t n i c (RSAR0 , ( addr&0 x f f ) ) ; / / s e t DMA s t a r t i n g a d d r e s s

o u t n i c (RSAR1 , ( addr >>8));
o u t n i c ( ISR , 0 xFF ) ; / / c l e a r ISR
o u t n i c (RBCR0 , ( dmalen&0 x f f ) ) ; / / s e t Remote DMA Byte Count

o u t n i c (RBCR1 , ( dmalen >>8));
o u t n i c (CMDR, CR WRITE | CR START ) ; / / s t a r t t h e DMA w r i t e − 0 x12
/ / change o r d e r o f MS/LS s i n c e DMA

/ / w r i t e s LS byte i n 1 5 − 8 , and MS byte i n 7−0
f or ( i = 0 ; i<c o u n t e r ; i ++){
word = ( data [ i ] < < 8 ) | ( data [ i ]>>8);
o u t n i c (DATAPORT, word ) ;
}
i f ( ! ( i n n i c ( ISR ) & ISR RDC ) ) {

// p r i n t ( ”Data − DMA d i d not f i n i s h \ r \n” ) ;
return 1 ;
}
o u t n i c (CMDR,CR COMPLETE) ;
return 0 ;
}
/∗ external i n t e r f a c e ∗/
/ ∗ t a k e s a 2 word sample , and s e n d s i t out . s e n d s p a c k e t i f needed ∗ /
/∗ 0 return i s success ∗/
BYTE o u t p u t s a m p l e (WORD ∗ sample ) {
BYTE r e t = 0 ;
/∗ WORD check ; ∗ /
/∗ r e t = append ( sample ) ; ∗ /
r e t = send ( sample , c u r p a y l o a d a d d r , 4 ) ;
/∗ i f ( ret )
return ret ; ∗/
c u r p a y l o a d a d d r +=4;
/ ∗ update checksums ∗ /
/∗ udp checksum += ∗( sample + 1 ) ; ∗ /
21
/∗ udp checksum += ∗( sample ) ; ∗ /

/∗ w h i l e ( udp checksum >>16) ∗/
/∗ udp checksum = ( udp checksum & 0 x f f f f ) + ( udp checksum > > 1 6 ) ; ∗ /
i f ( c u r p a y l o a d a d d r >= PACKET END ADDRESS) {

/∗ f i n a l i z e p a c k e t () ∗/
/ ∗ t a k e t h e o n e s complement , a s w e l l a s s h o v i n g i t i n t o a word ∗ /
/∗ check = ˜ ( (WORD) ( udp checksum&0 x f f f f ) ) ; ∗ /

/∗ check = 0 ; ∗ /
/∗ r e t = send (& check , UDP CHECKSUM ADDRESS , 2 ) ; ∗ /
/∗ i f ( ret ) { ∗/
/∗ p r i n t ( ” E r r o r w r i t i n g udp checksum \ r \n ” ) ; ∗ /
/∗ return ret ; ∗/
/∗ } ∗/
r e t = send ( ( (WORD ∗)& dynamic data ) + 1 , RTP SEQNUM ADDRESS , 6 ) ;
if ( ret ) {
p r i n t ( ” E r r o r w r i t i n g r t p h e a d e r data \ r \n” ) ;
}
if ( ret ) {
p r i n t ( ” E r r o r f i n a l i z i n g p a c k e t . d r o p p i n g . \ r \n” ) ;
} else {
r e t = t r a n s m i t (PACKET SIZE ) ;
// p r i n t ( ” p r o b a b l e s u c c e s s t r a n s m i t t i n g p a c k e t . happy ! happy ! \ r \n” ) ;
}
/∗ next packet setup ( ) ; ∗ /

++dynamic data . sequence number ;
dynamic data . time stamp += 20;
/∗ udp checksum = dynamic data . sequence number + ( u n s i g n e d s h o r t ) ( ( dynamic data . time st

/∗ udp checksum += UDP INIT CHECKSUM ; ∗ /
c u r p a y l o a d a d d r=PAYLOAD START ADDRESS;
}
return r e t ;
}
A.1.3 main.c
/∗−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
#
# SOBA S e r v e r
#
# Team W a r r i o r s : Avraham Sh i nn a r as1619@columbia . edu
22
#
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−∗/
#include ” x p a r a m e t e r s . h”
#include ” e t h e r . h”
#include ” x i n t c l . h”
unsigned long u a r t o u t = 0 ;
BYTE new data =0;
void a u d i o s a m p l e r h a n d l e r ( void ∗ c a l l b a c k )
{
// m i c r o b l a z e d i s a b l e i n t e r r u p t s ( ) ;
new data =1;
// m i c r o b l a z e e n a b l e i n t e r r u p t s ( ) ;
}
int main ( )
{
int r e t ;
/ / FIRST : Run d i a g n o s t i c s , i n i t e t h e r n e t c o n t r o l l e r , and s t u f f p a c k e t s
p r i n t ( ”\ r \n” ) ;
p r i n t ( ” H e l l o World ! \ r \n” ) ;
p r i n t ( ” Running d i a g n o s t i c s \ r \n” ) ;
i f ( r e t=d i a g n o s t i c s ( ) ) {
p r i n t ( ” D i a g n o s t i c s f a i l e d . i n t e r n a l e r r o r number ” ) ;
putnum ( r e t ) ;
p r i n t ( ”\ r \n” ) ;
} else {
p r i n t ( ” D i a g n o s t i c s s u c c e s s f u l . \ r \n” ) ;
}
if ( init ()) {
p r i n t ( ” E t h e r n e t NIC not p r e s e n t o r not i n i t i a l i z i n g c o r r e c t l y \ r \n” ) ;
return 1 ;
}
/∗ i n i t i a l i z i n g interrupts ∗/
XI ntc mEnableIntr (XPAR INTC SINGLE BASEADDR , XPAR AUDIO SAMPLER INTERRUPT MASK ) ;
XIntc mMasterEnable (XPAR INTC SINGLE BASEADDR ) ;
X I n t c R e g i s t e r H a n d l e r (XPAR INTC SINGLE BASEADDR , XPAR INTC AUDIO SAMPLER INTERRUPT INTR ,
a u d i o s a m p l e r h a n d l e r , ( void ∗ ) 0 ) ;
microblaze enable interrupts ();
for ( ; ; ) {
/ ∗ new data i s s e t i n t h e i n t e r r u p t h a n d l e r when new data i s ready . ∗ /
i f ( new data == 1) {
23
A.2 clkgen A CODE LISTING
new data = 0 ;
/ ∗ grab t h e data from t h e a u d i o c o n t r o l l e r ∗/

u a r t o u t = X I o I n 3 2 (XPAR AUDIO SAMPLER BASEADDR ) ;
/ ∗ t h e s t a n d a r d a u d i o format i s l i t t l e e n d i a n , s o we swap t h e b y t e s :
we have 4 b y t e s , they g e t r e o r d e r e d from 1 2 3 4 t o 2 1 4 3 . ∗ /
u a r t o u t = ( ( u a r t o u t >> 24 & 0 x f f ) < < 1 6 ) |
( ( u a r t o u t >> 16 & 0 x f f ) < < 2 4 ) |
( u a r t o u t >> 8 & 0 x f f ) |
(( uart out & 0 x f f ) << 8);
/ ∗ output t h e new sample t o t h e e t h e r n e t c a r d ∗ /

o u t p u t s a m p l e ( (WORD ∗ ) ( & u a r t o u t ) ) ;
}
}
return 0 ;
}
A.2 clkgen
A.2.1 data/clkgen v2 1 0.pao
################################################################################
##
## Copyright ( c ) 1 9 9 5 − 2 0 0 2 X i l i n x , I n c . A l l r i g h t s r e s e r v e d . X i l i n x , I n c .
##
## MicroBlaze Brd ZBT ClkGen v2 0 0 a . pao
##
## P e r i p h e r a l Analyze Order
##
################################################################################
l i b clkgen v1 00 a clkgen
A.2.2 data/clkgen v2 1 0.mpd
###################################################################
##
## M i c r o p r o c e s s o r P e r i p h e r a l D e f i n i t i o n : g e n e r a t e d by p s f u t i l
##
## Template MPD fo r P e r i p h e r a l : MicroBlaze Brd ZBT ClkGen
##
###################################################################
BEGIN c l k g e n , IPTYPE = IP
## P e r i p h e r a l Options
#OPTION IPTYPE = IP
OPTION HDL = VERILOG
OPTION IMP NETLIST = TRUE
## P o r t s
24
A CODE LISTING A.2 clkgen
PORT FPGA CLK1 = ”” , DIR = IN , IOB STATE = BUF
PORT s y s c l k = ”” , DIR = OUT

PORT p i x e l c l o c k = ”” , DIR = OUT
PORT f p g a r e s e t = ”” , DIR = OUT
PORT i o c l o c k =”” , DIR = OUT
END
A.2.3 hdl/verilog/clkgen.v
module c l k g e n (
FPGA CLK1 ,
sys clk ,
pixel clock ,
io clock ,
fpga reset
);
i n p u t FPGA CLK1 ;
output s y s c l k , p i x e l c l o c k , i o c l o c k , f p g a r e s e t ;
wire c l k i b u f , c l k 1 x i , c l k 2 x i ;
// w i r e c l k 1 x , c l k 0 5 x ;
// w i r e c l k i b u f , c l k 1 x i , c l k 0 5 x i , c l k 2 x i ;
wire locked ;
a s s i g n p i x e l c l o c k = 0 ; / / new
IBUFG c l k i b u f ( . I (FPGA CLK1 ) , . O( c l k i b u f ) ) ;

BUFG bg1 ( . I ( c l k 1 x i ) , . O( s y s c l k ) ) ;
//BUFG bg05 ( . I ( c l k 0 5 x i ) , . O( p i x e l c l o c k ) ) ;
BUFG bg2 ( . I ( c l k 2 x i ) , . O( i o c l o c k ) ) ;
// synopsys t r a n s l a t e o f f
/ / defparam v d l l . CLKDV DIVIDE = 2 . 0 ;
// synopsys t r a n s l a t e o n
/ / s y n t h e s i s a t t r i b u t e CLKDV DIVIDE o f v d l l i s 2
//CLKDLL v d l l ( . CLKIN( c l k i b u f ) , . CLKFB( s y s c l k ) , . CLK0( c l k 1 x i ) ,
// .CLKDV( c l k 0 5 x i ) , . CLK2X( c l k 2 x i ) , . RST ( 1 ’ b0 ) , . LOCKED( l o c k e d ) ) ;
CLKDLL v d l l ( . CLKIN( c l k i b u f ) , . CLKFB( s y s c l k ) , . CLK0( c l k 1 x i ) ,
.CLK2X( c l k 2 x i ) , . RST ( 1 ’ b0 ) , . LOCKED( l o c k e d ) ) ;
assign fpga reset = ˜ locked ;
endmodule
25
A.3 Audio Controller A CODE LISTING
A.3 Audio Controller

Note that this code, while functional, was not used because of the conflict with the ethernet device. This
could be resolved by writing an intelligent bus master, but we did not have time.
A.3.1 data/opb audio cntlr v2 1 0.pao

###############################################################
#
# o p b a u d i o c n t l r pao f i l e
#
###############################################################
lib opb audio cntlr v1 00 a opb audio cntlr

A.3.2 data/opb audio cntlr v2 1 0.mpd
###################################################################
##
## M i c r o p r o c e s s o r P e r i p h e r a l D e f i n i t i o n
##
###################################################################
BEGIN o p b a u d i o c n t l r , IPTYPE = PERIPHERAL , EDIF=TRUE
BUS INTERFACE BUS = SOPB , BUS STD = OPB , BUS TYPE = SLAVE
## G e n e r i c s for VHDL
PARAMETER c baseaddr = 0xFFFFFFFF , DT = s t d l o g i c v e c t o r , MIN SIZE = 0xFF
PARAMETER c highaddr = 0 x00000000 , DT = std logic vector
PARAMETER c opb awidth = 32, DT = integer
PARAMETER c opb dwidth = 32, DT = integer
## P o r t s
PORT opb abus = OPB ABus , DIR = IN , VEC = [ 0 : ( c o p b a w i d t h − 1 ) ] , BUS = SOPB
PORT opb be = OPB BE , DIR = IN , VEC = [ 0 : ( ( c o p b d w i d t h / 8 ) − 1 ) ] ,BUS = SOPB
PORT o p b c l k = ”” , DIR = IN , SIGIS=CLK, BUS = SOPB
PORT opb dbus = OPB DBus , DIR = IN , VEC = [ 0 : ( c o p b d w i d t h − 1 ) ] , BUS = SOPB
PORT opb rnw = OPB RNW, DIR = IN , BUS = SOPB
PORT o p b r s t = OPB Rst , DIR = IN , BUS = SOPB
PORT o p b s e l e c t = OPB select , DIR = IN , BUS = SOPB
PORT o p b s e q a d d r = OPB seqAddr , DIR = IN , BUS = SOPB
PORT s l n d b u s = Sl DBus , DIR = OUT, VEC = [ 0 : ( c o p b d w i d t h − 1 ) ] , BUS = SOPB
PORT s l n e r r a c k = S l e r r A c k , DIR = OUT, BUS = SOPB
PORT s l n r e t r y = Sl retry , DIR = OUT, BUS = SOPB
PORT s l n t o u t s u p = S l t o u t S u p , DIR = OUT, BUS = SOPB
PORT s l n x f e r a c k = S l x f e r A c k , DIR = OUT, BUS = SOPB
PORT AU CSN = ”” , DIR=OUT, IOB STATE=BUF

PORT PB D = ”” , DIR = INOUT , VEC = [ 1 5 : 0 ] , 3 STATE=FALSE , IOB STATE=BUF
END
A.3.3 data/opb audio cntlr.vhd
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
−−
26
A CODE LISTING A.3 Audio Controller
−− Audio C o n t r o l l e r OPB P e r i p h e r a l
−−
−− Benjamin Dweck
−− bjd2102@columbia . edu
−−
−− O l i v e r I r w i n
−− omi3@columbia . edu
−−
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
−−
−− Clock D i v i d e r
−−
−− Notes : Clock output s t a r t s out low a f t e r r e s e t
−−
−− Used t o d i v i d e OPB Clk t o g e n e r a t e AU CCLK
−−
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
library ieee ;
use i e e e . s t d l o g i c 1 1 6 4 . a l l ;
entity clock divider is
generic (
FACTOR : i n t e g e r : = 1 0 ) ; −− Clock d i v i d e−by f a c t o r
port (
c l k i n : in s t d l o g i c ; −− Input c l o c k
rst : in s t d l o g i c ; −− Reset s i g n a l
c l k o u t : out s t d l o g i c ) ; −− Output c l o c k
end c l o c k d i v i d e r ;
a r c h i t e c t u r e arch of c l o c k d i v i d e r i s
s i g n a l count : i n t e g e r : = 0 ;
s i g n a l output : s t d l o g i c : = ’ 0 ’ ;
begin
c l k o u t <= output ;
divide : process ( clk in , rst )

begin
i f ( r s t = ’ 1 ’ ) then
output < = ’ 0 ’ ;
count <= 0;
e l s i f ( c l k i n ’ e v e n t and c l k i n = ’ 1 ’ ) then
27
count <= count + 1 ;
i f ( count = (FACTOR/ 2 ) − 1 ) then

output <= NOT output ;
count <= 0;
end i f ;
end i f ;
end p r o c e s s d i v i d e ;
end a r c h ;
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
−−
−− 5− b i t Unsigned N e g a t i v e Edge T r i g g e r e d Up Counter
−− with Asynchronous Reset
−−
−− Used t o keep t r a c k o f number o f AU CCLK c y c l e s
−−
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
library ieee ;
use i e e e . s t d l o g i c u n s i g n e d . a l l ;
entity counter i s
port (
clk , reset : in s t d l o g i c ;
count : out s t d l o g i c v e c t o r ( 4 downto 0 )
);
end c o u n t e r ;
a r c h i t e c t u r e arch of counter i s
s i g n a l tmp : s t d l o g i c v e c t o r ( 4 downto 0 ) ;
begin
process ( clk , reset )

begin
i f ( r e s e t = ’ 1 ’ ) then
tmp <= ”00000” ;
e l s i f ( c l k ’ e v e n t and c l k = ’ 0 ’ ) then
tmp <= tmp + 1 ;
end i f ;
end p r o c e s s ;
count <= tmp ;
end a r c h ;
28
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
−−
−− 16− b i t N e g a t i v e Edge T r i g g e r e d Right S h i f t R e g i s t e r
−− with A c t i v e High Load and S e r i a l Out
−−
−− Used t o l a t c h onto data t o be output t o t h e a u d i o c o d e c and
−− s h i f t i t out s e r i a l l y .
−−
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
library ieee ;
entity shift out is

port (
C , ALOAD : i n s t d l o g i c ;
D : i n s t d l o g i c v e c t o r ( 1 5 downto 0 ) ;
SO : out s t d l o g i c
);
end s h i f t o u t ;
a r c h i t e c t u r e arch of s h i f t o u t i s
s i g n a l tmp : s t d l o g i c v e c t o r ( 1 5 downto 0 ) ;
begin
p r o c e s s (C , ALOAD, D)
begin
i f (ALOAD= ’ 1 ’ ) then
tmp <= D;
e l s i f (C ’ e v e n t and C= ’ 0 ’ ) then
tmp < = ’ 0 ’ & tmp ( 1 5 downto 1 ) ;
end i f ;
end p r o c e s s ;
SO <= tmp ( 0 ) ;
end a r c h ;
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
−−
−− 8− b i t P o s i t i v e Edge T r i g g e r e d Right S h i f t R e g i s t e r
−− with S e r i a l In and P a r a l l e l Out
−−
−− Used t o r e c e i v e data s e r i a l l y from t h e a u d i o c o d e c
−−
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
29
library ieee ;
entity shift in is
port (
SI : i n s t d l o g i c ;
C : in s t d l o g i c ;
D : out s t d l o g i c v e c t o r ( 7 downto 0 )
);
end s h i f t i n ;
a r c h i t e c t u r e arch of s h i f t i n i s
s i g n a l tmp : s t d l o g i c v e c t o r ( 7 downto 0 ) ;
begin
p r o c e s s (C)
begin
i f (C ’ e v e n t and C= ’ 1 ’ ) then
tmp <= SI & tmp ( 7 downto 1 ) ;
end i f ;
end p r o c e s s ;
D <= tmp ;
end a r c h ;
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
−−
−− Audio P e r i p h e r a l
−−
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
library ieee ;
entity opb audio cntlr is
generic (
C OPB AWIDTH : integer := 32;
C OPB DWIDTH : integer := 32;
C BASEADDR : s t d l o g i c v e c t o r ( 0 to 3 1 ) := X”00000000” ;
C HIGHADDR : s t d l o g i c v e c t o r ( 0 to 3 1 ) := X”FFFFFFFF” ) ;
port (
−− OPB Input S i g n a l s
OPB Clk : in s t d logic ;
OPB Rst : in s t d logic ;
OPB ABus : in s t d logic v e c t o r ( 0 t o C OPB AWIDTH−1);
OPB BE : in s t d logic v e c t o r ( 0 t o C OPB DWIDTH/8−1);
30
OPB DBus : in std logic v e c t o r ( 0 t o C OPB DWIDTH−1);

OPB RNW : in std logic ;
OPB select : in std logic ;
OPB seqAddr : in std logic ; −− S e q u e n t i a l Address
−− OPB Output Signals

Sln DBus : out s t d logic v e c t o r ( 0 t o C OPB DWIDTH−1);
Sln errAck : out s t d logic ; −− ( unused )
Sln retry : out s t d logic ; −− ( unused )
Sln toutSup : out s t d logic ; −− Timeout s u p p r e s s
Sln xferAck : out s t d logic ; −− T r a n s f e r acknowledge
−− Audio IO S i g n a l s
AU CSN : out std logic ; −− Audio Chip S e l e c t ( A c t i v e LOW)
PB D : i n o u t s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; −− O f f−FPGA P e r i p h e r a l
−− Data Bus
−− AU CCLK : out s t d l o g i c ; −− Audio Cntl Clock

−− AU CDTI : out s t d l o g i c ; −− Audio Cntl Data In (TO Codec )
−− AU CDTO : in s t d l o g i c ) ; −− Audio Cntl Data Out (FROM Codec )
end o p b a u d i o c n t l r ;
architecture behavioral of opb audio cntlr i s
−− Audio Address and Data Bus Widths

c o n s t a n t AU AWIDTH : i n t e g e r : = 8 ; −− Width o f a u d i o c o n t r o l l e r a d d r e s s
c o n s t a n t AU DWIDTH : i n t e g e r : = 8 ; −− Width o f a u d i o c o n t r o l l e r data word
−− I n t e r n a l b u f f e r / u t i l l i t y signals
signal int au csn : std logic := ’1’; −− Used a s a u d i o c o d e c c h i p s e l e c t ( a
signal int au cclk : std logic ; −− Used a s s e r i a l c l o c k s i g n a l t o a u d
signal int au cclk count : std logic v e c t o r ( 4 downto 0 ) ; −− Used t o keep t r a c k o
signal int au cclk count rst : std logic ; −− To r e s e t c c l k c o u n t e r
signal int au cdti : std logic ; −− AU CDT
signal int au cdti buff : std logic v e c t o r ( 1 5 downto 0 ) ; −− Input t o CDTI s h i f t r e g
signal int au cdti load : std logic ; −− CDTI s
signal int au cdto buff : std logic v e c t o r (AU DWIDTH−1 downto 0 ) ; −− Data t o be s
−− I n t e r n a l u t i l l i t y s i g n a l s
signal int selected : std logic ; −− I n t e r n a l c h i p s e l e c t s i g n a l
signal int output enable : std logic ; −− Enable output from p e r i p h e r a l t o OPB bus
−− S t a t e c o n s t a n t s
−− C r i t i c a l : S l n x f e r A c k i s g e n e r a t e d d i r e c t l y from s t a t e b i t 0 !
c o n s t a n t STATE BITS : i n t e g e r : = 2 ;
constant Idle : std logic vector ( 0 t o STATE BITS− 1 ) : = ”00” ;
constant Transfer : std logic vector ( 0 t o STATE BITS− 1 ) : = ”01” ;
c o n s t a n t Ack : std logic vector ( 0 t o STATE BITS− 1 ) : = ”11” ;
s i g n a l p r e s e n t s t a t e , n e x t s t a t e : s t d l o g i c v e c t o r ( 0 t o STATE BITS−1);
31
−− Clock d i v i d e r ( used with OPB Clk t o g e n e r a t e AU CCLK)

component c l o c k d i v i d e r i s
g e n e r i c (FACTOR : i n t e g e r : = 1 0 ) ; −− D i v i d e 5 0 MHz OPB Clk => 5 MHz AU CCLK
port (
clk in : in s t d l o g i c ;
rst : in s t d l o g i c ;
c l k o u t : out s t d l o g i c ) ;
end component ;
−− CCLK Counter
component c o u n t e r i s
port (
clk : in s t d l o g i c ;
reset : in s t d l o g i c ;
count : out s t d l o g i c v e c t o r ( 4 downto 0 ) ) ;
end component ;
−− Transmit R e g i s t e r ( AU CDTI)
component s h i f t o u t i s
port (
C , ALOAD : i n s t d l o g i c ;
D : i n s t d l o g i c v e c t o r ( 1 5 downto 0 ) ;
SO : out s t d l o g i c ) ;
end component ;
−− R e c e i v e R e g i s t e r (AU CDTO)
component s h i f t i n i s
port (
D : out s t d l o g i c v e c t o r ( 7 downto 0 ) ) ;
end component ;
−− Output b u f f e r for AU CSN

component OBUF F 8
port (
O : out s t d u l o g i c ; −− Out t o Audio c o d e c
I : in s t d ul og i c ) ; −− In from Audio c o d e c
end component ;
−− T r i s t a t e output b u f f e r fo r AU CCLK and AU CDTI

component IOBUF F 8
port (
O : out s t d u l o g i c ; −− Out from t h e b u f f e r
I : in s t d ul og i c ; −− In t o t h e b u f f e r
IO : i n o u t s t d l o g i c ; −− In /Out t o p i n
T : in s td ul og i c ) ; −− A c t i v e−low output e n a b l e
end component ;
begin −− b e h a v i o r a l
−− A / 6 Clock D i v i d e r t o g e n e r a t e CCLK
clkdiv : clock divider
32
g e n e r i c map (FACTOR => 12)

p o r t map ( OPB Clk , i n t a u c s n , i n t a u c c l k ) ;
−− CCLK Counter
ccounter : counter
p o r t map ( i n t a u c c l k , i n t a u c c l k c o u n t r s t , i n t a u c c l k c o u n t ) ;
−− Transmit R e g i s t e r
cdti buff : shift out
p o r t map ( i n t a u c c l k , i n t a u c d t i l o a d , i n t a u c d t i b u f f , i n t a u c d t i ) ;
−− R e c e i v e R e g i s t e r
cdto buff : s h i f t i n
p o r t map ( PB D ( 2 ) , i n t a u c c l k , i n t a u c d t o b u f f ) ;
−− Output b u f f e r s for output s i g n a l s

a u c s n o b u f f : OBUF F 8
p o r t map (
O => AU CSN ,
I => i n t a u c s n ) ;
a u c c l k i o b u f f : IOBUF F 8
p o r t map (
O => n u l l ,
I => i n t a u c c l k ,
IO => PB D ( 0 ) ,
T => i n t a u c s n ) ;
a u c d t i i o b u f f : IOBUF F 8
p o r t map (
O => n u l l ,
I => i n t a u c d t i ,
IO => PB D ( 1 ) ,
T => i n t a u c s n ) ;
d b u s i o b u f f g e n : for i i n 3 t o 1 5 g e n e r a t e
d b u s i o b u f f : IOBUF F 8
p o r t map (
O => n u l l ,
I => ’0’,
IO => PB D( i ) ,
T => i n t a u c s n ) ;
end g e n e r a t e ;
end g e n e r a t e d b u s i o b u f f g e n ;
−− Produce c h i p s e l e c t s i g n a l by d e c o d i n g OPB a d d r e s s and c h e c k i n g OPB select
i n t s e l e c t e d <=
’ 1 ’ when OPB select = ’ 1 ’ and
OPB ABus ( 0 t o C OPB AWIDTH−AU AWIDTH−1) =
C BASEADDR( 0 t o C OPB AWIDTH−AU AWIDTH−1)
else ’ 0 ’ ;
−− Unused o u t p u t s
33
Sln errAck <= ’0’;

Sln retry <= ’0’;
Sln DBus ( 0 t o C OPB DWIDTH−AU DWIDTH−1) <= ( o t h e r s = > ’ 0 ’ ) ;
−− Tie OPB ABus and OPB DBus t o t h e AU CDTI b u f f e r

int au cdti buff (0) <= ’1’; −− S e t Op Code b i t s
int au cdti buff (1) <= ’1’;
int au c d t i b u f f (2) <= NOT OPB RNW;
int au c d t i b u f f (3) <= OPB ABus ( 3 1 ) ; −− S e t R e g i s t e r Address b i t s
int au c d t i b u f f (4) <= OPB ABus ( 3 0 ) ;
int au cdti buff (7) <= ’0’;
int au c d t i b u f f (8) <= OPB DBus ( 3 1 ) ; −− S e t C o n t r o l Data b i t s
int au c d t i b u f f (9) <= OPB DBus ( 3 0 ) ;
−− Tie t h e 0 ’ th s t a t e b i t t o S l n x f e r A c k
S l n x f e r A c k <= p r e s e n t s t a t e ( 0 ) ;
−− P r o c e s s t o q u a l i f y OPB output u s i n g i n t o u t p u t e n a b l e
r e g i s t e r o p b o u t p u t s : p r o c e s s ( OPB Rst , OPB RNW, i n t o u t p u t e n a b l e )
begin
i f OPB Rst = ’ 1 ’ then
Sln DBus (C OPB DWIDTH−AU DWIDTH t o C OPB DWIDTH−1) <= ( o t h e r s = > ’ 0 ’ ) ;
else
i f i n t o u t p u t e n a b l e = ’ 1 ’ and OPB RNW = ’ 1 ’ then
Sln DBus (C OPB DWIDTH−AU DWIDTH t o C OPB DWIDTH−1) <= i n t a u c d t o b u f f ;
else
Sln DBus (C OPB DWIDTH−AU DWIDTH t o C OPB DWIDTH−1) <= ( o t h e r s = > ’ 0 ’ ) ;
end i f ;
end i f ;
end p r o c e s s r e g i s t e r o p b o u t p u t s ;
−− S e q u e n t i a l p a r t o f t h e FSM
f s m s e q : p r o c e s s ( OPB Clk , OPB Rst )
begin
i f OPB Rst = ’ 1 ’ then −− Asynchronous r e s e t t o I d l e s t a t e
p r e s e n t s t a t e <= I d l e ;
e l s i f OPB Clk ’ e v e n t and OPB Clk = ’ 1 ’ then −− P o s i t i v e edge OPB Clk
p r e s e n t s t a t e <= n e x t s t a t e ; −− advance t o next s t a t e
end i f ;
end p r o c e s s f s m s e q ;
−− Combinational p a r t o f t h e FSM
fsm comb : p r o c e s s ( OPB Clk , p r e s e n t s t a t e , i n t s e l e c t e d , i n t a u c c l k c o u n t )
begin
34
case p r e s e n t s t a t e i s
when I d l e =>
Sln toutSup < = ’ 0 ’ ; −− D i s a b l e S u p r e s s−Timeout
int au csn <= ’1’; −− D e s e l e c t Audio Codec
int au cdti load <= ’1’; −− Open i n p u t t o CDTI s h i f t r e g
int output enable <= ’0’; −− D i s a b l e output t o Sln DBus
int au cclk count rst <= ’1’; −− Reset AU CCLK c o u n t e r
i f i n t s e l e c t e d = ’ 1 ’ then
n e x t s t a t e <= T r a n s f e r ;
else
n e x t s t a t e <= I d l e ;
end i f ;
when T r a n s f e r =>
Sln toutSup < = ’ 1 ’ ; −− S u p r e s s OPB Timeout
int au cdti load <= ’0’; −− Latch a u d i o c o d e c a d d r e s s / data from OPB
int au cclk count rst <= ’0’; −− S t a r t c o u n t e r
i f i n t a u c c l k c o u n t = ”10000” then −− IF l a s t ( 1 6 th ) CCLK c y c l e e l a p s e d . . .

int au csn <= ’1’; −− D e s e l e c t a u d i o c o d e c
int output enable <= ’1’; −− Enable Sln DBus output
n e x t s t a t e <= Ack ; −− Ack t r a n s f e r
else −− ELSE . . .
int au csn <= ’0’; −− Keep a u d i o c o d e c s e l e c t e d
int output enable <= ’0’; −− Keep Sln DBus output s u p r e s s e d
n e x t s t a t e <= T r a n s f e r ; −− Continue t r a n s f e r i n g data t o a u d i o c o d e c
end i f ;
else −− I f d e s e l e c t e d by OPB master => I d l e

Sln toutSup <= ’0’;
int au csn <= ’1’;
int au cdti load <= ’1’;
int output enable <= ’0’;
int au cclk count rst <= ’1’;
end i f ;
when Ack => −− Send ACK

Sln toutSup < = ’ 1 ’ ; −− Keep t i m e o u t s u p r e s s e d
int au csn <= ’1’; −− D e s e l e c t audio codec
i n t o u t p u t e n a b l e < = ’ 1 ’ ; −− Enable OPB output
when o t h e r s => −− ELSE => I d l e

int au csn <= ’1’;
int output enable <= ’0’;
35
A.4 Audio Sampler A CODE LISTING
end case ;
end p r o c e s s fsm comb ;
end b e h a v i o r a l ;
A.4 Audio Sampler
A.4.1 data/opb audio sampler v2 1 0.pao
#−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
#− CSEE 4 8 4 0 Embedded System Design − Audio Sampling OPB P e r i p h e r a l ( pao )
#−
#− SOBA S e r v e r
#−
#− Team W a r r i o r s : Avraham Sh i nn a r as1619@columbia . edu
#− Benjamin Dweck bjd2102@columbia . edu
#− Oliver Irwin omi3@columbia . edu
#− Sean White sw2061@columbia . edu
#−
#−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
###############################################################
#
# o p b a u d i o s a m p l e r pao f i l e
#
###############################################################
l i b opb audio sampler v1 00 a opb audio sampler

A.4.2 data/opb audio sampler v2 1 0.mpd
#−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
#− CSEE 4 8 4 0 Embedded System Design − Audio Sampling OPB P e r i p h e r a l ( mpd)
#−
#− SOBA S e r v e r
#−
#− Team W a r r i o r s : Avraham Sh i nn a r as1619@columbia . edu
#− Benjamin Dweck bjd2102@columbia . edu
#− Oliver Irwin omi3@columbia . edu
#− Sean White sw2061@columbia . edu
#−
#−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
###################################################################
##
##
## P e r i p h e r a l : Audio Sampler
##
###################################################################
BEGIN o p b a u d i o s a m p l e r , IPTYPE = PERIPHERAL , EDIF=TRUE
36
A CODE LISTING A.4 Audio Sampler
# Bus I n t e r f a c e
PARAMETER c baseaddr = 0xFFFFFFFF , DT = s t d l o g i c v e c t o r , MIN SIZE = 0xFF
PARAMETER c highaddr = 0 x00000000 , DT = std logic vector
PARAMETER c opb awidth = 32, DT = integer
PARAMETER c opb dwidth = 32, DT = integer
## P o r t s
PORT opb be = OPB BE , DIR = IN , VEC = [ 0 : ( ( c o p b d w i d t h / 8 ) − 1 ) ] , BUS = SOPB
PORT a u s d b u s = Sl DBus , DIR = OUT, VEC = [ 0 : ( c o p b d w i d t h − 1 ) ] , BUS = SOPB
PORT a u s e r r a c k = Sl errAck , DIR = OUT, BUS = SOPB
PORT a u s r e t r y = Sl retry , DIR = OUT, BUS = SOPB
PORT a u s t o u t s u p = Sl toutSup , DIR = OUT, BUS = SOPB
PORT a u s x f e r a c k = Sl xferAck , DIR = OUT, BUS = SOPB
PORT I n t e r r u p t = ”” , DIR = OUT, SENSITIVITY = LEVEL HIGH , SIGIS = INTERRUPT , INTERRUPT PRIO
#PORT AU CLK = ”” , DIR=IN , SIGIS=CLK
PORT AU MCLK = ”” , DIR=OUT, IOB STATE=BUF

PORT AU LRCK = ”” , DIR=OUT, IOB STATE=BUF
PORT AU BCLK = ”” , DIR=OUT, IOB STATE=BUF
PORT AU SDTI = ”” , DIR=OUT, IOB STATE=BUF
PORT AU SDTO0 = ”” , DIR=IN , IOB STATE=BUF
END
A.4.3 hdl/vhdl/opb audio sampler v2 1 0.vhd
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
−− CSEE 4 8 4 0 Embedded System Design − Audio Sampling OPB P e r i p h e r a l
−−
−− SOBA S e r v e r
−−
−− Team W a r r i o r s : Avraham Sh i n n a r as1619@columbia . edu
−− Benjamin Dweck bjd2102@columbia . edu
−− Oliver Irwin omi3@columbia . edu
−− Sean White sw2061@columbia . edu
−−
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
−−
−− 32− b i t P o s i t i v e Edge T r i g g e r e d L e f t S h i f t R e g i s t e r
37
−− with S e r i a l In and P a r a l l e l Out

−−
−− Used t o r e c e i v e samples s e r i a l l y from t h e a u d i o c o d e c
−−
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
library ieee ;
entity shift 32 is
port (
D : out s t d l o g i c v e c t o r ( 3 1 downto 0 )
);
end s h i f t 3 2 ;
a r c h i t e c t u r e arch of s h i f t 3 2 i s
begin
p r o c e s s (C)
begin
i f C ’ e v e n t and C= ’ 1 ’ then
tmp <= tmp ( 3 0 downto 0 ) & SI ;
end i f ;
end p r o c e s s ;
D <= tmp ;
end a r c h ;
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
−−
−− 32− b i t P o s i t i v e Edge T r i g g e r e d Latch
−− with Asynchronous Reset
−−
−− Used t o r e c e i v e s amples s e r i a l l y from t h e a u d i o c o d e c
−−
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
library ieee ;
entity latch 32 is
port (
R : in s t d logic ;
C : in s t d logic ;
D : in s t d l o g i c v e c t o r ( 3 1 downto 0 ) ;
38
Q : out s t d l o g i c v e c t o r ( 3 1 downto 0 )
);
end l a t c h 3 2 ;
a r c h i t e c t u r e arch of l a t c h 3 2 i s
begin
p r o c e s s (C , R)
begin
i f R= ’ 1 ’ then
tmp <= X”00000000” ;
e l s i f C’ e v e n t and C= ’ 1 ’ then
tmp <= D;
end i f ;
end p r o c e s s ;
Q <= tmp ;
end a r c h ;
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
−−
−− Audio Sampler P e r i p h e r a l
−−
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
library ieee ;
use i e e e . s t d l o g i c u n s i g n e d . a l l ;
entity opb audio sampler i s
generic (
C HIGHADDR : s t d l o g i c v e c t o r ( 0 to 3 1 ) := X”FFFFFFFF” ) ;
port (
−− OPB Input S i g n a l s
OPB Clk : in s t d logic ;
OPB Rst : in s t d logic ;
OPB ABus : in s t d logic v e c t o r ( 0 t o C OPB AWIDTH−1);
OPB BE : in s t d logic v e c t o r ( 0 t o C OPB DWIDTH/8−1);
OPB DBus : in s t d logic v e c t o r ( 0 t o C OPB DWIDTH−1);
OPB RNW : in s t d logic ;
OPB select : i n s t d logic ;
OPB seqAddr : i n s t d logic ; −− S e q u e n t i a l Address
39
−− OPB Output Signals

AUS DBus : out s t d logic v e c t o r ( 0 t o C OPB DWIDTH−1);
AUS errAck : out s t d logic ; −− ( unused )
AUS retry : out s t d logic ; −− ( unused )
AUS toutSup : out s t d logic ; −− Timeout s u p p r e s s
AUS xferAck : out s t d logic ; −− T r a n s f e r acknowledge
−− I n t e r r u p t
Interrupt : out s t d l o g i c ; −− I n t e r r u p t S i g n a l
−− Audio IO S i g n a l s
AU MCLK : out s t d logic ; −− Audio Chip Master Clock
AU LRCK : out s t d logic ; −− Audio L e f t / Right Channel Clock
AU BCLK : out s t d logic ; −− Audio B i t Clock
AU SDTI : out s t d logic ; −− Audio Data In (TO Codec )
AU SDTO0 : in s t d logic ); −− Audio Data Out 0 (FROM Codec )
end o p b a u d i o s a m p l e r ;
a r c h i t e c t u r e behavioral of opb audio sampler i s
−− Clock c o u n t e r used t o g e n e r a t e a u d i o t r a n s m i s s i o n c l o c k s
s i g n a l o p b c l k c o u n t : s t d l o g i c v e c t o r ( 1 0 downto 0 ) ;
−− I n t e r n a l U t i l i t y S i g n a l s
signal int selected : std logic ; −− Decoded c h i p s e l e c t s i g n a l
signal int aus dbus en : std logic ; −− Enable s output t o AUS DBus
signal int shift out : std logic v e c t o r ( 3 1 downto 0 ) ; −− Output o f s h i f t−i n r e g i s t
signal int sample : std logic v e c t o r ( 3 1 downto 0 ) ; −− Last r e c e i v e d sample
−− I n t e r n a l B u f f e r S i g n a l s
signal int interrupt : std logic ;
signal int au mclk : std logic ;
signal int au bclk : std logic ;
signal int au lrck : std logic ;
signal int au sdto0 : std logic ;
−− S t a t e c o n s t a n t s
constant Idle : s t d l o g i c : = ’ 0 ’ ;
constant Xfer : s t d l o g i c : = ’ 1 ’ ;
signal present state , next state : std logic ;
−− 32− b i t S h i f t L e f t R e g i s t e r with S e r i a l In and P a r a l l e l Out

component s h i f t 3 2 i s
port (
SI : i n s t d logic ;
C : in s t d logic ;
D : out s t d l o g i c v e c t o r ( 3 1 downto 0 ) ) ;
end component ;
−− 32− b i t Latch with Asynchronous Reset
40
component l a t c h 32 is
port (
R : in std logic ;
C : in std logic ;
D : in std logic v e c t o r ( 3 1 downto 0 ) ;
Q : out std logic v e c t o r ( 3 1 downto 0 ) ) ;
end component ;
−− Output b u f f e r for FPGA o u t p u t s t o a u d i o c o d e c

component OBUF F 8 i s
port (
O : out s t d u l o g i c ; −− Out t o Audio c o d e c
I : in s t d ul og ic ) ; −− In from Audio c o d e c
end component ;
component IBUF i s
port (
I : in s t d l o g i c ;
O : out s t d l o g i c ) ;
end component ;
begin
−− R e c e i v i n g S h i f t R e g i s t e r
shift rcv : shift 32
p o r t map ( SI => i n t a u s d t o 0 ,
C => i n t a u b c l k ,
D => i n t s h i f t o u t ) ;
−− Sample Latch
latch sample : latch 32
p o r t map (R => OPB Rst ,
C => i n t a u l r c k ,
D => i n t s h i f t o u t ,
Q => i n t s a m p l e ) ;
−− AU MCLK B u f f e r
a u m c l k b u f f : OBUF F 8
p o r t map (
O => AU MCLK,
I => i n t a u m c l k ) ;
−− AU BCLK B u f f e r
a u b c l k b u f f : OBUF F 8
p o r t map (
O => AU BCLK,
I => i n t a u b c l k ) ;
−− AU LRCK B u f f e r
a u l r c k b u f f : OBUF F 8
p o r t map (
O => AU LRCK,
I => i n t a u l r c k ) ;
41
−− AU SDTI B u f f e r
a u s d t i b u f f : OBUF F 8
p o r t map (
O => AU SDTI ,
I => i n t a u s d t o 0 ) ;
−− AU MCLK B u f f e r
a u s d t o 0 b u f f : IBUF
p o r t map (
O => i n t a u s d t o 0 ,
I => AU SDTO0 ) ;
−− Produce c h i p s e l e c t s i g n a l by d e c o d i n g OPB a d d r e s s and c h e c k i n g OPB select

i n t s e l e c t e d < = ’ 1 ’ when OPB select = ’ 1 ’ and
OPB ABus ( 0 t o C OPB AWIDTH−9) =
C BASEADDR( 0 t o C OPB AWIDTH−9)
else ’ 0 ’ ;
−− Tie unused OPB s l a v e o u t p u t s

AUS errAck < = ’ 0 ’ ;
AUS retry < = ’ 0 ’ ;
AUS toutSup < = ’ 0 ’ ;
−− Tie OPB ack t o output e n a b l e s i g n a l

AUS xferAck <= i n t a u s d b u s e n ;
−− Tie unused a u d i o output

−−AU SDTI < = ’ 0 ’ ;
−− Tie o f f−FPGA s i g n a l s t o i n t e r n a l b u f f e r s i g n a l s
INTERRUPT <= i n t i n t e r r u p t ;
−−i n t a u s d t o 0 <= AU SDTO0 ;
−− Generate Audio T r a n s m i s s i o n C l o c k s
int au mclk <= o p b c l k c o u n t ( 1 ) ;
int au bclk <= o p b c l k c o u n t ( 4 ) ;
int au lrck <= NOT o p b c l k c o u n t ( 9 ) ;
o p b c l k c o u n t p r o c : p r o c e s s ( OPB Clk , OPB Rst )

begin
o p b c l k c o u n t <= ”00000000000” ;
e l s i f OPB Clk ’ e v e n t and OPB Clk = ’ 1 ’ then
o p b c l k c o u n t <= o p b c l k c o u n t + 1 ;
end i f ;
end p r o c e s s o p b c l k c o u n t p r o c ;
−− Gate output t o AUS DBus with i n t a u s d b u s e n

g a t e a u s d b u s o u t p u t : p r o c e s s ( OPB Rst , OPB RNW, i n t a u s d b u s e n )
begin
42

AUS DBus ( 0 t o C OPB DWIDTH−1) <= ( o t h e r s = > ’ 0 ’ ) ;
else
i f i n t a u s d b u s e n = ’ 1 ’ then
AUS DBus ( 0 t o C OPB DWIDTH−1) <= i n t s a m p l e (C OPB DWIDTH−1 downto 0 ) ;
else
AUS DBus ( 0 t o C OPB DWIDTH−1) <= ( o t h e r s = > ’ 0 ’ ) ;
end i f ;
end i f ;
end p r o c e s s g a t e a u s d b u s o u t p u t ;
−− Send i n t e r r u p t p u l s e upon r e c e i v i n g sample

−− SMALL HACK: Using i n t a u m c l k t o r e s e t t h e i n t e r r u p t
send interrupt : process ( int au mclk , int au lrc k , int interrupt )
begin
i f i n t a u m c l k = ’ 1 ’ then
int interrupt <= ’0’;
e l s i f i n t a u l r c k ’ e v e n t and i n t a u l r c k = ’ 1 ’ then
int interrupt <= ’1’;
end i f ;
end p r o c e s s s e n d i n t e r r u p t ;
begin
i f OPB Rst = ’ 1 ’ then −− Asynchronous r e s e t t o I d l e s t a t e
e l s i f OPB Clk ’ e v e n t and OPB Clk = ’ 1 ’ then −− P o s i t i v e edge OPB Clk
p r e s e n t s t a t e <= n e x t s t a t e ; −− advance t o next s t a t e
end i f ;
fsm comb : p r o c e s s ( p r e s e n t s t a t e , i n t s e l e c t e d )
begin
int aus dbus en <= ’0’;
when I d l e =>
n e x t s t a t e <= X f e r ;
else
end i f ;
when X f e r =>
when o t h e r s =>
43
A.5 opb ethernet A CODE LISTING
end case ;
end b e h a v i o r a l ;
A.5 opb ethernet
A.5.1 data/opb ethernet v2 1 0.pao
#−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
#
# SOBA S e r v e r
#
# Team W a r r i o r s : Avraham S h i nn a r as1619@columbia . edu
#
#
# o p b e t h e r n e t pao f i l e
#
#−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
lib opb ethernet v1 00 a memoryctrl

lib opb ethernet v1 00 a pad io
lib opb ethernet v1 00 a opb ethernet
A.5.2 data/opb ethernet v2 1 0.mpd
#−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
#
# SOBA S e r v e r
#
# Team W a r r i o r s : Avraham S h i nn a r as1619@columbia . edu
#
#−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
BEGIN o p b e t h e r n e t , IPTYPE = PERIPHERAL , EDIF=TRUE

OPTION HDL = VHDL
PARAMETER c b a s e a d d r = 0xFFFFFFFF ,DT = s t d l o g i c v e c t o r , MIN SIZE=0x100 , BUS=SOPB
PARAMETER c h i g h a d d r = 0 x00000000 , DT = s t d l o g i c v e c t o r , BUS=SOPB
44
A CODE LISTING A.5 opb ethernet
PARAMETER c opb awidth = 32, DT = i n t e g e r

PARAMETER c opb dwidth = 32, DT = i n t e g e r
PARAMETER c ethernet dwidth = 16, DT = i n t e g e r
PARAMETER c ethernet awidth = 10, DT = i n t e g e r
## P o r t s
PORT opb be = OPB BE , DIR = IN , VEC = [ 0 : ( ( c o p b d w i d t h / 8 ) − 1 ) ] , BUS = SOPB
PORT s l n d b u s = Sl DBus , DIR = OUT, VEC = [ 0 : ( c o p b d w i d t h − 1 ) ] , BUS = SOPB
PORT s l n e r r a c k = Sl errAck , DIR = OUT, BUS = SOPB
PORT s l n r e t r y = Sl retry , DIR = OUT, BUS = SOPB
PORT s l n t o u t s u p = Sl toutSup , DIR = OUT, BUS = SOPB
PORT s l n x f e r a c k = Sl xferAck , DIR = OUT, BUS = SOPB
PORT ETHERNET CS N = ”” , DIR = OUT, IOB STATE=BUF

PORT ETHERNET RDY = ”” , DIR = IN
PORT ETHERNET IREQ = ”” , DIR = IN
PORT ETHERNET IOCS16 N = ”” , DIR = IN
PORT PB D = ”” , DIR = INOUT , VEC = [ c e t h e r n e t d w i d t h − 1 : 0 ] , 3STATE=FALSE

PORT PB A = ”” , DIR = OUT, VEC = [ 1 9 : 0 ] , 3 STATE=FALSE , IOB STATE=BUF
PORT PB OE N = ”” , DIR = OUT, IOB STATE=BUF
PORT PB WE N = ”” , DIR = OUT, IOB STATE=BUF
PORT PB UB N = ”” , DIR = OUT, IOB STATE=BUF
PORT PB LB N = ”” , DIR = OUT, IOB STATE=BUF
PORT RAM CE N = ”” , RAM CE N , DIR = OUT, IOB STATE=BUF
PORT i o c l o c k = ”” , DIR=IN
END
A.5.3 hdl/vhdl/memoryctrl.vhd
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
−− CSEE 4 8 4 0 Embedded System Design
−−
−−
−− Team W a r r i o r s : Avraham Sh i nn a r as1619@columbia . edu
−−
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
−− Based on Jaycam e t h e r n e t vhdl
l i b r a r y IEEE ;
45
u s e IEEE . STD LOGIC 1164 . ALL ;

u s e IEEE . STD LOGIC ARITH . ALL ;
u s e IEEE . STD LOGIC UNSIGNED . ALL ;
−− Uncomment t h e f o l l o w i n g l i n e s t o u s e t h e d e c l a r a t i o n s t h a t a r e
−− p r o v i d e d f or i n s t a n t i a t i n g X i l i n x p r i m i t i v e components .
−−l i b r a r y UNISIM ;
−−u s e UNISIM . VComponents . a l l ;
e n t i t y memoryctrl i s
Port ( r s t : i n s t d l o g i c ;
c s : i n s t d l o g i c ; −− any o f my d e v i c e s s e l e c t e d
o p b s e l e c t : i n s t d l o g i c ; −− o r i g i n a l s e l e c t
rnw : i n s t d l o g i c ;
eth io : in s t d l o g i c ;
fullword : in s t d l o g i c ;
r e a d e a r l y : out s t d l o g i c ;
w r i t e e a r l y : out s t d l o g i c ;
b u s r e q : out s t d l o g i c ;
v i d e o c y c l e : out s t d l o g i c ;
h i h a l f : out s t d l o g i c ;
w r r e q : out s t d l o g i c ;
r d r e q : out s t d l o g i c ;
x f e r : out s t d l o g i c ;
c e 0 : out s t d l o g i c ;
r r e s : out s t d l o g i c ;
vreq : in s t d l o g i c ;
v i d e o c e : out s t d l o g i c
);
end memoryctrl ;
a r c h i t e c t u r e B e h a v i o r a l o f memoryctrl i s
signal r i d l e , r common , r w32 , r r a , r r b , r r c , r x f e r : s t d l o g i c ;

signal r weth1 , r weth2 , r weth3 : s t d l o g i c ;
signal r v1 , r v0 , r v2 : s t d l o g i c ;
signal wr req i , rd req i , videocycle i : std logic ;
begin
process ( rst , clk )

begin
i f r s t = ’ 1 ’ then
r i d l e <= ’1’;
r common < = ’ 0 ’ ;
r w32 < = ’ 0 ’ ;
r r a < = ’ 0 ’ ; r r b < = ’ 0 ’ ; r r c < = ’ 0 ’ ; r x f e r < = ’ 0 ’ ; r weth1 < = ’ 0 ’ ;
46
r weth2 < = ’ 0 ’ ; r weth3 < = ’ 0 ’ ;
e l s i f c l k ’ e v e n t and c l k = ’ 1 ’ then
r i d l e <= ( r i d l e and not c s ) o r ( r x f e r ) o r ( not o p b s e l e c t ) ;

r common <= o p b s e l e c t and ( r i d l e and c s ) ;
r w e t h 1 <= o p b s e l e c t and ( r common and not rnw and e t h i o ) ;

r w e t h 2 <= o p b s e l e c t and ( r w e t h 1 ) ;
r w e t h 3 <= o p b s e l e c t and ( r w e t h 2 ) ;
r w32 <= o p b s e l e c t and ( r common and not rnw and f u l l w o r d ) ;
r r a <= o p b s e l e c t and ( r common and rnw ) ;

r r b <= o p b s e l e c t and ( r r a ) ;
r r c <= o p b s e l e c t and ( r r b and ( f u l l w o r d o r e t h i o ) ) ;
r x f e r <= o p b s e l e c t and ( ( r common and not rnw and not f u l l w o r d and not e t h i o )
o r ( r w32 ) o r ( r r b and not f u l l w o r d and not e t h i o )

or ( r r c )
or ( r weth2 ) ) ;
end i f ;
end p r o c e s s ;
r e a d e a r l y <= r r a and e t h i o ;
w r i t e e a r l y <= not ( ( r common and not rnw and e t h i o ) o r ( r w e t h 1 ) o r r w e t h 2 ) ;
h i h a l f <= r w32 o r ( r r a and f u l l w o r d ) ;
w r r e q i <= ( r common and not rnw and not e t h i o ) o r ( r w32 ) o r ( r w e t h 1 ) o r ( r w e t h 2 ) o r (

r d r e q i <= ( r common and rnw ) o r ( r r a and ( f u l l w o r d o r e t h i o ) ) ;
w r r e q <= w r r e q i ;
r d r e q <= r d r e q i ;
b u s r e q <= r d r e q i o r w r r e q i o r r common ;
x f e r <= r x f e r ;
r r e s <= r x f e r ;
c e 0 <= r r b o r ( r r c and e t h i o ) ;
c e 1 <= r r b o r r r c ;
−− t h e v i d e o s t a t e machine
−− smw : k i l l e d t h e v i d e o s t a t e machine and s e t e v e r y t h i n g t o 0
v i d e o c y c l e i <= ( r v 1 o r r v 0 ) and not ( r d r e q i o r w r r e q i ) ;

−−v i d e o c y c l e <= v i d e o c y c l e i ;
videocycle <= ’0’;
video ce <= ’0’;
47
r v0 <=’0’;
r v1 <=’0’;
r v2 <=’0’;
end B e h a v i o r a l ;
A.5.4 hdl/vhdl/opb ethernet.vhd
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
−−
−−
−−
−− based on Jaycam e t h e r n e t vhdl
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
−− Uncomment t h e f o l l o w i n g l i n e s t o u s e t h e d e c l a r a t i o n s t h a t a r e
−− p r o v i d e d f or i n s t a n t i a t i n g X i l i n x p r i m i t i v e components .
l i b r a r y UNISIM ;
u s e UNISIM . VComponents . a l l ;
entity opb ethernet i s

generic (
C BASEADDR : s t d l o g i c v e c t o r : = X”2000 0 0 0 0 ” ;
C HIGHADDR : s t d l o g i c v e c t o r : = X”2000 00FF ” ;
C ETHERNET DWIDTH : integer := 16;
C ETHERNET AWIDTH : integer := 10
);
Port ( OPB Clk : i n s t d l o g i c ;

OPB Rst : i n s t d l o g i c ;
OPB ABus : i n s t d l o g i c v e c t o r ( 3 1 downto 0 ) ;
OPB BE : i n s t d l o g i c v e c t o r ( 3 downto 0 ) ;
OPB DBus : i n s t d l o g i c v e c t o r ( 3 1 downto 0 ) ;
OPB RNW : i n s t d l o g i c ;
OPB select : i n s t d l o g i c ;
OPB seqAddr : i n s t d l o g i c ;
i o c l o c k : in s t d l o g i c ;
Sln DBus : out s t d l o g i c v e c t o r ( 3 1 downto 0 ) ;
S l n e r r A c k : out s t d l o g i c ;
S l n r e t r y : out s t d l o g i c ;
S l n t o u t S u p : out s t d l o g i c ;
48
S l n x f e r A c k : out s t d l o g i c ;
PB A : out s t d l o g i c v e c t o r ( 1 9 downto 0 ) ;
PB UB N : out s t d l o g i c ;
PB LB N : out s t d l o g i c ;
PB WE N : out s t d l o g i c ;
PB OE N : out s t d l o g i c ;
RAM CE N : out s t d l o g i c ;
ETHERNET CS N : out s t d l o g i c ;
ETHERNET RDY : i n s t d l o g i c ;
ETHERNET IREQ : i n s t d l o g i c ;
ETHERNET IOCS16 N : i n s t d l o g i c ;
PB D : i n o u t s t d l o g i c v e c t o r ( 1 5 downto 0 )
);
end o p b e t h e r n e t ;
architecture Behavioral of opb ethernet i s
signal addr mux : s t d l o g i c v e c t o r ( 1 9 downto 0 ) ;

signal v i d e o a d d r : s t d l o g i c v e c t o r ( 1 9 downto 0 ) ;
signal v i d e o d a t a : s t d l o g i c v e c t o r ( 1 5 downto 0 ) ;
signal video req : std logic ;
signal video ce : std logic ;
signal i : integer ;
signal cs : s t d l o g i c ;
signal fullword , eth io , read early , write early : std logic ;

signal v i d e o c y c l e , amuxsel , h i h a l f : std logic ;
signal rce0 , rce1 , r r e s e t : s t d l o g i c ;
signal xfer : std logic ;
signal wr req , rd req , bus req : s t d logic ;
signal pb rd , pb wr : s t d l o g i c ;
s i g n a l sram ce : s t d l o g i c ;
signal ethernet ce : std logic ;
s i g n a l rnw : s t d l o g i c ;
s i g n a l addr : s t d l o g i c v e c t o r ( 2 3 downto 0 ) ;
s i g n a l be : s t d l o g i c v e c t o r ( 3 downto 0 ) ;
s i g n a l p b b y t e s e l : s t d l o g i c v e c t o r ( 1 downto 0 ) ;
s i g n a l wdata : s t d l o g i c v e c t o r ( 3 1 downto 0 ) ;
s i g n a l wdata mux : s t d l o g i c v e c t o r ( 1 5 downto 0 ) ;
s i g n a l r d a t a : s t d l o g i c v e c t o r ( 1 5 downto 0 ) ; −− r e g i s t e r data r e a d − FDRE
component memoryctrl
Port ( rst : in s t d l o g i c ;
49
c s : i n s t d l o g i c ; −− any o f my d e v i c e s s e l e c t e d
o p b s e l e c t : i n s t d l o g i c ; −− o r i g i n a l s e l e c t
rnw : i n s t d l o g i c ;
eth io : in s t d l o g i c ;
fullword : in s t d l o g i c ;
r e a d e a r l y : out s t d l o g i c ;
w r i t e e a r l y : out s t d l o g i c ;
v i d e o c y c l e : out s t d l o g i c ;
h i h a l f : out s t d l o g i c ;
w r r e q : out s t d l o g i c ;
r d r e q : out s t d l o g i c ;
b u s r e q : out s t d l o g i c ;
x f e r : out s t d l o g i c ;
r r e s : out s t d l o g i c ;
vreq : in s t d l o g i c ;
v i d e o c e : out s t d l o g i c ) ;
end component ;
component p a d i o
Port ( s y s c l k : i n s t d l o g i c ;
read early : in s t d l o g i c ;
write early : in s t d l o g i c ;
PB D : i n o u t s t d l o g i c v e c t o r ( 1 5 downto 0 ) ;
pb addr : i n s t d l o g i c v e c t o r ( 1 9 downto 0 ) ;
pb ub : i n s t d l o g i c ;
pb lb : in s t d l o g i c ;
pb wr : i n s t d l o g i c ;
pb rd : i n s t d l o g i c ;
ram ce : i n s t d l o g i c ;
ethernet ce : in s t d l o g i c ;
pb dread : out s t d l o g i c v e c t o r ( 1 5 downto 0 ) ;
p b d w r i t e : i n s t d l o g i c v e c t o r ( 1 5 downto 0 ) ) ;
end component ;
begin
50
−− t h e c o n t r o l l e r s t a t e machine
memoryctrl1 : memoryctrl
p o r t map ( r s t => OPB Rst ,
c l k => OPB Clk ,
c s => c s ,
o p b s e l e c t => OPB select ,
rnw => rnw ,
f u l l w o r d => f u l l w o r d ,
e t h i o => e t h i o ,
r e a d e a r l y => r e a d e a r l y ,
w r i t e e a r l y => w r i t e e a r l y ,
v i d e o c y c l e => v i d e o c y c l e ,
h i h a l f => h i h a l f ,
w r r e q => w r r e q ,
r d r e q => r d r e q ,
b u s r e q => b u s r e q ,
x f e r => x f e r ,
c e 0 => r c e 0 ,
c e 1 => r c e 1 ,
r r e s => r r e s e t ,
v r e q => v i d e o r e q ,
v i d e o c e => v i d e o c e ) ;
−− PADS
pad io1 : pad io

p o r t map ( s y s c l k => OPB Clk ,
i o c l o c k => i o c l o c k ,
r e a d e a r l y => r e a d e a r l y ,
w r i t e e a r l y => w r i t e e a r l y ,
r s t => OPB Rst ,
PB A => PB A ,
PB UB N => PB UB N ,
PB LB N => PB LB N ,
PB WE N => PB WE N ,
PB OE N => PB OE N ,
RAM CE N => RAM CE N ,
ETHERNET CS N => ETHERNET CS N ,
ETHERNET RDY => ETHERNET RDY,
ETHERNET IREQ => ETHERNET IREQ ,
ETHERNET IOCS16 N => ETHERNET IOCS16 N ,
PB D => PB D ,
pb addr => addr mux ,

pb wr => pb wr ,
pb rd => pb rd ,
pb ub => p b b y t e s e l ( 1 ) ,
p b l b => p b b y t e s e l ( 0 ) ,
ram ce => s r a m c e ,
51
e t h e r n e t c e => e t h e r n e t c e ,
pb dread => r d a t a ,
p b d w r i t e => wdata mux ) ;
amuxsel <= v i d e o c y c l e ;
addr mux <= v i d e o a d d r when ( amuxsel = ’ 1 ’ ) e l s e ( addr ( 2 0 downto 2 ) & ( addr ( 1 ) o r h
f u l l w o r d <= be ( 2 ) and be ( 0 ) ;
wdata mux <= wdata ( 1 5 downto 0 ) when ( ( addr ( 1 ) o r h i h a l f ) = ’ 1 ’ ) e l s e wdata ( 3 1 down
−− p r e p a r e c o n t r o l s i g n a l s
p r o c e s s ( v i d e o c y c l e , be , addr ( 1 ) , h i h a l f , r d r e q , w r r e q )
begin
i f v i d e o c y c l e = ’ 1 ’ then p b b y t e s e l <= ”11” ;

e l s i f b u s r e q = ’ 1 ’ then
i f addr ( 1 ) = ’ 1 ’ o r h i h a l f = ’ 1 ’ then
p b b y t e s e l <= be ( 1 downto 0 ) ;
else
p b b y t e s e l <= be ( 3 downto 2 ) ;
end i f ;
else
p b b y t e s e l <= ”00” ;
end i f ;
end p r o c e s s ;
pb rd <= r d r e q o r v i d e o c y c l e ;
pb wr <= w r r e q ;
−−pb wr <= OPB Clk ;
c s <= OPB select when OPB ABus ( 3 1 downto 2 3 ) = ”000000001” e l s e ’ 0 ’ ;

s r a m c e < = ’ 1 ’ when addr ( 2 2 downto 21)= ”00” and ( b u s r e q = ’ 1 ’ ) e l s e ’ 0 ’ ;
e t h e r n e t c e < = ’ 1 ’ when addr ( 2 2 downto 2 1 ) = ”01” and ( b u s r e q = ’ 1 ’ ) e l s e ’ 0 ’ ;
e t h i o < = ’ 1 ’ when addr ( 2 2 downto 2 1 ) / = ”00” e l s e ’ 0 ’ ;
p r o c e s s ( OPB Clk , OPB Rst )

begin
−− r e g i s t e r rw
i f OPB Clk ’ e v e n t and OPB Clk = ’ 1 ’ then

rnw < = ’ 0 ’ ;
else
52
rnw <= OPB RNW;

end i f ;
end i f ;
−− r e g i s t e r a d r e s s e s A23 . . A0
for i i n 0 t o 2 3 l o o p
addr ( i ) < = ’ 0 ’ ;
else
addr ( i ) <= OPB ABus( i ) ;
end i f ;
end l o o p ;
end i f ;
−− r e g i s t e r BE
be <= ”0000” ;
else
be <= OPB BE ;
end i f ;
end i f ;
−− r e g i s t e r data w r i t e
wdata ( i ) < = ’ 0 ’ ;
else
wdata ( i ) <= OPB DBus( i ) ;
end i f ;
end l o o p ;
end i f ;
−− t h e fun b e g i n s
−− c e 0 / c e 1 e n a b l e s w r i t i n g MSB ( low ) / LSB ( h i g h ) h a l v e s
−−always @( po s e dg e OPB Rst o r p o s e d g e OPB Clk ) b e g i n ( synchrounous o r a s y n c h r o n o u s r e s e t ? ? )
Sln DBus ( i ) < = ’ 0 ’ ;

i f r r e s e t = ’ 1 ’ then
Sln DBus ( i ) < = ’ 0 ’ ;
e l s i f ( r c e 1 o r r c e 0 ) = ’ 1 ’ then
Sln DBus ( i ) <= r d a t a ( i ) ;
end i f ;
end i f ;
end l o o p ;
53
for i i n 1 6 t o 3 1 l o o p
Sln DBus ( i ) < = ’ 0 ’ ;
i f r r e s e t = ’ 1 ’ then
Sln DBus ( i ) < = ’ 0 ’ ;
e l s i f r c e 0 = ’ 1 ’ then
Sln DBus ( i ) <= r d a t a ( i −16);
end i f ;
end i f ;
end l o o p ;

if v i d e o c e = ’ 1 ’ then
v i d e o d a t a <= r d a t a ;
end i f ;
end i f ;
end p r o c e s s ;
−− t i e unused t o ground
S l n x f e r A c k <= x f e r ;
A.5.5 hdl/vhdl/pad io.vhd
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
−−
−−
−−
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
−− Based on Jaycam e t h e r n e t vhdl
l i b r a r y UNISIM ;
u s e UNISIM .VCOMPONENTS. ALL ;
54
entity pad io i s
Port ( s y s c l k : i n s t d l o g i c ;
read early : in s t d l o g i c ;
write early : in s t d l o g i c ;
PB D : i n o u t s t d l o g i c v e c t o r ( 1 5 downto 0 ) ;
pb addr : i n s t d l o g i c v e c t o r ( 1 9 downto 0 ) ;
pb ub : i n s t d l o g i c ;
pb lb : in s t d l o g i c ;
pb wr : i n s t d l o g i c ;
pb rd : i n s t d l o g i c ;
ram ce : i n s t d l o g i c ;
ethernet ce : in s t d l o g i c ;
pb dread : out s t d l o g i c v e c t o r ( 1 5 downto 0 ) ;
p b d w r i t e : i n s t d l o g i c v e c t o r ( 1 5 downto 0 ) ) ;
end p a d i o ;
architecture Behavioral of pad io i s
component FDCE
p o r t (C : i n s t d l o g i c ;
CLR : i n s t d l o g i c ;
CE : i n s t d l o g i c ;
D : in s t d l o g i c ;
Q : out s t d l o g i c ) ;
end component ;
component FDPE
p o r t (C : i n s t d l o g i c ;
PRE : i n s t d l o g i c ;
CE : i n s t d l o g i c ;
D : in s t d l o g i c ;
Q : out s t d l o g i c ) ;
end component ;
a t tr ib ut e iob : s t r i n g ;
a t t r i b u t e i o b o f FDCE : component i s ” t r u e ” ;
a t t r i b u t e i o b o f FDPE : component i s ” t r u e ” ;
55
component OBUF F 24
p o r t (O : out STD ULOGIC ;
I : i n STD ULOGIC ) ;
end component ;
component IOBUF F 24
p o r t (O : out STD ULOGIC ;
IO : i n o u t STD ULOGIC ;
I : i n STD ULOGIC ;
T : i n STD ULOGIC ) ;
end component ;
signal io half : std logic ;

signal p b a d d r 1 : s t d l o g i c v e c t o r ( 1 9 downto 0 ) ;
signal p b d w r i t e 1 : s t d l o g i c v e c t o r ( 1 5 downto 0 ) ;
signal p b t r i s t a t e : s t d l o g i c v e c t o r ( 1 5 downto 0 ) ;
signal p b t r i s t a t e 1 : s t d l o g i c v e c t o r ( 1 5 downto 0 ) ;
signal p b d r e a d a : s t d l o g i c v e c t o r ( 1 5 downto 0 ) ;
signal we n , pb we n1 : s t d l o g i c ;
signal oe n , pb oe n1 : s t d l o g i c ;
signal lb n , pb lb n1 : s t d l o g i c ;
signal ub n , pb ub n1 : s t d l o g i c ;
signal ethce n , eth ce n1 : s t d l o g i c ;
signal ramce n , r a m c e n 1 : s t d l o g i c ;
signal dataz : s t d l o g i c ;
s i g n a l rd ce , wr ce , din c e , r d e a r l y , wr early : s t d l o g i c ;
−−a t t r i b u t e e q u i v a l e n t r e g i s t e r r e m o v a l : s t r i n g ;
−−a t t r i b u t e e q u i v a l e n t r e g i s t e r r e m o v a l o f p b t r i s t a t e 1 : s i g n a l i s ”no” ;
−−a t t r i b u t e e q u i v a l e n t r e g i s t e r r e m o v a l o f p b d w r i t e 1 : s i g n a l i s ”no” ;
begin
−−−−−−−−−−−−−−−−−−−−−−−− !!!!!!!!!!!!!!!!!!!!!!! −−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

−−p r o c e s s ( i o c l o c k )
−−b e g i n
−− i f i o c l o c k ’ e v e n t and i o c l o c k = ’ 1 ’ then
−− i o h a l f <= s y s c l k ;
−− end i f ;
−−end p r o c e s s ;
i o h a l f <= not s y s c l k ;
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
process ( rst , sys clk )

begin
i f r s t = ’ 1 ’ then
rd early <= ’0’;
wr early <= ’0’;
e l s i f s y s c l k ’ e v e n t and s y s c l k = ’ 1 ’ then
r d e a r l y <= r e a d e a r l y ;
w r e a r l y <= w r i t e e a r l y ;
56
end i f ;
end p r o c e s s ;
d a t a z <= ( not pb wr ) o r pb rd ;
p b t r i s t a t e <= ”1111111111111111” when d a t a z = ’ 1 ’ e l s e ”0000000000000000” ;
−− a d d r e s s
a f f : for i in 0 to 1 9 generate
a f f : FDCE p o r t map (
C => i o c l o c k , CLR => r s t ,
CE => i o h a l f ,
D => pb addr ( i ) ,
Q => p b a d d r 1 ( i ) ) ;
−− data
d i n c e <= i o h a l f xor r d e a r l y ;
d f f : for i in 0 to 1 5 generate
d r f f : FDPE p o r t map (
C => i o c l o c k , PRE => r s t ,
CE => d i n c e ,
D => p b d r e a d a ( i ) ,
Q => pb dread ( i ) ) ;
d w f f : FDPE p o r t map (
CE => i o h a l f ,
D => p b d w r i t e ( i ) ,
Q => p b d w r i t e 1 ( i ) ) ;
d t f f : FDPE p o r t map (
CE => i o h a l f ,
D => p b t r i s t a t e ( i ) ,
Q => p b t r i s t a t e 1 ( i ) ) ;
−− c o n t r o l
we n <= not pb wr o r ( not i o h a l f and w r e a r l y ) ;
w r c e <= i o h a l f o r w r e a r l y ;
w e f f : FDPE p o r t map (
CE => w r c e ,
D => we n ,
Q => pb we n1 ) ;
o e n <= not pb rd o r ( not i o h a l f and r d e a r l y ) ;

r d c e <= i o h a l f o r r d e a r l y ;
o e f f : FDPE p o r t map (
57
CE => r d c e ,
D => o e n ,
Q => p b o e n 1 ) ;
l b n <= not p b l b ;
l b f f : FDPE p o r t map (
CE => i o h a l f ,
D => l b n ,
Q => p b l b n 1 ) ;
ub n <= not pb ub ;
u b f f : FDPE p o r t map (
CE => i o h a l f ,
D => ub n ,
Q => pb ub n1 ) ;
ramce n <= not ram ce ;

r a m c e f f : FDPE p o r t map (
C => i o c l o c k ,
PRE => r s t ,
CE => i o h a l f ,
D => ramce n ,
Q => r a m c e n 1 ) ;
e t h c e n <= not e t h e r n e t c e ;
e t h c e f f : FDPE p o r t map (
C => i o c l o c k ,
PRE => r s t ,
CE => i o h a l f ,
D => e t h c e n ,
Q => e t h c e n 1 ) ;
−− I /O BUFFERS
webuf : OBUF F 24
p o r t map (O => PB WE N ,
I => pb we n1 ) ;
o e b u f : OBUF F 24
p o r t map (O => PB OE N ,
I => p b o e n 1 ) ;
ramcebuf : OBUF F 24
p o r t map (O => RAM CE N ,
I => r a m c e n 1 ) ;
e t h c e b u f : OBUF F 24
p o r t map (O => ETHERNET CS N ,
I => e t h c e n 1 ) ;
58
−− ETHERNET RDY : i n s t d l o g i c ;
−− ETHERNET IREQ : i n s t d l o g i c ;
−− ETHERNET IOCS16 N : i n s t d l o g i c ;
ubbuf : OBUF F 24
p o r t map (O => PB UB N ,
I => pb ub n1 ) ;
l b b u f : OBUF F 24
p o r t map (O => PB LB N ,
I => p b l b n 1 ) ;
abuf : f or i i n 0 t o 1 9 g e n e r a t e
abuf : OBUF F 24 p o r t map (
O => PB A( i ) ,
I => p b a d d r 1 ( i ) ) ;
dbuf : f o r i i n 0 t o 1 5 g e n e r a t e
dbuf : IOBUF F 24 p o r t map (
O => p b d r e a d a ( i ) ,
IO => PB D( i ) ,
I => p b d w r i t e 1 ( i ) ,
T => p b t r i s t a t e 1 ( i ) ) ;
A.5.6 hdl/vhdl/opb ethernet.vhd.old
Note that this file represents our original attempt to get ethernet working without using JAYcam’s code.
We did not get it working, but felt that it might be useful to future groups (we did get parts of it functioning
correctly). This code is not, however actually used in our project.
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
−−
−−
−−
−− our o r i g i n a l attempt g e t t i n g e t h e r n e t working . not used .
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
library ieee ;
entity opb ethernet i s
59
generic (
C OPB AWIDTH : i n t e g e r := 32;
C OPB DWIDTH : i n t e g e r := 32;
C HIGHADDR : s t d l o g i c v e c t o r ( 0 to 3 1 ) := X”FFFFFFFF” ;
C ETHERNET DWIDTH : i n t e g e r : = 1 6 ; −− Number o f a d d r e s s l i n e s on t h e
C ETHERNET AWIDTH : i n t e g e r : = 1 0 ) ; − − Number o f data l i n e s on t h e RAM
port (
OPB Clk : in std logic ;
OPB Rst : in std logic ;
OPB ABus : in std logic v e c t o r ( 0 t o C OPB AWIDTH−1);
OPB BE : in std logic v e c t o r ( 0 t o C OPB DWIDTH/8−1);
OPB DBus : in std logic v e c t o r ( 0 t o C OPB DWIDTH−1);
OPB RNW : in std logic ;
OPB select : in std logic ;
OPB seqAddr : in std logic ; −− S e q u e n t i a l Address
Sln DBus : out std logic v e c t o r ( 0 t o C OPB DWIDTH−1);
Sln errAck : out std logic ; −− ( unused )
Sln retry : out std logic ; −− ( unused )
Sln toutSup : out std logic ; −− Timeout s u p p r e s s
Sln xferAck : out std logic ; −− T r a n s f e r acknowledge
PB D : i n o u t s t d l o g i c v e c t o r (C ETHERNET DWIDTH−1 downto 0 ) ;

PB A : out s t d l o g i c v e c t o r (C ETHERNET AWIDTH−1 downto 0 ) ;
PB OE : out s t d l o g i c ; −− a c t i v e low , IOR
PB WE : out s t d l o g i c ; −− a c t i v e low , IOW
PB UB : out s t d l o g i c ; −− a c t i v e low , BHE N
PB LB : out s t d l o g i c ; −− a c t i v e low , AE N
ETHERNET CS N : out s t d l o g i c ; −− c h i p s e l e c t ( a c t i v e )
ETHERNET RDY : i n s t d l o g i c ; −− i n s e r t w a i t s t a t e d u r i n g RW when low
ETHERNET IREQ : i n s t d l o g i c ; −− i n t e r r u p t r e q u e s t output
ETHERNET IOCS16 N : i n s t d l o g i c ; −− i n d i c a t e s 1 6 b i t a d d r e s s when low
ether clk : in s t d l o g i c ) ;
end o p b e t h e r n e t ;
architecture Behavioral of opb ethernet i s
component OBUF F 24
port (
O : out s t d l o g i c ; −− t h e p i n
I : in s t d l o g i c ) ; −− s i g n a l t o p i n
end component ;
component IOBUF F 24
port (
O : out s t d l o g i c ; −− s i g n a l from p i n
I : in s t d l o g i c ; −− s i g n a l t o p i n
IO : i n o u t s t d l o g i c ; −− t h e p i n
T : in s t d l o g i c ) ; −− 1 = d r i v e IO with O
end component ;
s i g n a l a b u f i n p u t : s t d l o g i c v e c t o r ( 0 t o C ETHERNET AWIDTH−1);
60
s i g n a l d b u f o u t p u t , d b u f i n p u t : s t d l o g i c v e c t o r ( 0 t o C ETHERNET DWIDTH−1);
signal tristate control : std logic ;
s i g n a l RNW : s t d l o g i c ;
signal chip select : std logic ;
signal output enable : s t d l o g i c ;
type s t a t e s i s ( I d l e , S e l e c t e d , Read0 , Read1 , Read2 , Read3 , Write1 , Write2 , Write3 , T r a n

signal present state , next state : states ;
signal ETHERNET CS N i : s t d l o g i c ;
signal PB OE i : s t d l o g i c ;
signal PB WE i : s t d l o g i c ;
signal ae n i : std logic ;
signal bhe n i : std logic ;
signal be : s t d l o g i c v e c t o r ( 0 t o C OPB DWIDTH/8−1);
signal fullword : std logic ;
signal s t a t e v a l u e : s t d l o g i c v e c t o r ( 0 to 7 ) ;
s i g n a l pb read : s t d l o g i c ;
signal pb write : s t d l o g i c ;
begin
ADDRPADGEN: fo r i i n 0 t o C ETHERNET AWIDTH−2 g e n e r a t e

addrpad : OBUF F 24 p o r t map (
O => PB A(C ETHERNET AWIDTH−1−i ) ,
I => a b u f i n p u t ( i ) ) ;
addr0pad : OBUF F 24 p o r t map (

O => PB A ( 0 ) ,
I => ’0’ );
DATAPADGEN: f or i i n 0 t o C ETHERNET DWIDTH−1 g e n e r a t e

datapad : IOBUF F 24 p o r t map (
O => d b u f o u t p u t ( i ) ,
IO => PB D(C ETHERNET DWIDTH−1−i ) ,
I => d b u f i n p u t ( i ) ,
T => t r i s t a t e c o n t r o l ) ;
−− datapad9 : IOBUF F 24 p o r t map (

−− O => d b u f o u t p u t ( 1 5 ) ,
−− IO => PB D ( 0 ) ,
−− I => ’1’,
−− T => ’0’);
e t h e r n e t c s n p a d : OBUF F 24 p o r t map (
O => ETHERNET CS N ,
I => ETHERNET CS N i ) ;
61
p b o e p a d : OBUF F 24 p o r t map (
O => PB OE ,
I => PB OE i ) ;
pb we pad : OBUF F 24 p o r t map (

O => PB WE,
I => PB WE i ) ;
pb ub pad : OBUF F 24 p o r t map ( −− BHE N

O => PB UB ,
I => b h e n i ) ;
p b l b p a d : OBUF F 24 p o r t map ( −− AE N
O => PB LB ,
I => a e n i ) ;
f u l l w o r d <= be ( 2 ) and be ( 0 ) ;
s t a t e v a l u e <= X”02” when p r e s e n t s t a t e = Idle

e l s e X”03” when p r e s e n t s t a t e = Selected
e l s e X”04” when p r e s e n t s t a t e = Read0
e l s e X”08” when p r e s e n t s t a t e = Write1
e l s e X”09” when p r e s e n t s t a t e = Write2
e l s e X”0A” when p r e s e n t s t a t e = Write3
e l s e X”0B” when p r e s e n t s t a t e = Transfer done
e l s e X”0C” ;
r e g i s t e r o p b i n p u t s : p r o c e s s ( OPB Clk , OPB Rst )

begin
be <= ”0000” ;
d b u f i n p u t <= ( o t h e r s = > ’ 0 ’ ) ;
a b u f i n p u t <= ( o t h e r s = > ’ 0 ’ ) ;
RNW < = ’ 0 ’ ;
be <= OPB BE ;
−− d b u f i n p u t <= OPB DBus(C OPB DWIDTH−C ETHERNET DWIDTH t o C ETHERNET DWIDTH−1);
d b u f i n p u t <= OPB DBus(C OPB DWIDTH−C ETHERNET DWIDTH t o C OPB DWIDTH−3) & ”11” ;
a b u f i n p u t <= OPB ABus(C OPB AWIDTH−C ETHERNET AWIDTH t o C OPB AWIDTH−1);
−− a b u f i n p u t <= OPB ABus(C OPB AWIDTH−1 downto C OPB AWIDTH−C ETHERNET AWIDTH ) ;
−− a b u f i n p u t <= OPB ABus ( 2 t o 1 1 ) ;
−− check and abuf i n p u t i s g e t t i n g t h e c o r r e c t a d d r e s s data from t h e OPB Bus
−− a l s o checked p i n s and t h e E t h e r n e t c o n t r o l l e r i s g e t t i n g data on t h e
−− data l i n e s .
−− t h i s v a l u e s h o u l d be o n l y 1 0 b i t s a t t h e top , not b i t s 18−29
−−a b u f i n p u t <= OPB ABus(C OPB AWIDTH−3−(C ETHERNET AWIDTH−1) t o C OPB AWIDTH−3);
RNW <= OPB RNW;
62
end i f ;
end p r o c e s s r e g i s t e r o p b i n p u t s ;
r e g i s t e r o p b o u t p u t s : p r o c e s s ( OPB Clk , OPB Rst , OPB select , c h i p s e l e c t )

begin
Sln DBus ( 0 t o C ETHERNET DWIDTH−1) <= ( o t h e r s = > ’ 0 ’ ) ;
i f ( c h i p s e l e c t = ’ 1 ’ ) then
Sln DBus ( 0 t o C ETHERNET DWIDTH−1) <= d b u f o u t p u t ( 0 t o 1 5 ) ;
−− Sln DBus ( 0 t o C ETHERNET DWIDTH−1) <= d b u f o u t p u t ( 0 t o 1 1 ) & s t a t e v a l u e ( 4 t o
else
Sln DBus ( 0 t o C ETHERNET DWIDTH−1) <= ( o t h e r s = > ’ 0 ’ ) ;
end i f ;
end i f ;
end p r o c e s s r e g i s t e r o p b o u t p u t s ;
e t h e r n e t p b o u t p u t s : p r o c e s s ( OPB Rst , OPB Clk , c h i p s e l e c t , p b r e a d , p b w r i t e )

b e g i n −− p r o c e s s
ETHERNET CS N i < = ’ 1 ’ ;
ae n i <= ’1’;
bhe n i <= ’1’;
PB OE i < = ’ 1 ’ ; −− a c t i v e low
PB WE i < = ’ 1 ’ ; −− a c t i v e low
i f c h i p s e l e c t = ’ 1 ’ then
ae n i <= ’0’;
bhe n i <= ’0’;
else
ae n i <= ’1’;
bhe n i <= ’1’;
end i f ;
i f p b r e a d = ’ 0 ’ then
PB OE i < = ’ 0 ’ ;
else
PB OE i < = ’ 1 ’ ;
end i f ;
i f p b w r i t e = ’ 0 ’ then
PB WE i < = ’ 0 ’ ;
else
PB WE i < = ’ 1 ’ ;
end i f ;
end i f ;
end p r o c e s s ;
63
−− Unused o u t p u t s
Sln DBus (C ETHERNET DWIDTH t o C OPB DWIDTH−1) <= ( o t h e r s = > ’ 0 ’ ) ;
c h i p s e l e c t <= −− OPB select when OPB Abus ( 3 1 downto 20)=X”FF1” e l s e ’ 0 ’ ;
’ 1 ’ when OPB select = ’ 1 ’ and

OPB Abus ( 0 t o 1 1 ) =
C BASEADDR( 0 t o 1 1 ) e l s e
’0’;
−− chip select <= ’0’;
−− OPB ABus ( 0 t o C OPB AWIDTH−3−C ETHERNET AWIDTH) =

−− C BASEADDR( 0 t o C OPB AWIDTH−3−C ETHERNET AWIDTH) e l s e
begin
p r e s e n t s t a t e <= n e x t s t a t e ;
end i f ;
fsm comb : p r o c e s s ( OPB Rst , p r e s e n t s t a t e , c h i p s e l e c t , OPB Select , RNW)
begin

t r i s t a t e c o n t r o l <=’1’;
output enable <= ’0’;
pb read < = ’ 1 ’ ; −− a c t i v e low
pb write <= ’1’; −− a c t i v e low
else
when I d l e =>
t r i s t a t e c o n t r o l <=RNW;
i f c h i p s e l e c t = ’ 1 ’ then
n e x t s t a t e <= S e l e c t e d ;
else
end i f ;
64
when S e l e c t e d =>
t r i s t a t e c o n t r o l <= RNW;
p b r e a d <= not RNW; −− a c t i v e low
p b w r i t e <= RNW; −− a c t i v e low
i f OPB Select = ’ 1 ’ then
i f RNW = ’ 1 ’ then
n e x t s t a t e <= Read0 ;
else
n e x t s t a t e <= Write1 ;
end i f ;
else
end i f ;
when Read0 => −− we don ’ t h a n d l e r e a d s y e t .

else
end i f ;
when Read1 => −− we don ’ t h a n d l e r e a d s y e t .

else
end i f ;−−
when Read2 =>

n e x t s t a t e <= T r a n s f e r d o n e ;
else
65

end i f ;−−
when Read3 =>

else
end i f ;−−
−−
when Write1 =>
when Write2 =>

−−
when Write3 =>
when T r a n s f e r d o n e =>
t r i s t a t e c o n t r o l <= RNW; −− 0
when o t h e r s =>
66
A CODE LISTING A.6 misc
end case ;
end i f ;
Sln toutSup < = ’ 0 ’ ; −− −− t i e t h i s h i g h i n case we t a k e t o o long

S l n x f e r A c k < = ’ 1 ’ when p r e s e n t s t a t e = T r a n s f e r d o n e e l s e ’ 0 ’ ;
−− b h e n i <= ’0’; −− UB
−− L o c a l V a r i a b l e s :
−− c o m p i l e−command : ” g h d l −a o p b e t h e r n e t . vhd”
−− End :
A.6 misc
A.6.1 Makefile
# M a k e f i l e fo r CSEE 4 8 4 0
SYSTEM = system
MICROBLAZE OBJS = \
c s o u r c e f i l e s /main . o c s o u r c e f i l e s / ether . o
LIBRARIES = mymicroblaze / l i b / l i b x i l . a
ELF FILE = $ (SYSTEM) . e l f
NETLIST = i m p l e m e n t a t i o n /$ (SYSTEM) . ngc
# B i t s t r e a m s fo r t h e FPGA
FPGA BITFILE = i m p l e m e n t a t i o n /$ (SYSTEM) . b i t

MERGED BITFILE = i m p l e m e n t a t i o n / download . b i t
# F i l e s t o be downloaded t o t h e SRAM
SRAM BINFILE = i m p l e m e n t a t i o n / sram . b i n

SRAM HEXFILE = i m p l e m e n t a t i o n / sram . hex
MHSFILE = $ (SYSTEM) . mhs

MSSFILE = $ (SYSTEM) . mss
FPGA ARCH = s p a r t a n 2 e
DEVICE = x c2 s 300 e p q208−6
LANGUAGE = vhdl
PLATGEN OPTIONS = −p $ (FPGA ARCH) − l a n g $ (LANGUAGE)
67
A.6 misc A CODE LISTING
LIBGEN OPTIONS = −p $ (FPGA ARCH) $ (MICROBLAZE LIBG OPT)
# Paths f or programs
XILINX = / u s r / cad / x i l i n x / i s e 6 . 2 i
ISEBINDIR = $ ( XILINX ) / b i n / l i n
ISEENVCMDS = LD LIBRARY PATH=$ ( ISEBINDIR ) XILINX=$ ( XILINX ) PATH=$ ( ISEBINDIR ) : $ (PATH)
XILINX EDK = / u s r / cad / x i l i n x / edk6 . 2 i

EDKBINDIR = $ (XILINX EDK) / b i n / l i n
EDKENVCMDS = LD LIBRARY PATH=$ ( ISEBINDIR ) : $ (EDKBINDIR ) XILINX=$ ( XILINX ) XILINX EDK=$ (XILINX
MICROBLAZE = $ (XILINX EDK) / gnu/ m i c r o b l a z e / l i n

MBBINDIR = $ (MICROBLAZE) / b i n
XESSBINDIR = / u s r / cad / x e s s / b i n
# Executables
PLATGEN = $ (EDKENVCMDS) $ (EDKBINDIR) / p l a t g e n

LIBGEN = $ (EDKENVCMDS) $ (EDKBINDIR) / l i b g e n
XST = $ (ISEENVCMDS) $ ( ISEBINDIR ) / x s t

XFLOW = $ (ISEENVCMDS) $ ( ISEBINDIR ) / x f l o w
BITGEN = $ (ISEENVCMDS) $ ( ISEBINDIR ) / b i t g e n
DATA2MEM = $ (ISEENVCMDS) $ ( ISEBINDIR ) / data2mem
XSLOAD = $ (XESSBINDIR) / x s l o a d
XESS BOARD = XSB−300E
MICROBLAZE CC = $ (MBBINDIR) /mb−g c c

MICROBLAZE CC SIZE = $ (MBBINDIR) /mb−s i z e
MICROBLAZE OBJCOPY = $ (MBBINDIR) /mb−o b j c o p y
# External Targets
all :
@echo ” M a k e f i l e t o b u i l d a M i c r o p r o c e s s o r system : ”
@echo ”Run make with any o f t h e f o l l o w i n g t a r g e t s ”
@echo ” make l i b s : C o n f i g u r e s t h e sw l i b r a r i e s f o r t h i s system ”
@echo ” make program : Compiles t h e program s o u r c e s f o r a l l t h e p r o c e s s o r i n s t a n c
@echo ” make n e t l i s t : G e n e r a t e s t h e n e t l i s t f o r t h i s system ( $ (SYSTEM) ) ”
@echo ” make b i t s : Runs Imple mentation t o o l s t o g e n e r a t e t h e b i t s t r e a m ”
@echo ” make i n i t b r a m : I n i t i a l i z e s b i t s t r e a m with BRAM data ”
@echo ” make download : Downloads t h e b i t s t r e a m onto t h e board ”
@echo ” make n e t l i s t c l e a n : D e l e t e s n e t l i s t ”
@echo ” make hwclean : D e l e t e s i m p l e m e n t a t i o n d i r ”
@echo ” make l i b s c l e a n : D e l e t e s sw l i b r a r i e s ”
@echo ” make prog ram c le a n : D e l e t e s c o m p i l e d ELF f i l e s ”
@echo ” make c l e a n : Deletes a l l generated f i l e s / d i r e c t o r i e s ”
@echo ” make cd : D e l e t e s some s t u f f and downloads ”
@echo ” ”
@echo ” make < t a r g e t > : ( D e f a u l t ) ”
@echo ” C r e a t e s a M i c r o p r o c e s s o r system u s i n g d e f a u l t i n i t i a l i z a t i o n s ”
@echo ” s p e c i f i e d f o r each p r o c e s s o r i n MSS f i l e ”
68
b i t s : $ (FPGA BITFILE)
n e t l i s t : $ (NETLIST)
l i b s : $ (LIBRARIES)
program : $ ( ELF FILE )
i n i t b r a m : $ (MERGED BITFILE)
cd : c l p a r t download
clpart :
rm − f i m p l e m e n t a t i o n / system . ngc i m p l e m e n t a t i o n / e t h e r n e t p e r i p h e r a l w r a p p e r . ngc i m p
c l e a n : hwclean l i b s c l e a n p ro gra m c l e a n
rm − f b r a m i n i t . sh p l a t g e n . l o g p l a t g e n . opt l i b g e n . l o g
rm − f i m p a c t . cmd x f l o w . h i s
hwclean : n e t l i s t c l e a n
rm − r f i m p l e m e n t a t i o n s y n t h e s i s x s t h d l
rm − r f x s t . s r p $ (SYSTEM) x s t . s r p
netlistclean :
rm − f $ (FPGA BITFILE ) $ (MERGED BITFILE ) \
$ (NETLIST ) i m p l e m e n t a t i o n / $ (SYSTEM) bd .bmm
libsclean :
rm − r f mymicroblaze / l i b
p r og ra m c le an :
rm − f $ ( ELF FILE ) $ (SRAM BITFILE ) $ (SRAM HEXFILE)
#
# Software r u l e s
#
MICROBLAZE MODE = e x e c u t a b l e
# Assemble s o f t w a r e l i b r a r i e s from t h e . mss and . mhs f i l e s
$ (LIBRARIES ) : $ (MHSFILE ) $ (MSSFILE)

$ (LIBGEN ) $ (LIBGEN OPTIONS ) $ (MSSFILE)
# C o m p i l a t i on
MICROBLAZE CC CFLAGS =
#MICROBLAZE CC OPT = −O3 #−mxl−gp−opt
MICROBLAZE CC OPT = −Os #−mxl−gp−opt
MICROBLAZE CC DEBUG FLAG =# −g s t a b s
MICROBLAZE INCLUDES = − I . / mymicroblaze / i n c l u d e / # − I
69
MICROBLAZE CFLAGS = \
$ (MICROBLAZE CC CFLAGS) \
−mxl−b a r r e l−s h i f t \
$ (MICROBLAZE CC OPT) \
$ (MICROBLAZE CC DEBUG FLAG) \
$ (MICROBLAZE INCLUDES)
$ (MICROBLAZE OBJS ) : % . o : % . c
PATH=$ (MBBINDIR ) $ (MICROBLAZE CC) $ (MICROBLAZE CFLAGS) − c $< −o $@
# Linking
# Uncomment t h e f o l l o w i n g t o make l i n k e r p r i n t l o c a t i o n s f o r e v e r y t h i n g
MICROBLAZE LD FLAGS = −Wl,−M
#MICROBLAZE LINKER SCRIPT = −Wl,−T −Wl , m y l i n k s c r i p t
MICROBLAZE LIBPATH = −L . / mymicroblaze / l i b /
MICROBLAZE CC START ADDR FLAG= −Wl,− defsym −Wl , TEXT START ADDR=0x00000000
MICROBLAZE CC STACK SIZE FLAG= −Wl,− defsym −Wl , STACK SIZE=0x200
MICROBLAZE LFLAGS = \
−x l−mode−$ (MICROBLAZE MODE) \
$ (MICROBLAZE LD FLAGS) \
$ (MICROBLAZE LINKER SCRIPT ) \
$ (MICROBLAZE LIBPATH) \
$ (MICROBLAZE CC START ADDR FLAG) \
$ (MICROBLAZE CC STACK SIZE FLAG)
$ ( ELF FILE ) : $ (LIBRARIES ) $ (MICROBLAZE OBJS)

PATH=$ (MBBINDIR ) $ (MICROBLAZE CC) $ (MICROBLAZE LFLAGS) \
$ (MICROBLAZE OBJS) − o $ ( ELF FILE )
$ (MICROBLAZE CC SIZE ) $ ( ELF FILE )
#
# Hardware r u l e s
#
# Hardware c o m p i l a t i o n : o p t i m i z e t h e n e t l i s t , p l a c e and r o u t e
$ (FPGA BITFILE ) : $ (NETLIST ) \

e t c / f a s t r u n t i m e . opt e t c / b i t g e n . ut data / $ (SYSTEM) . u c f
cp − f e t c / b i t g e n . ut i m p l e m e n t a t i o n /
cp − f e t c / f a s t r u n t i m e . opt i m p l e m e n t a t i o n /
cp − f data /$ (SYSTEM) . u c f i m p l e m e n t a t i o n / $ (SYSTEM) . u c f
$ (XFLOW) −wd i m p l e m e n t a t i o n −p $ (DEVICE) − implement f a s t r u n t i m e . opt \
$ (SYSTEM) . ngc
cd i m p l e m e n t a t i o n ; $ (BITGEN) − f b i t g e n . ut $ (SYSTEM)
# Hardware assembly : C r e a t e t h e n e t l i s t from t h e . mhs f i l e
$ (NETLIST ) : $ (MHSFILE)
$ (PLATGEN) $ (PLATGEN OPTIONS) − s t x s t $ (MHSFILE)
$ (XST) − i f n s y n t h e s i s /$ (SYSTEM) x s t . s c r
# p e r l synth modules . pl < s y n t h e s i s / xst . s c r > xst . s c r
# $ (XST) − i f n x s t . s c r
70
# rm − r x s t x s t . s c r
# $ (XST) − i f n s y n t h e s i s /$ (SYSTEM) . s c r
#
# Downloading
#
# Add s o f t w a r e code t o t h e FPGA b i t f i l e
$ (MERGED BITFILE ) : $ (FPGA BITFILE ) $ ( ELF FILE )

$ (DATA2MEM) −bm i m p l e m e n t a t i o n / $ (SYSTEM) bd \
−bt i m p l e m e n t a t i o n /$ (SYSTEM) \
−bd $ ( ELF FILE ) t a g bram −o b $ (MERGED BITFILE)
# C r e a t e a . hex f i l e with data fo r t h e SRAM
$ (SRAM HEXFILE ) : $ ( ELF FILE )

$ (MICROBLAZE OBJCOPY) \
−j . s r a m t e x t − j . s d a t a 2 − j . s d a t a − j . r o d a t a − j . data \
−O b i n a r y $ ( ELF FILE ) $ (SRAM BINFILE)
. / bin2hex −a 6 0 0 0 0 < $ (SRAM BINFILE) > $ (SRAM HEXFILE)
# Download t h e f i l e s t o t h e t a r g e t board
download−sram : $ (MERGED BITFILE ) $ (SRAM HEXFILE)

$ (XSLOAD) −ram −b $ (XESS BOARD ) $ (SRAM HEXFILE)
$ (XSLOAD) − f p g a −b $ (XESS BOARD ) $ (MERGED BITFILE)
download : $ (MERGED BITFILE)

$ (XSLOAD) − f p g a −b $ (XESS BOARD ) $ (MERGED BITFILE)
A.6.2 system.mhs
#−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
# CSEE 4 8 4 0 Embedded System Design − System C o n s t r a i n t s F i l e
#
# SOBA S e r v e r
#
# Team W a r r i o r s : Avraham Sh i nn a r as1619@columbia . edu
#
#−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
# Parameters
PARAMETER VERSION = 2 . 1 . 0
####PORTS
# Clock Port
PORT FPGA CLK1 = FPGA CLK1 , DIR = IN
# UART P o r t s
71
PORT RS232 TD = RS232 TD , DIR=OUT

PORT RS232 RD = RS232 RD , DIR=IN
# Ethernet Ports
PORT PB D = PB D , DIR = INOUT , VEC= [ 1 5 : 0 ]
PORT PB A = PB A , DIR = OUT, VEC= [ 1 9 : 0 ]
PORT PB OE N = PB OE N , DIR = OUT
PORT PB WE N = PB WE N , DIR = OUT
PORT PB UB N = PB UB N , DIR = OUT
PORT PB LB N = PB LB N , DIR = OUT
PORT RAM CE N = RAM CE N , DIR = OUT
PORT ETHERNET CS N = ETHERNET CS N , DIR = OUT

PORT ETHERNET IOCS16 N = ETHERNET IOCS16 N , DIR = IN
PORT ETHERNET RDY = ETHERNET RDY , DIR = IN
PORT ETHERNET IREQ = ETHERNET IREQ , DIR = IN
# Audio Codec P o r t s
PORT AU CSN = 0 b1 , DIR=OUT
PORT AU MCLK = AU MCLK , DIR=OUT

PORT AU LRCK = AU LRCK , DIR=OUT
PORT AU BCLK = AU BCLK , DIR=OUT
PORT AU SDTI = AU SDTI , DIR=OUT
PORT AU SDTO0 = AU SDTO0 , DIR=IN
#### PERIPHERALS
# Ethernet p e r i p h e r a l
BEGIN o p b e t h e r n e t
PARAMETER INSTANCE = e t h e r n e t p e r i p h e r a l
PARAMETER HW VER = 1 . 0 0 . a
PARAMETER C BASEADDR = 0 x00800000
PARAMETER C HIGHADDR = 0x00FFFFFF
# PARAMETER C BASEADDR = 0 xFF100000
# PARAMETER C HIGHADDR = 0xFF1FFFFF
PORT OPB CLK = s y s c l k

# PORT ETHER CLK = ETHER CLK
# do we need t o add an e t h e r n e t c l o c k h e r e ?
BUS INTERFACE SOPB = myopb bus
PORT ETHERNET CS N = ETHERNET CS N

PORT ETHERNET RDY = ETHERNET RDY
PORT ETHERNET IREQ = ETHERNET IREQ
PORT ETHERNET IOCS16 N = ETHERNET IOCS16 N
PORT PB D = PB D
PORT PB A = PB A
PORT PB OE N = PB OE N
72
PORT PB WE N = PB WE N
PORT PB UB N = PB UB N
PORT PB LB N = PB LB N
PORT RAM CE N = RAM CE N
PORT i o c l o c k = i o c l o c k
END
# Audio Sampler P e r i p h e r a l
BEGIN o p b a u d i o s a m p l e r
PARAMETER INSTANCE = a u d i o s a m p l e r
PARAMETER C HIGHADDR = 0 x100001FF
# PORT AU CLK = a u d i o c l k
PORT OPB Clk = s y s c l k
PORT AU MCLK = AU MCLK
PORT AU LRCK = AU LRCK
PORT AU BCLK = AU BCLK
PORT AU SDTI = AU SDTI
PORT AU SDTO0 = AU SDTO0
PORT INTERRUPT = s a m p l e r i n t r
END
# The MICROBLAZE
BEGIN m i c r o b l a z e
PARAMETER INSTANCE = mymicroblaze
PARAMETER C USE BARREL = 1
PARAMETER C USE ICACHE = 0
PORT Clk = s y s c l k
PORT Reset = f p g a r e s e t
PORT I n t e r r u p t = i n t r
BUS INTERFACE DLMB = d lmb
BUS INTERFACE ILMB = i l m b
BUS INTERFACE DOPB = myopb bus
BUS INTERFACE IOPB = myopb bus
END
# Interrupt Controller
BEGIN o p b i n t c
PARAMETER INSTANCE = i n t c
PARAMETER HW VER = 1 . 0 0 . c
PARAMETER C BASEADDR = 0 xFFFF0000
PARAMETER C HIGHADDR = 0xFFFF00FF
PORT I n t r = u a r t i n t r & s a m p l e r i n t r
PORT I r q = intr
73
END
# Block RAM for code and data i s c o n n e c t e d through two LMB b u s s e s

# t o t h e M i c r o b l a z e , which has two p o r t s on i t fo r j u s t t h i s r e a s o n .
# Data LMB bus
BEGIN lmb v10

PARAMETER INSTANCE = d lmb
PORT LMB Clk = s y s c l k
PORT SYS Rst = f p g a r e s e t
END
BEGIN l m b b r a m i f c n t l r
PARAMETER INSTANCE = l m b d a t a c o n t r o l l e r
PARAMETER HW VER = 1 . 0 0 . b
PARAMETER C HIGHADDR = 0 x00000FFF
BUS INTERFACE SLMB = d lmb
BUS INTERFACE BRAM PORT = conn 0
END
# I n s t r u c t i o n LMB bus
BEGIN lmb v10

PARAMETER INSTANCE = i l m b
PORT LMB Clk = s y s c l k
END
BEGIN l m b b r a m i f c n t l r
PARAMETER INSTANCE = l m b i n s t r u c t i o n c o n t r o l l e r
PARAMETER C HIGHADDR = 0 x00000FFF
BUS INTERFACE SLMB = i l m b
BUS INTERFACE BRAM PORT = conn 1
END
# The a c t u a l b l o c k memory
BEGIN bram block

PARAMETER INSTANCE = bram
BUS INTERFACE PORTA = conn 0
BUS INTERFACE PORTB = conn 1
END
# Clock d i v i d e r t o make t h e whole t h i n g run
BEGIN c l k g e n
74
PARAMETER INSTANCE = c l k g e n 0
PORT FPGA CLK1 = FPGA CLK1
PORT i o c l o c k = i o c l o c k
PORT s y s c l k = s y s c l k
PORT f p g a r e s e t = f p g a r e s e t
END
# The OPB bus c o n t r o l l e r c o n n e c t e d t o t h e M i c r o b l a z e

# All p e r i p h e r a l s are connected to t h i s
BEGIN opb v20

PARAMETER INSTANCE = myopb bus
PARAMETER C DYNAM PRIORITY = 0
PARAMETER C REG GRANTS = 0
PARAMETER C PARK = 0
PARAMETER C PROC INTRFCE = 0
PARAMETER C DEV BLK ID = 0
PARAMETER C DEV MIR ENABLE = 0
PARAMETER C BASEADDR = 0 x 0 f f f 1 0 0 0
PARAMETER C HIGHADDR = 0 x 0 f f f 1 0 f f
END
# UART: S e r i a l p o r t hardware
BEGIN o p b u a r t l i t e
PARAMETER INSTANCE = myuart
PARAMETER C CLK FREQ = 50 0 0 0 0 0 0
PARAMETER C USE PARITY = 0
PARAMETER C BASEADDR = 0 xFEFF0100
PARAMETER C HIGHADDR = 0xFEFF01FF
PORT RX=RS232 RD
PORT TX=RS232 TD
PORT INTERRUPT = u a r t i n t r
END
A.6.3 system.mss
#−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
#
# SOBA S e r v e r
#
#
#−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
75
PARAMETER VERSION = 2 . 2 . 0
PARAMETER HW SPEC FILE = system . mhs
BEGIN PROCESSOR
PARAMETER HW INSTANCE = mymicroblaze
PARAMETER DRIVER NAME = cpu
PARAMETER DRIVER VER = 1 . 0 0 . a
END
BEGIN OS
PARAMETER PROC INSTANCE = mymicroblaze
PARAMETER OS NAME = s t a n d a l o n e
PARAMETER OS VER = 1 . 0 0 . a
PARAMETER STDIN = myuart
PARAMETER STDOUT = myuart
END
BEGIN DRIVER
PARAMETER HW INSTANCE = myuart
PARAMETER DRIVER NAME = u a r t l i t e
PARAMETER DRIVER VER = 1 . 0 0 . b
END
BEGIN DRIVER
PARAMETER HW INSTANCE = i n t c
PARAMETER DRIVER NAME = i n t c
PARAMETER DRIVER VER = 1 . 0 0 . c
END
# Use n u l l d r i v e r s for p e r i p h e r a l s t h a t don ’ t need them

# This s u p r e s s e s w arni n gs
BEGIN DRIVER
PARAMETER HW INSTANCE = l m b d a t a c o n t r o l l e r
PARAMETER DRIVER NAME = g e n e r i c
END
BEGIN DRIVER
PARAMETER HW INSTANCE = l m b i n s t r u c t i o n c o n t r o l l e r
END
BEGIN DRIVER
PARAMETER HW INSTANCE = e t h e r n e t p e r i p h e r a l
END
BEGIN DRIVER
PARAMETER HW INSTANCE = a u d i o s a m p l e r
76

END
A.6.4 data/system.ucf
#−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
#
# SOBA S e r v e r
#
#
#−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
# NOTE: p r o b a b l y need some o t h e r c l o c k s i n h e r e b e s i d e s system c l o c k

# t h e XSB manual s a y s t h e r e i s an e x s i t i n g 2 5 Mhz e t h e r n e t c l o c k
# and CLKC i s a l r e a d y 1 0 0 Mhz s o why would we need a n o t h e r c l o c k ?
# ETHER−CLK c o n n e c t s t o AX88796 p i n 7 9
# a l s o n o t e t h a t t h e PB
net s y s c l k period = 2 0 . 0 0 0 ;
#n e t p i x e l c l o c k p e r i o d = 3 6 . 0 0 0 ;
net i o c l o c k period = 9 . 0 0 0 ;
#n e t ICLK p e r i o d = 3 0 . 0 0 0 ;
n e t FPGA CLK1 l o c=” p77 ” ;
n e t RS232 TD l o c=” p71 ” ;

n e t RS232 RD l o c=” p73 ” ;
# Ethernet
n e t ETHERNET CS N l o c=” p82 ” ;
n e t ETHERNET RDY l o c=” p81 ” ;
n e t ETHERNET IREQ l o c=” p75 ” ;
n e t ETHERNET IOCS16 N l o c=” p74 ” ;
# OPB ETHERNET
n e t PB OE N l o c=” p125 ” ;
n e t PB WE N l o c=” p123 ” ;
n e t PB UB N l o c=” p146 ” ;
n e t PB LB N l o c=” p140 ” ;
n e t RAM CE N l o c=” p147 ” ;
# OPB Data
n e t PB D<0> l o c=” p153 ” ;
n e t PB D<1> l o c=” p145 ” ;
n e t PB D<2> l o c=” p141 ” ;
n e t PB D<3> l o c=” p135 ” ;
77
net PB D<4> l o c=” p126 ” ;

net PB D<5> l o c=” p120 ” ;
net PB D<6> l o c=” p116 ” ;
net PB D<7> l o c=” p108 ” ;
net PB D<8> l o c=” p127 ” ;
net PB D<9> l o c=” p129 ” ;
net PB D<10> l o c=” p132 ” ;
net PB D<11> l o c=” p133 ” ;
net PB D<12> l o c=” p134 ” ;
net PB D<13> l o c=” p136 ” ;
net PB D<14> l o c=” p138 ” ;
net PB D<15> l o c=” p139 ” ;
#OPB Address
n e t PB A<0> l o c=” p83 ” ;
n e t PB A<1> l o c=” p84 ” ;
n e t PB A<2> l o c=” p86 ” ;
n e t PB A<3> l o c=” p87 ” ;
n e t PB A<4> l o c=” p88 ” ;
n e t PB A<5> l o c=” p89 ” ;
n e t PB A<6> l o c=” p93 ” ;
n e t PB A<7> l o c=” p94 ” ;
n e t PB A<8> l o c=” p100 ” ;
n e t PB A<9> l o c=” p101 ” ;
n e t PB A<10> l o c=” p102 ” ;
n e t PB A<11> l o c=” p109 ” ;
n e t PB A<12> l o c=” p110 ” ;
n e t PB A<13> l o c=” p111 ” ;
n e t PB A<14> l o c=” p112 ” ;
n e t PB A<15> l o c=” p113 ” ;
n e t PB A<16> l o c=” p114 ” ;
n e t PB A<17> l o c=” p115 ” ;
n e t PB A<17> l o c=” p115 ” ;
n e t PB A<18> l o c=” p121 ” ;
n e t PB A<19> l o c=” p122 ” ;
# Audio Codec
n e t AU CSN l o c=” p165 ” ;
n e t AU MCLK l o c=” p167 ” ;
n e t AU LRCK l o c=” p168 ” ;
n e t AU BCLK l o c=” p166 ” ;
n e t AU SDTI l o c=” p169 ” ;
n e t AU SDTO0 l o c=” p173 ” ;
78

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SOBA Server: RTP Streaming Audio over Ethernet

Final Project Report ver. 1.0

Avraham Shinnar as1619@columbia.edu

“...no pain no tears”

May 10, 2005

4 Lessons Learned and Advice for Future Projects 11

2.2 Audio Codec

Figure 1: System Block Diagram

2.2.1 Audio Control Peripheral

Figure 2: Audio Controller Timing Diagram

2.2.2 Audio Sample Peripheral

2.3 Ethernet Codec

AU_CDTI_ AU_CSN_ AU_CCLK

AU_CDTI AU_CSN AU_CCLK Sln_DBus

Figure 3: Audio Controller Block Diagram

Figure 4: Audio Sampler Timing Diagram

Figure 5: Audio Sampler Block Diagram

[0:9] PB_A PB_D

[15:0] [0:15] [0:15] SIn_DBus

Figure 6: Ethernet Block Diagram

1. Write 21h to Command Register to abort current DMA operations.

IDLE Selected Read Read2 Done

Figure 7: Ethernet Timing Diagram (for Read Only)

2.5 RTP Packet Structure and Construction

MAC hdr Ethernet destination address

2.6 RTP Client

4 Lessons Learned and Advice for Future Projects

Avi Hardware is evil!!!

#define MAC HEADER SIZE 1 4

#define IP LENGTH ( PACKET SIZE−MAC HEADER SIZE)

#define IP CHECKSUM OFFSET 2 4

#define DATA CHUNK SIZE 1 6

#define PAYLOAD SIZE ( DATA CHUNKS IN PACKET∗DATA CHUNK SIZE)

#define PACKET BUFFERS 1

/ / B u f f e r Length and F i e l d D e f i n i t i o n Info

#define BASE ADDR (XPAR ETHERNET PERIPHERAL BASEADDR+0x400 )

#define PACKET END ADDRESS PACKET START ADDRESS+PACKET SIZE

#define PAYLOAD START ADDRESS PACKET START ADDRESS+HEADER SIZE ;

/∗ function prototypes , external i n t e r f a c e . ∗ /

void w a i t ( int mult ) ;

#define ISR PTX 0 x02 / / p a c k e t t r a n s m i t t e d with no error

#define CR STOP 0 x01

/∗ function prototypes , i n t e r n a l helpers ∗/

/ ∗ n o t e t h a t a t one p o i n t we had l o t s more f u n c t i o n s . t h e code

should be : ) . s i n c e time stamp and s e q u e n c e number a r e i n c r e m e n t s ,

/ ∗ t h e r e a l n o t e : udp checksum can a c t u a l l y be ( and now i s ) 0 . This

n o t e t o f u t u r e p e o p l e : smashing your s t a c k i s a bad i d e a .

/∗ # d e f i n e UDP INIT CHECKSUM ( ˜ ( (WORD) ( 0 xaa78 ) ) ) ; ∗ /

s t a t i c BYTE h e a d e r [ HEADER SIZE ] = {

/ ∗ D i a g n o s t i c s based on page 3 1 o f t h e E t h e r n e t C o n t r o l l e r manual

o u t n i c (CMDR, 0 x21 ) ; / / switch t o page 0

/ ∗ i n i t i a l i z e s t h e e t h e r n e t c a r d and our data s t r u c t u r e s . s e t s up t h e

o u t n i c (NE RESET , i n n i c (NE RESET ) ) ; / / t r i g g e r a r e s e t

/ ∗ Write 2 1 h t o Command R e g i s t e r t o a b o r t c u r r e n t DMA o p e r a t i o n s . ∗ /

/∗ udp checksum = UDP INIT CHECKSUM ; ∗ /

o u t n i c (CMDR, CR COMPLETE| CR TXP ) ; / / s t a r t t r a n s m i s s i o n

/ ∗ low l e v e l f u n c t i o n t h a t d o e s dma t o send data t o c a r d . ∗ /

o u t n i c (RSAR0 , ( addr&0 x f f ) ) ; / / s e t DMA s t a r t i n g a d d r e s s

o u t n i c ( ISR , 0 xFF ) ; / / c l e a r ISR

o u t n i c (RBCR0 , ( dmalen&0 x f f ) ) ; / / s e t Remote DMA Byte Count

o u t n i c (CMDR, CR WRITE | CR START ) ; / / s t a r t t h e DMA w r i t e − 0 x12

/ / change o r d e r o f MS/LS s i n c e DMA

i f ( ! ( i n n i c ( ISR ) & ISR RDC ) ) {

/∗ udp checksum += ∗( sample + 1 ) ; ∗ /