AD630
FEATURES FUNCTIONAL BLOCK DIAGRAM
Recovers Signal from 100 dB Noise
CM OFF CM OFF DIFF OFF DIFF OFF
2 MHz Channel Bandwidth ADJ ADJ ADJ ADJ
45 V/s Slew Rate 6 5 4 3
2.5k⍀
–120 dB Crosstalk @ 1 kHz RINA 1 AD630
AMP A
Pin Programmable, Closed-Loop Gains of ⴞ1 and ⴞ2
CH A+ 2 12 COMP
0.05% Closed-Loop Gain Accuracy and Match
CH A– 20
100 V Channel Offset Voltage (AD630BD) 2.5k⍀
A 11 +VS
REV. E
NOTES
1
If one terminal of each differential channel or comparator input is kept within these limits the other terminal may be taken to the positive supply.
2
ISINK @ VOL = (–VS + 1); V is typically 4 mA.
3
Pin 12 Open. Slew rate with Pin 12 and Pin 13 shorted is typically 35 V/ µs.
Specifications subject to change without notice.
–2– REV. E
AD630
ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 18 V
Internal Power Dissipation . . . . . . . . . . . . . . . . . . . . 600 mW JC JA
Output Short-Circuit to Ground . . . . . . . . . . . . . . . Indefinite 20-Lead PDIP (N) 24°C/W 61°C/W
Storage Temperature, Ceramic Package . . . –65°C to +150°C 20-Lead Ceramic DIP (D) 35°C/W 120°C/W
Storage Temperature, Plastic Package . . . . . –55°C to +125°C 20-Lead Leadless Chip Carrier LCC (E) 35°C/W 120°C/W
Lead Temperature Range (Soldering, 10 sec) . . . . . . . . 300°C 20-Lead SOIC (R-20) 38°C/W 75°C/W
Maximum Junction Temperature . . . . . . . . . . . . . . . . . 150°C
ORDERING GUIDE
RINA 1 20 CH A–
CH A+ 2 19 CH B–
20-Terminal CLCC
OFF ADJ
CH A+
CH A–
CH B–
RIN A
DIFF
3 2 1 20 19
CHIP AVAILABILITY
The AD630 is available in laser trimmed, passivated chip DIFF OFF ADJ 4 18 CH B+
form. The figure above shows the AD630 metallization pattern, CM OFF ADJ 5
AD630 17 RINB
bonding pads and dimensions. AD630 chips are available; con- CM OFF ADJ 6 TOP VIEW 16 RA
CHANNEL STATUS B/A 7 (Not to Scale) 15 RF
sult factory for details.
–VS 8 14 RB
9 10 11 12 13
SEL B
VOUT
COMP
+VS
SEL A
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD630 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
REV. E –3–
AD630
AD630–Typical Performance Characteristics
15 15 18
5k⍀ 5k⍀
15 Vi
RL= 2k⍀ CL = 100pF VO
10
5k⍀ 5k⍀
Vi 5k⍀ 5k⍀
VO Vi
5 5
2k⍀ VO
100pF 5
RL
100pF f = 1kHz
CAP IN CL = 100pF
0 0 0
1k 10k 100k 1M 1 10 100 1k 10k 100k 1M 0 5 10 15
FREQUENCY (Hz) RESISTIVE LOAD (⍀) SUPPLY VOLTAGE (ⴞV)
TPC 1. Output Voltage vs. Frequency TPC 2. Output Voltage vs. Resistive TPC 3. Output Voltage Swing vs.
Load Supply Voltage
120 60 120 0
UNCOMPENSATED
COMMON-MODE REJECTION (dB)
100 40
100
UNCOMPENSATED
60 0
60 90
COMPENSATED
dVO
dt
40 –20 40 COMPENSATED
135
20 –40 20
0 –60 0 180
1 10 100 1k 10k 100k –5 –4 –3 –2 –1 0 1 2 3 4 5 0 10 100 1k 10k 100k 1M 10M
FREQUENCY (Hz) INPUT VOLTAGE (V) FREQUENCY (Hz)
dVO
TPC 4. Common-Mode Rejection TPC 5. vs. Input Voltage TPC 6. Gain and Phase vs. Frequency
vs. Frequency dt
–4– REV. E
AD630
20mV 10V 1mV 5s
ⴞ10V 20kHz
100 100
90 90
(Vi)
20mV/DIV
(Vo)
1mV/DIV
(B)
20mV/DIV 10 10V/DIV 10
(Vi) 0% (Vo) 0%
16 15
5k⍀ 10k⍀ 10k⍀
2
Vi
20 CH A 14 15 20
VO TOP VO
13 13
TRACE 10k⍀
19 2 CH A BOTTOM
12 12 TRACE
18 CH B
10k⍀
10k⍀ 10k⍀ (B)
MIDDLE
14 TRACE
9 HP5082-2811
Vi
10
TPC 7. Channel-to-Channel Switch-Settling Characteristic TPC 9. Large Signal Inverting Step Response
50mV 1mV
50mV/DIV 100
90
(Vi)
1mV/DIV
(A)
10
0%
100mV/DIV
(Vo) 100mV 500ns
TOP TRACE: Vi
MIDDLE TRACE: SETTLING
ERROR (A)
BOTTOM TRACE: Vo
10k⍀
14 10k⍀ 15 20
13 VO
Vi
2 CH A BOTTOM
TOP 12 TRACE
TRACE 10k⍀
1k⍀
MIDDLE
TRACE
(A)
30pF 10k⍀
TEKTRONIX
7A13
REV. E –5–
AD630
TWO WAYS TO LOOK AT THE AD630 The two closed-loop gain magnitudes will be equal when RF/RA
The functional block diagram of the AD630 (see page 1) shows = 1 + RF/RB, which will result from making RA equal to RFRB/
the pin connections of the internal functions. An alternative archi- (RF + RB) the parallel equivalent resistance of RF and RB.
tectural diagram is shown in Figure 1. In this diagram, the
The 5 kΩ and the two 10 kΩ resistors on the AD630 chip can
individual A and B channel preamps, the switch, and the inte- be used to make a gain of 2 as shown below. By paralleling
grator output amplifier are combined in a single op amp. This the 10 kΩ resistors to make RF equal to 5 kΩ and omitting RB,
amplifier has two differential input channels, only one of which the circuit can be programmed for a gain of ± 1 (as shown in
is active at a time. Figure 9a). These and other configurations using the on-chip
+VS
resistors present the inverting inputs with a 2.5 kΩ source imped-
15 11
ance. The more complete AD630 diagrams show 2.5 kΩ resistors
16 14 available at the noninverting inputs which can be conveniently
RA 5k⍀ RB
used to minimize errors resulting from input bias currents.
1 10k⍀
2.5k⍀
2 RF RF 10k⍀
A 10k⍀
20 RA
13
19 5k⍀
B Vi
18 RF
2.5k⍀ 12 RB
VO = – V
17 10k⍀ RA i
7 B/A
SEL B 9
SEL A 10
8 Figure 3. Inverting Gain Configuration
–VS
Q44
SEL A
Figure 2. AD630 Symmetric Gain (± 2) 10 Q52 Q53 Q62 Q65 Q67 Q70 13 VOUT
When Channel B is selected, the resistors RA and RF are 9 Q74
connected for inverting feedback as shown in the inverting SEL B
Q30
C121
12
gain configuration diagram in Figure 3. The amplifier has suffi- Q31 COMP
C122
cient loop gain to minimize the loading effect of RB at the Q28 Q32
Q29
virtual ground produced by the feedback connection. When the Q24 Q25
sign of the comparator input is reversed, Input B will be dese- i22 i23
Q3 Q4
lected and A will be selected. The new equivalent circuit will be
the noninverting gain configuration shown in Figure 4. In this –VS 8
3 4 5 6
case, RA will appear across the op amp input terminals, but since
DIFF DIFF CM CM
the amplifier drives this difference voltage to zero, the closed-loop OFF ADJ OFF ADJ OFF ADJ OFF ADJ
gain is unaffected. Figure 5. AD630 Simplified Schematic
–6– REV. E
AD630
The collectors of each switching cell connect to an input trans- desired signal multiplied by the low frequency gain (which may
conductance stage. The selected cell conveys bias currents i22 be several hundred for large feedback ratios) with the switching
and i23 to the input stage it controls, causing it to become active. signal and interference superimposed at unity gain.
The deselected cell blocks the bias to its input stage which, as a
C C
consequence, remains off. 2k⍀ 2k⍀
REV. E –7–
AD630
the system input tied to 0 V, and a switching or carrier wave- AD630 when used to modulate a 100 kHz square wave carrier
form applied to the comparator, a low level square wave will with a 10 kHz sinusoid. The result is the double sideband sup-
appear at the output. The differential offset adjustment potenti- pressed carrier waveform.
ometers can be used to null the amplitude of this square wave These balanced modulator topologies accept two inputs, a signal
(Pins 3 and 4). The common-mode offset adjustment can be (or modulation) input applied to the amplifying channels and a
used to zero the residual dc output voltage (Pins 5 and 6). reference (or carrier) input applied to the comparator.
These functions should be implemented using 10k trim poten-
tiometers with wipers connected directly to Pin 8 as shown in 10k⍀ CM 10k⍀ DIFF
Figures 9a and 9b. ADJ ADJ
100k⍀
9
7 10k⍀ 10k⍀ DIFF
CM
10 ADJ ADJ
8
100⍀ –15V 6 5 4 3
2.5k⍀
MODULATION 1 AMP A
INPUT 12
2 A
11 +VS
Figure 7. Comparator Hysteresis 20
13
2.5k⍀ B
10k⍀ MODULATED
The channel status output may be interfaced with TTL inputs 17 AMP B
14 OUTPUT
18 –V SIGNAL
as shown in Figure 8. This circuit provides appropriate level 10k⍀
15
19
shifting from the open-collector AD630 channel status output to CARRIER AD630 16
COMP 5k⍀
TTL inputs. INPUT
9
7
10
+5V 8
–VS
+15V 22k⍀
6.8k⍀
100k⍀
Figure 9b. AD630 Configured as a Gain-of-Two Balanced
AD630 IN 914s Modulator
7 TTL INPUT
2N2222
8
5V 5V 20s
–15V
MODULATION
Figure 8. Channel Status—TTL Interface INPUT
–8– REV. E
AD630
BALANCED DEMODULATOR E1000
AD544
SCHAEVITZ AD630
The balanced modulator topology described above will also act as A LVDT
FOLLOWER
ⴞ2 DEMODULATOR
a balanced demodulator if a double sideband suppressed carrier 16 B 5k⍀
15
waveform is applied to the signal input and the carrier signal is 10k⍀
1 2.5k⍀
applied to the reference input. The output under these circumstances 2.5kHZ 20 A
C
will be the baseband modulation signal. Higher order carrier 2V p-p 13 100k⍀
SINUSOIDAL 14 10k⍀ 19 D
components that can be removed with a low-pass filter will EXCITATION 17 B 12
1F
also be present. Other names for this function are synchro- 2.5k⍀
nous demodulation and phase-sensitive detection.
PHASE 9
PRECISION PHASE COMPARATOR SHIFTER 10
The balanced modulator topologies of Figures 9a and 9b can
also be used as precision phase comparators. In this case, an ac
waveform of a particular frequency is applied to the signal input Figure 11. LVDT Signal Conditioner
and a waveform of the same frequency is applied to the refer- AC BRIDGE
ence input. The dc level of the output (obtained by low-pass Bridge circuits that use dc excitation are often plagued by
filtering) will be proportional to the signal amplitude and phase errors caused by thermocouple effects, 1/f noise, dc drifts in the
difference between the input signals. If the signal amplitude is electronics, and line noise pick-up. One way to get around these
held constant, the output can be used as a direct indication of problems is to excite the bridge with an ac waveform, amplify the
the phase. When these input signals are 90° out of phase, they bridge output with an ac amplifier, and synchronously demodulate
are said to be in quadrature and the AD630 dc output will be zero. the resulting signal. The ac phase and amplitude information
from the bridge is recovered as a dc signal at the output of the
PRECISION RECTIFIER ABSOLUTE VALUE
synchronous demodulator. The low frequency system noise,
If the input signal is used as its own reference in the balanced
dc drifts, and demodulator noise all get mixed to the carrier
modulator topologies, the AD630 will act as a precision recti-
frequency and can be removed by means of a low-pass filter.
fier. The high frequency performance will be superior to that
Dynamic response of the bridge must be traded off against the
which can be achieved with diode feedback and op amps. There
amount of attenuation required to adequately suppress these
are no diode drops that the op amp must “leap over” with the
residual carrier components in the selection of the filter.
commutating amplifier.
Figure 12 is an example of an ac bridge system with the AD630
LVDT SIGNAL CONDITIONER used as a synchronous demodulator. The bridge is excited by a
Many transducers function by modulating an ac carrier. A linear 1 V 400 Hz excitation. Trace A in Figure 13 is the amplified
variable differential transformer (LVDT) is a transducer of bridge signal. Trace B is the output of the synchronous demodu-
this type. The amplitude of the output signal corresponds to lator and Trace C is the filtered dc system output.
core displacement. Figure 11 shows an accurate synchronous
demodulation system which can be used to produce a dc voltage
that corresponds to the LVDT core position. The inherent
precision and temperature stability of the AD630 reduce
demodulator drift to a second-order effect.
+15V
1V
400Hz
350⍀ 350⍀
+IN 9 11
A SEL B +VS
350⍀ 350⍀
49.9⍀ AD8221 16 RA AD630AR B C
REF 4.99k⍀ 4.99k⍀ 4.99k⍀
17 RINB VOUT 13
–IN 2F 2F 2F
19 CH B–
COMP 12
20 CH A–
–15V
REV. E –9–
AD630
[ T ]
5V 5V 5s
500s/DIV
B. 200mV/DIV 100
MODULATED SIGNAL (A)
90
(UNATTENUATED)
ATTENUATED SIGNAL
PLUS NOISE (B)
T
3 10
0% OUTPUT
5mV
C. 200mV/DIV
A. 200mV/DIV
–10– REV. E
AD630
OUTLINE DIMENSIONS
20-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP]
(D-20)
Dimensions shown in inches and (millimeters)
20 11
0.300 (7.62)
PIN 1 0.280 (7.11)
1 10
0.320 (8.13)
1.060 (28.92)
0.060 (1.52) 0.300 (7.62)
0.990 (25.15)
0.015 (0.38)
0.200 (5.08)
MAX 0.150
0.200 (5.08) (3.81)
0.125 (3.18) MIN
0.015 (0.38)
0.023 (0.58) 0.100 0.070 (1.78) SEATING
PLANE 0.008 (0.20)
0.014 (0.36) (2.54) 0.030 (0.76)
BSC
0.985 (25.02)
0.965 (24.51)
0.295 (7.49)
0.945 (24.00)
0.285 (7.24)
20 11 0.275 (6.99)
1 10
0.325 (8.26)
0.310 (7.87)
0.180 (4.57) 0.300 (7.62) 0.150 (3.81)
MAX 0.015 (0.38) MIN 0.135 (3.43)
0.120 (3.05)
0.150 (3.81)
0.130 (3.30) 0.015 (0.38)
0.110 (2.79) 0.022 (0.56) 0.100 0.060 (1.52) SEATING
(2.54) 0.050 (1.27) PLANE 0.010 (0.25)
0.018 (0.46) BSC 0.008 (0.20)
0.014 (0.36) 0.045 (1.14)
REV. E –11–
AD630
20-Lead Standard Small Outline Package [SOIC]
Wide Body
(R-20)
Dimensions shown in millimeters and (inches)
13.00 (0.5118)
C00784–0–6/04(E)
12.60 (0.4961)
20 11
7.60 (0.2992)
7.40 (0.2913)
10.65 (0.4193)
1 10
10.00 (0.3937)
8ⴗ
1.27 0.51 (0.0201) SEATING 0.33 (0.0130) 0ⴗ 1.27 (0.0500)
COPLANARITY
0.10
(0.0500) 0.31 (0.0122) PLANE 0.20 (0.0079) 0.40 (0.0157)
BSC
Revision History
Location Page
6/04—Data Sheet changed from REV. D to REV. E.
Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Replaced Figure 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Changes to AC BRIDGE section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Replaced Figure 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Changes to LOCK-IN AMPLIFIER APPLICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
6/01—Data Sheet changed from REV. C to REV. D.
Changes to SPECIFICATION TABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Changes to THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Changes to PIN CONFIGURATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Changes to OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
–12– REV. E