MSPDCoE-Antenna Effect

By
Nirmal Kumar G B

Sankalp Semiconductor Confidential

 Antenna Effect
Antenna Effect
It is an plasma induced gate-oxide damage that can potentially cause yield and reliability problems during
manufacture of MOS integrated circuits.
 Antenna effect occurs during manufacturing process

 Antennae are floating conduction layers without shielding layer of oxide -effects poly and metal layers

 The random discharge of the floating node could permanently damage the transistor

 Modern wafer processing uses Plasma Etch or Dry Etch.

 Several unwanted things happen just because of Plasma Etching and one of them is Charging Damage

 Plasma charging damage refers to the unintended high-field stressing of the gate-oxide in MOS during plasma
processing.
 Both electrons and positive ions from plasma are impinging on the exposed conductor during processing.

 Depending on charge balance condition, the electron flux might

not equal to ion flux and hence a net positive or negative charge
collection rate exists.
 If the length of conductor is so long, the collected net charges are
channeled to the gate where it is neutralized by current tunneling
across gate oxide and this phenomenon is called Antenna Effect.

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mspdcoe@san Question of the week
kalpsemi.com What is plasma? List some advantages and disadvantages of plasma etching.

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 Antenna Ratio and Antenna Effect Example
Classical Definition of Antenna Ratio (AR)
Antenna Ratio is defined as ratio of total area and/or perimeter of conducting layer attached to gate to gate area

Example for Antenna Effect

In the above example, charges are accumulated on poly gate since M1 left floating until M2 is fabricated and there is chance
Contact Us of gate-oxide breakdown if M1 routing length is sufficiently long. A long floating interconnect can act as a temporary
capacitor collecting charges from plasma Etching.
mspdcoe@san
Question of the week
kalpsemi.com
List few measures to reduce Antenna Effect.

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 Methods to Reduce Antenna Effect
Metal Jumpers
 Break signal wires and route to upper metal layers by jumper insertion

 All metal being etched is not connected to a gate until the last metal layer is etched
Fig 1: Metal Jumpers

Dummy transistors
 Addition of extra gates will reduce the capacitance ratio Fig2: Diode Insertion
 PFETs more susceptible than NFETs
Embedded Protection Diode
 Connect reverse biased diodes to the gate of transistor

 During normal circuit operation, the diode does not affect functionality
Diode Insertion after placement and route
 Connected of diodes only to those layers with antenna violations
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 One diode can be used to protect all input ports that are connected to the same output ports
mspdcoe@san
Question of the week
kalpsemi.com
Which type of diode is used to prevent antenna effect?. Why?

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 Comparison of Antenna Effect solutions
Comparison of Proposed solutions

Summary
 PID can have little-no dependence on AR

 Ratio of gate capacitance to the antenna capacitance is a more important PID determinant

 PFETs can be more susceptible to PID than NFETs

Contact Us  Dynamic diode insertion after placement and route is best technique to reduce antenna effect
mspdcoe@san  Modern CAD tools do not incorporate true measure of antenna effect
kalpsemi.com

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