ELECTRONICS AND ELECTRICAL ENGINEERING DEPARTMENT

Logic Circuits and Switching Theory Manual

ACTIVITY 1: SSI Gates Familiarization

(IC Package Pin Configuration. Input and Output Logic Levels of a Gate)

2.1 Program Outcomes (POs) Addressed by the Activity

a. ability to apply knowledge of mathematics and science to solve engineering problems
b. identify, formulate, and solve engineering problems.
c. use techniques, skills, and modern engineering tools necessary for electronics
engineering practice.

2.2 Activity’s Intended Learning Outcomes (AILOs)

At the end of this activity, the student shall be able to:
a. identify the different basic logic gates and their truth table
b. implement a function using logic gates

2.3 Objectives of the Activity

The objectives of this activity are to:
a. identify the input and output terminals of a gate in an IC package.
b. identify the supply terminals of SSI IC.
c. determine the state of input and output terminals of SSI gates using Logic Probe.

2.4 Principle of the Activity

Some TTL circuits as shown in Figure 1. Each IC is enclosed within a 14- or 16-
pin package. A notch placed on the left side of the package is used as reference for the pin
numbers. The pins are numbered along the two sides starting from the notch and continuing
counterclockwise. The inputs and outputs of the gates are connected to the package pins.

The TTL IC’s are distinguished by their numerical designation, e.g., the 5400 and
7400 series. The former has a wide temperature range and is suitable for military use,
while the latter has a narrower temperature range and is suitable for commercial use. The
numerical designation of the 7400 series means that the IC packages are numbered as 7400,
7401, 7402, etc.

The TTL logic family actually consists of several subfamilies or series. Table 1-1.
lists the name of each series and the prefix designation that identifies the IC as being part
of that series. ICs that are part of the standard TTL have an identification number that
starts with 74. Likewise, ICs that are part of the high-speed TTL series have an
identification number that starts with 74H; ICs in the Schottky TTL series starts with 74S;
and similarly, for the other series.

ACTIVITY 1: SSI Gates Familiarization 1

 The differences between the various TTL series are in their electrical
characteristics, e.g., power dissipation, propagation delay, and switching speed. They do
not differ in pin assignment nor on the logic operation performed by the internal circuits.
For example, all the ICs listed in Table 1 with an 86 number, no matter what the prefix,
contain four EXOR gates with the same pin assignment in each package.

Table 1. Various Series of the TTL Logic Family

TTL Series Prefix Example

Standard TTL 74 7486
High-Speed TTL 74H 74H86
Low-Power TTL 74L 74L86
Schottky TTL 74S 74S86
Low-Power Schottky TTL 74LS 74LS86
Advanced Schottky TTL 74AS 74AS86
Advanced Low-Power Schottky TTL 74ALS 74ALS86

2.5 Materials/Equipment

1 Logic Probe 1 Breadboard

1 Power supply 1 Cutter pliers
1 Long nose pliers Connecting wires

Integrated Circuit (IC)

1 74LS00 1 74LS02
1 74LS04 1 74LS08
1 74LS32 1 74LS86

ACTIVITY 1: SSI Gates Familiarization 2

2.6 Circuit Diagrams / Figures

Figure 1. Some typical integrated circuit gates pin configurations

ACTIVITY 1: SSI Gates Familiarization 3

 Figure 2. Experiment Set – up

2.7 Procedure/s

A. Examining Logic Gate IC

1. Examine the ICs supplied to you. The number is printed on the surface of each
IC.
2. Wire the 74LS00 as shown in Figure 2. Set the power supply to 5V and connect
it to your circuit.
3. Using the logic probe, test the status condition or logic level at the input and
output terminals of each gate in the IC. Record the logic values in the
corresponding tables.
4. Remove the IC mounted on the breadboard and replace it with another IC.
5. Repeat step 3 for each of the other IC’s.

ACTIVITY 1: SSI Gates Familiarization 4

2.8 Activity Report

Section: Date Performed:

Course Code: Date Submitted:
Course Title:
Instructor:
Group No.: Activity No.:

Group Members: Signature:

1.
2.
3.
4.
5.

ACTIVITY 1: SSI Gates Familiarization 5

 2.8.1 Data and Results

Table 2. Test Results for 74LS00 IC

Output
Input Terminals
Terminals

Pin No. Logic Indication Pin No. Logic Indication

1 3
2 6
4 8
5 11
9
10
12
13

Table 1. Test Results for 74LS02 IC

Output
Input Terminals
Terminals
Pin No. Logic Indication Pin No. Logic Indication

2 1

3 4

5 10

6 13

11

12

ACTIVITY 1: SSI Gates Familiarization 6

 Table 4. Test results for 74LS04 IC
Output
Input Terminals
Terminals
Pin No. Logic Indication Pin No. Logic Indication

1 2

3 4

5 6

9 8

11 10

13 12

Table 5. Test Results for 74LS08 IC

Output
Input Terminals
Terminals

Pin No. Logic Indication Pin No. Logic Indication

1 3
2 6
4 8
5 11
9
10
12
13

ACTIVITY 1: SSI Gates Familiarization 7

 Table 6. Test Results for 74LS32 IC

Output
Input Terminals
Terminals

Pin No. Logic Indication Pin No. Logic Indication

1 3
2 6
4 8
5 11
9
10
12
13

Table 7. Test Results for 74LS86 IC

Output
Input Terminals
Terminals

Pin No. Logic Indication Pin No. Logic Indication

1 3
2 6
4 8
5 11
9
10
12
13

ACTIVITY 1: SSI Gates Familiarization 8

 2.8.2 Questions

1. What is the logical equivalent of the “hang” input?

2. Identify the following ICs with the same pin configuration.

3. Describe the pin configurations of 74LS02 and 74LS04 ICs.

2.8.3 Observations

2.8.4 Conclusion/s

ACTIVITY 1: SSI Gates Familiarization 9

 2.8.5 Rating (include Rubric)

ACTIVITY 1: SSI Gates Familiarization 10