EMC Design Guidelines For Microcontroler Board Layout

A p pl i c at i o n N ot e, V 3.
3, October 2006
AP24026
Microcontroller
E M C D e s i g n G u i d e l i n e s fo r
M ic r o c o n t r o l l e r B o a r d L a y o u t
Microcontrollers
N e v e r s t o p t h i n k i n g .
Edition 2006-10
Published by
Infineon Technologies AG
81726 München, Germany
© Infineon Technologies AG 2006.
All Rights Reserved.
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AP24026
EMC Design Guidelines
Revision History: 2006-10 V 3.3

Previous Version: 2006-07
Page Subjects (major changes since last revision)
25 Updated example for oscillator GND connection
Controller Area Network (CAN): License of Robert Bosch GmbH
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Application Note 3 V 3.3, 2006-10

AP24026
Table of Contents
Table of Contents Page
1 Overview .......................................................................................................... 5
1.1 Noise sources .................................................................................................. 6
1.2 Coupling paths ............................................................................................... 10
2 PCB considerations ....................................................................................... 13
3 Design measures........................................................................................... 18
3.1 Power supply ................................................................................................. 19
3.1.1 Layout structures ....................................................................................... 21
3.1.1.1 Two-layer boards.................................................................................. 26
3.1.1.2 Multilayer boards .................................................................................. 28
3.1.2 Components............................................................................................... 32
3.1.2.1 Capacitors ............................................................................................ 32
3.1.2.2 Inductors and ferrite beads .................................................................. 42
3.2 Signals ........................................................................................................... 45
3.2.1 Layout structures for two-layer and multilayer boards .............................. 46
3.2.2 Components............................................................................................... 55
3.2.2.1 Resistors............................................................................................... 55
3.2.2.2 EMI filters.............................................................................................. 56
4 Microcontroller special remarks..................................................................... 57
5 Simulations .................................................................................................... 59
6 Formula appendix .......................................................................................... 61
7 Glossary......................................................................................................... 62
8 Literature........................................................................................................ 63

AP24026
Overview
1 Overview
The topic of electromagnetic compatibility (EMC) is important for the functionality and
security of electronic devices. Today’s designers have to deal with permanently
increasing system frequencies, changing power limits, high density layouts by more
complex systems and the steady need of low manufacturing cost. Therefore it is
necessary to look after EMC.
In this EMC design guideline we are concentrating on some rules, examples,
simulations and measurements for printed circuit board (PCB) layout. By using these
rules, it is possible to prevent high electromagnetic emission already through a good
PCB design. This design guide is made for various applications with their different
purpose. Therefore, each application will show different reaction on the realized EMC
design improvements. The rules are faced mainly to the problem of electromagnetic
emission (EME). Due to the fact that an EME-optimized board layout is not so sensitive
to interference, using these rules will also decrease the susceptibility (EMS). This
guideline is structured in order to fit the needs of a PCB designer. Basics, PCB
considerations, design measures, board stack and trace design are followed by
various rules for decoupling.
Electromagnetic compatibility is the quality of a subsystem or circuit to not affect and
become not affected in the system where it is used. It has to be seen that measures to
realize a good EMC-behaviour of an application have to be started and implemented
already into the first steps of development. In other words, EMC measures have to be
considered as a system or circuit specification. Measures and actions taken later on,
at an already manufactured printed-circuit board (PCB), are not as effective and
additionally will lead to higher costs.
Electromagnetic disturbance is the interference to the normal function of an electric
circuit by coupling in an additional voltage. There are various paths to couple into a
circuit and various ways to avoid these interferences.
The EM disturbance countermeasures follow three steps:
The source: This is the place where the noise or disturbance is created. Reason for
this can be e.g. switching noise of a circuit with high current (high di/dt), fast signals,
fast rise time, resonance, antenna structures, wrong termination, reflections and
electric potential differences. Major goal must be the RF noise suppression at the
source.
The coupling path: The path or medium where the disturbance is distributed from the
’source’ to the ’victim’. Goal: the ’coupling path’ has to be made inefficient.
The victim: The electrical circuit which becomes influenced by the disturbance coming
from the ’source’. This disturbance can lead to some imperceptible noise added on a

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Overview
signal. But this disturbance can also have some major impact on the functionality of a
signal or the whole application.
Goal: Low susceptibility to emission at the ’victim’.
At all three steps it is possible to damp or even eliminate the electromagnetic
disturbance by various design measures.
1.1 Noise sources

This is the place where the noise or disturbance is created. There are a lot of sources
which can cause RF noise. The most important sources are microcontrollers, oscillator
circuits, digital ICs, switching regulators, transmitters, ESD and lightning.
Major goal must be the RF noise suppression at the source.
Figure 1 Typical application board and noise source paths
From the sight of the PCB design, the most common radiation is coming from the
supply network due to the switching noise of the core activity and toggling I/O ports of

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Overview
the microcontrollers or other ICs which have driving I/O ports. Generally the driver
outputs are connected to long traces on the board, which are also connected to the
cables. These cables are running to the other system components. The nature of the
traces and cables is very close to the antenna behavior and the radiation of the energy
through these antennas can cause very serious problems. The emission (radiated and
conducted) of the switching noise through the power pins and the connected planes
are a significant portion of the EMC behavior of the microcontrollers. The capacitive
and inductive coupling between adjacent traces can provide a path to distribute the
noise on the board.
Oscillator circuits produce a trapezoid wave which has a fundamental frequency and
harmonics. If a careful placement of the board is not realized, then a coupling to the
nearest components and traces is probable.
In digital systems the radiation behavior of a switching circuit depends on the form of
the digital signal. As it can be seen in figure 2, the emission spectrum is related to the
duty cycle and rise/fall times of the switching signals. The high time determines the
point where the spectrum begins to fall with 20 dB/decade, and rise/fall time gives the
second point where it begins to fall with 40 dB/decade.
Figure 2 Spectrum of a trapezoidal signal

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Overview
Figure 3 shows calculation results which depict the spectrum of a periodic pulse for
different pulse widths and clarifies the relationship between pulse width and resulting
spectrum. The magnitude in spectrum increases as the pulse width increases.
Figure 3 Relation of spectrum and pulse width

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Overview
Figure 3 Relation of spectrum and pulse width (continued)
For the high speed design of PCBs, it is important to decide how to handle the traces if
they carry high speed signals and under which circumstances the line length is critical.
Generally we can say, if the one half rise/fall time of the signal is smaller than the
propagation delay of the PCB trace, the trace should be treated as transmission line
and should be routed applying additional measures and terminated with its
characteristic impedance (see also Chapter “3.2.1. Layout Structures”).
Next important point is the design of the integrated circuits. Most designs of
microcontrollers are synchronous clock systems, which cause some EMC problems on
the power supply network of the ICs due to the synchronous construction of the logic
circuits. A careful design of the IC´s power supply network is also required.

AP24026
Overview
1.2 Coupling paths

The path or medium where the noise is distributed from the ’source’ to the ’victim’.
The goal is to make ’the coupling path’ inefficient.
The coupling can be effective in two ways: radiated and conducted.
The radiated coupling paths are electromagnetic fields and crosstalk (inductive or
capacitive). The radiation path of the signals less then 30MHz are conducted and for
the signals above the 30MHz the noise will increasingly radiate.
The conducted coupling paths are galvanic coupling, supply network (power &
ground). Interference current and voltage of an electrical system can be described as
common-mode (CM) or differential-mode (DM).
Common-mode interference is an asymmetrical disturbance. It often occurs between
a cable system and its electrical reference potential. Signal and noise current have the
same (a common) direction in the loop. The cables radiate the energy caused by the
ground system noise. The common-mode radiation can be reduced by reducing the
impedance of the ground system.
Figure 4 Common-mode and differential-mode
Differential-mode interference is a symmetrical disturbance which occurs between

two traces or lines. One of these lines can also be the ground path. Signal and noise
current have different directions in the electrical loop. If the loop area of the signal and
return path increases, then the differential-mode radiation is also increasing.
Switching of a signal produces a current transition that goes through the trace,
receiving device and returns over the power system (VDD or VSS) to the transmitting
device. This path forms a current loop.

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Overview
Current loops have significant inductance and can be modeled as a coil of a

transformer. The inductance of the loop depends on the loop size and increases with
it. Usually on a PCB there are many such loops, which interact with each other. As
Figure 5 depicts, if any change occurs in loop current A it induces a proportional
voltage in loop B, because a part of the total flux from loop A goes through the loop B
and induces the voltage v(t). To minimize the inductive coupling between the loops,
the loop inductance has to be reduced. This can be done with reducing the loop size.
Using power planes gives a very low impedance connection possibility for VDD and
VSS power buses.
Due to the fact that the low frequency signals follow the least resistance path and the
high frequency signals follow the least impedance path, the signal return paths have to
be designed so that the loop inductance is as low as possible. In case of the power
plane design, the power plane must show no break or discontinuity in the signal return
path, so that least impedance path can be used.
I(t)
Loop A
Loop B V(t)
Figure 5 Interaction of two loops
Crosstalk is the coupling between two adjacent traces. The crosstalk effectiveness
depends on two parameters: capacitance and inductance between adjacent traces.
In case of the inductive crosstalk, both of the traces form a loop which acts like two
windings of a transformer. The loops are the traces on the PCB with their signal and
return paths. The distance and loop area determine the crosstalk. To reduce the
inductive crosstalk the loop area should be reduced.
The circuit in Figure 6 shows two adjacent traces, one trace acting as source and one
trace acting as receiver. Because of the capacitance between the lines, the noise

AP24026
Overview
generated by the source can couple to the other trace. The noise generates a current
which is coupled through the capacitance to the next signal line.
The dV/dt of a signal source produces a current depending on the coupling
capacitance between the two traces.
dV
I =C
dt
The di/dt of a signal source produces a voltage depending on the mutual inductance
between the two loops.
di
V =L
dt
The capacitive crosstalk can be reduced by separating the traces/loops. More distance
between traces leads to less crosstalk. But in many applications the PCB area is
limited so that a separation of the traces is not always possible. In this case the
placement of a guard trace between the traces can help. The guard trace can be an
approach for two-layer boards, but for multilayer boards the benefit is not so high
because in most cases a solid ground plane is designed. The most effective measure
is the proper termination of the signal lines.
Signal Source
Trace
Loop 1
C coupling
L coupling
Trace
Loop 1
Figure 6 Capacitive and inductive coupling

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PCB considerations
2 PCB considerations
A good EMC-optimized PCB design includes three design stages: component
selection/placement, design of the grounding concept (power supply system) and
decoupling concept. Before the placement, the critical paths and circuits have to be
identified, so that a functional grouping can be made. The analog circuits should be
isolated from the source of noisy signals. High-speed ground and analog ground must
be sparated from each other. The ground areas of different circuits should not overlap.
For reason of EMS and signal integrity, external logic with high input threshold (Vih)
should be chosen. E.g. prefer HC (High Speed CMOS) or AC (Advanced CMOS)
standard ICs due to higher Vih. Select optimum (i.e. not unnecessarily fast) rise-/fall
times to decrease di/dt noise. Use the criterion of low cross-currents for the selection
of other ICs.
Supply voltage
When a higher supply voltage is used, more power is inside the electrical system. This
implies that a higher voltage fluctuation happens and therefore a higher emission will
be created. Consequently, to minimize electromagnetic emission, use the lowest
possible supply voltage. If susceptibility is a matter of concern, the supply voltage
should not be too low. A low voltage level implies a small signal-to-noise ratio.
Oscillator
Use lowest speed for oscillator and crystal. Adjust to the demands of the application
hardware and software. Use PLL for higher frequencies. An isolated ground plane
under the oscillator circuit can be used to reduce the propagation of the clock noise to
the board. This ground isle should be connected (high impedant) at one point to the
board ground. For details please refer to Figure 18 on page 25.
Attaching cables to a PCB
Group connectors by function. E.g. separate analog signals from high speed signals.
Provide decoupling measures (capacitors, ferrites, optical systems, etc.). Note: Do not
let any noise go from the PCB on the cables since this increases emission
dramatically. Do not let any noise go from the cables to the PCB since this may cause
functional instabilities.
Provide enough GND pins for a cable transferring critical signals. Avoid cables if
possible. If they are necessary, make them as short as possible. Fix them so they will
not move - otherwise their EMC behaviour is unpredictable.
Twist power or signal cables with the corresponding GND cable. Thus, the flow of
current and the back current will be close together. Both electromagnetic fields will
compensate each other.

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PCB considerations
Two-layer / multilayer boards

Multilayer boards provide many advantages compared to two-layer boards with respect
to EMC behavior. But in some cases two layer boards are prefered because of their
low cost. Multilayer boards cost more then two-layer boards.
With multilayer boards it is possible to design low impedance power supply and ground
connections using power/gnd planes, which cover at least one layer or a part of one
layer. Realizing EMC-related measures is easier with a multilayer board than with a
two-layer board.
Traces
In high-speed designs the reference (ground) for the traces is very important. The
design of a trace can affect the emission and/or signal integrity behavior of the trace.
Two types of traces can be used: microstrip and stripline (more information in 3.2.1.
layout structures, Figure 43). The stripline has the reference plane on both sides which
results in lower impedance than for the microstrip.
To avoid EMC disturbances of adjacent traces, try to keep the distance between
sensitive traces as big as possible. For high speed signals even guard traces might be
necessary. This means that between two signal traces a ground trace should be
designed.
In general, sensitive traces should not be designed in parallel to high speed or noisy
traces. If you cannot avoid such a design, make the parallel paths as short as possible.
Vias
For reason of EMC it can be of advantage to use different kinds of vias on a high
speed signal application.
Microvias: They have a hole diameter of about 100µm and can be designed into the
pads of discrete components. Because of the small diameter much space can be
saved on the PCB and therefore the power plane structures are not cut as much as by
bigger vias. For same reasons, multiple microvias can be designed instead of one big
via. That lowers the inductance of the connection since they behave like inductors in
parallel.
Buried vias: This kind of via can be used at a multilayer design. They are connecting
some signals or power traces at the inner layers of the PCB (e.g. from the 3th to the 4th
layer). They are not drilled from top to bottom layer but just through the inner layers.
With buried vias, some layers of a multilayer board can be made high-frequency
sealed, while not cutting the outer planes. In addition to that, area for trace design can
be saved.

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PCB considerations
Blind vias: They are drilled from an outer layer to one of the inner layers. Because of
that, not all layers of a PCB are cut for a signal or power trace connection with the first
or last few layers. Blind vias are most efficient if used in combination with buried vias.
High impedance traces

By using traces with higher impedance (smaller or narrower traces), disturbances can
be kept locally, e.g. traces to the voltage regulator.
Figure 7 High impedance traces
Package
For packages of BGA (ball grid array) type, most Vss pins are grouped in the center of
the microcontroller. In general the corresponding Vdd pins are located on the inner row
of the outer circle. This pinning allows a short connection to the decoupling capacitors
(decaps) when placed on the opposite side of the PCB. For lead-frame packages, the
decaps must be placed between VDD and GND pins. The connection to the supply
and ground planes or traces has to be made by vias placed on the “outer” side of the
capacitor, see Figure 8.

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PCB considerations
VDD Via VCC
VSS Via GND
CAP
Figure 8 Decoupling of a typical BGA (left) and lead-frame (right) package
PCB material
The dielectric permittivity r is an important parameter for calculating the wave
impedance of a trace or a plane. For the PCB material this constant, at the frequency
of 1 MHz, can be provided from the board manufacturer. For fast signals it has to be
considered that the dielectric permittivity is frequency dependent. Example: FR4
material has an r of 4.7 at 1 kHz, 4.5 at 1 MHz and 4.35 at 16 MHz.
In high-speed systems above 4GHz it is recommended to use other materials than
FR4. This can be Teflon or BT-material.
The impact of the dielectric permittivity r on the PCB impedance is shown by a
simulation with different r boards ( r = 4, 10, 100). For the simulation a board with
10x10 cm² dimensions and a PCB thickness of 20mil was used. Figure 9 shows that
with increasing r value, the impedance of the board gets lower. The resonance
frequency is shifted towards higher frequencies with lower r values.

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PCB considerations
Figure 9 Impedance of PCB for different r

values

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Design measures
3 Design measures
The following guidelines are recommended, however each measure described here
must be evaluated for each application. The realization of all measures can be very
difficult, particularly in complex applications, so that a trade off has to be made.
For more complex structures it is not possible to determine general design rules.
These structures have to be investigated and optimized using SPICE simulation in
conjunction with 2D- or 3D-field solvers.
General design recommandations :
• Define functional units. Classify also by speed: analog / sensor, digital low speed,
digital high speed, power elements. Place all components operated with the same
clock together.
• Keep elements of same functional unit in close distance to keep critical signal traces
as short as possible. Provide enough space for decoupling capacitors close to the
IC and spread them over the whole PCB.
• High speed traces should be placed near the center of the board far from the edge
of the board.
• Keep the lead length of the decoupling capacitors as short as possible and locate
the capacitors as close as possible to the VDD/VSS pins of the component.
• Consider the usage of special “low-inductance” capacitors.
• Before beginning the routing, identify critical signals according to highest carried
frequency and shortest rise/fall time of the signal.
• Place high current carrying lines as close as possible to the voltage regulator´s
output.
• Provide connections for series resistors within high speed traces close to the driver.
Take care that the signal timing does still meet the specification.
• Place oscillators adjacent to the clock driver. If an asymmetrical board stack design
is used, place the crystal oscillator on the side of the PCB which has the largest
distance from the reference ground layer. This can prevent a direct coupling from
the crystal oscillator package into the ground system of the PCB. To reduce the
radiation / coupling from oscillator circuit, a separated ground isle on the GND layer
should be made. Please refer to Figure 18 on page 25.
• For two layer boards: Keep a minimum distance between functional units by
geometry – see Figures 19 and 20.
• Separate parallel running traces by not less than 2x trace width.
• Changing of layers affects also the impedance, which causes reflections at these
points.
• Remove 20*H of metal from the edges of the VCC supply plane to reduce edge
radiation. H is board layer height or thickness (see Figure 10).
• Place I/O connectors carrying external signals on one edge of the PCB.
• Prefer manual routing to the auto router of the layout tools for critical signals.

AP24026
Design measures
• Do not place the connectors close to high speed circuits.

• Place crystals, oscillators and clock generators away from I/O ports and board
edges.
VCC Metal
20*H
4 Layer PCB H : Height of PCB
PCB edge
Figure 10 Removing metal of power plane from the edge of PCB (20*H rule)
3.1 Power supply

In the first step of the PCB layout, the power supply system should be designed. A
proper power bus and grounding design is the basic requirement for voltage stability
and reduced electromagnetic emission. Decide for the PCB technology: two-layer or
multilayer board. For the multilayer boards a proper stack-up of the PCB should be
designed (See also part 3.1.1.2.: Multilayer Boards).
Note: Concerning EMC, a good design of a two-layer board is more difficult to realize
than a four or more layer board. A trade-off between lower cost of a two-layer board
plus additional filter components and the higher cost of a multilayer board without
additional filter components should be done carefully.
Depending on the chosen PCB technology, different grounding systems can be used.
For the power systems, the mostly used distribution method is single or star
connection type (see also 3.1.1.1.: Two-Layer Boards). But in high speed systems the
star grounding is not the best solution. Because of the high frequency path of the
noise, an increase in radiation can result.
In case of multilayer PCB, the use of power layers is a good solution. Covering one
layer with metal provides much less impedance for the connection to the decoupling
components.

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Design measures
Voltage regulator: canalizing the RF current

Energy which is transformed to heat or canalized otherwise cannot radiate anymore.
See an example to position capacitors to isolate and disturb reflected (high frequency)
energy. In fact, the high frequency current is created inside the IC. By using block
capacitors, this RF energy will not leave the circuit via this supply line. But be aware
that energy can couple out via other paths which are connected to the µC.
Figure 11 Flow of the canalized energy
Separate the digital from the analog supply system. Use at the output of the voltage
regulator decoupling capacitors and inductors to reduce the noise propagated over the
powerlines. For the decoupling at the supply level, tantalum capacitors are prefered.
Since supply systems themselves have a parallel resonance frequency, it has to be
considered to shift this resonance out of the range of critical frequencies. This can be
done by shortening the length of the supply trace. Since board geometries are given
from the application functionality, it is not always possible. In this case a capacitor in
the range of 100nF can be implemented into the current path. This has the effect of
shifting the electrical length of the system with the resulting parallel resonance
frequency getting higher.

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Design measures
Vregulator Vcore
Vsupply
Voltage µC
Regulator
C1 C2 C3 C.. Cx-1 Cx
GND
Figure 12 Decoupling of the power circuit
3.1.1 Layout structures

Keep power and ground nets which belong to each other close together in order to
reduce impedance. The GND trace should be as close to the VDD trace as possible.
Best choice is to design them in parallel. If the current and its corresponding ground
trace have to go different ways, there will be different potentials and common mode
problems. Figure 13 shows GND-trace and VDD-trace on different sides of the PCB.
µC µC
PCB PCB
VDD Trace VDD Trace
GND Trace GND Trace
Connector Connector
Wrong design of current return path Better design of return current path
Figure 13 Design of ground traces

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Design measures
In general, power and ground traces should lead directly from the supply connector to
each component / functional unit. If possible, use one side as a complete ground plane
for an optimized current flow. Ground area fills have to be handled with care.
Otherwise the emission may increase because of resonance structures and antenna
effects. Connect them by several vias or wide traces to the reference ground of the
board. Since there are various effects which influence the radiation and susceptibility
of the PCB, each application has to be handled individually.
Signal currents use both power plane and ground plane as return paths. Keep supply
planes as “clean” as possible: Avoid areas of high impedance (groups of vias, gaps).
Avoid segments in the ground planes. This measure keeps the current return path
short. The supply planes should also be as small as possible to reduce the coupling
and radiation of the noise to the power system and it should use enough area to
deliver power to all components which are connected to the power system.
Example for placements of vias are shown in Figure 14. In the upper-left case the
return current is forced to flow around the group of vias. In the upper-right case the
current can flow nearly directly from one side to the other. The best solution for a
current return path is shown in the lower-left configuration.
Figure 14 No Blocking of Current Return Path
In some cases, splitting power or ground planes can cause a big improvement in the
EMC behaviour and for signal integrity. This splitting has to be done under several

AP24026
Design measures
considerations of the signal and current flow. A separation of very sensitive parts from
noisy areas of a PCB keeps the disturbance low and minimizes the possibility of
galvanic coupling. If the VDD plane is to be divided into segments, provide one area
for every functional unit. These zones should be still connected together if they have
the same power supply. That influences the way and the impedance of the current
flow. For the ground plane a path with low impedance has to be guaranteed. The
separated zones should be connected together again at a common supply starpoint,
which should be close to the power supply connector or voltage regulator on the PCB.
A functional unit can contain all RF-components, all analog components, etc. Another
way of building functional units is to distinguish them by supply voltage (5.0V, 2.5V,
etc.).
Figure 15 Example: Segmentation of the supply plane with voltage regulator

as common ’supply star-point’.
Resonances of the board structures influence the EMC behavior in a direct way. If the
harmonics of the work frequencies have the same frequency as the parallel
resonances, a significantly high amplitude may be produced. These harmonics can
then couple to the other supply paths and traces. The board structures should be
selected so that no parallel resonances are in the interested range. As it can be seen
in the simulation results in Figure 17, the smaller the board structures are, the higher is
the resonance. These parallel resonance frequencies can be seen on the emission
spectra and can be critical for signal integrity.

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Design measures
Since board resonance is mainly caused between two planes, one option is to realize
the VDD power by traces (i.e. power star-point, separate traces for different board
sections, distance to ground plane).
Traces have a higher impedance compared to a plane structure. Using VDD traces,
local disturbances on the PCB can be prevented from spreading over the whole board.
To provide the necessary current potential for switching operations, locally decoupled
’power islands’ should be realised directly underneath the microcontroller and logic
devices. From these islands the noise has a path of high impedance to other devices
and will be kept locally.
Figure 16 Example: Using VDD islands and traces over ground plane.
The capacitance and inductance of the planes cause a high frequency resonance,
depending on their values.
In some high-speed applications, the power plane capacitance can be used as a
distributed capacitance to reach an attenuation of the total impedance of the power
network on the PCB in high frequency range. In this case it is important to calculate
the impedance and determine the dimension of the power plane to reach an adequate
decoupling effect. The capacitance of a plane structure depends on the board
thickness, dimensions and dielectric permittivity of the board.

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Design measures
Figure 17 shows the change of the power plane impedance if the thickness of the
board varies, and the change of the board impedance if the dimensions of the power
plane vary.
The first board resonance shifts to higher frequencies if the plane area gets smaller.
Figure 17 Impedance for different board thickness and plane dimensions
In some cases the grounds should be separated to reduce propagation of noise. This
is possible only in low speed systems. In high speed systems care should be taken

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Design measures
because a cut in the ground plane may affect the high frequency noise path. High
frequency signals require a homogenous ground reference.
Figure 18 gives an example of a local oscillator ground island which is carved out of
the global ground plane. The oscillator current loop formed between the external
oscillator components (crystal, capacitors) and the oscillator VSS pin VSSosc at the
microcontroller must not contain any contact to the global ground plane. The global
ground plane should be connected on the opposite side of the VSSosc pin. Take also
care that the two load capacitors are placed between the microcontroller’s oscillator
pins and the crystal.
GND Plane
Separated GND Crystal

island on toplayer
(carved out from Load capacitors
global GND layer)
Vias to GND island

XTALin/out VSSosc
Via to global
GND layer µC
Figure 18 Layout example for crystal oscillator circuit
3.1.1.1 Two-layer boards

Each component should have its own power/ground system. It is not easy to realize
this in two layer boards. Generally there are two concepts to design a power
distribution on two layer boards (see Figure 19).
The power connections over the whole board can be designed as a star connection.
The distribution of the power to each component can be routed from the regulator
output by traces. A power island can be placed at the regulator output to realize the
star point. It is also important that all supply traces have ground as their reference.

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Digital
Analog High speed

Circuits
Power Supply &

GND Star Point
Supply input for board
Figure 19 Power / ground distribution example with star connection system
Another good solution for the power network in two-layer boards is to build a grid
system (see example in Figure 20) with ground and supply nets. The ground and
supply nets are routed over the whole board on each layer. The traces of each power
system (GND/VDD) on each layer are connected by vias. With this grid it is possible to
provide a low-impedance connection of the power system to each location on the
board. Generally, traces on the toplayer of the board are routed in vertical and on
bottom layer in horizontal direction so that it will be easy to realize the grid system. But
this solution requires a trade-off with signal traces changing layers which causes
impedance changes of the traces.
GND VDD
Figure 20 Example for the grid power system on the PCB shown in Figure 19

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3.1.1.2 Multilayer boards

For the design of a multilayer board, the selection of the construction plan is very
important. This construction plan, called stack-up, can be built with the technological
data of the manufacturer. It depends on the requirements of the high speed design.
Following some samples of 4-layer and 6-layer board stack-ups are shown.
Figure 21 Stack-up examples for four / six layer PCBs
Design at least one power/ground layer pair. Realize power and ground planes on
adjacent layers. The smaller the distance between power and ground layer, the lower
becomes the impedance of the power supply. The target distance between the layers
can be reached with substrates and prepregs of different thickness.

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Design measures
Use the shielding effects of supply planes to reduce electromagnetic emission. If you
have more than four layers, you may route a signal layer for critical traces between two
continuous ground/power layers. This provides a good current return path which is not
interfering with other signals. It is also effective as a shield against radiation to the
outside of the PCB. If there is enough space, implement more extra ground planes in
your layer stack, so that each signal layer has its own corresponding ground layer.
Having an extra ground plane for a signal layer makes it possible to keep the
determined characteristic wave impedance.
Different stack-ups for the VDD and GND layers can also be considered for an EMC-
optimized board design. The simulation results in Figure 22 show a comparison of the
effect of three different stack-ups, where in the first case the signal layer is placed
between the VDD/GND layers, in the second case the signal layer is placed on
toplayer and in the third case the signal layer is placed between two GND layers. The
resulting currents flowing through the decoupling capacitor are displayed in Figure 23.
The stack-ups with the signal layer embedded between the GND/GND or VDD/GND
layers deliver best results. But it must also be taken into account that an increased
distance between the VDD and GND layers decreases the plane capacitance of the
board. The plane capacitance supports the decoupling effect of the board at high
frequencies.
Placing noisy signals like clock traces between two ground layers can avoid a lot of
radiation problems.
OUT IN
OUT IN OUT IN
Cde
VDD SIG VDD
SIG VDD GND
Cde Cde
VOID GND SIG
GND VOID GND

Stack - up 1 Stack - up 2 Stack - up 3
Via Signal Trace In/Out Buffer
Figure 22 Different stack-ups for reference plane

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Figure 23 Currents through decap for different stack-ups
It is also important to select the right layer for critical signals. Designing critical signals
as stripline can reduce the switching noise on the power network VDD. Figure 24
shows a comparison of noise levels on VDD in case of different layer routing of a
signal trace (stripline vs. microstrip). The advantage of a stripline layout can be seen
clearly up to 500 MHz. For the construction of stripline and microstrip configurations
see Figure 43.

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VDD Spectrum Envelope Curves for Different Board Stackups,

16,7MHz and 150MHz Noise Sources
1.00E+00
8.00E-01
Normalized Amplitude
6.00E-01
4.00E-01
2.00E-01
0.00E+00
0.00E+00 5.00E+08 1.00E+09 1.50E+09 2.00E+09 2.50E+09 3.00E+09
Frequency [Hz]
NONE-GND-SIG-PWR PWR-GND-SIG-GND NONE-GND-PWR-SIG PWR-GND-GND-SIG
Figure 24 Noise level on power network with different stack-up

configurations for the signal line.
The connection of the decoupling capacitors is important in the high frequency range.
While the connection on two-layer PCBs are made with traces, on multilayer PCBs the
connection can be made through vias directly to the power/ground layers. Depending
on the length and width of the traces, the parasitic inductance takes effect on the
impedance and also on the decoupling efficiency. A comparison between the via and
trace connection of a decoupling capacitor shows that a via connection has lower
impedance above 400 MHz. Additionally it can be seen that the trace thickness plays
also a role as the impedance decreases with increasing trace thickness.

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Design measures
Figure 25 Impedance comparison of different connection types (via

connection vs. trace connection of decoupling caps)
3.1.2 Components
Passive components are used to reduce the electromagnetic emission in circuits. For
the optimum usage of these components, their behavior has to be understood.
3.1.2.1 Capacitors
Capacitors are used to deliver required energy locally while circuits are switching. They
reduce the power supply radiation loops.
There are two types of common capacitors: aluminum/tantalum and ceramic
capacitors.
• Aluminum / tantalum capacitors: They are used mainly for bulk decoupling at supply
lines. The capacitance value decreases with increasing frequency. But
tantalum/aluminum capacitors have a very stable temperature and bias behavior.
For the applications where high values are required, tantalum capacitors should be
preferred.
• Ceramic capacitors: Due to their low ESR they are preferred for the decoupling at
ICs. They are more stable in the high frequency range. For filtering both tantalum
and ceramic work well. The impedance at interesting frequencies is very important
for the decision of capacitor type and value.

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Figure 26 shows the equivalent RF circuit of a capacitor: Besides the pure capacitance
there is an equivalent series inductance ESL and an equivalent series resistance ESR
as parasitics of the capacitor.
Figure 26 Equivalent circuit of capacitor (simplified manufacturer model)
A capacitor shows capacitive behaviour in the lower frequency range; for frequencies
higher than the series resonance frequency its behavior becomes inductive. Optimum
decoupling effect is found at series resonance frequency. This information should be
available in capacitor data sheets. Figure 27 shows the impedance curves of different
capacitor values (1nF, 10nF, 100nF, 470nF). One impedance curve in Figure 27
shows the effect of the parallel connection of two capacitors. A positive resonance
(increasing of the impedance at 100 MHz) occurs due to the resonance of inductance
of the 100nF and capacitance of the 1nF capacitor. Between the resonance peaks of
each capacitor, there is an increase in impedance. This is caused by the L of the
100nF and the C of the 1nF capacitor. The 100nF is inductive in this range and the
1nF is still capacitive, so that a resonance is formed. The parallel combination of these
parameters forms a parallel resonance which inreases the impedance. To avoid or
reduce this effect, connect capacitors in parallel with one or two decades value
difference.
For the supply lines, the main target is to reach an impedance as low as possible in a
wide frequency range. The lower the impedance of the supply system, the higher is the
ability of the system to respond to switching current demands. A low impedance supply
system can deliver this high frequency current and prevent the RF energy from

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Design measures
propagating elsewhere. With the parallel connection of capacitors, the impedance can
be reduced in a wide frequency range. But one important rule has to be obeyed: the
parallel connected capacitors should have value differences of at least factor 10 (e.g.
100nF and 10nF parallel connection) to prevent higher peaks on the impedance curve
due to the parallel resonance.
Capacitor impedance
1000.00 Ohms
100.00 Ohms
Parallel Resonance
10.00 Ohms
1.00 Ohms
0.10 Ohms
Serial/Self Resonance
0.01 Ohms
1 MHz 10 MHz 100 MHz 1000 MHz
1nF 10nF 100nF 470nF 100nF + 1nF
Figure 27 Impedance characteristics of different capacitors
Selection of decoupling capacitors

For the selection of decoupling capacitors, the working frequencies of the application
have to be taken into account. The self resonance frequency of the capacitor must be
in the range of the clock or working frequency of the application. The total decoupling
concept has to cover some harmonics of the fundamental frequency. The self
resonance frequency can be calculated by the equation:
1
Xc =
2πfC
Where: Xc = capacitance reactance, f = frequency, C = capacitance value

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Design measures
Take care of additional resonance frequencies caused by decoupling. Figure 28 shows

an equivalent circuit of a decoupled power bus which consists of the capacity of the
planes Cboard on one side, on the other side there is the equivalent circuit of the
decoupling capacitor. This structure is an oscillator with certain resonance frequencies.
If one decoupling C is used, then there is just one resonance frequency. In case you
use two or more values of capacitors, check for additional resonance frequencies.
Figure 28 Additional resonance frequencies
Using surface mounted device (SMD) capacitors reduces additional lead inductance.
The inductance causes the increase of the impedance curve. To get an optimum
decoupling effect, the total inductance along the connection path of decoupling
capacitors has to be minimized.

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Design measures
Capacitive Inductive
Z
Leadinductance +
Traceinductance
Leadinductance +
Traceinductance
VDD
IC Parasitics of
capacitance Parasitics of
capacitance
GND
Figure 29 Effect of the inductance on impedance characteristics
Figure 30 clarifies the effect of lead inductance. The effect is mainly visible in high
frequency range. This means that the decoupling is less effective in high frequencies
with increasing inductance along the decoupling path.
Capacitor Type 0805 vs. 0508
100.000
10.000
0805
1.000
Z [Ohm]
0508
0.100
0.010
0.001
1.00E+05 1.00E+06 1.00E+07 1.00E+08 1.00E+09 1.00E+10
Freq [Hz]
Figure 30 Low ESL package 0508 vs. standard package 0805

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Design measures
The low ESL type of capacitors (Figure 30) have optimized packages with a reduced
inductance value and provide further inductance reduction.
The development of new technologies allow to manufacture also high value multilayer
ceramic capacitors which have values up to 10 ~ 22µF. Using these capacitors, lower
impedance values can be reached and the total decoupling capacitor count can be
reduced, thus saving cost. But as it can be seen in Figure 31, the capacitors are only
effective up to ca. 100 MHz.
Comparison of different Decoupling capacitor values

(16-bit microcontroller, 8MHz CPU Frequency)
60
A
50
40
D
dBµV
30
C
E
B F
20
10
0
0MHz 50MHz 100MHz 150MHz 200MHz 250MHz 300MHz 350MHz 400MHz
Frequency
A=No Decaps B=22µF C=10µF D=1µF E=3X100nF F=4X100nF
Figure 31 Comparison of different high value decoupling capacitors
In general, the suggested value for ceramic capacitors to decouple the power pins of
the microcontroller is in the range from 10nF to 100nF. Capacitors have a limited
frequency response, which prevents them from delivering power at higher frequencies.
Therefore other values of capacitors have to be chosen if special frequencies are
critical. For global decoupling of the power system, single capacitors in the value range
of 10nF up to 100nF are typical. It is efficient to place different values in parallel (while
considering the antiresonance on impedance). Decoupling at the connectors and the
power supply star point (e.g. voltage regulator) should be realized with additional
tantalum-electrolyte capacitors.

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Design measures
Beside the capacitive effect of the ground plane under the microcontroller, the fast
current has to be delivered from the discrete decoupling capacitors. Decide for pin-
decoupling or/and global decoupling strategies.
Layout measures for decoupling capacitors:
By pin-decoupling each pair of VDD-GND pads is first contacted to the capacitor(s)
and then to the supply layers/nets. Advantage: Optimised decoupling for every pin
possible. Disadvantage: High number of capacitors required.
Figure 32 Placement of blocking capacitor
Place the capacitor pads as close as possible to the microcontroller’s VDD/GND pins.
First contact the capacitor, then contact the vias to GND and VDD plane (see figure
32). The connection from the decoupling capacitor to the ground plane can also be
realized by several microvias inside the outline of the capacitor pad. This guarantees a
low impedance and low inductive connection to ground.
If possible, keep the decoupling capacitors on the same side as the microcontroller.
Remember that vias cause additional inductance. Design traces between pads and
capacitor as wide as possible.
If you have to place the capacitors on the bottom side of the board, provide two or
more vias in parallel to reduce the connection inductance and think about using
microvias if possible. Keep GND-vias and VDD-vias as closely together as possible.
Figure 33 shows four different connection types of decoupling capacitors to the
VDD/VSS planes. The impedance curves of the connection types show a reduction of
the impedance if two vias are connected in parallel and further reduction in case of
placing the vias directly on the capacitor pads.

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Design measures
One via to trace
Two vias to trace
One via directly
Two vias directly
Figure 33 Impedance change caused by different types of decap connections
By global decoupling each pair of VDD-GND pads is first contacted to the supply
layers. The capacitors are placed around the microcontroller, directly contacted to the
supply plane. Advantage: Lower number of capacitors required since some VDD-GND
pairs can share one capacitor. Disadvantage: larger current loops compared to pin-
decoupling.

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Design measures
Figure 34 Global decoupling on multilayer PCB
• Provide at least half as many capacitors of the same value as there are
supply pairs at your microcontroller.
• Avoid long traces between µC pads and vias to supply plane (additional
inductance).
• Provide two vias in parallel if possible.
• Keep GND-vias and VDD-vias as closely together as possible.
Note: Global decoupling cannot be used on two layer boards since there exist no
power supply planes for VDD and GND.
The best decoupling concept is a combination of local and global decoupling. This will
imply additional cost for discrete components, but can save much development time
and redesign activities for critical applications.

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Design measures
Calculation of decoupling capacitor values

To determine the requirements of optimum decoupling capacitors, the capacitive and
inductive values must be calculated. The capacitive value has to be large enough to
support local switching current and the inductive value has to be small enough to get
low impedance paths to the capacitors.
The steps of calculation of decoupling capacitors:
1. Determine the tolerable noise level on the power supply.

Example: V = 5% Æ V= ±125mV for VDD=5V
2. Average current at application: I

Determine the maximum impedance:
∆V
Z=
∆I
3. On board required minimum capacitance:
1
C =
2 π F tran Z
Ftran ~ 1Mhz (up to this frequency the current changes will be delivered from the
voltage regulator)
4. Calculation of maximum board inductance for the power supply connection to the
capacitors:
1
Ftran , max =
2πC on Z
Ftran,max = highest frequency where the on-chip capacitance is still effective
Con = on-chip capacitance (from specification of chip or from manufacturer)
1
Lmax =
2πFtran , max
Lmax = maximum inductance on supply connection path (trace + via + package)

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3.1.2.2 Inductors and ferrite beads

The next important components for lower electromagnetic emission are inductors and
ferrite beads. If the current produced by the microcontroller cannot be supplied from
the decoupling loop, the noise will couple to the power supply lines. The ferrite
prevents the noise from spreading out over the power supply line. Even though the
ferrite beads were not so popular in the past because of area requirement on board
and cost issues, with new technologies it is possible to manufacture multilayer ferrite
chip beads, which have very good impedance characteristics. They are available in
standard SMD packages.
As shown in Figure 35, the equivalent circuit of the ferrite contains some parasitics and
builds a parallel resonance.
Freq [Hz]
1.00E+05 1.00E+06 1.00E+07 1.00E+08 1.00E+09 1.00E+10

IMPEDANCE [Ohm]
Figure 35 Typical impedance characteristics of an inductor

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Design measures
The ferrites have to be placed on the supply line, see Figure 36. The current
consumption of the supply path must also be considered with the selection of the
ferrite beads. A high current ferrite bead can cause a voltage drop on the supply line.
The noise suppression mechanism is shown in Figure 37. The decoupling capacitor
has a series resonance in lower frequency range and the ferrite has a parallel
resonance in higher frequency range. The total frequency behavior of the circuit (seen
from the IC side) is drawn in the diagram on the right side.
Figure 36 Placement of ferrite beads
1000
100
Switching Noise
IC 10
1
1 10 100 1000
Figure 37 Total impedance of the noise filter circuit with capacitor and chip
ferrite bead.
Some measurement results of a 16-bit microcontroller are shown in Figure 38 with a

ferrite in the supply line (no decaps used). The ferrite blocks the noise on regulator
side but the noise on IC side (red curve) is as much as without ferrite (blue curve).
The maximum improvement of the ferrite on regulator side (green curve) ist about
30dBµV.

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Design measures
Ferrite Placed on Supply (No Decaps)
80
70
60
50
dBµV
40
30
20
10
0
0MHz 100MHz 200MHz 300MHz 400MHz 500MHz 600MHz 700MHz 800MHz 900MHz
Frequency
No Ferrite Ferrite 1608HW241 (Flat)—Measured at Regulator Ferrite 1608HW241 (Flat)—Measured at µC
Figure 38 Measurement with ferrite on different points on board (no decaps)
Figure 39 shows the same measurements with additional use of decoupling capacitors.
The additional emission reduction by the capacitors delivers an emission level on
regulator side below 10 dBµV.
Ferrite Placed on Supply (500nF decoupling capacitors)
80
70
60
50
dBµV
40
30
20
10
0
0MHz 100MHz 200MHz 300MHz 400MHz 500MHz 600MHz 700MHz 800MHz 900MHz
Frequency
No decaps Ferrite 1608HW241—Measured at µC Ferrite 1608HW241—Measured at Regulator
Figure 39 Measurement with ferrite beads on different points on board (with

500nF decoupling capacitors)

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Design measures
3.2 Signals
Before routing, determine critical nets by their rise and fall times, and driver strength.
The shorter the rise and fall times are, the more high-frequency components are
contained in the spectrum. The higher the signal frequency becomes, the higher the
corresponding harmonic frequencies – multiples of the base frequency – are.
Figure 40 shows the spectra of signals with different rise times (worst case setting)
Figure 40 Effect of Rise Time on the Spectrum
Typical critical nets (if available):

Most critical signals in single chip applications are: Clock out, SSC (Synchronous
Serial Channel), MLI, MSC.
Most critical signals in other applications are: Clock out, ALE, Read, Data bus, Address
bus, SSC (Synchronous Serial Channel), MLI, MSC.

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Design measures
3.2.1 Layout structures for two-layer and multilayer boards

During the routing some important rules have to be considered:
• Avoid to put traces with high speed signals along edges of a PCB. Disturbances can
be coupled easily into a metal case/shielding of the application.
• Route high speed signals as short as possible and without vias.
• For high speed signals route traces with a corner angle of 45°.
• Do not place sensitive signals close to traces of high current switching signals.
• Route critical signals with a low impedance trace (wide trace, micro-strip, stripline;
see Figure 43) and if neccesary with guard traces.
A simulation result in Figure 41 shows that the improvement with guard traces is
approximately 10dB.
-10dB
Figure 41 Effect of the guard trace
• Critical signals should be routed away from the signals and traces which lead to the
connectors.
• Very critical signals (Interrupt Request and Reset) should be filtered properly. Any
noise on these signals can cause malfunction of the whole circuit.
• Low frequency signal return path is along lowest resistance. High frequency (i.e.
above 1 MHz) signal return path is along lowest inductance.

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Design measures
Figure 42 Return current of high-speed signals
• If possible, do not design any signal traces across the separation areas. Due to the
slot in the power plane the loop size can be increased. Especially, avoid high speed
nets leading from one zone over to the other one. Design short traces.
• To limit crosstalk (XTalk): Determine a maximum overshoot on crosstalk. Determine
a minimum distance / maximum parallel length between high speed nets in order to
minimize crosstalk. Use simulation tools for this estimation.
• To ensure signal integrity (SI) and radiation: Take care of the characteristic wave
impedance of traces when using more than one layer. The possible types of signal
lines are microstrip and stripline (see Figure 43). A microstrip can be designed when
the trace is routed over a ground plane and a stripline can be designed when the
trace is placed on a layer between two ground planes.
GND plane
W
W
T Trace
H
εr H εr
GND plane
Microstrip Stripline
v
Figure 43 Construction of microstrip and stripline

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Design measures
• Determine widths of especially high-speed traces to guarantee the same

characteristic wave impedance over the whole PCB.
Figure 44 shows the changes in characteristic wave impedance due to a smaller
distance trace to groundplane or due to a wider trace.
εr=4.5 εr=4.5
εr=4.5
Figure 44 Wave impedance
• If the half rise/fall time of the signal is smaller than the propagation delay of the PCB
trace, the trace should be treated as a transmission line. These traces should be
terminated with their characteristic impedance. This means that if the critical length
is exceeded then the trace should be terminated. The critical length of the traces
can be calculated as follows:
Tr
L=
2T pd
εr
T pd =
c
Tr: rise / falltime; Tpd: propagation delay; c: speed of light
The characteristic impedance of the stripline can be calculated with:

(valid when 0.1<W/H<2.0 and 1< ε rel <15)
Z 87   5.98 H 
= ln 
Ω ε rel + 1.41   0.8W + T 
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Design measures
For micro-strips the following formula can be used:

(valid when W/H<0.35 and T/H<0.25)
Z 60   4H 
= ln 
Ω ε rel   0.67π(T + 0.8W) 
H: height of dielectrica between trace and ground plane; W: width of trace; T: height of
trace.
Termination methods:
A mismatch between the output impedance of the driver and the line impedance
causes reflections on the line. These reflections influence the performance of the
circuits. Most popular measure against the reflections is to use terminations. There are
different methods to realize the terminations.
If the characteristic impedance of the line is matched on the source side, the line is
source terminated (Figure 45a). In this case the reflections will be cancelled at the
source because of the matching and zero reflection coefficient. The output impedance
of the driver should be subtracted from the ideal value of the source termination.
If the termination is placed at the end of the line, the line is load terminated (Figure
45b). The reflections will be cancelled at the end of the line. The received voltage is
equal to the transmitted voltage. A variation of the load termination is the DC biasing
termination, with a resistance connected to the supply in additional to the resistance to
the ground. The parallel combination of both resistances must be equal to the
characteristic impedance Z0. The source termination results in a slower rise time of the
signal and smaller reflections than for load terminations. Because of the often
unacceptably high DC current consumption in case of load termination, two other types
of termination can be used: DC-load termination (Figure 45c) and AC-load termination
(Figure 45d).
There are three goals for termination: to minimize reflection, voltage swing and
emission. To minimize reflection, match the driver’s Ri with Z0 by a series resistor Rx
close to the driver. A matching termination of a high speed signal trace on both sides is
very important, especially when the rise time of the driver signal is short in comparison
to the signal propagation delay.

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Design measures
To optimize the voltage swing, determine a series resistor Rx that cuts half of the
voltage swing on a two-point-net (with a characteristic wave impedance Z0) while
regarding the non-linear Ri.
To minimize electromagnetic emission, provide resistors (20-200 Ohms) and adjust for
a smooth rising edge. If provided in the microcontroller, use software settings for edge
and driver strength control.
VDD
ZS ZS
RM Trace
Source Imp.
Trace
R1
Source Imp.
Receiver Receiver
Matching Imp.
Driver Z0 Driver Z0 RM
a) Source Termination
Z0=RM+ZS c) DC-Load Termination RM=Z0
ZS ZS
Source Imp. Source Imp. Matching Imp.
Trace Matching Imp. Trace
Receiver
Receiver
RM
Driver Z0 RM Driver Z0 C
b) Load Termination
RM=Z0 d) AC-Load Termination RM=Z0
Figure 45 Source, load, DC-load and AC-load terminations
To ensure signal integrity and reduce electromagnetic emission, provide series

resistors close to the drivers. Optimize their values by simulation or by approximate
calculation from VI-tables of the driver and the trace impedance.
The simulation results in Figures 46-47 show that both series and parallel terminations
deliver best signal integrity behavior if the source or load termination matches with the
driver´s output or trace impedance.

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Figure 46 Series source termination of a 50Ohm trace with 25 / 50 / 75 / 100 /

150 Ohm impedances (signals at source and load)

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Design measures
Figure 47 Load termination of a 50Ohm trace with 50 / 75 / 100 / 200 Ohm

impedances (signals at source and load)

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Design measures
Use controlled impedance for critical signals. To reach the termination targets (as
explained above), calculate the impedance of the trace from the technological and
geometrical data of the PCB.
Critical signals should be routed with a ground reference, if possible as a strip line on a
power layer surrounded with ground.
Avoid overlapping power planes in multilayer boards because the noise is easily
coupled between the different supply domains.
Keep the return current path as short as possible for high-speed traces. In four or more
layer boards, avoid gaps or batteries of vias within a ground plane in order to keep the
loop of the current return path small. On two-layer boards provide power and ground
nets close to the high-speed trace.
The smaller the return current loop the lower the electromagnetic emission will be.
Keep in mind that return currents can also use the VDD system!
Figure 48 Return current loop area for multilayer boards
If fast signals are provided on the PCB, design a ground ring around each layer of your
board. This ground ring should be connected by several vias along the edge of the
board to the reference ground plane. The distance from one via to the next should be
not longer than 5mm. This builds a reference ground ring around the board which
helps to decrease radiation from the inner layers. Additionally it avoids that currents at
the edges of the PCB can build antenna structures and radiate to the outside. If very
high frequencies are transferred, the distance between the connecting vias has to be

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Design measures
even smaller. The efficiency of this measure is increasing if you have more ground
planes. Then this construction forms a faraday cage for the middle signal layers.
Figure 49 Return current loop area for two-layer boards
Avoid vias in high speed traces and through the power planes. Vias through the power
planes can cause coupling of the signal to the power supply network. Vias have an
additional inductance of ca. 0.5nH ~ 1nH.
Avoid turns in high speed traces. Turns mean a change in the characteristic wave
impedance of a trace. Better use 45 degree turns (or even less!) instead of 90 degree
turns. 90 degree turns cause a change in the trace’s width. Changes in the trace’s
width cause changes in the characteristic wave impedance which will result in
undesired reflections.
Provide room for a series resistor close to the driving component. If you have not set
up a specific design rule yet, optimize the resistor value.
If you have two adjacent signal layers, realize x-y-tracing to reduce crosstalk. Place
and layout decoupling capacitors.
Finally design all other traces. This chapter should be kept in mind there as well.

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3.2.2 Components
3.2.2.1 Resistors
As mentioned in the chapter “Termination”, the resistors are used for the impedance
matching, biasing and pull-up / pull-down circuits. Resistors are commonly used in
surface mount packages (SMD). This package type has low parasitic elements
compared to the lead packages.
Rs Ls
Cp
Impedance of 1 Ohm Resistance (MELF package)

1000
100
Z [Ohm]
10
1
1.00E+06 1.00E+07 1.00E+08 1.00E+09 1.00E+10
Freq.[Hz]
Figure 50 Equivalent circuit of a resistor and impedance of a 1 Ohm resistor
Figure 50 shows the equivalent circuit of a resistor and the impedance characteristic
of a 1 Ohm resistor. Impedance increases at higher frequencies because of the
parasitic inductance. The inductance becomes dominant above 30 MHz.

AP24026
Design measures
3.2.2.2 EMI filters

Filters are commonly used for the power lines, but they are also very effective in signal
lines. Especially on clock and bus lines which are propagation paths for the noise in
applications.
Source Impedance Filter Load Impedance
High π-Type High

High L-Type1 Low
Low L-Type2 High
Low T-Type Low
L L
C C C
π-type L-type1
L L
L
C C
L-type2 T-type
Figure 51 Different types of EMI-filters and usage conditions
The filters consist of L and C elements. Depending on the required insertion loss of the
filter they are configured as π-, L- and T-filter. If the source and load impedance is
high, then a π-type filter is the best solution. The π-type filter has an inductor
surrounded by two capacitors so that the capacitances are lowering the impedance on
both sides according their selected frequency characteristics.
Figure 51 shows the equivalent circuits of different types of EMI-filters together with
their optimum application cases.

AP24026
Microcontroller special remarks
4 Microcontroller special remarks

Dedicated input pins:
These pins, when not used, should be tied to the level which represents the inactive
level for the associated function, e.g.:
NMI# (which has no internal pull-up) should be tied to VDD.
READY# (which has an internal pull-up) should be tied to VDD.
XTAL3# (input clock for auxiliary oscillator) should be tied to defined level. Because of
various types of auxiliary oscillators please specify this level according the Application
Note 2420 of infineon Technologies.
For unused “Output, Supply, Input and I/O“ pins following points must be
considered:
1. Supply Pins (Modules) - see product specification
2. I/O-pins - must be configured as outputs and driven to static

low in the weakest driver mode
- solder pads should be left open and not be

connected to any other net (layout isolated PCB-
pads only for soldering)
3. Output pins including LVDS - should be driven static in the weakest driver mode
- if static output level is not possible, the output

driver should be disabled
- solder pads should be left open and not be

connected to any other net (layout isolated PCB-
pads only for soldering)
4. Input pins without internal pull - for pins with alternate function see product target
device specification to define the necessary logic level
- must be connected with a high-ohmic resistor to

GND (range 10k – 1Meg)
- groups of 8 pins can be used to reduce the number

of external pull-up/down devices (keep in mind the
leakage current)

AP24026
Microcontroller special remarks
5. Input pins with internal pull - for pins with alternate function see product
device specification to define the necessary logic level
- according to the product specification the pull

devices must be configured as pull-down or pull-up
and should be set to static low (exception: if the
product specification requires a high level for
alternate functions)
- solder pads should not be connected to any other

net (isolated PCB-pads only for soldering)

AP24026
Simulations
5 Simulations
An additional way to improve the design of an application is to test certain structures in
the layout by simulation. Find below a description of the most common tools and
techniques which are offered by several software manufacturers. By simulation of
EMC-relevant parameters like emission, susceptibility and signal integrity of electrical
systems, an assessment of the necessary effort and the most effective measures can
be made. Electrical systems can be: modules, printed circuit boards (PCB), electrical
circuits, sub-circuits and even integrated devices. More and better simulation models
are provided from the different manufacturers or distributors.
In the last few years, there are some efforts to get accurate models for the power
supply network of the microcontrollers, which are missing in IBIS models. These
models are called ICEM (Integrated Circuit Emission Model). ICEM is an IEC
standard proposal with project number 62014-3 from October 2001. The model
describes the high frequency behavior of power supply networks of core and I/Os of
integrated circuits. The models can today be used with all SPICE-based simulators. An
IBIS4 integration is planned.
For the 16-bit and 32-bit microcontrollers from Infineon Technologies, IBIS-models are
provided and ICEM models are under construction.
SPICE
SPICE is a simulation program with integrated circuit emphasis. SPICE allows the
analysis of electrical circuits. For EMI/SI items it allows the analysis of electrical
systems (e.g. bus systems) regarding parasitic effects (coupling to adjacent nets,
reflections, etc.). The parasitics themselves are calculated by using a 2D- or 3D-field
solver. The driver and receiver models are supplied by the manufacturers as transistor
based models or in the IBIS format. There exist plenty of SPICE-like programs.
Generation of SPICE models

To achieve good results from SPICE simulations, modeling know-how is a basic
requirement. The better the SPICE models (subcircuits) are, the more efficient the
analysis becomes. For the analysis of e.g. a bus system, IBIS models (mostly provided
by the chip manufacturer) and transmission line models (generation by 2D- and 3D-
field solvers) are necessary.
2D-field-solver
A 2D-field solver is needed for the determination of the parasitics (capacitance,
inductance and resistance values) for transmission lines or transmission line systems

AP24026
Simulations
which are geometrically uniform in the 3rd dimension, i.e. traces or trace structures.
These values can be used to model SPICE subcircuits for the analysis of bus systems
or other structures.
3D-field solver
For more complex structures like vias and rectangular traces, or structures in
integrated circuits like packages, wirebonds and leadframe etc., a 3D-field solver is
needed to determine the parasitics. Again, these values can be used to model SPICE
subcircuits.
The electric or magnetic field in any given point in the space around a conducting 3D-
structure (especially a PCB) is calculated by adding the corresponding field vectors
caused by all current-vectors of this structure for a given moment in time and a given
frequency.
Pre-layout analysis
Pre-layout analysis means the investigation of certain design configurations (even in

the specification phase) in order to find an optimum solution early. Pre-layout analysis
also means the setup of a bundle of design rules for subsequent design stages (e.g.
minimum distance of traces to keep crosstalk low, etc.).
Post-layout analysis
Post-layout analysis means the partial or full investigation of already designed
electrical systems like PCBs in order to detect design hazards, e.g. areas of high
electromagnetic emission, before any hardware prototype is built.

AP24026
Formula appendix
6 Formula appendix
Calculation of Decibel
Decibel [dB] is a dimensionless ratio of levels. Electromagnetic emission measurement

results are expressed in spectra or limit curves with the unit [dBµV].
Power [dB] = 10 log(P1/P0), P[dBmW or dBm] = 10 log(P1/1mW);
dBm is defined for a 50Ohm system with P1 being the measured power and P0 being
the reference power.
Voltage [dB] = 20 log (V1/V0), V[dBµV] = 20 log(V1/1µV);
with V1 being the measured voltage, V0 being the reference voltage.
(e.g. harmonic of 100µV amplitude = 20 log(100) = 40 dBµV )

AP24026
Glossary
7 Glossary
2D-field solver Simulation tool for analysis (couplings, characteristic wave
impedance, etc.) of two-dimensional trace structures.
3D-field solver Simulation tool for analysis (couplings, characteristic wave
impedance, etc.) of three-dimensional trace structures like via
holes.
Cross (bar) current Current which flows across two or more transistors connected in
line, in case they are conducting at the same time.
Decap Decoupling capacitor.
DUT Device under test.
EMC Electromagnetic compatibility (compatibility regarding emission
and susceptibility of electromagnetic disturbances between
ÆDUT and environment).
EME Electromagnetic emission (radiated or conducted emission of
electromagnetic noise by an electronic device).
EMI Electromagnetic interference (undesired or illegal generation of
electromagnetic signals; bandwidth DC to daylight.
EMS Electromagnetic susceptibility (an adverse reaction of electronic
equipment to radiated or conducted signals).
ESL Equivalent series inductance of capacitors at high frequency.
ESR Equivalent series resistor of capacitors at high frequency.
GND Board ground net (trace or plane structure).
IBIS Input/output buffer information specification (a widely established
standard for electrical behavioral specifications of digital
integrated circuit input/output analog characteristics).
ICEM Integrated circuit emission model
Microvia Via with a diameter of about 100µm.
PCB Printed circuit board.
RF Radio frequency (high frequency).
SPICE Name of a common simulation tool.
SI Signal integrity (reflection, timing, crosstalk).
VI - Table Static behavioral driver description voltage vs. current.
Vih Input threshold voltage.
VCC Board supply net (trace or plane structure).
VDD IC supply pin.
VSS IC ground pin.
XTK Crosstalk (interference between two adjacent traces).
x-y-tracing Orthogonally routed adjacent signal layers to minimize crosstalk.
Z0 Characteristic wave impedance.

AP24026
Literature
8 Literature
For more detailed information and physical explanations, it might be useful to have a
book or lecture about the subject of EMC. The following list is a selection of literature
which includes the various subjects of EMC like emission, susceptibility and
electrostatic discharge.
• A. Schwab, Elektromagnetische Verträglichkeit, 3. Ausgabe, Springer Verlag,

1994 Berlin-Heidelberg. (German language). [Comment: Good book for wide basic
knowledge of EMC] ISBN: 3-540-57658-4
• Michael Mardiguian, Controlling Radiated Emission by Design, Chapman & Hall,

1992 New York. [Comment: detailed and special for radiation] ISBN: 0-442-00949-6
• Howard Johnson, Martin Graham, High-Speed Digital Design - A Handbook of

Black Magic, 1993 by Prentice Hall PTR. [Comment: very detailed and
mathematically oriented] ISBN: 0-13-395724-1
• Mark Montrose: EMC and the Printed Circuit Board: Design, Theory and Layout
Made Simple, IEEE Electromagnetic Compatibility Society. [Contents: EMC
fundamentals; EMC inside the PCB; components and EMC; image planes;
bypassing and decoupling; transmission lines; signal integrity and crosstalk;
grounding concept.] ISBN 0-7803-4703-X
• EMC Kompendium / E+E Kompendium 1999 - 2006, publish-industry Verlag

GmbH, Munich (German language)
• Paper to the workshop "Optimized Decoupling Concepts for Digital VLSI

Circuits", Joachim Held, Siemens AG Munich; Prof. Thomas Wolf, University of
Applied Sciences, Landshut; IEEE - EMC seminar 2001
• Paper to the seminar ‘‘EMV auf Leiterplatten 1999‘‘, Prof. Chr. Dirks, published
by Nils Dirks Corporate Consulting, Donaueschingen. (German language)
• Paper to the workshop ‘‘EMV auf Leiterplattenebene‘‘, Werner John, published

by MESAGO GmbH Stuttgart (German language)
• Paper to the workshop ‘‘Techniques for PCB and Circuit Level Radiation
Reduction‘‘, David A. Weston, published by MESAGO GmbH Stuttgart.
• High-Speed Digital System Design “A Handbook of Interconnect Theory and

Design Practices”, Stephen H. Hall, Garret W. Hall, James A. McCall, 2000 by
John Wiley & Sons , Inc. ISBN:0-471-36090-2

AP24026
Literature
• Paper to the EMC COMPO 2004, “IC Emission Models from Measurement and
from Netlist”, Mehmet Gökcen, Thomas Steinecke, Angers, France
• Taiyo-Yuden ‘‘The Fundamental Technical Knowledge of passive

Components’’ Appl. Notes. www.taiyo-yuden.com
• Ilfa GmbH, “Layoutstrategien und Leiterplattentechnik”, Arnold Wiemers.

www.ilfa.de
• Murata , Technical Specification of Murata Capacitors. www.murata.com
• Kemet , Technical Specification of Kemet Capacitors. www.kemet.com

http://www.infineon.com
Published by Infineon Technologies AG

EMC Design Guidelines For Microcontroler Board Layout

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A p pl i c at i o n N ot e, V 3.

THE INFORMATION GIVEN IN THIS APPLICATION NOTE IS GIVEN AS A HINT

Revision History: 2006-10 V 3.3

Controller Area Network (CAN): License of Robert Bosch GmbH

We Listen to Your Comments

Application Note 3 V 3.3, 2006-10

Table of Contents Page

Application Note 4 V 3.3, 2006-10

Application Note 5 V 3.3, 2006-10

1.1 Noise sources

Figure 1 Typical application board and noise source paths

Application Note 6 V 3.3, 2006-10

Figure 2 Spectrum of a trapezoidal signal

Application Note 7 V 3.3, 2006-10

Figure 3 Relation of spectrum and pulse width

Application Note 8 V 3.3, 2006-10

Figure 3 Relation of spectrum and pulse width (continued)

Application Note 9 V 3.3, 2006-10

1.2 Coupling paths

Figure 4 Common-mode and differential-mode

Differential-mode interference is a symmetrical disturbance which occurs between

Application Note 10 V 3.3, 2006-10

Current loops have significant inductance and can be modeled as a coil of a

Figure 5 Interaction of two loops

Application Note 11 V 3.3, 2006-10

Figure 6 Capacitive and inductive coupling

Application Note 12 V 3.3, 2006-10

Application Note 13 V 3.3, 2006-10

Two-layer / multilayer boards

Application Note 14 V 3.3, 2006-10

High impedance traces

Figure 7 High impedance traces

Application Note 15 V 3.3, 2006-10

VDD Via VCC

VSS Via GND

Figure 8 Decoupling of a typical BGA (left) and lead-frame (right) package

Application Note 16 V 3.3, 2006-10

Figure 9 Impedance of PCB for different r

Application Note 17 V 3.3, 2006-10

Application Note 18 V 3.3, 2006-10

• Do not place the connectors close to high speed circuits.

4 Layer PCB H : Height of PCB

3.1 Power supply

Application Note 19 V 3.3, 2006-10

Voltage regulator: canalizing the RF current

Figure 11 Flow of the canalized energy

Application Note 20 V 3.3, 2006-10

Figure 12 Decoupling of the power circuit

3.1.1 Layout structures

GND Trace GND Trace

Figure 13 Design of ground traces

Application Note 21 V 3.3, 2006-10

Figure 14 No Blocking of Current Return Path

Application Note 22 V 3.3, 2006-10

Figure 15 Example: Segmentation of the supply plane with voltage regulator

Application Note 23 V 3.3, 2006-10

Application Note 24 V 3.3, 2006-10

Figure 17 Impedance for different board thickness and plane dimensions

Application Note 25 V 3.3, 2006-10

Separated GND Crystal

Vias to GND island

Figure 18 Layout example for crystal oscillator circuit

3.1.1.1 Two-layer boards