1
24. Compare CISC and RISC.
25. Distinguish between Daisy chaining arbitration and independent request arbitration?
26. What are the reasons of having interrupts in computers?
How can the interrupts be handled in a computer?
Suggest a scheme that can handle multiple interrupts at a time. 2+2+1
27. What are vectored interrupts? How are they used in implementing hardware interrupts?
28. What are the differences between hardwired control unit and micro-programmed control unit?
29. Draw the block diagram and describe the functionality of micro-programmed control unit.
30. What are the different hazards in pipeline?
2. a. Give the Booth’s algorithm for multiplication of signed 2’s complement numbers in flowchart and explain.
b. Multiply -7 and -3 using Booth’s algorithm.
c. Give the flowchart for division of two binary numbers and explain. 5+5+5
3. a. Explain Booth’s algorithm. Apply Booth’s algorithm to multiply the two numbers (+15) 10 and (-11)10.
Assume the multiplier and multiplicand to be of 5 bits each.
b. With suitable logic diagram explain the design of carry save adder. [ 10 + 5]
4. a. What is cache mapping? Explain cache mapping for 256 x 8 RAM and 64 x 8 cache.
b. Explain how a RAM of capacity 2 Kbytes can be mapped into the address space (1000)H to (17FF)H of a CPU
having a 16 bit address lines. Show how the address lines are decoded to generate the chip-select condition for
the RAM. [5 + 10]
5. a. Give the merits and demerits of the floating point and fixed-point representations for storing real numbers.
b. What are guard bits?
c. A floating-point number system uses 16 bits for representing a number. The most significant bit is the sign bit.
The least significant nine bits represent the mantissa and remaining 6 bits represent the exponent. Assume that
the numbers are stored in normalized format with one hidden bit.
i. Give the representation of –1.6 X 103 in this number system.
ii. What is the value represented by 0000100110000000.
d. Give the timing diagrams of basic memory read and write operations. [4+ 2+6+3]
2
9. a. Explain the reading and writing operations of a basic Static MOS cell.
b. Why a DRAM cell needs refreshing?
c. Given the following, determine size of the sub-fields (in bits) in the address for the Direct Mapping, associative
and set associative mapping cache schemes:
We have 256 MB main memory and 1 MB cache memory.
The address space of this processor is 256 MB.
The block size is 128 bytes
There are 8 blocks in a cache set. [6+ 3+ 6]
12. a. Differentiate between I/O mapped I/O and memory mapped I/O.
b. Distinguish between vectored and non-vectored interrupt.
c. Why do peripherals need interface circuit with them?
d. Discuss the advantage of interrupt initiated I/O over programmed I/O. [4 + 4 + 4 + 3]
14. a. What is the difference between computer organization and computer architecture?
b. Name the characteristics present in Von-Neumann architecture.
c. How does the fetch-decode-execute cycle work?
d. Assume you have a machine that uses 32-bit integers and you are storing the hex value 1234 at address 0:
i. Show how this is stored on a big endian machine.
ii. Show how this is stored on a little endian machine. [3 + 4 + 4 + 4]
16. a. Draw the internal cell diagram of PROM and explain its functionality.
b. What is cache memory? How does it increase the performance of a computer? What is hit ratio?
c. A three-level memory system having cache access time of 5 nsec and disk access time of 40 nsec, has a cache
hit ratio of 0.96 and main memory hit ratio of 0.9. What should be the main memory access time to achieve
an overall access time of 16 nsec?
d. Define i) rotational latency ii) seek time. [4+4+5+2]
17. a. What is instruction cycle? Draw the time diagram for memory write operation.
b. Explain the basic DMA operations for transfer of data between memory and peripherals.
c. Evaluate the arithmetic statement X = (A* B) / (C+D) in one, two and three address machines.
[1+4+5+5]
18. a. What is Cache memory? Why is it needed? Explain the Write-through and Write –back mechanism.
b. Why is set-associative mapping technique more advantageous than direct or associative mapping technique?
c. A computer has 512 KB cache memory and 2 MB main memory. If the block size is 64 bytes, then find out
the subfields for
i. direct mapping cache
ii. associative
iii. 8-way set associative cache
d. Why memory hierarchy is needed? What are the different levels in memory hierarchy? [ 2+2+2+2+3+2+2]
19. a. Show that when K jobs are processed over an N-stage pipeline, the speed-up obtained is S=NK/
(N+K-1)
b. Define speed-up of a parallel processing system.
c. Explain structural hazards in a pipeline processing.
d. With the help of a neat diagram, show the structure of a typical arithmetic pipeline performing subtraction.
3
e. Show that if a single powerful processor P is replaced by n small processors PZ having computational speed
1/nth the computational speed P then no advantage in speed-up is obtained. [3+2+3+4+3]
21. a. What is meant by DMA? Why is it useful? Briefly explain with suitable diagram, the DMA operation in
association with CPU.
b. Draw the schematic diagram for daisy chain polling arrangement in case of vectored interrupt for three
devices
[2+2+4+7]
22. a. What is interrupt? What are the difference between vectored and non vectored interrupt?
b. Why is refreshing required in Dynamic MOS? Define volatile and non volatile memory.
c. How do ALU and CU work? Explain. [1+4+2+3+3+2]
23. a.
Explain the basic DMA operation for transfer of data bytes between memory and peripherals.
b.
Give the main reason why DMA based I/O is better in some circumstances than interrupt drive I/O?
c.
What is programmed I/O technique? Why is it not very useful?
d.
According to the following information, determine size of the subfields ( in bits) in the address for direct
Mapping and Set Associative Mapping cache memory.
256 MB main memory and 1 MB cache memory
The address space of the processor is 256 MB
The block size is 128 bytes
There are 8 blocks in a cache set
24. a. What are the various modes of data transfer between computer and peripherals? Explain.
b. Differentiate isolated I/O and memory mapped I/O.
c. Show how computer bus is organized using tri-state buffer. [5+5+5]
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