Analysis of an OTA/Output Stage for a SC

Integrator in a Hybrid ΣΔ Modulator

D. Calderón-Preciado1, F. Sandoval-Ibarra2, J. G. García-Sánchez3, S. Ortega-Cisneros4
Cinvestav, Unidad Guadalajara
Av. del Bosque 1145, 45019 Col. El Bajío, Zapopan, México
1
dcalderon@gdl.cinvestav.mx
2
sandoval@gdl.cinvestav.mx
3
ggarcia@gdl.cinvestav.mx
4
sortega@gdl.cinvestav.mx

Abstract— In this paper SIMSIDES-based (Simulink-based
Sigma Delta Simulator) high level simulation of a 4th order
Hybrid ΣΔ Modulator was carried out to find the performance
requirements of several Analog Building Blocks (ABB). Once
the requirements have been defined, the next step is to design
each ABB at the transistor level. One of them, a fully
differential OTA, was sized through a Design of Experiments
(DOE) by assessing the required performance of a 2nd order
Switched Capacitor (SC) ΣΔ Modulator. By using this design
strategy how to translate performance requirements into a set
of values −at transistor level− is established by the desired
performance of the architecture, i.e. the 4th order Hybrid ΣΔ
Modulator. In line with this design strategy, a CFCFC
(Complementary Folded Cascode Feedforward Compensated)
OTA was designed with design rules of a standard 130nm
CMOS process. However, since charging time (τch) is a design
requirement deduced from the desired performance of the DT
modulator, an output stage (voltage follower) was designed in
order to obtain an output resistance of a few ohms, so that
charging time satisfies τch<2ns. CADENCE simulation results
allow us to highlight that the accuracy of mathematical models,
obtained from small-signal analysis (OTA+output stage),
enhance high level analysis and minimize simulation time.
Resumen—En este trabajo se usa la simulación
comportamental (en SIMSIDES) de un Modulador ΣΔ Híbrido
de 4º orden para obtener características eléctricas de varios
bloques analógicos, y luego diseñarlos a nivel transistor. Uno
de ellos, un OTA completamente diferencial, se dimensionó con
un diseño de experimentos mediante la evaluación del
desempeño de modulador ΣΔ con capacitores conmutados.
Usando esta estrategia de diseño es inmediato trasladar las
consideraciones de diseño en un conjunto de valores de tal
manera que el diseño a nivel transistor está establecido por el
desempeño deseado de la arquitectura propuesta. Con esta
estrategia se diseñó un CFCFC OTA en un proceso estándar
CMOS 130nm. Sin embargo, ya que el tiempo de carga (τch) es
un requerimiento de diseño establecido por el desempeño del
modulador SC, una etapa de salida se diseña con una
resistencia de salida de pocos ohms, y así satisfacer el tiempo
de carga τch≤2ns. Simulaciones con CADENCE muestran que
la exactitud de los modelos analíticos de diseño (OTA y etapa
de salida), obtenidos de los circuitos eléctricos equivalentes de
pequeña señal, enriquecen la simulación de alto nivel y
reducen el tiempo de simulación.
performance [1]. Analog designers also know that bias and
the aspect ratio (width and length) of MOS transistors are
his/her design variables, while both technology models and
simulation tools (High level approach, SPICE, etc.) are
resources to assess the desired performance of the selected
architecture [2]. As described in [3] an individual analysis
strategy for each design step is not a suitable one because
design steps are deeply correlated. That is why the
integrated analysis presented in [4] is widely used in this
work (see Section II). In this paper, SIMSIDES-based
behavioral modeling [5] of a 4th order hybrid ΣΔ modulator
is used as a vehicle to find the performance requirements of
a fully-differential Operational Transconductance Amplifier
(OTA) in order to satisfy the design requirements of the
discrete-time (DT) back-end shown in Fig.1 (see Section
III). As can be seen, the front-end is a continuous-time (CT)
proposal while the DT back-end takes into consideration
some SC integrator’s non-idealities effects on the expected
modulator performance. Note that the back-end is connected
to the digital cancellation logic, so the quantizer must
correctly convert the discrete signal to the required Number
of Bits (NOB). The latter is the correct one if the charging
time is as short as few ns. Unfortunately, an OTA presents
an output resistance of several kΩ, and taking into account
that the load is capacitive type, an output stage with low
output resistance must be designed without affecting the
overall performance of the DT ΣΔ modulator (see Section
IV). In this paper, all design specifications were properly
selected in order to cover communication standards with a
frequency band ranging from 890MHz to 2.48GHz.

I. INTRODUCTION
Analog designers know that the design of analog systems
consists of the architecture selection, the establishment of
performance requirements for each ABB and minimize as Fig. 1. Block diagram of the modulator under design.
much as possible non-idealities effects on the whole system
 II. SIMSIDES-BASED HIGH LEVEL SIMULATION
The ΣΔ Modulator (ΣΔM) under design is a 4th order
system where the front-end/back-end is a CT/DT 2nd order
modulator (see Fig. 1). The back-end includes a SC
integrator based on a fully-differential OTA including a
complementary folded cascode array. Table I shows the
simulation conditions for assessing the SIMSIDES-based
performance of the SC ΣΔM. These values have been
properly selected in order to cover communication standards
(GSM, UMTS, Bluetooth and WLAND) where the
frequency band is 0.89-2.48 GHz [3]. By using SIMSIDES,
a DOE was carried out in order to determine the effect of
multiple factors on the desired integrated in-band error (IBE)
and also to identify specific characteristics of ABB. One of
these, the OTA, when satisfies the values shown in Table I
the output spectrum is as shown in Fig. 2. High level
simulation does not take into account any OTA topology,
but a mathematical model based on basic parameters (gain,
0dB frequency, output resistance, etc.). However, once the
designer chooses an OTA, additional characteristics are
optimized, where low power consumption, high slew-rate,
and large output swing, are some examples.
As mentioned above, SIMSIDES allows us to
systematically fulfil the desired performance by finding
design variables under the designer’s control and then
synthesis it into a set of values, so that the parameters of the
transistor-based circuits can be defined [7]. However, it is
known that parameters affecting the overall behavior of SC
integrators depend on the OTA performance. That is why
the SIMSIDES simulation allows us to find the OTA
characteristics shown in Table I [3].
TABLE I
SIMULATION CONDITIONS AND SELECTED PARAMETERS FOR THE ΣΔM
Simulation Conditions
Bias ±1.2V
Quantizer
Number of levels 3 capacitors are calculated by taking into account the size of
Amplitude -10dB
Input
Frequency, fi 991.234kHz
signal
Bandwidth 10MHz
Sampling frequency, fs 200MHz
Selected Parameters
Output current, IO ≥ 0.3mA
Effective
transconductance, gm,eff ≥ 3mS
OTA
Open-loop gain, A0 ≥ 60dB
Bandwidth, f0dB ≥ 1GHz
Phase margin, ΦM 45o-60o
Fig. 2. ΣΔ modulator output spectrum.
Note that the quantization process generates an intrinsic
error (see Fig. 2). In other words, a high level simulation
allows us not only to obtain the desired performance, but to
define a suitable reference to assess the effect of unwanted
factors once each behavioral block has been substituted by a
suitable transistor-level circuit. The overall performance of
the system under design must be as close as shown in Fig. 2
in order to validate well-defined metrics before going to
silicon.
III. OTA: SMALL-SIGNAL ANALYSIS
Differential signal Processing (DsP) requires the design
of a fully-differential OTA, so that a SC integrator fulfils
the performance specifications. By using DsP, several non-
idealities (common mode noise, clock feedthrough, charge
injection, and harmonic distortion) are minimized [9]-[10]).
However, basic OTA parameters (open-loop gain,
bandwidth, effective transconductance, output current and
fast settling) must be carefully analyzed in order to fulfill
the desired performance of the SC integrator. Once the
sampling frequency (fs=200MHz) is defined, an OTA with a
unity-gain bandwidth f0dB=1GHz at CL=2.5pF must be
designed [11]-[12]. In order to fulfill design parameters
shown in Table I, the design rules of a 130nm CMOS
process were used. The chosen OTA architecture is based
on a CFCFC array [9] including capacitors Cf to
approximately model the OTA as a two poles system [13].
The OTA under design is shown in Fig. 3.
The simulation of the transistor-based SC modulator is
carried out in time-domain, which means long a simulation
time mainly when simulation range is large. In order to
minimize simulation time, circuits based on equivalent
lumped circuits are recommended. Because of symmetry,
Fig. 4 shows only the differential half equivalent circuit
where small signal parameters are obtained from
CADENCE throughout operation point conditions, and
each transistor. The sizing of transistors was done by
looking for the equilibrium between A0 and f0dB. In practice
both parameters are maximized by increasing the
transconductance of both input transistors. However, large
parasitic capacitances affect the settling behavior so the
two-pole approach goes to an unpractical design approach.
The better performance was obtained by using wide input
devices and also by proposing that transistor bias current
must be higher than the bias of cascode transistors [11]. The
sizing of the OTA is described in [7]; here, Table II
summarizes the simulation results and Fig. 5 shows an
open-loop comparison between lumped-based simulation
results and CADENCE transistor level results. In this work
lumped-based circuits does not take into account the bulk
transconductance because VSB=0. This fact surely affects the
response between 100MHz and 1.0GHz. At frequencies
below 100MHz, the relative error between both responses is
approximately 1% [7].
In this paper, we do not show the analytic model that
describes the response of the small-signal circuit. However,
the analytic model allows us to minimize the simulation
time of the 4th order modulator; another advantage is that
the accuracy of the behavioral models based on well-known
circuits reduces the black box status of the high level
simulation tools.
 TABLE II both the output resistance and the low frequency gain.
BASIC PARAMETERS OBTAINED FROM SIMULATION RESULTS
However, CL and rout represent a time constant given
IO 0.311mA approximately by τch≈2routCL, which must be lower than
gm,eff 30.2mS 0.5/fs (=2.5ns) to make an acceptable charge transfer.
A0 60dB Taking into account our design variables, the time constant
f0dB 1.047GHz is 33kΩ×2.5pF=85.2ns, which means that a newer OTA
OTA
CL 2.5pF sizing must be done or alternatively an output stage has to
ΦM 48.5o be added to the OTA. The authors choice is the design of a
rout 33kΩ source follower in order to reduce power consumption. The
PS 11.82mW output stage reduces the time constant towards acceptable
values whereas the overall frequency response remains
unchanged.

IV. OUTPUT STAGE: DESIGN AND SMALL-SIGNAL ANALYSIS

The chosen output stage is the Voltage Follower (VF)
shown in Fig. 6. The design technique for sizing all MOS
transistors is presented in [6]. This circuit comprises two
compound transistors in a push-pull array. Current mirrors
use complementary transistors (M3-M4 and M7-M8) to
force the gate-to-source voltages of both NMOS and PMOS
to be equal. The latter allows the difference between VGS of
M1-M2 and M5-M6 to be compensated; otherwise, an error
would appear as an offset voltage.

Fig. 3. CFCFC OTA under design.

Fig. 4. Differential half, medium-frequency Model for the CFCFC OTA

Fig. 6. Voltage Follower as depicted in [6]

B. Output Stage Small-Signal Analysis

Fig. 5. Transistor Level Simulation vs OTA Equivalent Model
A. Preliminary results
Certainly cascode stages provide high gain and fast
operation even when a low power supply is used [12]. In
this design, the current driven by the input transistors is
1.2mA in order to increase gm,eff whereas the current at the
output stages is of the order of 311µA. This fact increases
The small-signal equivalent circuit shown in Fig. 7 is
analyzed in order to obtain a mathematical model to
compute (by substituting suitable values) an output
resistance as low as possible and an output-to-input ratio
equal to 1. By solving the equivalent circuit and taking into
account small-signal values, a gain of 0.96 was obtained. In
other words, the gain of the OTA+VF decreases to 59.64dB
that means a loss of 4%. Fig, 8 shows the frequency
response comparison between lumped-based simulation
results and CADENCE transistor level results. Note that the
performance of this circuit covers the OTA bandwidth; thus,
it can be added to the OTA for simulating both the SC
integrator and the ΣΔ Modulator. In this design, the output
resistance is as low as 2Ω and the time constant is of the
order of 2.0ps. According to these results, a new DOE must
be carried out in order to measure the IBE power due to the
open-loop gain on the overall performance of the 4th order
modulator.
 V. CONCLUSION AND FUTURE WORK
This paper has presented the full custom design of a two-
stage fully differential CMOS amplifier with outstanding
characteristics of 1.047GHz unity gain bandwidth and a
59.64dB open-loop gain. Both small-signal circuits and
transistor-level simulations are compared in order to show
the accuracy and usefulness of mathematical models when
added to high level simulation tools. The simulation results
in 130nm CMOS process from ±1.2V voltage supply
demonstrate that the designed amplifier has covered the
desired performance of a 4th order ΣΔ Modulator with a
dedicated design technique: the amplifier exhibits an output
resistance of 2Ω, and a charging time of 2.0ps.
Fig. 7. Voltage Follower equivalent circuit
Fig. 7. Transistor level simulation vs Output stage equivalent model
SIMSIDES has been used for developing several DOE in
order to list basic characteristics of several building blocks,
where the OTA is an example. This amplifier was designed
by adding a complementary folded cascade feedforward
compensated array, and its design specifications were
verified throughout at the transistor level. In this design, we
have taken into account design specifications for assessing
the performance of a 4th order hybrid ΣΔ Modulator. These
specifications were selected in order to cover
communication standards (GSM, UMTS, Bluetooth, and
WLAND) with a frequency band ranging from 890MHz to
2.48GHz. Future work will include several strategies for
enhancing the performance of the hybrid ΣΔ Modulator.
One of these is by using Over Sampling at the front-end
(OSfront), and different Over Sampling at the back-end
(OSback), so that OSback< OSfront. In this way, the complexity
of the SC modulator is lower than mono-rate approaches, so
that the design specifications of all analog block are
certainly relaxed. This design strategy does not force an
increase in the noise-shaping filter order. In that sense, it is
basic to design a test chip, which includes the CFCFC OTA,
the SC integrator, as well as other ABB as the simplest
folded cascade OTA, the Complementary Folded Cascode
(CFC) OTA, and the Complementary Folded Regulated
Cascode (CFRC) OTA to assess a 2nd order CT ΣΔ
Modulator throughout the test of the CT integrator.
ACKNOWLEDGMENT
This work is supported by the Mexican Council of
Science and Technology (CONACyT) under grant 169660.
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