sa0 sa1
A x sa0 sa1 sa0 A x sa1
sa1 sa0
sa1
x Z A x x Z
sa0
x Z
sa1 sa0 sa1 sa0
B x B x
sa0 sa1
Minimum Set of Test Vectors Minimum Set of Test Vectors Minimum Set of Test Vectors
01 0 00
10 1 01
11 10
Gate level fault model accurate for NMOS but not for CMOS
1 gate input stuck-
stuck-at = 2 transistors stuck-
stuck-at in CMOS
Vdd Vdd
A PFET A NFET B PFET B NFET
A B A B
AB Z s-on s-
s- s-off s-
s-on s-
s-off s-
s-on ss--off ss--on ss--off
00 1 1 1 1 1 1 1 1 1 Z Z
01 1 1 mem IDDQ 1 1 1 1 1 A A
10 1 1 1 1 1 1 mem IDDQ 1
B NFET B NFET
11 0 IDDQ 0 0 mem IDDQ 0 0 mem B B
stuck--on
stuck stuck--off
stuck
Vss Vss
C. Stroud 6/08 Fault Models, Detection & 16
Simulation
Transistor Level Fault Equivalence & Collapsing
Stuck-off faults in series transistors are equivalent
Stuck-
Stuck--on faults in parallel transistors are equivalent
Stuck
# collapsed transistor faults = 2T
2T - Nser + Gser - Npar + Gpar
Nser = total # series transistors
Gser = total # groups of series transistors
Npar = total # parallel transistors
Gpar = total # groups of parallel transistors
Vdd
# collapsed faults = 6
A B A PFET s-s-on = B PFET s-
s-on
Z A NFET s-s-off = B NFET ss--off
A A PFET s-s-off
2-input B PFET s-s-off
B NAND A NFET s-s-on
B NFET s-s-on
Vss
C. Stroud 6/08 Fault Models, Detection & 17
Simulation
Transistor Level Fault Detection
Transistor fault detection more difficult than gate level
Stuck
Stuck--on faults
voltage divider may not produce incorrect logic values
monitoring IDDQ is best approach
small currents may be lost in leakage of >2M transistors
Stuck
Stuck--off can Vectors to detect:
A PFET stuck-
stuck-off
will produce wrong logic values, but 11 - to get Z=0
need ordered set of 2 vectors to detect 01 - to detect Z=0
Vdd
B PFET stuck-
stuck-off
A B 11 - to get Z=0
A PFET A NFET B PFET B NFET
10 - to detect Z=0
Z AB Z s-on s-
s- s-off s-
s-on s-
s-off s-
s-on s-
s-off s-
s-on s-
s-off
A/B NFETs s- s-off
A 00 1 1 1 1 1 1 1 1 1
0x or x0 - to get Z=1
2-input 01 1 1 mem IDDQ 1 1 1 1 1
11 to detect Z=1
B NAND 10 1 1 1 1 1 1 mem IDDQ 1
Min. #vectors = 4
11 0 IDDQ 0 0 mem IDDQ 0 0 mem
Vss detects s-
s-on w/ IDDQ
B B’ 11 11 11 11 11 11
B B’
Wired-OR fault model B dominates A model
C. Stroud 6/08 Fault Models, Detection & 20
Simulation
A Newer Bridging Fault Model
Dominant-AND/Dominant
Dominant- AND/Dominant--OR (aka 4- 4-way BF model):
Stronger driving gate dominates short for only one logic value
Behavior has been observed in ASICs and FPGAs
Disadvantage: 4 faults per fault site
2 vectors (01 and 10) with 2 outputs (A’ and B’)
harder to detect than Wired-
Wired-AND/OR BF (less(less observable)
observable)
dominant-AND/OR BFs ⇒ detects all dominant
Detecting all dominant-
BFs and all Wired-
Wired-AND/OR BFs
Dominant-AND fault model
A A’ A A’
AB A’B’ AdandB BdandA AdorB BdorA
B B’ B B’ 00 00 00 00 00 00
A Dom-AND B B Dom-AND A 01 01 00 01 01 11
Dominant-OR fault model 10 10 10 00 11 10
A A’ A A’ 11 11 11 11 11 11
B B’ B B’
A Dom-OR B B Dom-OR A
C. Stroud 6/08 Fault Models, Detection & 21
Simulation
Bridging Fault Extraction
Considering all possible shorts between any two wires is not practical
Large number of faults to simulate
For N wires, number of possible fault sites = N-choose N2-N)/2
choose--2 = ((N
# faults = N2-N for dominant and wired-
wired-AND/OR bridging faults
# faults = 2(
2(NN2-N) for dominant-
dominant-AND/OR bridging faults
But wires at opposite sides of IC or PCB not likely to short
Capacitance extraction identifies those wires most likely to short
Parallel plate capacitance, C = εA/d
Proportional to area of parallelism, A d1 d2
Inversely proportional to distance between wires, d l
Also proportional to probability of bridging fault
d1 << d2
Weighted fault coverage FCWBF Higher
More accurate FC D probability of
∑C i
bridging
faults d
FCWBF = i =1
T
l1
l2
∑C
j =1
j
d
l1 >> l2
70%
Bridging Original New BF 60%
Fault Test Test 50%
Un-
Un- 30%
57.5% 96.5% 20%
weighted
10%
Weighted 29.9% 99.994%
0%
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C. Stroud 6/08 Fault Models, Detection & 23
Simulation
Fault Detection
Recall:
Fault detection requires:
observation of an error (from fault) at a primary output
observability of the fault site
the ease at which we can observe the fault behavior
input stimuli that creates an error as a result of fault
controllability of the fault site
the ease at which we can control the fault behavior
controllability of path from fault site to primary output
typically considered part of observability
But any given fault may be:
Detectable
Undetectable
Potentially detectable
C. Stroud 6/08 Fault Models, Detection & 24
Simulation
Gate Level Fault Detection - Path Sensitization