US009 178423B2

(12) United States Patent (10) Patent No.: US 9,178.423 B2

Min et al. (45) Date of Patent: Nov. 3, 2015

(54) RAMP CIRCUIT AND DIRECT CURRENT
(DC)-DC CONVERTER THEREOF
(71) Applicant: MagnaChip Semiconductor, Ltd.,
Cheongju-si (KR)
(72) Inventors: Jun Sik Min, Cheongju-si (KR);
Hyoung Kyu Kim, Cheongju-si (KR):
Tae Kyoung Kang, Cheongju-si (KR)
(58) Field of Classification Search
CPC. H02M 3/156; H02M 3/1588; H02M 3/1563:
G05F 3/362; G05F 3/30; G05F 3/265
USPC .................................. 323/282,288,315, 316
See application file for complete search history.
(56) References Cited
U.S. PATENT DOCUMENTS

(73) Assignee: Magnachip Semiconductor, Ltd., 5,973,490 A * 10/1999 Nauta ........................... 323,316
Cheongju-si (KR) 6,768,655 B1* 7/2004 Yang et al. ... 363.21.01
2002/0057079 A1* 5, 2002 Horie ............................ 323,282
2006/0164168 A1* 7/2006 Liu et al. ....................... 330,296
(*) Notice: Subject to any disclaimer, the term of this
patent is extended or adjusted under 35 FOREIGN PATENT DOCUMENTS
U.S.C. 154(b) by 91 days.
KR 10-2012-0000426 A 1, 2012
(21) Appl. No.: 14/225,820
* cited by examiner
(22) Filed: Mar. 26, 2014
Primary Examiner — Adolf Berhane
(65) Prior Publication Data
US 2014/O347O3O A1 Nov. 27, 2014 (57) ABSTRACT
Provided area ramp circuit and a DC-DC converter. The ramp
(30) Foreign Application Priority Data circuit generates a current flowing in a resistor using Voltages
affected by an output voltage and an input Voltage of a DC
May 23, 2013 (KR) ........................ 10-2013-0058437 DC converter, and generates a ramp signal through copying of
the current and charging and discharging of a capacitor using
(51) Int. C. a current mirror unit. The ramp signal is generated by con
H02M 3/56 (2006.01) sidering the input Voltage and the output Voltage, and thus the
G05F 3/30 (2006.01) ramp signal has an optimal slope to provide an adaptive
H02M 3/58 (2006.01) response to state change in the input Voltage and the output
H02M I/4 (2006.01) voltage. The DC-DC converter uses such a ramp circuit to
(52) U.S. C. facilitate its operation.
CPC .............. H02M 3/158 (2013.01); H02M 1/143
(2013.01) 20 Claims, 4 Drawing Sheets

100

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sR RESET SW C
104
U.S. Patent Nov. 3, 2015 Sheet 1 of 4 US 9,178.423 B2

FIG. 1

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U.S. Patent Nov. 3, 2015 Sheet 2 of 4 US 9,178.423 B2

FIG 2
U.S. Patent Nov. 3, 2015 Sheet 3 of 4 US 9,178.423 B2

FIG 3
100
-- - - - -- -- - --- -- - - - - - - -- -- -- - - - - --
U.S. Patent Nov. 3, 2015 Sheet 4 of 4 US 9,178.423 B2
 US 9,178.423 B2
1.
RAMP CIRCUIT AND DIRECT CURRENT
(DC)-DC CONVERTER THEREOF
CROSS-REFERENCE TO RELATED
APPLICATIONS
This application claims the benefit under 35 U.S.C. S 119
(a) of Korean Patent Application No. 10-2013-0058437 filed
on May 23, 2013, in the Korean Intellectual Property Office,
the entire disclosure of which is incorporated herein by ref
erence for all purposes.
BACKGROUND
1. Field
The following description relates to a direct current (DC)-
DC converter. The following description also relates to a ramp
circuit that improves output characteristics by appropriately
compensating a slope of a ramp signal according to an input
Voltage and an output Voltage of a current-controlled mode
DC-DC converter, and a corresponding DC-DC converter.
2. Description of Related Art
DC-DC converters include an inductor and a power switch,
and are configured to store input power in the inductor and
transmit the power. It is theoretically possible for a DC-DC
converters have 100% efficiency, or close to such efficiency.
Therefore, as recent integrated circuit technology has devel
oped, two or more DC-DC converters are used as an efficient
power management circuit in the field of portable apparatus
design. Such DC-DC converters are also used in fields of
design for apparatuses that require considerable power. Such
as displays for computers, home appliances, or lights for
vehicles.
DC-DC converters are divided into two types of DC-DC
converters, including DC-DC converters that use a Voltage
controlled mode and DC-DC converters that use a current
controlled mode, according to the control method that is used
in the DC-DC converter.
A voltage-controlled mode DC-DC converter includes a
simple design because the voltage-controlled mode DC-DC
converter generates a pulse for driving a power Switch only
using a specific output voltage. However, because the DC-DC
converter operates in a Switching frequency lower thanan LC
resonant frequency in order to have stable frequency stability,
the voltage-controlled mode DC-DC converter has a small
frequency range.
Alternatively, because a current-controlled mode DC-DC
converter generates a pulse for driving a power Switch using
an inductor current, the current-controlled mode DC-DC con
verter operates more stably than in the voltage-controlled
mode, without a limitation of an LC resonant frequency. The
current-controlled mode DC-DC converter must sense the
inductor current stably without reduction of an efficiency.
However, the current-controlled mode DC-DC converter
reduces the number of devices outside the chip or a size of the
device by comparison to a DC-DC converter in the voltage
controlled mode. Therefore, the current-controlled mode DC
DC converter is used in various fields for purposes where
these aspects are beneficial.
The current-controlled mode DC-DC converter uses a
ramp signal as a signal for generating a pulse width modula
tion (PWM) signal. The PWM signal produced from the ramp
signal is used to remove Sub-harmonic oscillation produced
by the DC-DC converter. Thus, in the current-controlled
mode DC-DC converter, when an output power is larger than
an input power, a PWM signal has a duty ratio of 50% or
more, and an inductor current operates in a continuous current
2
mode (CCM). When the current-control mode DC-DC con
verter operates in a CCM mode, and requires a duty ratio 50%
or more, there is sub-harmonic oscillation. For example, there
is sub-harmonic oscillation in which the inductor current is
oscillated in a 1/N frequency of a base wave is caused due to
characteristics of an inductor. When the duty ratio is 50% or
less, the Sub-harmonic oscillation is not caused, and hence the
ramp signal is not used.
The ramp signal used for preventing the Sub-harmonic
10 oscillation of the current-controlled mode DC-DC converter
has a sawtooth shape having a certain slope. The ramp signal
is closely related to a sensing signal used for sensing a current
flowing in an inductor or a power Switch. That is, the ramp
signal has to be output so as to remove the Sub-harmonic
15 oscillation, after slope compensation is performed, to provide
a suitable slope to be used as the sensing signal. The slope
compensation of the ramp signal is described with reference
to FIG.1.
FIG. 1 is a waveform diagram illustrating a relationship
between a sensing signal and a slope of a ramp signal in a
current-controlled mode DC-DC converter. Hereinafter, a
current-controlled mode DC-DC converter is referred to sim
ply as a DC-DC converter, although certain aspects of certain
examples may also apply to a Voltage-controlled mode DC
25 DC converter.
In FIG. 1, (a) is a waveform of a sensing signal (SENSE),
(b) is a waveform of a ramp signal (RAMP), and (c) is a
waveform of a signal (VISEN) in which the sensing signal
and the ramp signal are combined. The signals are signals that
30 are applied to a non-inverting (+) terminal of a comparator
configured to generate a PWM signal for the DC-DC con
verter. In FIG. 1, the reference numeral m1 denotes a rising
slope of the sensing signal, m2 denotes a falling slope of the
sensing signal, and m3 denotes a slope value of the ramp
35 signal.
The suitable slope compensation in the DC-DC converter
of FIG. 1 has to satisfy a condition in which the slope m3 of
the ramp signal is at least twice as large as the falling slope m2
of the sensing signal.
40 That is, Equation 1 is as follows, and Summarizes a condi
tion for the relationships between the slopes.
Equation 1
Here, ml>V/L. m2a(V-V)/L. V., is the input Volt
45 age, and V, is the output Voltage.
The slope m3 and falling slope m2 have opposite signs,
because slope m3 must have a value that compensates for
falling slope m2.
A magnitude of the rising slope ml of the sensing signal is
50 proportional to an input voltage of the DC-DC converter.
Additionally, a magnitude of the falling slope m2 of the
sensing signal is proportional to a difference between an
output voltage and the input voltage of the DC-DC converter.
Therefore, when the input Voltage is increased, the falling
55 slope m2 decreases, and when the output voltage is increased,
the falling slope m2 increases.
Theoretically, when a value of the slope m3 of the ramp
signal is set to 0.5 times of m2, slope compensation is suc
cessful for all duty ratios.
60 However, due to relationships between the rising slope and
the falling slope and between the input Voltage and the output
Voltage, the value of the slope m3 of the ramp signal has to be
set based on both the output Voltage and the input Voltage.
When the value of the slope m3 of the ramp signal is not
65 Suitably compensated, several issues arise. When the slope
m3 of the ramp signal is too small, the Sub-harmonic oscilla
tion is not removed properly. When the slope m3 of the ramp
 US 9,178.423 B2
3 4
signal is too large, input/output characteristics of the DC-DC
converter are degraded. For example, a dynamic characteris
tic of the DC-DC converter is degraded or usable power is
reduced.
To maintain a stable operation state of the DC-DC con
Verter, the slope m3 of the ramp signal is restricted to have a
Suitable value. Thus, as described above, compensation is
continuously made to maintain the slope as being at least
twice larger than (m2-m1), as presented in Equation 1, above.
To this end, a ramp circuit for slope compensation is used.
Such a ramp circuit compensates slope m3 to cause it to
maintain a suitable value.
FIG. 2 is a view illustrating a configuration of a ramp
circuit.
The ramp circuit 10 includes an operation amplifier 12. The
operation amplifier 12 receives a first voltage (VA) that is
affected by an output voltage, applied to a non-inverting (+)
terminal of the operation amplifier 12.
The ramp circuit 10 also includes a first PMOS transistor
14 to which a power voltage (VDD) is applied to its source,
and a first NMOS transistor 16 of which a drain is connected
to a drain of the first PMOS transistor 14. An output signal of
the operational amplifier 12 is input to a gate of the first
NMOS transistor 16, and a source signal of the first NMOS
transistor 16 is applied to an inverting (-) terminal of the
operational amplifier 12.
A resistor (R) of which one side is connected to a ground is
also connected to a source of the first NMOS transistor 16.
A second voltage (NA) of the operational amplifier 12 is
applied to a node a between the first NMOS transistor 16 and
the resistor (R).
The ramp circuit 10 also includes a second PMOS transis
tor 18 that forms a current mirror structure with the first
PMOS transistor 14. The Second PMOS transistor 18 receives
the power voltage (VDD) at a source. A capacitor (C) of
which one side is grounded is connected to a drain of the
second PMOS transistor 18. An output terminal, which out
puts a ramp signal (RAMP), is connected to a node b between
the second PMOS transistor 18 at a drain and the capacitor
(C). A switch (SW), configured to turn on and off according to
a reset signal (RESET), is connected parallel to the capacitor
(C).
The ramp circuit 10 for slope compensation copies a cur
rent flowing through the resistor (R), that is, a current value
VA/R in which an interlock voltage (VA) is divided by the
resistor (R) using a current mirror structure to the second
PMOS transistor 18. The ramp circuit 10 charges/discharges
a current flowing through the drain of the second PMOS
transistor 18 into the capacitor (C). Accordingly, the ramp
signal (RAMP) generated according to the charge/discharge
operation is output through an output terminal connected to
the node b.
However, the ramp circuit in this approach generates the
ramp signal by considering only output Voltage, as described
above.
When a slope of the ramp signal is set by considering a case
in which an input Voltage is at its lowest, excessive slope
compensation is potentially performed when the input Volt
age is increased. Thus, the excessive slope compensation
potentially leads to slope compensation that is more than a
preset driving range, to impair dynamic characteristics of the
DC-DC converter.
When the input voltage is reduced with respect to the
driving range that the ramp circuit is able to compensate for,
the slope compensation is not accomplished, and thus the
Sub-harmonic oscillation is still present. This means that the
ramp circuit, which is used for eliminating the Sub-harmonic
oscillation, is not functioning properly.
As described above, since the slope-compensated ramp
signal is generated in the previous examples based only on the
output voltage of the DC-DC converter, the scenario in which
an oscillation or degradation of input/output characteristics of
the DC-DC converter is generated by a change in the input
Voltage, is not completely eliminated.
10 SUMMARY
This Summary is provided to introduce a selection of con
cepts in a simplified form that are further described below in
the Detailed Description. This Summary is not intended to
15 identify key features or essential features of the claimed sub
ject matter, nor is it intended to be used as an aid in determin
ing the scope of the claimed Subject matter.
Examples provide a ramp circuit that variably changes a
slope of a ramp signal according to changes in an input
voltage and an output voltage of a DC-DC converter and
provides the ramp signal to the DC-DC converter.
Other examples provide a DC-DC converter that improves
output characteristics by employing a ramp circuit configured
to adjust a slope of a ramp signal according to change in an
25 input voltage and an output Voltage.
In one general aspect, a ramp circuit includes a first ampli
fier configured to receive a first Voltage corresponding to an
output Voltage, a second amplifier configured to receive a
second Voltage corresponding to an input Voltage, a resistor
30 provided between output terminals of the first amplifier and
the second amplifier, a current mirror unit configured to copy
a current value that flows in the resistor, and an output unit
configured to control a current output from the current mirror
unit into a capacitor to output a ramp signal through an output
35 terminal of the output unit.
The current mirror unit may include a first transistor and a
second transistor of which a power Voltage is received
through sources and whose gates are connected to each other,
a drain of the first transistor may be connected to the gates of
40 the first transistor and second transistor, and a current value
flowing in the resistor may be transferred to the second tran
sistor through current copying from the first transistor.
The ramp circuit may further include a third transistor, and
the third transistor may be connected to the output terminal of
45 the first amplifier, a drain of the third transistor may be con
nected to the drain of the first transistor, and a source of the
third transistor may be connected to one side of the resistor.
The first and second transistors may be PMOS transistors,
and the third transistor may be an NMOS transistor.
50 The ramp circuit may further include a switch connected
parallel to the capacitor, and the Switch may be configured to
perform a Switching operation based on a reset signal.
The slope of the ramp signal may be varied according to the
output Voltage and the input Voltage.
55 When the output voltage is increased, the slope of the ramp
signal may be increased.
When the input voltage is increased, the slope of the output
Voltage may be reduced.
The current value may be determined to have the value of
60 the difference between a first Voltage and a second Voltage,
divided by a resistor value.
The first amplifier may be configured to receive the first
Voltage at a non-inverting (+) terminal, and the second ampli
fier may be configured to receive the second Voltage at a
65 non-inverting (+) terminal.
An output-side voltage of the first amplifier may be fed
back to an inverting (-) terminal of the first amplifier and an
 US 9,178.423 B2
5 6
output-side voltage of the second amplifier may be fed back to Throughout the drawings and the detailed description,
an inverting (-) terminal of the second amplifier. unless otherwise described or provided, the same drawing
In another general aspect, a direct current (DC)-DC con reference numerals will be understood to refer to the same
Verter includes a ramp circuit configured to vary a slope of a elements, features, and structures. The drawings may not be
ramp signal according to an input voltage and an output 5 to scale, and the relative size, proportions, and depiction of
Voltage and output the ramp signal, a comparator configured elements in the drawings may be exaggerated for clarity,
to receive a signal in which the ramp signal and a sensing illustration, and convenience.
signal of an inductor are combined through a non-inverting DETAILED DESCRIPTION OF THE
(+) terminal, and configured to receive an output signal of an 10 EMBODIMENTS
error amplifier through an inverting (-) terminal, a logic
device configured to generate a pulse width modulation The following detailed description is provided to assist the
(PWM) signal according to an output signal of the compara readeringaining a comprehensive understanding of the meth
tor and a clock signal; and a power Switch configured to turn ods, apparatuses, and/or systems described herein. However,
on and off by the PWM signal. 15 various changes, modifications, and equivalents of the sys
The ramp circuit may include a first amplifier and a second tems, apparatuses and/or methods described herein will be
amplifier configured to output Voltage values according to the apparent to one of ordinary skill in the art. The progression of
input voltage and the output Voltage, and a resistor connected processing steps and/or operations described is an example:
between output terminals between the first amplifier and the however, the sequence of and/or operations is not limited to
second amplifier. that set forth herein and may be changed as is known in the art,
The ramp circuit may further include a current mirror unit with the exception of steps and/or operations necessarily
configured to copy a current value that flows in the resistor. occurring in a certain order. Also, descriptions of functions
The ramp circuit may further include an output unit con and constructions that are well known to one of ordinary skill
figured to controla current output from the current mirror unit in the art may be omitted for increased clarity and concise
into a capacitor to output a ramp signal through an output 25 CSS.
terminal of the output unit. The features described herein may be embodied in differ
In another general aspect, a ramp circuit includes a resistor ent forms, and are not to be construed as being limited to the
provided between output terminals of a first amplifier config examples described herein. Rather, the examples described
ured to receive a first Voltage corresponding to an output herein have been provided so that this disclosure will be
Voltage and a second amplifier configured to receive a second 30 thorough and complete, and will convey the full scope of the
Voltage corresponding to an input Voltage, a current mirror disclosure to one of ordinary skill in the art.
unit configured to copy a current value that flows in the It will be understood that, although the terms first, second,
resistor, and an output unit configured to control a current A, B, etc. may be used herein in reference to elements of the
output from the current mirror unit into a capacitor to output invention, Such elements should not be construed as limited
a ramp signal through an output terminal of the output unit. 35 by these terms. For example, a first element could be termed
The current mirror unit may include a first transistor and a a second element, and a second element could be termed a
second transistor of which a power Voltage is received first element, without departing from the scope of the present
through sources and whose gates are connected to each other, invention. Herein, the term “and/or includes any and all
a drain of the first transistor may be connected to the gates of combinations of one or more referents.
the first transistor and second transistor, and a current value 40 The terminology used herein is for the purpose of describ
flowing in the resistor may be transferred to the second tran ing particular embodiments only and is not intended to be
sistor through current copying from the first transistor. limiting of the present inventive concept. As used herein, the
The ramp circuit may further include a third transistor, and singular forms “a” “an and “the are intended to include the
the third transistor may be connected to the output terminal of plural forms as well, unless the context clearly indicates oth
the first amplifier, a drain of the third transistor may be con- 45 erwise. It will be further understood that the terms “com
nected to the drain of the first transistor, and a source of the prises' and/or "comprising, when used in this specification,
third transistor may be connected to one side of the resistor. specify the presence of stated features, integers, steps, opera
The slope of the ramp signal may be varied according to the tions, elements, and/or components, but do not preclude the
output Voltage and the input Voltage. presence or addition of one or more other features, integers,
The current value may be determined to have the value of 50 steps, operations, elements, components, and/or groups
the difference between a first Voltage and a second Voltage, thereof.
divided by a resistor value. In examples, a ramp signal is appropriately slope-compen
Other features and aspects will be apparent from the fol sated by considering changes in an output Voltage and an
lowing detailed description, the drawings, and the claims. input Voltage of a DC-DC converter. The ramp signal is gen
55 erated to stably maintain an operation of a DC-DC converter.
BRIEF DESCRIPTION OF THE DRAWINGS Examples improve output characteristics of the DC-DC con
Verter, even when a duty ratio changes according to condi
FIG. 1 is a waveform diagram illustrating a relationship tions of an input Voltage and an output Voltage.
between a sensing signal and a ramp signal in a DC-DC Hereinafter, examples of a ramp circuit and a DC-DC
converter. 60 converter using Such a ramp circuit are described with refer
FIG. 2 is a view illustrating a configuration of a ramp ence to the accompanying drawings.
circuit in the related art. First, a configuration of a ramp circuit is described with
FIG. 3 is a view illustrating a configuration of a ramp reference to FIG. 3. FIG. 3 is a view illustrating a configura
circuit according to an example. tion of a ramp circuit according to an example.
FIG. 4 is a view illustrating an entire configuration of a 65 A ramp circuit 100 includes a first operational amplifier
DC-DC converter to which the ramp circuit of FIG. 3 is 102. The first operational amplifier 102 has a first voltage
applied, according to an example. (VA) affected by an output Voltage input to a non-inverting (+)
 US 9,178.423 B2
7 8
terminal. An output-side voltage (NA) of the first operational
amplifier 102 is fed back to an inverting (-) terminal of the
first operational amplifier 102. The output-side voltage (NA)
has substantially the same voltage level as that of the first
voltage (VA).
In this example, additional elements are added since an
input voltage of the DC-DC converter is to be taken into
consideration, in addition to the output Voltage.
Therefore, the ramp circuit 100 also includes a second
operational amplifier 104 that has a second voltage (VB)
affected by an input Voltage is input to a non-inverting (+)
terminal. An output-side voltage (NB) of the second opera
tional amplifier 104 is fed back to an inverting (-) terminal of
the second operational amplifier 104. The output-side voltage
(NB) has substantially the same voltage level as that of the
second voltage (VB).
Thus, the output-side voltages (NA and NB) are main
tained at the levels of the first voltage (VA) and the second
voltage (VB). As described above, the first voltage (VA) and
the second voltage (VB) are voltages affected by the output
voltage and the input voltage of the DC-DC converter. There
fore, the output-side voltages (NA and NB) are also voltages
affected by the output voltage and the input voltage of the
DC-DC converter. Hereinafter, the output-side voltages (NA
and NB) are referred to as a third voltage and a fourth Voltage,
respectively.
The ramp circuit 100 includes a first PMOS transistor 112
of which a voltage power (VDD) is applied to its source. The
first PMOS transistor 112 forms a current mirror structure
with a second PMOS transistor 114.
The ramp circuit 100 also includes a first NMOS transistor
116 that has a drain that is connected to a drain of the first
PMOS transistor 112. The first NMOS transistor 116 also has
an output signal of the first operational amplifier 102 is input
through a gate, and a source that is connected to the inverting
(-) terminal of the first operational amplifier 102 through a
first node (I).
A resistor (R) is connected between the first node (I)
extending from a source of the first NMOS transistor 116, and
a second node (II) extending from an output terminal of the
second operational amplifier 104. The resistor (R) generates a
current value when the third voltage and the fourth voltage are
applied to both sides of the resistor (R). The current value
flowing in the resistor R has a value of (NA-NB)/R.
The ramp circuit 100 also includes a second PMOS tran
sistor 114. The second PMOS transistor 114 forms a current
mirror structure with the first PMOS transistor 112 and a
power voltage (VDD) is applied to a source of the second
PMOS transistor 114. The current value output through a
drain of the second PMOS transistor 114 according to the
current mirror operation has a value of (NA-NB)/R.
The ramp circuit 100 also includes a capacitor (C) of which
one side is connected to the drain of the second PMOS tran
sistor 114 and the other side is connected to a ground. A
switch (SW) is provided, connected parallel to the capacitor
(C). The switch (SW) performs a switching operation by
selectively transmitting a reset signal (RESET).
The output terminal configured to output a ramp signal
(RAMP) is connected to a third node (III) provided between
the second PMOS transistor 114 and the capacitor (C). In an
example, the ramp signal output through the third node (III) is
used to generate a PWM signal in the DC-DC converter, as is
described further later.
The ramp circuit having the configuration of the example
outputs the ramp signal to have an appropriate slope that is
chosen to provide slope-compensation according to the input
Voltage and the output Voltage.
That is, since the input Voltage and the output Voltage are
taken into consideration in this example, the current value,
which is (VA-VB)/R, in which the fourth voltage is sub
tracted from the third voltage and is divided by the resistor(R)
flows in the resistor (R) located between the first node (I) and
the second node (II). Therefore, in this example, the current
value changes according to changes in the output Voltage and
the input Voltage.
The current value (VA-VB)/R is copied to the second
10 PMOS transistor 114 through the current mirror structure,
and the second PMOS transistor 114 outputs the same current
value as the current value (VA-VB)/R. That is, even when the
current value flowing in the resistor (R) changes continu
ously, the current value sent through the current mirror is
15 copied and transferred to the second PMOS transistor 114
accordingly.
The current value output through a drain of the second
PMOS transistor 114 is charged and discharged to the capaci
tor (C), and a ramp signal generated according to the charge?
discharge operation is output through the output terminal
connected to the third node (III).
The ramp signal output (RAMP) through the output termi
nal in this example includes the characteristic of taking both
input and output Voltages into consideration.
25 That is, the ramp circuit according to the example takes the
input and output voltages into consideration as described
above by using both of them to generate the ramp signal
output (RAMP).
When the output voltage is increased, the first voltage (VA)
30 affected by the output Voltage is input to the non-inverting (+)
terminal of the first operational amplifier 102, and the third
voltage applied to the node I as the output is increased. Hence,
the slope of the ramp signal increases due to these increases in
Voltage. When the input Voltage is increased, the second
35 voltage (VB) affected by the input voltage is input to the
non-inverting (+) terminal of the second operational amplifier
104, and the fourth voltage applied to the node II as the output
is increased. Hence, the slope of the ramp signal decreases
due to these decreases in Voltage.
40 When the output voltage (VA) and the input voltage (VB)
of the DC-DC converter change, the slope, that is, an m3 value
of the ramp signal, as shown in FIG. 1 is changed as well.
Therefore, in the example, a DC-DC converter that has a large
difference between output power and input power, the slope
45 compensation of the ramp signal is still appropriately per
formed according to changes in the input Voltage and the
output Voltage.
FIG. 4 is a view illustrating a configuration of a DC-DC
converter to which the ramp circuit is applied, according to an
50 example.
A DC-DC converter 200 according to the example includes
a sensor 210 configured to sense a current value flowing in the
inductor (or a power switch) since the DC-DC converter 200
operates in a current-controlled mode. The sensor 210 is
55 directly connected to the power switch (SW). In an example,
as the power switch (SW), a NMOS transistor is used.
A PWM signal generator 220 configured to generate a
PWM signal for turning on/off the power switch (SW) is
included. The PWM signal generator 220 includes a com
60 parator 222 and a SR-latch 224 configured to receive an
output of the comparator 222 and a clock signal (CLK).
Therefore, the PWM signal is generated by driving the SR
latch 224 by the clock signal (CLK) and the output of the
comparator 222.
65 The comparator 222 receives as inputs two different sig
nals. An output signal (VERR) of an error amplifier 226 is
input to an inverting (-) terminal of the comparator 222. A
 US 9,178.423 B2
signal (VISEN) in which a sensing signal and a ramp signal
are combined is input to a non-inverting (+) terminal of the
comparator 222. The sensing signal is a current value sensed
by the sensor 210, and the ramp signal is a signal transferred
from the ramp circuit (see 100 of FIG. 3) suggested for slope
compensation.
A reference voltage (VREF) is applied to a non-inverting
(+) terminal of the error amplifier 226, and a feedback voltage
is applied to an inverting (-) terminal. The feedback Voltage
is transferred from the output unit 230 of the DC-DC con
verter 200. Further, a capacitor (CC) and a resistor (RZ) con
nected parallel to an output side of the error amplifier 226 are
configured to perform frequency compensation.
When the DC-DC converter 200 generates the PWM sig
nal, the ramp signal generated in the ramp circuit 100 of FIG.
3 is transferred, and the slope of the ramp signal can be
appropriately compensated based on the interaction of the
elements in the DC-DC converter 200 with the ramp circuit
1OO of FIG. 3.
According to the above-described example, the ramp sig
nal has a slope of an optical condition. The slope is based on
considering the state change between the input Voltage and
the output voltage of the DC-DC converter. Therefore, an
operation of the DC-DC converter is stable and output char
acteristics are improved.
The ramp circuit having the above-described configuration
and the DC-DC converter including the ramp circuit accord
ing to the example has the following effects.
The example takes changes in both the input Voltage and
output voltage of the DC-DC converter into consideration.
That is, the ramp circuit adaptively responds to the changes in
both the output Voltage and input Voltage to generate a ramp
signal having an optimal slope.
Therefore, sub-harmonic oscillation caused when the ramp
signal slope-compensates by considering only the output
voltage can be completely removed. An effect of improved
input/output characteristics of the DC-DC converter accord
ing to use of the stable ramp signal results.
The apparatuses and units described herein may be imple
mented using hardware components. The hardware compo
nents may include, for example, controllers, sensors, proces
sors, generators, drivers, and other equivalent electronic
components. The hardware components may be implemented
using one or more general-purpose or special purpose com
puters, such as, for example, a processor, a controller and an
arithmetic logic unit, a digital signal processor, a microcom
puter, a field programmable array, a programmable logic unit,
a microprocessor or any other device capable of responding to
and executing instructions in a defined manner. The hardware
components may run an operating system (OS) and one or
more software applications that run on the OS. The hardware
components also may access, store, manipulate, process, and
create data in response to execution of the software. For
purpose of simplicity, the description of a processing device is
used as singular; however, one skilled in the art will appreci
ate that a processing device may include multiple processing
elements and multiple types of processing elements. For
example, a hardware component may include multiple pro
cessors or a processor and a controller. In addition, different
processing configurations are possible, such as parallel pro
CSSOS.
The methods described above can be written as a computer
program, a piece of code, an instruction, or some combination
thereof, for independently or collectively instructing or con
figuring the processing device to operate as desired. Software
and data may be embodied permanently or temporarily in any
10
type of machine, component, physical or virtual equipment,
computer storage medium or device that is capable of provid
ing instructions or data to or being interpreted by the process
ing device. The software also may be distributed over network
5 coupled computer systems so that the Software is stored and
executed in a distributed fashion. In particular, the software
and data may be stored by one or more non-transitory com
puter readable recording mediums. The media may also
10
include, alone or in combination with the Software program
instructions, data files, data structures, and the like. The non
transitory computer readable recording medium may include
any data storage device that can store data that can be there
after read by a computer system or processing device.
15 Examples of the non-transitory computer readable recording
medium include read-only memory (ROM), random-access
memory (RAM), Compact Disc Read-only Memory (CD
ROMs), magnetic tapes, USBs, floppy disks, hard disks, opti
cal recording media (e.g., CD-ROMs, or DVDs), and PC
interfaces (e.g., PCI, PCI-express, WiFi, etc.). In addition,
functional programs, codes, and code segments for accom
plishing the example disclosed herein can be construed by
programmers skilled in the art based on the flow diagrams and
block diagrams of the figures and their corresponding
25 descriptions as provided herein.
As a non-exhaustive illustration only, a terminal/device?
unit described herein may refer to mobile devices such as, for
example, a cellular phone, a Smartphone, a wearable Smart
device (such as, for example, a ring, a watch, a pair of glasses,
30 a bracelet, an ankle bracket, a belt, a necklace, an earring, a
headband, a helmet, a device embedded in the cloths or the
like), a personal computer (PC), a tablet personal computer
(tablet), a phablet, a personal digital assistant (PDA), a digital
camera, a portable game console, an MP3 player, a portable/
35 personal multimedia player (PMP), a handheld e-book, an
ultra mobile personal computer (UMPC), a portable lab-top
PC, a global positioning system (GPS) navigation, and
devices such as a high definition television (HDTV), an opti
cal disc player, a DVD player, a Blu-ray player, a setup box,
40 or any other device capable of wireless communication or
network communication consistent with that disclosed
herein. In a non-exhaustive example, the wearable device
may be self-mountable on the body of the user, such as, for
example, the glasses or the bracelet. In another non-exhaus
tive example, the wearable device may be mounted on the
45 body of the user through an attaching device, such as, for
example, attaching a Smartphone or a tablet to the arm of a
user using an armband, or hanging the wearable device
around the neck of a user using a lanyard.
While this disclosure includes specific examples, it will be
50 apparent to one of ordinary skill in the art that various changes
in form and details may be made in these examples without
departing from the spirit and scope of the claims and their
equivalents. The examples described herein are to be consid
55
ered in a descriptive sense only, and not for purposes of
limitation. Descriptions of features or aspects in each
example are to be considered as being applicable to similar
features or aspects in other examples. Suitable results may be
achieved if the described techniques are performed in a dif
60 ferent order, and/or if components in a described system,
architecture, device, or circuit are combined in a different
manner and/or replaced or Supplemented by other compo
nents or their equivalents. Therefore, the scope of the disclo
sure is defined not by the detailed description, but by the
65 claims and their equivalents, and all variations within the
Scope of the claims and their equivalents are to be construed
as being included in the disclosure.
 US 9,178.423 B2
11 12
What is claimed is: a comparator configured to receive a signal in which the
1. A ramp circuit, comprising: ramp signal and a sensing signal of an inductor are
a first amplifier configured to receive a first voltage corre combined through a non-inverting (+) terminal, and con
sponding to an output voltage; figured to receive an output signal of an error amplifier
a second amplifier configured to receive a second voltage 5 through an inverting (-) terminal;
corresponding to an input voltage; a logic device configured to generate a pulse width modu
a resistor provided between output terminals of the first lation (PWM) signal according to an output signal of the
amplifier and the second amplifier; comparator and a clock signal; and
a current mirror unit configured to copy a current value that a power switch configured to turn on and off by the PWM
flows in the resistor; and 10 signal.
an output unit configured to control a current output from circuit 13. The DC-DC converter of claim 12, wherein the ramp
the current mirror unit into a capacitor to output a ramp comprises:
signal through an output terminal of the output unit. a first amplifier and a second amplifier configured to output
2. The ramp circuit of claim 1, wherein the current mirror Voltage values according to the input voltage and the
unit comprises a first transistor and a second transistor of 15 output Voltage; and
which a power Voltage is received through sources and whose a resistor connected between output terminals between the
gates are connected to each other, first amplifier and the second amplifier.
a drain of the first transistoris connected to the gates of the circuitThe
14. DC-DC converter of claim 13, wherein the ramp
further comprises:
first transistor and second transistor, and
a current value flowing in the resistor is transferred to the 20 a current mirror unit configured to copy a current value that
flows in the resistor.
Second transistor through current copying from the first
transistor. 15. The DC-DC converter of claim 14, wherein the ramp
3. The ramp circuit of claim 2, further comprising a third circuit further comprises:
an output unit configured to control a current output from
transistor,
wherein the third transistor is connected to the outputter- 25 the current mirror unit into a capacitor to output a ramp
minal of the first amplifier, signal through an output terminal of the output unit.
a drain of the third transistoris connected to the drain of the 16. A ramp circuit, comprising:
first transistor, and a resistor provided between output terminals of a first
a source of the third transistor is connected to one side of amplifier configured to receive a first voltage corre
the resistor. 30 sponding to an output voltage and a second amplifier
4. The ramp circuit of claim3, wherein the first and second configured to receive a second voltage corresponding to
transistors are PMOS transistors, and the third transistor is an an input voltage;
NMOS transistor. a current mirror unit configured to copy a current value that
5. The ramp circuit of claim 1, further comprising a switch flows in the resistor; and
connected parallel to the capacitor, and wherein 35 an output unit configured to control a current output from
the Switch is configured to perform a switching operation the current mirror unit into a capacitor to output a ramp
based on a reset signal. signal through an output terminal of the output unit.
6. The ramp circuit of claim 1, wherein the slope of the mirror The 17. ramp circuit of claim 16, wherein the current
unit comprises a first transistor and a second transistor
ramp signal is varied according to the output voltage and the of which a power voltage is received through sources and
input voltage. 40
7. The ramp circuit of claim 6, wherein when the output whose gates are connected to each other,
Voltage is increased, the slope of the ramp signal is increased. a drain of the first transistor is connected to the gates of the
8. The ramp circuit of claim 6, wherein when the input first transistor and second transistor, and
Voltage is increased, the slope of the output voltage is a current value flowing in the resistor is transferred to the
reduced. 45 second transistor through current copying from the first
transistor.
9. The ramp circuit of claim 1, wherein the current value is 18. The ramp circuit of claim 17, further comprising a third
determined to have the value of the difference between a first
Voltage and a second Voltage, divided by a resistor value. transistor,
10. The ramp circuit of claim 1, wherein the first amplifier wherein the third transistor is connected to the outputter
is configured to receive the first voltage at a non-inverting (+) 50 a drainminal of the first amplifier,
of the third transistoris connected to the drain of the
terminal, and the second amplifier is configured to receive the first transistor, and
Second Voltage at a non-inverting (+) terminal. a source of the third transistor is connected to one side of
11. The ramp circuit of claim 10, wherein an output-side the resistor.
Voltage of the first amplifier is fed back to an inverting (-) 19. The ramp circuit of claim 16, wherein the slope of the
terminal of the first amplifier and an output-side voltage of the 55 ramp signal
second amplifier is fedback to an inverting (-) terminal of the input Voltage.is varied according to the output voltage and the
second amplifier.
12. A direct current (DC)-DC converter comprising: 20. The ramp circuit of claim 16, wherein the current value
a ramp circuit configured to vary a slope of a ramp signal is determined to have the value of the difference between a
according to an input voltage and an output voltage and 60 first Voltage and a second voltage, divided by a resistor value.
output the ramp signal; ck ck ck ck ck