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BUS COMMUNICATION

A data connection between two or more devices connected to


the computer

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Bus uses

Used to connect major components


• CPU

• DMA

• Memory modules

• Peripheral devices, etc.

• Can be synchronous or asynchronous

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Different Buses

• Buses that work in sync with CPU and system clock are called the local buses

or system buses.

• Buses that work asynchronously with the CPU are called the expansion buses.

• Ex. The memory bus is a local bus while the ISA bus is an expansion bus.

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What Does a Bus carry?
• Electrical Power.
• Control Signals.
• Memory Address.
• Data.

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Bus Communication for networking
• Bus communication simplifies the number of connections
and provides a common way (protocol) of connecting
different or same type of I/O devices

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IO Bus
• I/O devices communicate with the processor through an I/O
bus, which is separate from the memory bus that the
processor uses to communicate with the memory system.

• A bus has a fixed bandwidth that must be shared by all of


the devices on the bus.

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Serial Bus
• A serial bus has very few lines and the number of lines as
per the protocol.
• A wide range of I/O devices without having to implement a
specific interface for each I/O device.
• All can communicate through a common serial bus.

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Parallel Bus
• Using a parallel I/O bus allows a computer or controller or
embedded system to interface with number of internal
systems at very short distances without having to implement
a specific interface for each I/O device.

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Local Bus
• A set of parallel conductors,
which allow devices attached to
it to communicate with the
CPU.
• The bus consists of three main
parts:
– Control lines, Address lines, Data
lines

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Serial communication bus

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Serial communication bus types

• I2C Bus – Inter-Integrated Circuit

• CAN Bus – Controller Area Network

• USB Bus – Universal Serial Bus

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Parallel communication bus

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Parallel communication bus types

• ISA bus – Industry Standard Architecture

• EISA bus – Extended Industry Standard Architecture

• PCI bus – Peripheral Component Interconnect

• PCI-X bus – Peripheral Component Interconnect eXtended

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ISA bus – Industry Standard
Architecture

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ISA BUS

8-bit
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ISA (8 Bit) Buses
• Used in the first 4.77-MHz PCs introduced in 1982.
• 62 - Pin Bus.
• 8 Data Lines (allowing for 8 bits of data to be transferred at a time).
• 20 address lines (1 Mbytes of addressing ).

ISA (16 Bit) Buses


• 8.33-MHz Bus introduced in 1984.
• 62 + 36 - Pin Bus.
• Eight more data lines (allowing for 16-bit data transfers).
• Four more address lines (allowing 16 Mbytes of addressing).
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ISA BUS
More More
DMA IRQ lines DMA ± 5, ±12V
IRQ lines
8 - 15 clock lines Power & G
lines 2-7

Extra 8 bits of Extra 4 bits of 20 bits of Address bus


I/O bus Address bus 8 bits of I/O bus

16 bit Original 8 bit ISA

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ISA Bus
• The BUS is divided into two sides.
• The first side pins are named A1 to A31 and it
is the components side.
– It consists of the address and data buses.
• The second side pins are named B1 to B31
and it is the solder side.
– This side contents the power pins and the signals
related to interrupts and DMA transfers.

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ISA Bus
Advantages Disadvantages
• Low cost • Low speed
• Compatibility • Jumpers and DIP switches
• Becoming out-dated
• Used widely
• Limited number of interrupts.
• No central registry.

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EISA – Extended Industry
Standard Architecture

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EISA – Extended Industry Standard
Architecture
• Developed by the "Gang of Nine" (nine non-IBM manufacturers of
IBM-compatible PCs, led by Compaq) in 1988.
• 32 Bit Bus.
• Runs at 8.33 MHz.
• Pins - 98 + 100 inlay
• The theoretical maximum transfer speed is 33 Mbytes/s.
• Compatible with 8 bit ISA, 16 bit ISA, 32 bit EISA

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EISA
Advantages
• ISA Compatibility: ISA cards will work in EISA slots.
• 32 Bit Bus Width: Like MCA (Micro Channel Architecture, 1987) , the bus was
expanded to 32 bits.
• Bus Mastering: The EISA bus supports bus mastering adapters for greater
efficiency, including proper bus arbitration.
• Plug and Play: EISA automatically configures adapter cards, similar to the Plug
and Play standards of modern systems

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EISA
Disadvantages
• It never became widely used .
• It is no longer found in computers today.

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ISA bus

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ISA BUS

ISA Card

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EISA bus

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EISA – 1988
• EISA card – Does not fit in ISA slot.

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PCI + ISA Bus

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PCI bus

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PCI bus

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PCI Buses – Peripheral
Component Interconnect Buses

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Older PC Implementations

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Newer PC Implementations

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Block diagram of a PCI bus system
Processor/Main Memory System
Copro- Main
CPU Cache
cessor Memory

PCI Motion
Audio
Bridge Video
PCI Bus

SCSI host Interface to LAN Graphics


I/O
adapter Expansion Bus adapter adapter
Expansin Bus (ISA/EISA)

Bus Slot Bus Slot Bus Slot Bus Slot

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PCI Buses – Peripheral Component
Interconnect Buses
• Created by Intel (1992)
• PCI bus, 32 or 64-bit operating at 33 MHz
• PCI-X bus, 32 or 64-bit operating at 66/133 MHz
• Designed to support ISA and EISA buses.
• It interfaces the expansion bus and the memory bus.

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PCI Bus – Peripheral Component
Interconnect Bus
3 main goals:
• To get better performance when transferring data between the computer and
its peripherals.
• uses a higher clock rate (25 or 33 MHz) than ISA.

• To be as platform independent as possible.


• is used extensively on IA-32, Alpha, PowerPC, SPARC64, and IA-64 systems.

• To simplify adding and removing peripherals to the system.


• supports for auto detection of interface boards.

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PCI Express bandwidth comparison

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PCI Technology
Conventional PCI
• It is a parallel bus, synchronous to a single bus clock.
• Initial PCI 1.0 proposal by Intel in 1991
• Introduced by PCI-SIG as PCI 2.0 in 1993
• Version 2.1 approved in 1995
• Recent version 2.3 approved in March 2002
PCI-X
• PCI-X standard was developed jointly by IBM, HP, and Compaq and submitted for
approval in 1998.
• Version 1.0 approved in September 1999
• Version 2.0 approved in July 2002
PCI Express
• High-speed serial computer expansion bus standard, designed to replace the older
PCI, PCI-X, and AGP bus standards
• Formerly known as 3GIO
• Version 1.0 approved in July 2002

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Conventional PCI
• Plug-and-Play Functionality
• Standard PCI is 32 bit and operates at 33 MHz
• Throughput 133 MB/sec
• PCI 2.1 introduced
• Universal PCI cards supporting both 3.3V and 5V
• 32-Bit throughput @ 66 MHz: 266 MB/sec
• 64-Bit throughput @ 66 MHz: 532 MB/sec
• PCI 2.3 system no longer supports 5V-only adapters
• 3.3V and Universal PCI products are still fully supported

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PCI-X 1.0
• Based on existing PCI architecture
• 64-Bit slots with support for 3.3V and Universal PCI
• No support for 5V-only boards!
• Fully backwards-compatible
• Conventional 33/66 MHz PCI adapters can be used in PCI-X slots
• PCI-X adapters can be used in conventional PCI slots
• Provides two speed grades: 66 MHz and 133 MHz

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PCI-X 2.0
• Based on PCI-X 1.0
• Still fully backwards-compatible
• Introduces ECC (Error Correction Codes mechanism to improve
robustness and data integrity)
• Provides two additional speed grades
• PCI-X 266: 266 MHz (2.13 GB/sec)
• PCI-X 533: 533 MHz (4.26 GB/sec)
• Bandwidth sufficient to support new breed of cutting-edge
technologies
• 10 Gigabit Ethernet / Fiber Channel
• 4X/12X infiniBand
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PCI-X Speed Limitations
• PCI-X supports point-to-point and multi-drop loads
• Highest speed grades are supported exclusively with point-to-point
loads
• PCI-X 133
• PCI-X 266
• PCI-X 533
• Two PCI-X 133 loads operate at 100 MHz

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PCI Hardware

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PCI Card Connectors
5V 32-Bit Connector Keyway

33 MHz

5V 64-Bit Connector

3.3V 32-Bit Connector

33/66 MHz

3.3V 64-Bit Connector

Rear Front
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5 V To 3.3 V Migration Path

• 5 Volt Card • Dual-Voltage Card • 3 Volt Card

• 5 Volt • 3 Volt
System • Key away from System • Key near backpanel
backpanel

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PCI Configuration

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Configuration Space Header
Device ID Vendor ID 00
Status Command 04
Class Code Rev 08
BIST Header Type Latency Timer Cache Line Size 0C
Base Address 0 10
Base Address 1 14
Base Address 2 18
Base Address 3 1C
Base Address 4 20
Base Address 5 24
Cardbus CIS Pointer 28
Subsystem ID Subsystem Vendor ID 2C
Expansion ROM Base Address 30
Reserved 34
Reserved 38
Max_Lat Min_Gnt Interrupt Pin Interrupt Line 3C

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System Initialization

• Configuration allows software (BIOS) to initialize the system

• Each device has configuration registers

• At power up software scans bus(es)

• Software analyses system requirements

• Configuration registers are set to configure individual devices

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PCI Configuration Register
• Device ID
• Vendor ID
• Status / Command reg.
• Base Address [0,1,2,3,4,5]
• Maximum Latency
• Minimum GNT
• Subsystem ID, Subsystem Vendor ID

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PCI Configuration Register
• Device ID
• Vendor ID
• Status / Command reg.
• Base Address [0,1,2,3,4,5]
• Maximum Latency
• Minimum GNT
• Subsystem ID, Subsystem Vendor ID

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PCI Command Types [C/BE]
• 0000 -> INTR ack
• 0010 -> I/O Read
• 0011 -> I/O Write
• 0110 -> Memory Read
• 0111 -> Memory Write
• 1010 -> Configuration read
• 1011 -> Configuration write

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PCI device identification
• The hardware circuitry of each peripheral board will know memory
locations, I/O ports, and configuration registers.
• Memory locations and I/O ports are shared by all the devices on a PCI
bus.
• Each PCI peripheral is identified by a bus number(16-bits), combined
by bus (8), device(5), and function(3).
• Using the lspci tool, we can get the information of each PCI peripheral.
• BB:DD.F as three values (bus, device, and function)

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Each PCI device on Bus
• May contain a processor and software to perform a specific function.
• Each device has the specific memory address-range, specific
interrupt-vectors and the device I/O port addresses.
• A bus of appropriate specifications and protocol interfaces these to
the host computer system or compute
• PCI bus unique feature is its configuration address space.

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PCI controller Features
• Accesses one device at a time
• All the devices within host device or system can share the I/O port
and memory addresses, but cannot share the configuration registers
• Device cannot modify other configuration registers but can access
other device resources or share the work or assist the other device
PCI controller Features

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PCI Bus Configuration
• When power is applied to a PCI device, the hardware the will respond
only to configuration transactions.
Configuration Registers and Initialization
• PCI devices feature a 256-byte address space. The first 64 bytes are
standardized, while the rest are device dependent.
• The PCI registers are always little-endian.

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PCI Bus accessing
Accessing the Configuration Space
• After the driver has detected the device, it usually needs to read from
or write to the three address spaces: memory, port, and configuration.
• Because the microprocessor has no way to access the configuration
space directly, the computer vendor has to use the PCI controller to
write and read registers.
Accessing the I/O and Memory Spaces
• A PCI device implements up to 6 I/O address regions.
• Each region consists of either memory or I/O locations.

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PCI Bus

Advantages

• Very high speed, plug & play, dominant board-level bus

Disadvantages

• Incompatible with older systems, can cost more

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Overview of Speeds of buses
Bus Type Bus Width Bus Speed MB/sec
ISA 16 bits 8 MHz 16MBps

EISA 32 bits 8 MHz 32MBps

PCI 32 bits 33 MHz 132MBps

PCI 64 bits 33 MHz 264MBps

PCI 64 bits 66 MHz 512MBps

PCI 64 bits 133 MHz 1GBps

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BUS COMPARISON
Bus
Theoretical Maximum
Type of Bus Clock Bus Width Advantages Disadvantages
Transfer Rate
Signal
8 Mbytes/sec (64 Low cost, compatibility, Low speed, jumpers & DIP
ISA 8 MHz 16-bit
Mbits/sec) widely used switches. Becoming obsolete
Very high speed, plug
Incompatible with older systems,
PCI 133 MHz 64-bit 1 Gbytes/sec (8 Gbits/sec) & play, dominant
can cost more
board-level bus
Designed for industrial
Lower speed than PCI, need
132 Mbytes/sec (1 use, hot swapping/plug
Compact PCI 33 MHz 64-bit adapter for PC use, incompatible
Gbit/sec) & play, ideal for
with older systems
embedded systems
Low cost, ideal for
Slower than PCI and other plug-in
portable systems, hot
1.5 Mbytes/sec (12 busses (such as firewire), not
USB 1.1 n/a n/a swapping/plug & play,
Mbits/sec) compatible with older
up to 127 devices via 1
peripherals
port
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BUS COMPARISON
Bus
Theoretical Maximum
Type of Bus Clock Bus Width Advantages Disadvantages
Transfer Rate
Signal

All the advantages of


USB plus significantly
higher speeds making
60 Mbytes/sec (480 Not compatible with older
USB 2.0 n/a n/a it compatible with
Mbits/sec) peripherals, still slower than PCI
high-speed peripherals
such as data drives and
video cameras.
Enables multiple PCs to
Most peripheral devices cannot
remotely share
be connected directly to
information and
Ethernet 10 Base 1.25 Mbyte/sec (10 ethernet, adapter is required.
n/a n/a peripheral devices,
T Mbits/sec) Slow data communication by
provides error checking
current standards Possible
lacking in standard
security issues.
serial communication
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