Version: V6.20.62
ZTE CORPORATION
NO. 55, Hi-tech Road South, ShenZhen, P.R.China
Postcode: 518057
Tel: +86-755-26771900
Fax: +86-755-26770801
URL: http://ensupport.zte.com.cn
E-mail: support@zte.com.cn
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Revision History
I
4.2.2 Packet Switching Shelf (BPSN) ................................................................4-11
4.2.3 Resource Shelf (BUSN) .......................................................................... 4-15
4.3 Shelf Description (for GB Resource Shelf) ......................................................... 4-19
4.3.1 Control Shelf (BCTC).............................................................................. 4-19
4.3.2 Switching Shelf (BPSN) .......................................................................... 4-25
4.3.3 Gigabit Resource Shelf (BGSN) .............................................................. 4-29
4.4 Inter-Shelf Connection ...................................................................................... 4-33
4.4.1 Internal Connections (Using BUSN)......................................................... 4-33
4.4.2 Internal Connections (Using BGSN)......................................................... 4-40
II
5.5.4 CLKG (ICM) Interfaces ........................................................................... 5-21
5.5.5 CLKG (ICM) Buttons............................................................................... 5-24
5.5.6 CLKG (ICM) Indicators ........................................................................... 5-24
5.5.7 CLKG (ICM) DIP Switches ...................................................................... 5-27
5.6 Control Main Processing (CMP) Board .............................................................. 5-27
5.6.1 CMP Functions ...................................................................................... 5-27
5.6.2 CMP Principle ........................................................................................ 5-27
5.6.3 CMP Panel ............................................................................................ 5-28
5.6.4 CMP Interfaces ...................................................................................... 5-29
5.6.5 CMP Buttons ......................................................................................... 5-29
5.6.6 CMP Indicators ...................................................................................... 5-30
5.7 Digital Trunk Board (DTB) ................................................................................. 5-31
5.7.1 DTB Functions ....................................................................................... 5-31
5.7.2 DTB Principle......................................................................................... 5-31
5.7.3 DTB Panel ............................................................................................. 5-32
5.7.4 DTB Interfaces ....................................................................................... 5-34
5.7.5 DTB Buttons .......................................................................................... 5-34
5.7.6 DTB Indicators ....................................................................................... 5-34
5.7.7 DTB DIP Switches and Jumpers.............................................................. 5-35
5.8 E1 IP Interface Board (EIPI).............................................................................. 5-37
5.8.1 EIPI Functions ....................................................................................... 5-37
5.8.2 EIPI Principle ......................................................................................... 5-38
5.8.3 EIPI Panel ............................................................................................. 5-38
5.8.4 EIPI Interfaces ....................................................................................... 5-39
5.8.5 EIPI Buttons........................................................................................... 5-39
5.8.6 EIPI Indicators ....................................................................................... 5-40
5.9 GB Line Interface (GLI) Board ........................................................................... 5-40
5.9.1 GLI Functions ........................................................................................ 5-40
5.9.2 GLI Principle .......................................................................................... 5-40
5.9.3 GLI Panel .............................................................................................. 5-41
5.9.4 GLI Interfaces ........................................................................................ 5-42
5.9.5 GLI Buttons............................................................................................ 5-43
5.9.6 GLI Indicators ........................................................................................ 5-43
5.10 GB Line Interface (GLI4) Board ....................................................................... 5-44
5.10.1 GLI4 Functions..................................................................................... 5-44
5.10.2 GLI4 Principle ...................................................................................... 5-44
5.10.3 GLI4 Panel........................................................................................... 5-44
III
5.10.4 GLI4 Interfaces .................................................................................... 5-45
5.10.5 GLI4 Buttons........................................................................................ 5-46
5.10.6 GLI4 Indicators..................................................................................... 5-46
5.11 Gigabit Ethernet Network Interface (GIPI) Board............................................... 5-47
5.11.1 GIPI Functions ..................................................................................... 5-47
5.11.2 GIPI Principle ....................................................................................... 5-47
5.11.3 GIPI Panel ........................................................................................... 5-48
5.11.4 GIPI Interfaces ..................................................................................... 5-49
5.11.5 GIPI Buttons......................................................................................... 5-50
5.11.6 GIPI Indicators ..................................................................................... 5-50
5.12 Gigabit Universal Interface Module (GUIM) ...................................................... 5-51
5.12.1 GUIM Functions ................................................................................... 5-51
5.12.2 GUIM Principle ..................................................................................... 5-52
5.12.3 GUIM Panel ......................................................................................... 5-53
5.12.4 GUIM Interfaces ................................................................................... 5-53
5.12.5 GUIM Buttons ...................................................................................... 5-54
5.12.6 GUIM Indicators ................................................................................... 5-55
5.13 Gigabit Universal Interface Module (GUIM2) .................................................... 5-56
5.13.1 GUIM2 Functions ................................................................................. 5-56
5.13.2 GUIM2 Principle ................................................................................... 5-57
5.13.3 GUIM2 Panel ....................................................................................... 5-57
5.13.4 GUIM2 Interfaces ................................................................................. 5-58
5.13.5 GUIM2 Buttons .................................................................................... 5-59
5.13.6 GUIM2 Indicators ................................................................................. 5-59
5.14 GSM Universal Processing (GUP) Board ......................................................... 5-60
5.14.1 GUP Functions..................................................................................... 5-60
5.14.2 GUP Principle ...................................................................................... 5-60
5.14.3 GUP Panel........................................................................................... 5-62
5.14.4 GUP Interfaces .................................................................................... 5-63
5.14.5 GUP Buttons........................................................................................ 5-63
5.14.6 GUP Indicators..................................................................................... 5-64
5.15 GSM Universal Processing (GUP2) Board 2..................................................... 5-64
5.15.1 GUP2 Functions................................................................................... 5-64
5.15.2 GUP2 Principle .................................................................................... 5-65
5.15.3 GUP2 Panel......................................................................................... 5-66
5.15.4 GUP2 Interfaces................................................................................... 5-67
5.15.5 GUP2 Buttons ...................................................................................... 5-67
IV
5.15.6 GUP2 Indicators................................................................................... 5-68
5.16 Integrated Clock Module (ICM) ........................................................................ 5-68
5.16.1 ICM Functions...................................................................................... 5-68
5.16.2 ICM Principle ....................................................................................... 5-69
5.16.3 ICM Panel............................................................................................ 5-70
5.16.4 ICM Interfaces...................................................................................... 5-70
5.16.5 ICM Buttons ......................................................................................... 5-73
5.16.6 ICM Indicators...................................................................................... 5-73
5.16.7 ICM DIP Switches ................................................................................ 5-76
5.17 Operation and Maintenance Processing (OMP) Board ...................................... 5-77
5.17.1 OMP Functions .................................................................................... 5-77
5.17.2 OMP Principle ...................................................................................... 5-77
5.17.3 OMP Panel .......................................................................................... 5-77
5.17.4 OMP Interfaces .................................................................................... 5-78
5.17.5 OMP Buttons ....................................................................................... 5-79
5.17.6 OMP Indicators .................................................................................... 5-79
5.18 Packet Switching Network (PSN) Board ........................................................... 5-80
5.18.1 PSN Functions ..................................................................................... 5-80
5.18.2 PSN Principle....................................................................................... 5-80
5.18.3 PSN Panel ........................................................................................... 5-81
5.18.4 PSN Interfaces ..................................................................................... 5-82
5.18.5 PSN Buttons ........................................................................................ 5-82
5.18.6 PSN Indicators ..................................................................................... 5-83
5.19 Power Distribution (PWRD) Board ................................................................... 5-83
5.19.1 PWRD Functions.................................................................................. 5-83
5.19.2 PWRD Principle ................................................................................... 5-84
5.19.3 PWRD Panel........................................................................................ 5-84
5.19.4 PWRD DIP Switches and Jumpers ........................................................ 5-85
5.20 Server Board (SBCX) ..................................................................................... 5-86
5.20.1 SBCX Functions................................................................................... 5-86
5.20.2 SBCX Principle .................................................................................... 5-86
5.20.3 SBCX Panel......................................................................................... 5-87
5.20.4 SBCX Interfaces................................................................................... 5-88
5.20.5 SBCX Buttons ...................................................................................... 5-89
5.20.6 SBCX Indicators................................................................................... 5-90
5.21 SONET Digital Trunk Board (SDTB) ................................................................ 5-91
5.21.1 SDTB Functions ................................................................................... 5-91
V
5.21.2 SDTB Principle..................................................................................... 5-91
5.21.3 SDTB Panel ......................................................................................... 5-92
5.21.4 SDTB Interfaces................................................................................... 5-94
5.21.5 SDTB Buttons ...................................................................................... 5-94
5.21.6 SDTB Indicators ................................................................................... 5-94
5.22 SONET Digital Trunk Board2 (SDTB2)............................................................. 5-95
5.22.1 SDTB2 Functions ................................................................................. 5-95
5.22.2 SDTB2 Principle................................................................................... 5-95
5.22.3 SDTB2 Panel ....................................................................................... 5-96
5.22.4 SDTB2 Interfaces ................................................................................. 5-98
5.22.5 SDTB2 Buttons .................................................................................... 5-98
5.22.6 SDTB2 Indicators ................................................................................. 5-98
5.23 Signaling Processing Board (SPB)................................................................... 5-99
5.23.1 SPB Functions ..................................................................................... 5-99
5.23.2 SPB Principle ......................................................................................5-100
5.23.3 SPB Panel ..........................................................................................5-100
5.23.4 SPB Interfaces ....................................................................................5-101
5.23.5 SPB Buttons .......................................................................................5-102
5.23.6 SPB Indicators ....................................................................................5-102
5.23.7 SPB DIP Switches and Jumpers...........................................................5-103
5.24 Signaling Processing Board 2 (SPB2) .............................................................5-105
5.24.1 SPB2 Functions ..................................................................................5-105
5.24.2 SPB2 Principle ....................................................................................5-105
5.24.3 SPB2 Panel ........................................................................................5-106
5.24.4 SPB2 Interfaces ..................................................................................5-107
5.24.5 SPB2 Buttons......................................................................................5-108
5.24.6 SPB2 Indicators ..................................................................................5-108
5.25 Universal Interface Module for Control Plane (UIMC) .......................................5-109
5.25.1 UIMC Functions ..................................................................................5-109
5.25.2 UIMC Principle ....................................................................................5-109
5.25.3 UIMC Panel ........................................................................................ 5-110
5.25.4 UIMC Interfaces .................................................................................. 5-111
5.25.5 UIMC Buttons...................................................................................... 5-112
5.25.6 UIMC Indicators .................................................................................. 5-112
5.26 Universal Interface Module for User Plane (UIMU)........................................... 5-113
5.26.1 UIMU Functions .................................................................................. 5-113
5.26.2 UIMU Principle .................................................................................... 5-113
VI
5.26.3 UIMU Panel ........................................................................................ 5-114
5.26.4 UIMU Interfaces .................................................................................. 5-115
5.26.5 UIMU Buttons...................................................................................... 5-116
5.26.6 UIMU Indicators .................................................................................. 5-116
5.27 User Plane Processing Board (UPPB) ............................................................ 5-118
5.27.1 UPPB Functions.................................................................................. 5-118
5.27.2 UPPB Principle ................................................................................... 5-118
5.27.3 UPPB Panel........................................................................................ 5-119
5.27.4 UPPB Interfaces..................................................................................5-120
5.27.5 UPPB Buttons .....................................................................................5-120
5.27.6 UPPB Indicators..................................................................................5-121
VII
7.3.3 E1 at Abis and IP at A-Interface .............................................................. 7-10
7.3.4 IP at Abis and A Interfaces.......................................................................7-11
7.3.5 IP at Abis and E1 (T1) at A-Interface ....................................................... 7-12
7.3.6 IP at Abis and STM-1 at A-Interface......................................................... 7-13
7.3.7 IPoE at Abis and E1 (T1) at A-Interface ................................................... 7-14
7.3.8 IPoE at Abis and STM-1 at A-Interface .................................................... 7-15
7.3.9 IPoE at Abis and IP at A Interface ........................................................... 7-16
7.3.10 E1 (T1) at Abis and Ater Interfaces ........................................................ 7-17
7.3.11 IP at Abis and E1 (T1) at Ater ................................................................ 7-18
VIII
About This Manual
Purpose
ZXG10 is a GSM mobile communication system independently developed by ZTE
Corporation. It consists of ZXG10 MSS and ZXG10 BSS. ZXG10 BSS provides and
manages radio transmission in GSM, composed of BSC and BTS.
ZXG10 iBSC is a third-generation BSC product of ZTE. It features large capacity,
high reliability, cost-effectiveness, comprehensive functionality, and powerful service
provisioning.
ZXG10 iBSC software system comprises NetNumen M31 and OMM. NetNumen M31 is
the universal wireless network element management system. It manages and maintains
the entire network. OMM implements local operation and maintenance for iBSC. Its
hardware platform uses SBCX board, which is set inside an iBSC rack. iBSC is connected
to NetNumen M31 through OMM.
This manual introduces the hardware system of ZXG10 iBSC, including cabinet, subracks,
boards, auxiliary device, and system configuration.
Intended Audience
l System engineer
l Maintenance engineer
l Installation engineer
Chapter Description
Chapter 3, Subrack Describes the function, structure and panel of ZXG10 iBSC subrack.
Chapter 4, Shelf Describes the type and description of ZXG10 iBSC shelf and its
connection.
Chapter 5, Board Describes the functions, panels, interfaces, indicators, DIP switches,
and jumpers on the ZXG10 iBSC board.
Chapter 6, Auxiliary Device Describes the functions and structures of the ZXG10 iBSC auxiliary
device.
I
Chapter Description
Chapter 7, System Describes the configuration under the different transmission modes in
Configuration the ZXG10 iBSC system
Appendix A, Description of Describes the meaning of combination of RUN and ALM indicators.
Combined Indicator States
II
Chapter 1
Overview
Table of Contents
Product Description ....................................................................................................1-1
Hardware Architecture................................................................................................1-1
Component Description
1-1
Component Description
Describes the functions, principle, and panels of the alarm box, its
connection mode with iBSC equipment, GPS antenna lightening
Other Hardware Equipments protector, GPS antenna, and forwarder.
1-2
ZXG10 iBSC cabinet is compliant with the CompactPCI standard. The cabinet body and
its front door are navy blue, the latter with the compact vents.
2-1
The ZXG10 iBSC cabinet comprises of cabinet top, front door, rear door, rack, subrack,
and busbar.
2-2
The cabinet top consists of top frame component, cable outlet module, top fan, top filter
and fiber wrap tray. Figure 2-4 shows the structure of cabinet top.
2-3
2-4
Top Fan
The top fan is the important part for ventilation. The top fan comprises of base plate, (6)
fans, and monitoring circuit board.
Figure 2-7 shows the structure of the top fan.
2-5
Top Filter
It is the power input interface. The -48 V power cable from the equipment room is mounted
at its input terminal and the output terminal connects the power subrack in the cabinet.
Figure 2-8 shows the structure of the top filter.
2-6
Figure 2-10 shows the label information (If only one label is required, its distance from the
edge shall be 120 mm).
2-7
Office information label contains the cabinet consignment information for unpacking
check, such as product name, consignment number and recipients address.
l Serial No. lLabel
Serial No. label contains the cabinet serial number.
2.2.3 Rack
Rack consists of top frame, bottom frame, column, adjustment rail, and side door, as shown
in Figure 2-11.
2-8
Note:
For multiple cabinets in a single row, only the leftmost and rightmost door at the two ends
of the row need be installed.
2.2.4 Busbar
Busbar is used for providing power supply and grounding of ZXG10 iBSC system. Figure
2-12 show the busbar appearance.
Bus bars are located at the right side of rear cabinet. There are six groups of terminals.
1. From top to bottom, there are four terminals in group 1 and 6, listed as follows:
l -48 V
l -48 V GND
l PE
l PE
2-9
2. Group 1 connects the power distribution subrack and provides power supply input for
busbar.
3. Group 6 provides power supply for the third fan subrack.
4. Group 2 ~ 5 provide power supply for different fan subracks and shelves.
There are six connection terminals for these groups:
l -48 V
l -48 V GND
l -48 V
l -48 V GND
l PE
l PE
2-10
The external connection may vary while resource shelf (BUSN) or GB resource shelf
(BGSN) is used.
2-11
Figure 2-14 Connection of iBSC and Peripheral Device for GB Resource Shelf
In Figure 2-14, the blue line represents the E1 connection, the red line represents the fiber
connection, and the azury broken line represents the Ethernet connection.
1. A-Interface
There are three physical bearing modes at the A-interface between iBSC and
MSC/MGW.
a. STM-1 mode
It is implemented by the optical port on the front panel of SDTB2.
b. E1 mode
It is implemented by the E1 port on rear board RDTB of DTB and rear board RSPB
of SPB2.
c. Ethernet mode
It is implemented by the GE optical port on the front panel of GIPI or the GE electric
port on rear board RGER.
2. Gb interface
There are two physical bearing modes at the Gb interface between iBSC and SGSN.
a. E1 mode
It is implemented by the E1 port on the rear board SPB2.
b. Ethernet mode
It is implemented by the GE optical port on the front panel of GIPI or the GE electric
port on rear board RGER.
3. Abis interface
There are three physical bearing modes at the Abis interface between iBSC and BTS.
2-12
a. STM-1 mode
It is implemented by the optical port on the front panel of SDTB2.
b. E1 mode
It is implemented by the E1 port on rear board RDTB of DTB and rear board RSPB
of SPB2.
c. Ethernet mode
It is implemented by the GE optical port on front panel of GIPI or the GE electric
port on rear board RGER.
4. Ater Interface
There are two physical bearing modes at the interface Ater between iBSC and iTC.
a. STM-1 mode
It is implemented by the optical port on the front panel of SDTB2.
b. E1 mode
It is implemented by the E1 port on rear board RSPB of SPB2 and rear board
RDTB of DTB.
5. Connection with OMM
It is implemented by the FE interface of rear board RMPB for OMP and the FE interface
of rear board SBCX for RSVB. OMM interacts with NetNumen M31 mobile element
management system.
6. Connection with OMCB (SDR OMC)
It is implemented by the FE interface on the rear board of GIPI.
7. Connection with MR server
It is implemented by the FE interface on the rear board of GIPI.
Figure 2-15 Connection of iBSC and Peripheral Device for Resource Shelf
2-13
In Figure 2-15, the blue line represents the E1 connection, the red line represents the fiber
connection, and the azury broken line represents the FE connection.
1. A-Interface
There are two physical bearing modes at the A-interface between iBSC and
MSC/MGW.
a. STM-1 mode
It is implemented by the optical port on the front panel of SDTB.
b. E1 mode
It is implemented by the E1 port on the rear board RDTB of DTB.
2. Gb interface
There are two physical bearing modes at the Gb interface between iBSC and SGSN.
a. E1 mode
It is implemented by the E1 port on the rear board RSPB of SPB.
b. FE mode
It is implemented by the FE interface on the rear board RMNIC of BIPI.
3. Abis interface
There are three physical bearing modes at the Abis interface between iBSC and BTS.
a. E1 mode
It is implemented by the E1 port on the rear board RDTB of DTB.
b. FE mode
It is implemented by the FE interface on the rear board RMNIC of BIPI.
c. STM-1 mode
It is implemented by the optical port on the front panel of SDTB.
4. Ater Interface
There are two physical bearing modes at the Ater interface between iBSC and iTC.
a. STM-1 mode
It is implemented by the optical port on the front panel of SDTB.
b. E1 mode
It is implemented by the E1 port on rear board RSPB of SPB or rear board RDTB
of DTB.
5. Connection with OMM
It is implemented by the FE interface of rear board RMPB of OMP and the FE
interface of rear board SBCX of RSVB. OMM interacts NetNumen M31 mobile
element management system.
6. Connection with OMCB (SDR OMC)
2-14
1. Leading out cables from 2. Leading out cables from 4. Vertical cable trough
cabinet rear board 5. Leading out optical fibers
3. Rear transverse cable rack from front
In ZXG10 iBSC cabinet, the optical fiber is led out from the front board panel, while other
cables are led out from the rear board panel.
2-15
Power Supply
1. The system working voltage is -48 V DC, with a fluctuation ranging from -40 V DC to
-57 V DC.
2. An entirely distributed power supply mode is used. The power supply module on the
board implements conversion of the -48 V power supply into that needed by the board
(such as +5/+3.3/+2.5/1.8 V DC) and isolation between them.
3. The ingress of the cabinet power is power distribution subrack. The power distribution
subrack has two power inputs. Use the switch to select one channel to supply power
for all shelves and the fan subrack. The two inputs are mutually backed up. The -48
V power is piped downwards from the power distribution subrack through busbar. The
powers for each shelf and the fan subrack come from the same -48 V busbar.
Grounding
There are two types of grounding:
1. -48 V GND: -48 V ground.
2. GNDP: system protection ground.
For each shelf, board GND and static GNDE connect with GNDP via shelf filter, and the
rack busbar PE; they also connect rack GNDP with the grounding busbar in equipment
room via right PE post at the top of rack.
Note:
Judgement method of left & right PE post: viewed from the rear of the cabinet to the
front of the cabinet, the left one is left PE post and the right one is right PE post.
-48 V GND is led out from power subrack, and connects -48 VGND of different
subsystems via a busbar.
2-16
Dustproof Measures
1. A dustproof net is installed at the air inlet at the bottom of the cabinet. It uses ABS
plastic as the frame, which joins nylon net. The flexibility provides convenience for
installation and uninstallation.
2. The door air filter uses metal as the frame, with polyurethane second foaming plastic
inside.
Both types of air filters can be reused after being cleaned, and are easy for installation and
disassembling.
Heat Dissipation
Figure 2-17 shows the heat dissipation duct of ZXG10 iBSC.
2-17
EMC
The EMC design is manifested in the shielding and grounding processing of the rack and
subrack.
The shielding design is adopted at subrack level. When the frequency is within the range
30 MHz to 1 GHz, the minimum shielding characteristic is 40 dB.
The subracks support EMC shielding functions. The surfaces are totally electroplated to
ensure the excellent conductivity.
2-18
The joints between subrack and plug-in unit and between plug-in units are conducted by
conductive springs.
To ensure grounding, anti-static grounding devices are reserved on the subrack for the
connection of subrack and rack.
2-19
2-20
3.1.2 Structure
Figure 3-1 shows the structure of power distribution subrack.
3-1
The line connection terminal of power distribution subrack is installed on the rear frame.
The energy safety cover is added at the rear cover. The front panel of the subrack is fixed
with Power Distribution Board (PWRD). The front panel can be turned 90º outward, which
facilitates maintenance.
When the equipment is running, captive fastener can be used to fix the front panel in the
subrack.
3.1.3 Panel
The front plate of the power distribution box is shown in Figure 3-2.
The rear panel of the power distribution subrack is shown in Figure 3-3.
1. Indicator Description
There are eight indicators on the front panel of the power distribution subrack. Table
3-1 explains the panel indicators.
3-2
2. Switches
There are two switches on the front panel. Table 3-2 shows the description of the
switches.
3. Interface Description
Input/Output cables of power distribution and monitoring are connected to the power
distribution subrack through the interfaces. Table 3-3 explains the interfaces of the
power distribution subrack.
Interface Description
3-3
Interface Description
3.2.2 Structure
Figure 3-4 shows the structure of fan subrack.
Each fan subrack consists of three units. Each unit contains two fans. This structure
facilitates the operations such as onsite maintenance and hot swapping.
3.2.3 Panel
The front panel of the fan subrack is shown in Figure 3-5.
3-4
1. Indicator Description
A fan subrack consists of three fan units. Each fan unit has two indicators. Totally,
there are six indicators on the front panel of fan subrack.
Table 3-4 explains the panel indicators.
2. Buttons
Each of the three fan units in the fan subrack has one button on the front panel. Press
the button to pull out the fan unit.
3. Interface Description
The fan subrack interfaces are located at the rear board. Table 3-5 describes the
interfaces.
Interface Description
3-5
3-6
4-1
Figure 4-2 shows the positions of different shelves in ZXG10 iBSC when the resource shelf
is used.
If you use the ZXG10 iBSC system of resource shelf for expansion, you can add the GB
resource shelf for the whole shelf. You shall note that the boards for resource shelf and
GB resource shelf can not be inserted in mixed mode.
If the ZXG10 iBSC uses BUSN or BGSN, the configuration, principle, and backplane may
be varied for different shelves. The section below describes the different shelves for BUSN
and BGSN.
4-2
4.1.4 Backplane
Backplane is an important component of a shelf. Circuit boards in a shelf connect through
printed lines on the backplane. This reduces the cable routing on the backplane and
improves reliability of the entire system.
Figure 4-3 shows the backplane structure.
The shelf corresponds to the backplane. The corresponding relation is shown in Table 4-2.
Shelf Backplane
4-3
Each iBSC should be equipped with a control shelf. The control shelf should be located in
shelf 2 cabinet 1.
Configuration
Table 4-3 shows the boards that can be configured by the control shelf.
Table 4-3 The boards that can be configured by the control shelf
4-4
Note:
If the processing capacity should be expanded, CMP also can be inserted into other
shelves. The BPSN shelf is suggested.
3. There are two CLKG boards for active and standby configuration. They are inserted
into slot 13 & 14 and are mandatory.
Note:
CLKG in Figure 4-4 is one of CLKG (CLKG) and CLKG (ICM). You can use a pair of
boards for same type and can not use the different boards in mixed insertion mode.
4. There are two CHUB boards for active and standby configuration. They are inserted
into slots 15 and 16 and are mandatory.
5. There are two UIMC boards for active and standby configuration. They are inserted
into slots 9 and 10 and are mandatory.
6. A SBCX board should be configured. The SBCX board is inserted in slot 1 and rear
board RSVB is inserted in slot 1.
Principles
Figure 4-5 shows the working principle of control shelf.
4-5
4-6
b. The UIMC board is the signal switching center of control shelf, used to finish the
information exchange among different modules.
c. The OMP board implements the control of operation and maintenance in the whole
system (including operation and maintenance agent).
The OMP board is the core of ZXG10 iBSC operation and maintenance,
directly and indirectly monitors and manages the boards in the system, provides
the Ethernet and RS485 interfaces for the system boards for configuration
management.
d. SBCX can be used as the OMM server and also can save some files required by
OMP. Also, you can organize these files according to the format required by OMM.
e. The CMP board connects on the switching unit at control plane and handles the
protocols at all control planes.
Backplane
The backplane for the control shelf is the BCTC backplane, with two versions, such as
040203 and 060201.
Figure 4-6 shows the rear view of BCTC with version 040203.
Figure 4-7 shows the rear view of BCTC with version 060201.
4-7
060201 version of the BCTC backplane uses the RBID rear board and collects the DIP
switches on RBID, as shown in Figure 4-8.
4-8
Table 4-5 shows the description of DIP switches for the backplane.
4-9
4-position switch
S1 only uses the left 3 positions and X2 only uses
the bottom 3 positions.
S2/X3 uses all 4 positions.
The office information for
S3 only uses the left 2 positions and X4 only uses
S1/X2 the target shelf
the bottom 2 positions.
The rack information for All S1/X2 switches are ON: the value is binary
S2/X3 the target shelf "000";
All S2/X3 switches are ON: the value is binary
"0000";
Two positions for the S3/X4 switch are OFF and
other positions are ON: the value is binary "11".
From above description: 0, 0, and 3 are set for
S1/X2, S2/X3, and S3/X4. The actual rack id
and shelf id should be added by 1, so the setting
indicates that the BCTC shelf is located at: office
S3/X4 Shelf information 0, rack 1, and shelf 4.
Note:
There are DIP switches for BPSN, BCTC, and BUSN. Its ON/OFF setting method is
same.
Note:
The DIP switches on RBID and backplane can not be effective at the same time. If
you use RBID, all DIP switches on the backplane should be set to OFF, that is, all
represented by 1111.
4-10
Configuration
Table 4-6 shows the boards that can be configured in the packet switching shelf.
1. The packet switching shelf provides the level I IP switching platform for the system,
used by the user plane with multiple resource shelves. The packet switching shelf also
can directly provide the high-speed external interface.
2. Intra-Shelf Board Configuration
4-11
a. There are two UIMC boards to implement the switching function at control plane
for the packet switching shelf. The boards are inserted into slots 15 and 16 and
are mandatory.
b. There are two PSN boards to implement the data switching function between line
cards. The boards are inserted into slots 7 and 8 and are mandatory.
c. There are 2 ~ 4 GLI boards to implement the function of GE line card. The boards
can be inserted in slots 1 ~ 4. The number of boards depends on the configuration
capacity. You shall follow the direction from left to right.
d. There are 0 ~ 2 CMP boards for active and standby configuration. A pair of boards
are set per 1024 carriers and can be inserted in slot 11 ~ 14.
e. There is a RUIM2 board inserted in slot 15 and is mandatory.
f. There is a RUIM3 board inserted in slot 16 and is mandatory.
Principle
Figure 4-10 shows the principle of the packet switching shelf.
a. The different resource shelves are connected to the GLI of switching shelf through
the optical port on front panel of the UIMU board.
b. The control shelf connects the UIMC for switching shelf through the rear boards
RCHB1 and RCHB2 for the CHUB board.
c. The clock signal connects the UIMC for switching shelf through the rear boards
RCKG1 and RCKG2 for CLKG, to implement the clock transmission.
2. Intra-Shelf Communication Functions
4-12
Backplane
The backplane for the packet switching shelf is BPSN. It has two versions, 040203 and
070200.
Figure 4-11 shows the rear view of BPSN with version 040203.
Figure 4-12 shows the rear view of BPSN with version 070200.
4-13
Note:
On the field, you can use the RBID backplane and collect the DIP switches on RBID.
For RBID, refer to "Layout of DIP Switches on RBID". X2 corresponds to S1, X3
corresponds to S2, and X4 corresponds to S3. The DIP switches on RBID and
backplane can not be effective at the same time. If you use RBID, all DIP switches on
the backplane shall be set to OFF, that is, all represented by 1111.
4-14
Configuration
Table 4-8 shows the boards that can be configured by the resource shelf.
Table 4-8 The boards that can be configured by the resource shelf
There are multiple configurations for resource shelf. Here takes FE+E1 at Abis and E1 at
A interface as the example. The configuration of resource shelf is shown in Figure 4-13.
4-15
Principles
Figure 4-14 shows the working principle of resource shelf.
4-16
Backplane
The backplane for the resource shelf is BUSN. There are two versions: 040202 and
040203.
4-17
Figure 4-15 shows the BUSN rear view with version 040202.
Figure 4-16 shows the BUSN rear view with version 040203.
Table 4-9 shows the description of power interfaces for resource shelf.
4-18
The DIP switches on the BUSN backplane (S1/X2, S2/X3, and S3/X4) are similar to
those on the BCTC backplane. The DIP switches are used to set the information of
office, rack, and shelf. For the specific setting methods, refer to "Description of DIP
Switches on Backplane".
Note:
On the field, you can use the RBID backplane and collect the DIP switches on RBID.
For RBID, refer to "Layout of DIP Switches on RBID". X2 corresponds to S1, X3
corresponds to S2, and X4 corresponds to S3. The DIP switches on RBID and
backplane can not be effective at the same time. If you use RBID, all DIP switches on
the backplane shall be set to OFF, that is, all represented by 1111.
Configuration
Table 4-10 shows the boards that can be configured by the control shelf.
4-19
Table 4-10 The boards that can be configured by the control shelf
1. There are two OMP boards for active and standby configuration. They are inserted
into slot 11 & 12 and are mandatory.
2. There are 2~4 OMP boards for active and standby configuration. They can be inserted
into slot 1 & 4. The number of OMP boards depend on the required capacity.
4-20
Note:
If the processing capacity shall be expanded, CMP also can be inserted into other
shelves. The BPSN shelf is suggested.
3. There are two SBCX boards for active and standby configuration. The boards can be
inserted into slot 5 & 7.
4. There are two CLKG/ICM boards for active and standby configuration. They are
inserted into slot 13 & 14 and are mandatory.
Note:
You shall use one of CLKG (ICM) and ICM. You can use a pair of boards for same type
and can not use the different boards in mixed insertion mode.
5. There are two CHUB boards for active and standby configuration. They are inserted
into slot 15 & 16 and are mandatory.
6. There are two UIMC boards for active and standby configuration. They are inserted
into slot 9 & 10 and are mandatory.
7. There is a RUIM2 board inserted into slot 9 and is mandatory.
8. There is a RUIM3 board inserted into slot 10 and is mandatory.
9. There are two RMPB boards inserted into slot 11 & 12 and are mandatory.
10. There is a RCKG1 board inserted in slot 13.
11. There is a RCKG2 board inserted in slot 14.
12. There is a RCHB1 board inserted in slot 15.
13. There is a RCHB2 board inserted in slot 16.
14. There are two RSVB boards inserted in slot 5 & 7.
15. There is a RBID board configured on the BCTC shelf.
Principles
Figure 4-18 shows the working principle of control shelf.
4-21
4-22
b. The UIMC board is the signal switching center of control shelf, used to finish the
information exchange among different modules.
c. The OMP board implements the control of operation and maintenance in the whole
system (including operation and maintenance agent).
The OMP board is the core of ZXG10 iBSC operation and maintenance,
directly and indirectly monitors and manages the boards in the system, provides
the Ethernet and RS485 interfaces for the system boards for configuration
management.
d. SBCX can be used as the OMM server and also can save some files required
by OMP. Also, you can organize these files according to the formats required by
OMM.
e. The CMP board connects on the switching unit at control plane and handles the
protocols at all control planes.
Backplane
The backplane for the control shelf is the BCTC backplane, with version 060201. Figure
4-19 shows the rear view.
1. Power Interfaces
Table 4-11 shows the description of power interfaces for control shelf.
4-23
The DIP switches for the backplane are located on RBID, as shown in Figure 4-20.
Table 4-12 shows the description of DIP switches for the backplane.
4-24
Name of DIP
Switch Purpose Example
4-position switch
S1 only uses the left 3 positions and X2 only uses
the bottom 3 positions.
S2/X3 uses all 4 positions.
The office information
S3 only uses the left 2 positions and X4 only uses
S1/X2 for the target shelf
the bottom 2 positions.
The rack information All S1/X2 switches are ON: the value is binary
S2/X3 for the target shelf "000";
All S2/X3 switches are ON: the value is binary
"0000";
Two positions for the S3/X4 switch are OFF and
other positions are ON: the value is binary "11".
From above description: 0, 0, and 3 are set for
S1/X2, S2/X3, and S3/X4. The actual rack id and
shelf id shall be added by 1, so the setting indicates
that the BCTC shelf is located at: office 0, rack 1,
S3/X4 Shelf information and shelf 4.
Note:
There are DIP switches for BPSN, BCTC, and BGSN. Its ON/OFF setting method is
same.
OFF: Set to the lower position, represented by 1.
ON: Set to the upper position, represented by 0.
You also can use the jumpers to set the shelf information on the field. At this time,
a jumper indicates a number. There are 3 4-way jumpers, corresponding to the
information on office, rack, and shelf. For the specific meaning, refer to Table 4-12.
OFF: Unplug the short-circuit block, represented by 1.
Each iBSC system shall be equipped with a packet switching shelf, configured at layer 4
in the primary cabinet.
4-25
Configuration
Table 4-13 shows the boards that can be configured by the packet switching shelf.
Table 4-13 The Boards That can be Configured by Packet Switching Shelf
Universal Interface Module for Rear Board 2 of UIM (RUIM2) Backplane of packet switching
Control Plane (UIMC) Rear Board 3 of UIM (RUIM3) network (BPSN)
1. The packet switching shelf provides the level I IP switching platform for the system,
used by the user plane with multiple resource shelves. The packet switching shelf
also can directly provide the high-speed external interface. Each pair of GLIs provide 8
pair of optical ports for active/standby configuration. 3 pairs of GLI exactly introduce 24
pairs of optical ports, connected to 24 pairs of active/standby optical ports for resource
shelf GUIM at layer 6. Each GUIM board uses two pairs of optical ports.
2. Intra-shelf Board Configuration
a. There are two UIMC boards to implement the switching function at control plane
for the packet switching shelf. It is active/standby configuration, inserted in slots
15 and 16 and mandatory.
b. There are two PSN boards to implement the data switching function between line
cards. Load balancing, inserted in slots 7 ~ 8 and mandatory.
4-26
c. There are 2 ~ 6 GLI boards to implement the function of GE line card. The boards
can be inserted in slots 1 ~ 6. The number of boards depends on the configuration
capacity. You shall follow the direction from left to right for load balancing.
d. There are 0 ~ 2 CMP boards for active and standby configuration. A pair of boards
are set per 1024 carriers and can be inserted in slot 11~14.
e. There is a RUIM2 board inserted in slot 15 and is mandatory.
f. There is a RUIM3 board inserted in slot 16 and is mandatory.
g. There is a RBID board configured on the BPSN shelf.
Principles
Figure 4-22 shows the principle of packet switching shelf when the GB resource shelf is
used.
4-27
l Finally, GLI receives the switched data from PSN, finishes the proper
handling, and sends the data to destination port.
b. Data at control plane
UIMC switching takes the Ethernet bus as the inner control bus in the subsystem,
connects the different subsystem modules, implements the distribution and
collection of route information and the configuration maintenance management.
Meanwhile, it implements the delivery of high-layer protocol and signaling data.
Backplane
The backplane for the packet switching shelf is the BPSN, with version 070200. Figure
4-23 shows the rear view.
1. Backplane Interface
Table 4-14 shows the description of power interfaces for packet switching shelf.
4-28
information of office, rack, and shelf. For the specific setting methods, refer to
"Description of DIP Switches on Backplane".
Configuration
Table 4-15 shows the boards that can be configured by the GB resource shelf.
Table 4-15 The boards that can be configured by the GB resource shelf
There are multiple configurations for GB resource shelf. Here takes E1 or IPOE at Abis,
E1 at A interface, E1 at Gb as the example. The configuration of GB resource shelf is
shown in Figure 4-24.
4-29
4-30
10. There are RGUM1 and RGUM2 inserted in slots 9 & 10 and are mandatory.
11. RDTB, RSPB, and RGER/RMNIC are set properly with the front board.
12. The rear card RGIM1 for the SDTB2 board is used to extract 8K clock from STM-1 line.
If the line clock is not required to extract, the configuration is not required. In normal
case, if the number of configured SDTB2 is more than 1, you shall set two RGIM1. Set
two cables for clock extraction.
13. There is a RBID board configured on the BGSN shelf.
Principles
Figure 4-25 shows the working principle of GB resource shelf.
4-31
a. BGSN, as the backplane of GB resource shelf, can hold the different service
processing modules to form the universal service processing subsystem.
b. GUIM is the connection and switching center for different data in the GB resource
shelf, to finish the information switching among the different modules.
c. GUP2 handles the relevant radio protocol at user plane, TC transcoder conversion,
and handover from TDM to IP packet.
d. GIPI provides a GB electric port or four MB interfaces through the backplane at
media plane.
Backplane
The backplane for GB resource shelf is BGSN. Figure 4-26 shows its rear view.
1. Backplane Interface
Table 4-16 shows the description of power interfaces for GB resource shelf.
4-32
information of office, rack, and shelf. For the specific setting methods, refer to
"Description of DIP Switches on Backplane".
4-33
Note:
In Figure 4-27, CLKG refers to CLKG(CLKG) or CLKG(ICM). Both CLKG(CLKG)
and CLKG(ICM) can provide the clock. Other paragraphs in this section is same
as this, no more explanation later. DTB, STDB, SDTB2, and SPB can extract the
clock signal for CLKG. This figure only takes DTB as an example.
4-34
In Figure 4-28, real line represents the cable connection and dashed line
represents the printed connection on the backplane.
The Ethernet interconnection at control plane for the iBSC system can be
implemented by the CHUB board. The Ethernet interconnection mode at control
plane is described as follows.
l Connect CHUB to UIMC for resource shelf and packet switching shelf through
the cable.
l The UIMC board for the control shelf directly connects the CHUB board
through the printed lines on the backplane.
4-35
Figure 4-29 Wiring at User Plane in an iBSC Cabinet for Resource Shelf
The user plane interconnects in the iBSC system, the user plane in a resource
shelf interconnects through backplane, the user plane among different resource
shelves interconnect through the GLI and PSN boards in the packet switching
shelf. That is, connect the UIMU and GLI boards for all resource shelves through
the fibers.
d. Monitoring cable connection
Figure 4-30 shows the connection of monitoring cable in an iBSC cabinet.
4-36
Figure 4-30 Wiring of Monitoring Cables in an iBSC Cabinet for Resource Shelf
The fan subrack and power subrack are connected through the cables, to monitor
the fans.
The PWRD board connection between the OMP board and power subrack
implements the PWRD monitoring.
Different sensor and power subrack connections implement the monitoring of
external environment.
Dual Cabinet
1. For dual cabinet, the connections between ZXG10 iBSC cabinets contain:
a. Clock distribution cable and line clock extraction cable;
d. Monitoring cable.
2. Wiring Instance Description
a. Clock Distribution
4-37
Figure 4-31 shows the wiring of clock distribution & extraction in the iBSC
dual-cabinet.
The shelf in the iBSC system requires the system clock. The clock extraction and
distribution modes are described as follows:
l Clock extraction for reference clock base
Extracts the line clock from CN through the interface board and send it to the
CLKG board.
The CLKG board also can input the BITS clock base.
l Clock Distribution
Connect UIMU for different resource shelves or UIMC for packet switching
shelves from rear boards RCKG1 & RCKG2 for the CLKG board through the
clock cable and distribute to different slots in local shelf by UIMU/UIMC.
b. Ethernet interconnection at control plane
Figure 4-32 shows the Ethernet wiring at control plane in the iBSC dual-cabinet.
4-38
In Figure 4-32, real line represents the cable connection and dashed line
represents the printed connection on the backplane.
The Ethernet interconnection at control plane in the iBSC dual-cabinet is described
as follows.
l Connect the UIMC or UIMU board for all shelves other than the control shelf
in cabinet 1 to the CHUB board through the cable.
l The UIMC board for the control shelf in cabinet 1 directly connects the CHUB
board through the printed lines on the backplane.
Figure 4-33 Wiring at User Plane in the iBSC Dual-Cabinet for Resource Shelf
The user plane interconnects in the iBSC system, the user plane in a resource
shelf interconnects through backplane, the different resource shelves interconnect
mutually through the GLI and PSN boards among the different resource shelves.
4-39
That is, connect the UIMU and GLI boards for all resource shelves through the
fibers.
d. Monitoring cable connection
Figure 4-34 shows the connection of monitoring cables in the iBSC dual cabinet.
Figure 4-34 Wiring of Monitoring Cables in the iBSC Dual-Cabinet for Resource
Shelf
The fan subrack and power subrack are connected through the cables, to monitor
the fan subrack.
The OMP board in cabinet 1 connects the PWRD board in this cabinet. The PWRD
board in cabinet 2 connects that in cabinet 1, to monitor the PWRD in cabinet 1 &
2.
Different sensor and power subrack connections in cabinet 1 implement the
monitoring of external environment.
4-40
Figure 4-35 shows the wiring of clock extraction distribution in an iBSC cabinet.
Note:
In Figure 4-35, CLKG (ICM) can be changed to ICM. CLKG (ICM) and ICM can
provide the clock. Other paragraphs in this section is same as this, no more
explanation later. DTB, STDB, SDTB2, and SPB2 can be CLKG (ICM)/ICM
extraction clock signal. This figure only takes DTB as an example.
Extracts the line clock from CN through the interface board and send it to the
CLKG (ICM)/ICM board.
The CLKG (ICM)/ICM board also can input the BITS clock base or get the
clock base from the GPS module.
l Clock Distribution
4-41
Connect the GUIM/UIMC board in different shelves from rear boards RCKG1
& RCKG2 for the CLKG(ICM)/ICM board through the clock cable and
distribute to different slots in local shelf by GUIM/UIMC.
b. Ethernet interconnection at control plane
Figure 4-36 shows the Ethernet interconnection at control plane.
In Figure 4-36, real line represents the cable connection and dashed line
represents the printed connection on the backplane.
The Ethernet interconnection at control plane for the iBSC system can be
implemented by the CHUB board. The Ethernet interconnection mode at control
plane is described as follows.
l Connect CHUB to GUIM for GB resource shelf and UIMC for packet switching
shelf through the cables.
l The UIMC board for the control shelf directly connects the CHUB board
through the printed lines on the backplane.
The connection at user plane for an iBSC cabinet is shown in Figure 4-37.
4-42
Figure 4-37 Wiring at User Plane in an iBSC Cabinet for GB Resource Shelf
The user plane interconnects in the iBSC system, the user plane in a GB
resource shelf interconnects through backplane, the user plane among different
GB resource shelves interconnect through the GLI and PSN boards in the packet
switching shelf. That is, connect the GUIM and GLI boards for GB all resource
shelves through the fibers.
d. Monitoring cable connection
Figure 4-38 shows the connection of monitoring cable in an iBSC cabinet.
4-43
The fan subrack and power subrack are connected through the cables, to monitor
the fans.
The PWRD board connection between the OMP board and power subrack
implements the PWRD monitoring.
Different sensor and power subrack connections implement the monitoring of
external environment.
Dual Cabinet
1. For dual cabinet, the connections between ZXG10 iBSC cabinets contain:
a. Clock distribution cable and line clock extraction cable;
b. Ethernet cable at control plane;
c. Fiber at user plane;
d. Monitoring cable.
2. Wiring Instance Description
a. Clock Distribution
4-44
Figure 4-39 shows the wiring of clock distribution and extraction in the iBSC
dual-cabinet.
The shelf in the iBSC system requires the system clock. The clock extraction &
distribution modes are described as follows.
l Clock base for clock extraction reference
Extracts the line clock from CN through the interface board and send it to the
CLKG (ICM)/ICM board.
The CLKG (ICM)/ICM board also can input the BITS clock base or get the
clock base from the GPS module on the ICM board.
l Clock Distribution
Connect GUIM for different GB resource shelves or UIMC for packet switching
shelves from rear boards RCKG1 & RCKG2 for the CLKG(ICM)/ICM board
through the clock cable and distribute to different slots in local shelf by
GUIM/UIMC.
b. Ethernet interconnection at control plane
Figure 4-40 shows the Ethernet wiring at control plane in the iBSC dual-cabinet.
4-45
In Figure 4-40, real line represents the cable connection and dashed line
represents the printed connection on the backplane.
The Ethernet interconnection at control plane in the iBSC dual-cabinet is described
as follows:
l Connect the GUIM or UIMU board for all shelves other than the control shelf
in cabinet 1 to the CHUB board through the cables.
l The UIMC board for the control shelf in cabinet 1 directly connects the CHUB
board through the printed lines on the backplane.
c. Interconnection at user plane
Figure 4-41 shows the interconnection at user plane for the iBSC dual-cabinet.
Figure 4-41 Wiring at User Plane in the iBSC Dual-Cabinet for GB Resource
Shelf
The user plane interconnects in the iBSC system, the user plane in a GB resource
shelf interconnects through backplane, the different GB resource shelves
interconnect mutually through the GLI and PSN boards among the different GB
4-46
resource shelves. That is, connect the GUIM and GLI boards for all GB resource
shelves through the fibers.
d. Monitoring cable connection
Figure 4-42 shows the connection of monitoring cables in the iBSC dual cabinet.
The fan subrack and power subrack are connected through the cables, to monitor
the fan subrack.
The OMP board in cabinet 1 connects the PWRD board in this cabinet. The PWRD
board in cabinet 2 connects that in cabinet 1, to monitor the PWRD in cabinet 1
and 2.
Different sensor and power subrack connections in cabinet 1 implement the
monitoring of external environment.
4-47
4-48
The front board is inserted in the shelf slot, with a front panel. Indicators on the front panel
indicate the board status. Rear board consists of the external interfaces and debugging
5-1
interfaces. These interfaces are used to interconnect shelves of same cabinet or different
cabinets. The rear board and the front board work together. For some active/standby front
board, it is necessary to configure two kinds of rear boards.
Front board and rear board form a complete metal shield inside the shelf, reducing the
external electromagnetic radiation of the system and enhancing the anti-interference
capability.
Figure 5-1 shows the board assembly relation.
5-2
5-3
1. BIPI panel for front board 2. RMNIC panel for rear board
5-4
Name Description
5-5
5-6
It connects the logic unit and Ethernet switching unit via the control bus, to
configure the switching chip set.
b. Logic unit
It implements all logical processing functions of the board.
c. Ethernet switching unit
It performs Ethernet switching, implementing the gathering on the control plane.
2. Board data flow direction
a. The data of the control plane from all shelves is sent to Ethernet switching unit on
CHUB.
b. The data is sent to UIMC on the control shelf via Interface GE, and then is
distributed to RCB for processing and vice versa.
5-7
1. CHUB panel for front board 3. RCHB2 panel for rear 5. RCHB2 panel for rear
2. RCHB1 panel for rear board (version 040501) board (version 040502)
board (version 040501) 4. RCHB1 panel for rear
board (version 040502)
5-8
FE1-8 Bi.
FE9-16 Bi.
Connect the port at control plane
FE17-24 Bi. for UIM.
Note:
The rear board RCHB1 (version 040501) works with the rear board RCHB2 (version
040501), while the rear board RCHB1 (version 040502) works with the rear board RCHB2
(version 040502).
The rear board (version 040501) cannot be used with the rear board (version 040502).
5-9
Name Description
5-10
5-11
1. CLKG (CLKG) Panel for 2. Layout of CLKG (CLKG) for 3. RCKG1 panel for rear
front board front board board (version 040503)
5-12
4. RCKG2 panel for rear 5. RCKG1 panel for rear 6. RCKG2 panel for rear
board (version 040502) board (version 071200) board (version 071200)
5-13
5-14
Note:
The rear board RCKG1 (version 040503) is used with the rear board RCKG2 (version
040502). Two sets of 8K references are introduced from RCKG1. The rear board RCKG1
(version 071200) is used with the rear board RCKG2 (version 071200). Each rear board
connects a set of 8K clock reference and a set of BITS clock reference.
The rear board (version 0405xx) cannot be used with the rear board (version 071200).
5-15
Name Description
Running indica-
RUN Green tor Refer to "Description of combined indicator status"
5-16
5-17
5-18
5-19
It manages the board, communicates with the system control unit, implements the
core clock control algorithm, outputs the clock signals, and selects the reference
according to the data that the phase detection and phase locking unit provides.
b. Reference selection unit
It selects the suitable reference clock from several input clock under the
control of the main control unit. The clock reference can be from 8 KHz frame
synchronization signal of DTB or SDTB/SDTB2 clock reference, 2 MHz / 2 Mbits
of Building Integrated Timing System (BITS).
c. Voltage controlled oscillator unit
The constant temperature crystal oscillator that meets level-3 clock standard
provides the clock source with high precision.
d. Phase detection and phase lock unit
It compares the adjustment clock signal and input reference phase and provides
the quantized data for the main control unit, to control the voltage controlled
oscillator unit. The phase lock system uses the loose coupler phase lock principle.
e. Active/Standby changeover unit
a. Select one channel of input reference clock to lock the phase and output 16 M
and frame header signals that meets the requirements of scheduling. After being
balanced- driven, the data is distributed to UIMU/GUIM.
b. Perform the pulse expansion on the received PP2S and 16 CHIP signal, and then
distribute the new PP2S to shelves.
5-20
1. CLKG (ICM) Panel for front 3. RCKG1 panel for rear 5. RCKG1 panel for rear
board board (version 040503) board (version 071200)
2. Layout of CLKG (ICM) for 4. RCKG2 panel for rear 6. RCKG2 panel for rear
front board board (version 040502) board (version 071200)
5-21
RCKG2 panel for rear 1 x GPS reference input, connecting the ex-
board (version 040502) PP2S/16CHIP Input ternal GPS clock reference source.
5-22
RCKG2 panel for rear Bidirec- The system debugging serial port, connect-
board (version 071200) RS232 tional ing the debugger.
5-23
Note:
The rear board RCKG1 (version 040503) is used with the rear board RCKG2 (version
040502). Two sets of 8K references are introduced from RCKG1. The rear board RCKG1
(version 071200) is used with the rear board RCKG2 (version 071200). Each rear board
connects a set of 8K clock reference and a set of BITS clock reference.
The rear board (version 0405xx) cannot be used with the rear board (version 071200).
Name Description
5-24
5-25
5-26
Setting
S1 ON ON ON ON
75 ohms S5 ON ON ON ON
S1 ON ON ON ON
5-27
1. CPU unit
There are two independent CPU units on the board, CPU_A and CPU_B. Each
CPU unit provides FE electrical interface at control plane, the FE electrical interface
for communication of active/standby board, and RS232 and RS485 interfaces for
communication with other units. CPU_A is on the lower part of the board, which
implements the main control function of the board.
2. Logic unit
It implements all logical processing function of the board.
3. Power management unit
5-28
Name Description
5-29
Name Description
CPU_A ac-
tive/standby indica- ON: Indicates the board is active
ACT1 Green tor OFF: Indicates the board is standby
5-30
CPU_B ac-
tive/standby indica- ON: Indicates the board is active
ACT2 Green tor OFF: Indicates the board is standby
5-31
5-32
1. SDTB Panel of front board 2. Layout of DTB board 3. RDTB Panel for rear board
for front board (version
040501)
There are two versions for DTB: version 040501 and 060201. There is a difference
between version 060201 and 040501. The DTB with version 060201 has the different
positions. Its jumper position is shown in Figure 5-14.
Figure 5-14 Layout of DTB board for front board (version 060201)
5-33
Name Description
Running indica-
RUN Green tor Refer to "Description of combined indicator status"
5-34
5-35
5-36
Note:
Connection blocks of jumpers X9-X16 on RDTB should be removed if E1 uses 120
ohms PCM balanced transmission mode.
Setting Default
75
ohms ON ON ON ON
S1~S6 The matching
S9 impedance to connect 120 OF- OF- O- O- O- O-
S12 E1 is 75 or 120 ohms ohms F OFF OFF F N N N N
75
Used to indicate the
ohms ON ON ON ON
matching receiving re-
S7 sistance of proper E1 120 OF- OF- O- O- O- O-
S8 chips for CPU. ohms F OFF OFF F N N N N
short
Used to indicate the
haul ON ON ON ON
short/long haul of
S10 proper E1 chips for long OF- OF- O- O- O- O-
S11 CPU. haul F OFF OFF F N N N N
1. Each DIP switch corresponds to one E1 chip. S7 corresponds to E1 chips 1 to 4 (E1 channels 1
to 16). S8 corresponds to E1 chips 5 to 8 (E1 channels 17 to 32). CPU reads this status during
power-on and initiates each E1 chip according to this status.
2. Each DIP switch corresponds to four E1 chips. S10 corresponds to E1 chips 1 to 4 (E1 channels
1 to 16). S11 corresponds to E1 chips 5 to 8 (E1 channels 17 to 32). CPU reads this status
during power-on and initiates each E1 chip according to this status.
5-37
b. Logic unit
It implements all logical processing function of the board.
c. Interface Unit
EIPI does not provide external interface.
2. Board data flow direction
The interface unit accesses HW data, and sends the data to HPS subcard. After
being processed by HDLC protocol, the data is sent to the service processing unit and
separated to be data at user plane and control plane. The data at user plane is sent to
GUP2 for processing via switching network at user plane and the data at control plane
is sent to CMP for processing via switching network at control plane.
5-38
Name Description
5-39
Running indi-
RUN Green cator Refer to "Description of combined indicator status"
5-40
5-41
GLI panel TX-RX Bidirectional four GE optical ports in pair and for backup
5-42
Name Description
Running indica-
RUN Green tor Refer to "Description of combined indicator status"
The LED indica- ON: The logic is proper (OFF if there is logic in
tor at optical in- FPGA, otherwise always ON.)
terface is acti- Flashing: Indicates the system is receiving or
ACT1-8 Green vated. transmitting data after the logic is proper.
5-43
5-44
5-45
Name Description
5-46
5-47
It processes related protocol and implements the isolation of user plane and control
plane.
b. Logic unit
5-48
1. GIPI panel for front board 2. RGER panel for rear board 3. RMNIC panel for rear board
Note:
Usually, GIPI uses RGER as the rear board; when iBSC need connect OMCB or MR, GIPI
uses RMNIC as the rear board.
5-49
When iBSC need connect OMCB or MR, GIPI uses RMNIC as the rear board. For the
interfaces on rear board RMNIC, refer to "Relevant Interfaces on BIPI Board".
Name Description
5-50
GUIM provides the GB resource shelf management function and the RS-485 management
interface. It also provides the function of board reset and in-position signal collection for
the GB resource shelf.
5-51
The external data is from boards on the shelf where UIMU locates. It enters Ethernet
switching unit or TS switching unit for switching, and then is sent to the target board
or level-1 switching interface board.
5-52
1. GUIM panel for front board 2. RGUM1 panel for rear 3. RGUM2 panel for rear
board board
5-53
Direc-
Location Interface tion Description
RGUM1 panel for DEBUG- Bidirec- Debugging serial port for CPU system, connected to
rear board 232 tional the debug machine.
RGUM2 panel for DEBUG- Bidirec- Debugging serial port for CPU system, connected to
rear board 232 tional the debug machine.
Note:
The FE3, FE4, FE5, and FE6 interfaces on the rear board of GUIM cannot be used for
control plane cascading.
5-54
Name Description
Running indica-
RUN Green tor Refer to "Description of combined indicator status"
5-55
Circuit domain in- ON: indicates that the GUIM circuit domain is active
ACT-T Green dicator OFF: indicates that the GUIM circuit domain is standby
5-56
GUIM2 provides the clock-driven function in the gigabit resource shelf. Input PP2S, 8 kHz
and 16 MHz signals, distribute the signals to various slots after phase lock and driving,
and provide 16 MHz, 8 kHz and PP2S clocks to the boards in the gigabit resource shelf.
GUIM2 provides the GB resource shelf management function and the RS-485
management interface. It also provides the function of board reset and in-position signal
collection for the GB resource shelf.
5-57
5-58
connect to GLI/GLI4
boards, or connect to
GUIM2 Panel for front
4 pairs of RX-TX Bidirectional GUIM/GUIM2 boards
board
on other resource
shelves.
Name Description
Running indica-
RUN Green Refer to "Description of combined indicator status"
tor
5-59
The CS service and PS service from BTS are switched to the BIPB board through the
circuit switching network of the UIM board. The 20 ms TRU frames (or PCU frames) are
found out according to channel on BIPB, then the TRU frames (or PCU frames) are made
into IP packet and sent to TCU (or UPU) for processing.
The DRTB board realizes TRAU frame transcoding and rate adaptation and provides
FR/EFR/HR/AMR/TFO functions.
5-60
e. Clock unit
It provides necessary clock signal for each external unit on the board.
5-61
The uplink data flow direction is the opposite of the downlink data flow direction. The
following takes the uplink data flow for an example.
a. When it is used as BIPB, the TDM data accesses Abis interface, then it is
distributed to DSP unit for processing via circuit switching unit, converted to IP
data packet and sent to the other board via Ethernet switching unit.
b. When it is used as DRTB, the voice data IP package from user plane Ethernet
received by interface unit is distributed to DSP for code transformation and rate
adaptation, converted to PCM code flow and switched to trunk board by UIMU.
c. When it is used as TIPB, the user plane data from UIM board is distributed to DSP
through the Ethernet switching unit, converted to TDM data, and then sent to other
board through the circuit switching unit for processing.
5-62
Name Description
5-63
Running indica-
RUN Green tor Refer to "Description of combined indicator status"
The TIPB2 board realizes TDM/IP conversion at Ater interface. In other words, finding out
20 ms TRAU frames according to channel and making them into IP packet.
At STM-1 interface or E1 Abis interface, the CS and PS services from BTS are switched
to the BIPB2 board through the circuit switching network of the UIM board or through the
circuit switching network of the GUIM board. The 20 ms TRU frames (or PCU frames) are
found out according to channel on BIPB2, then the TRU frames (or PCU frames) are made
into IP packet and sent to TCU (or UPU) for processing. At IP Abis interface, in addition
to the above functions, the BIPB2 board is also used for RTP protocol processing.
5-64
The AIPB board is used for RTP protocol processing at A-interface and making data into
IP packet.
The UPPB2 board is used for user plane protocol processing under A/Gb mode, including
BSSGP, PDCP, and GTP_U protocol.
The DRTB board realizes TRAU frame transcoding and rate adaptation, and provides
FR/EFR/HR/AMR/TFO functions.
5-65
5-66
Name Description
5-67
Running indica-
RUN green tor Refer to "Description of combined indicator status"
5-68
The constant temperature crystal oscillator that meets level-3 clock standard
provides the clock source with high precision.
d. Phase detection and phase lock unit
5-69
It compares the adjustment clock signal and input reference phase and provides
the quantized data for the main processing unit, to control the voltage controlled
oscillator unit. The phase lock system uses the loose coupler phase lock principle.
e. Active/Standby changeover unit
It implements the active/standby changeover (the compact of the switching on the
clock shall be within the allowed range). The active/standby ICM is locked in the
same reference, for the smooth switchover.
2. Board data flow direction
a. Select one channel of input reference clock to lock the phase and output 16 M
and frame header signals that meets the requirements of scheduling. After being
balanced- driven, the data is distributed to GUIM.
b. Perform the pulse expansion on the received PP2S and 16 CHIP signal, and then
distribute the new PP2S to shelves.
c. Extract and generate 1PPS signal for the received GPS signal, take the generate
PP2S, 19.6608MHz, and system 8 K clock reference required by the system, and
distribute them to shelves.
1. ICM panel 3. RCKG1 panel for rear 5. RCKG1 panel for rear
2. Layout of ICM for front board (version 040503) board (version 071200)
board 4. RCKG2 panel for rear 6. RCKG2 panel for rear
board (version 040502) board (version 071200)
Direc-
Location Interface tion Description
5-71
Direc-
Location Interface tion Description
5-72
Direc-
Location Interface tion Description
Note:
The rear board RCKG1 (version 040503) is used with the rear board RCKG2 (version
040502). Two sets of 8K references are introduced from RCKG1. The rear board RCKG1
(version 071200) is used with the rear board RCKG2 (version 071200). Each rear board
connects a set of 8K clock reference and a set of BITS clock reference.
The rear board (version 0405xx) cannot be used with the rear board (version 071200).
Name Description
5-73
5-74
5-75
5-76
Setup
Name of Default
Mode DIP Switch 1 2 3 4 Mode
S1 ON ON ON ON
75 ohms S5 ON ON ON ON
S1 ON ON ON ON
The rear board for OMP board is RMPB. Figure 5-32 shows the OMP board.
5-77
1. OMP panel for front board 2. OMP layout 3. RMPB panel for rear board
USB1 Bi. -
5-78
Name Description
CPU_A ac-
tive/standby indica- ON: Indicates the board is active
ACT1 green tor OFF: Indicates the board is standby
5-79
CPU_B ac-
tive/standby indica- ON: Indicates the board is active
ACT2 green tor OFF: Indicates the board is standby
OMC network port ON: indicates that OMC network port 1 has been
OMC1 green indicator 1 connected
OMC network port ON: indicates that OMC network port 2 has been
OMC2 green indicator 2 connected
5-80
5-81
5-82
Name Description
5-83
l PWRD is monitored and managed by OMP through RS485 interface. It reports the
detected information to OMP and indicates through indicators on the power distribution
plug-in box panel.
By structure, PWRD falls into the following parts: one PDM, one PWRD, one PWRDB and
four fan group control modules.
1. PDM implements filter, lightning protection and isolation on 2-channel -48 V, sends
it to the busbar to supply shelves, samples and sends the samples to PWRD for
over-/under-voltage monitoring before the 2-channel power supply convergence.
2. PWRD detects the 2-channel -48 V over-/under-voltage, speed of 24 fans, ambient
temperature, ambient humidity, smoke alarm, infrared alarm, cabinet, and equipment
room door control.
PDM and PWRD form a power distribution subrack.
3. 2 x 3 fan group and the fan group control module form a fan subrack.
Fan subrack takes -48 V from the busbar and sends fan monitoring signals to PWRD.
4. PWRDB provides external monitoring signal interface for PWRD, accessing the
system monitoring signals.
5-84
Note:
You should reset the board by the reset switch after changing the DIP and jumper settings.
DIP Switches
Table 5-53 shows the description of DIP switches on PWRD board.
Setting Default
CONFIG
switch (set
the working
mode to nor-
mal or de-
bugging and
the default
value is nor- It is used to set the working mode O-
S2 mal). independent of the user. ON OFF N ON
5-85
Setting Default
corresponds
to the rack id
for the board.
Jumper
On the PWRD board, there are 2x5 pins to be used as the short-circuit jumper X8 for 485
signal. If iBSC uses multiple racks, you should set the working mode of 485 busbar on the
PWRD board depending on the rack position.
1. If the PWRD board is located at the end of 485 busbar, you should connect the
resistance terminal. Only pin 1-2 and pin 9-10 are connected in short circuit. This is
the default value, as shown in Figure 5-37.
2. If the PWRD board is located in the middle of 485 busbar, you should transfer the 485
signal to the output port. Only pin 3-4 and pin 7-8 are connected in short circuit.
5-86
5-87
1. SBCX Panel for front board 2. RSVB Panel for rear board
5-88
5-89
Name Description
5-90
SAS hard disk 1 ON: SAS hard disk 1 is not in position or is faulty.
ALM1 Yellow fault indicator OFF: SAS hard disk 1 is normal.
SAS hard disk 2 ON: SAS hard disk 2 is not in position or is faulty.
ALM2 Yellow fault indicator OFF: SAS hard disk 2 is normal.
FC interface 1
running indica-
ACT green tor Unused
FC interface 1
SD Yellow rate indicator Unused
FC interface 2
running indica-
ACT green tor Unused
FC interface 2
SD Yellow rate indicator Unused
5-91
a. Main control unit: It manages the boards and controls the internal connection.
b. Interface unit: It is connected with circuit switching unit, and provides STM-1
interface.
c. Circuit switching unit: It switches over the circuit HW for the interface unit.
d. Logic processing unit: It implements the inner logic switchover for the board and
the adaptation function.
e. Clock processing unit: It receives the clock from system clock board, and provides
the reference clock signal extracted from STM-1.
2. Board data flow direction
From the receiving direction, the STM-1 optical data from the line side is processed by
the interface unit, sent to the circuit switching unit for switching, and then sent to the
UIMU/GUIM board,
and vice versa.
5-92
1. SDTB Panel for front board 2. RGIM1 panel for rear board
Note:
If it does not require to extract the 8 K clock reference from SDTB, then RGIM1 is not be
used. If it requires to extract the 8 K clock reference from SDTB, then RGIM1 is used.
5-93
RGIM1 panel for 8KOUT/DEBUG- Leads out 8K reference clock signal and
rear board 232 Bi. debugging signal at RS232 serial port
Name Description
Running indi-
RUN green cator Refer to "Description of combined indicator status"
Alarm indica-
ALM Red tor Refer to "Description of combined indicator status"
5-94
Board Ac-
tive/Standby ON: board is active.
ACT green indicator OFF: Indicates the board is standby
Optical mod-
ule Ac- ON: optical interface is active.
tive/Standby OFF: optical interface is standby.
ACT green indicator This indicator is close to the SD indicator.
5-95
a. Main control unit: It manages the boards and controls the internal connection.
b. Interface unit: It is connected with circuit switching unit, and provides STM-1
interface.
c. Circuit switching unit: It switches over the circuit HW for the interface unit.
d. Logic processing unit: It implements the inner logic switchover for the board and
the adaptation function.
e. Clock processing unit: It receives the clock from system clock board, and provides
the reference clock signal extracted from STM-1.
2. Board data flow direction
From the receiving direction, the STM-1 optical data from the line side is processed by
the interface unit, sent to the circuit switching unit for switching, and then sent to the
GUIM board,
and vice versa.
5-96
Note:
If it does not require to extract the 8 K clock reference from SDTB2, then RGIM1 is not be
used. If it requires to extract the 8 K clock reference from SDTB2, then RGIM1 is used.
5-97
RGIM1 panel for rear Leads out 8K reference clock signal and
board 8KOUT/DEBUG-232 Bi. debugging signal at RS232 serial port
Name Description
5-98
Board Ac-
tive/Standby indi- ON: board is active.
ACT green cator OFF: Indicates the board is standby
LAPD mainly handles the LAPD signal. The LAPD signal from BTS is accessed by
DTB/SPB board, and switched to LAPD board through the circuit switching network
5-99
on UIMU/UIMC board in the resource shelf. The LAPD board implements the LAPD
processing.
SPB mainly handles the MTP2 and X.25 protocols. Extracts 8 kHz synchronization clock
from a line and transfer it through a cable to clock generation board as a reference clock.
GIPB handles GPRS FR and NS, and some BSSGPs, and some Gb interface functions.
SPB supports the following cables:
l Supports 120/75 Ω resistance selection, and supports coaxial cable and twisted pair.
l Supports 100 Ω twisted pair for T1.
a. Interface unit: It is connected with circuit switching unit, and provides E1 interface.
b. Circuit switching unit: The circuit of the interface unit and backplane realizes the
switching function.
The data from E1 interface or backplane is sent to the circuit switching unit for switching
after being processed by the interface unit, then sent to CPU, and at last sent to other
board by switching unit for processing.
5-100
1. SPB panel for front board 2. SPB Layout 3. RSPB Panel for rear board
5-101
Name Description
Running indi-
RUN green cator Refer to "Description of combined indicator status"
Ac-
tive/standby ON: Indicates the board is active
ACT green indicator OFF: Indicates the board is standby
5-102
Setup
Name of
DIP Switch Purpose Mode 1 2 3 4
a. S3~S6 are used to choose the receiving matching resistance in different E1s.
OFF indicates that the matching resistance is 120 ohms and ON indicates that
the matching resistance is 75 ohms.
l Channels 1-4 of S3 respectively represent the E1s in channel 1-4.
l Channels 1-4 of S4 respectively represent the E1s in channel 5-8.
l Channels 1-4 of S5 respectively represent the E1s in channel 9-12.
l Channels 1-4 of S6 respectively represent the E1s in channel 13-16.
b. S1 and S2 indicate the receiving matching impedance and long/short haul state
of each E1 chip respectively. CPU reads this status during power-on and initiates
each E1 chip according to this status.
5-103
2. Jumper Description
SPB supports two types of external trunk cables: 75 ohms co-axial cables and 120
ohms balanced symmetric cables. There are four jumpers on the RSPB panel, as
shown in Figure 5-46.
If co-axial cables are used, short-circuit blocks shall be added to the 32 jumpers of
X11, X12, X13 and X14. In other words, the negative end of E1 transmitting differential
cable is grounded directly, and the negative end of E1 receiving differential cable is
grounded through the capacitor.
On RSPB, the E1 line is configured as 75 ohms co-axial transmission mode by default.
The settings of X11-X14 are shown in Table 5-67.
5-104
Note:
Short-circuit blocks of jumpers X11-X14 on rear board shall be removed if E1 uses 120
ohms balanced cable.
5-105
5-106
1. SPB2 panel for front board 2. RSPB Panel for rear board
5-107
Name Description
5-108
5-109
5-110
1. UIMC Panel for front board 2. RUIM2 panel for rear board 3. RUIM3 panel for rear board
FE1 Bi.
FE3 Bi.
Provides 10 cascading network ports
FE5 Bi.
through the two rear boards in active and
FE7 Bi.
standby slots
FE9 Bi. FE7 and FE9 are used for TRUNK, unused.
5-111
FE2 Bi.
RUIM3 panel for rear Serial debugging network port on CPU sub-
board DEBUG-232 Bi. card, connected to the debug machine.
Name Description
5-112
UIMU provides the clock-driven function in the gigabit resource shelf. The input 8 kHz and
16 MHz signals are distributed to various slots after phase lock and driving, to provide 16
MHz and 8 kHz clocks to boards in the gigabit resource shelf.
UIMU provides the resource shelf management function, RS-485 management interface in
the resource shelf, and the signal collection function to reset boards of the resource shelf.
5-113
5-114
1. UIMU Panel for front board 2. RUIM1 panel for rear board
5-115
RUIM1 panel for Debugs serial port for CPU system, connects
rear board DEBUG-232 Bi. the debugging machine.
Name Description
5-116
5-117
5-118
a. The user plane data from UIMU board enters the board via FE interface at user
plane, passes the Ethernet switching unit, and is distributed to the DSP unit.
b. After the DSP unit processes relative user plane protocols, the data is switched to
SPB via FE interface at user plane.
5-119
5-120
Name Description
5-121
5-122
6-1
6.1.2 Principle
Figure 6-1 shows the working principle of ALB board.
6-2
The voice management at background realizes the voice recording, edit and
pre-play, and downloads the voice file into the FLASH of the alarm box.
c. LCD screen
6-3
There are some function buttons on the alarm box, which realize the operation
and maintenance functions together with LCM.
4. Logic unit
Use EPLD to implement the required combinational and sequential logic.
5. Power supply unit
The input voltage of the alarm box is -48 V DC from the equipment room, and is
converted to +5 V, +3.3 V and other voltages for each unit by DC-DC power converter.
When the alarm box is in the duty room outside the equipment room, there may not be -48
V DC power, in this case, a external AC/DC power adapter is required to convert 110/220
V AC to 48 V DC, providing -48 V DC power to the alarm box. AC/DC power adaptor is an
optional accessory of the alarm box.
6.1.3 Panel
Figure 6-2 shows the appearance of alarm box.
6-4
The left top of the panel is the indicator in arc shape and the LCD screen is located in the
center of the panel.
6.1.4 Interfaces
Figure 6-4 shows the interfaces of alarm box.
ZXG10 iBSC uses 2 to connect Hub and background EMS, 4 to download alarm box
versions, 6 to connect DC power supply, and 7 for power supply.
1. The alarm box comprises cover components, body components, PCB board,
apparatus, and assembly fasteners.
a. Cover components include LCD screen, buttons, indicators, and lamp plate.
b. Body components are the sheet-metal parts to mount the motherboard and
speakers.
6-5
d. Apparatus contains LCD screen, indicators, buttons, switches, RJ11, RJ45, DB9,
earphone hole, mobile antenna, GPS interface, 48V socket, and speakers.
e. Alarm box is locked.
f. The outline dimensions of an alarm box is: 220 mm x 310 mm x 58 mm (H x W x
D)
2. Interface Description
The relevant interfaces on the alarm box board are described in Table 6-1
The parallel bus of the master unit attaches cable MODEM chip,
to provide the external cable modem interface and to implement
Cable modem in- the cable transmission of alarm information (currently, ZXG10
Box back terface iBSC does not use this interface).
6-6
6.1.5 Buttons
Table 6-2 shows the buttons on ALB panel.
Name Description
6.1.6 Indicators
Table 6-3 explains the ALB indicators.
6-7
6-8
ALB expansion function enables ALB to be installed in remote areas and connected
to the remote server, and receives on-site alarms through the data network. One ALB
can simultaneously connect five background servers at most.
In feeder cable direct-connection solution, the GPS active antenna is used as outdoor
receiving antenna; while in indoor forwarding solution, the GPS active antenna is used as
indoor receiving antenna.
Function Description
The GPS antenna receives GPS satellite navigation and positioning signals, and
demodulates the frequency, clock signal, and AGPS information through GPS signal
receiver. The clock signal is sent to relevant units in ZXG10 iBSC system while the AGPS
information is sent to the processing unit.
6-9
Device Description
1. Figure 6-7 shows the active GPS antenna.
6-10
Wiring Description
Figure 6-9 shows connections between ICM, GPS active antenna, and GPS antenna
lightning protector/frequency divider (fixed on the cabinet top).
Figure 6-9 Connection of ICM, Active GPS Antenna, and Lightning Protector/Frequency
Divider
1. GPS antenna
2. GPS Antenna Lightning
Protector/Frequency
Divider
Technical Parameters
1. Table 6-4 shows the technical parameters of active GPS antenna.
Parameter Specification
DC voltage 4.5 ~ 6 V
DC current <35 mA
6-11
Parameter Specification
Insertion loss ≤ 4 dB
Parameter Specification
Gain 45 dB ± 2 dB
6-12
Parameter Specification
Connectors TNC
2. Table 6-7 describes technical parameters of the GPS L1 indoor transmitting antenna.
Parameter Specification
Gain 26 dB ± 2 dB
Connectors TNC
Cable length 10 m
Parameter Specification
Current 80 mA
Connectors TNC
6-13
Parameter Specification
DC voltage 5.5 V
Remained voltage 20 V
Installation Mode Installing through the wall; installing by the copper lug
6-14
7.1 Overview
ZXG10 iBSC has multiple interfaces. There are several connection modes for each
interface. The user can select the interface connection on demands.
The section below describes the typical configurations based on BUSN and BGSN.
7-1
7-2
7-3
Figure 7-3 IP+E1 at Abis and STM-1 at A interface for Resource Shelf
7-4
7-5
7-6
Figure 7-6 E1 at Abis and E1 (Outer TC) at Ater interface for Resource Shelf
7-7
Figure 7-7 E1 at Abis and STM-1 (Outer TC) at Ater interface for Resource Shelf
7-8
7-9
7-10
7-11
7-12
7-13
7-14
Figure 7-14 IPoE at Abis and E1 (T1) at A-interface for GB Resource Shelf
7-15
Figure 7-15 IPoE at Abis and STM-1 at A-interface for GB Resource Shelf
7-16
7-17
7-18
7-19
7-20
Periodically flashing
Running normally at 1 Hz Always OFF Normal running
Periodically flashing
at 5 Hz Always OFF Version being downloaded
Periodically flashing
Always OFF at 5 Hz Board self-test failure.
A-1
Periodically flashing
at 1 Hz Always ON Hardware clock is lost.
A-2
I
ZXG10 iBSC Hardware Description
II
Figures
Figure 4-37 Wiring at User Plane in an iBSC Cabinet for GB Resource Shelf ........... 4-43
Figure 4-38 Wiring of Monitoring Cables in an iBSC Cabinet for GB Resource
Shelf ..................................................................................................... 4-44
Figure 4-39 Wiring of Clock Extraction Distribution In the iBSC Dual-Cabinet for
GB Resource Shelf ............................................................................... 4-45
Figure 4-40 Ethernet Connection at Control Plane in the iBSC Dual-Cabinet for
GB Resource Shelf ............................................................................... 4-46
Figure 4-41 Wiring at User Plane in the iBSC Dual-Cabinet for GB Resource
Shelf ..................................................................................................... 4-46
Figure 4-42 Wiring of Monitoring Cables in the iBSC Dual-Cabinet for GB
Resource Shelf ..................................................................................... 4-47
Figure 5-1 Board Assembly....................................................................................... 5-2
Figure 5-2 Principle of BIPI Board............................................................................. 5-3
Figure 5-3 BIPI Board ............................................................................................... 5-4
Figure 5-4 Principle of CHUB Board.......................................................................... 5-7
Figure 5-5 CHUB Board............................................................................................ 5-8
Figure 5-6 Principle of CLKG (CLKG) board ........................................................... 5-11
Figure 5-7 CLKG (CLKG) Board ............................................................................. 5-12
Figure 5-8 Principle of CLKG (ICM) Board .............................................................. 5-20
Figure 5-9 CLKG (ICM) Board ................................................................................ 5-21
Figure 5-10 Principle of CMP Board........................................................................ 5-28
Figure 5-11 CMP Board .......................................................................................... 5-29
Figure 5-12 DTB Principle....................................................................................... 5-32
Figure 5-13 DTB Board........................................................................................... 5-33
Figure 5-14 Layout of DTB board for front board (version 060201).......................... 5-33
Figure 5-15 Jumpers on RDTB board ..................................................................... 5-36
Figure 5-16 Principle of EIPI Board ......................................................................... 5-38
Figure 5-17 EIPI Board ........................................................................................... 5-39
Figure 5-18 Principle of GLI Board .......................................................................... 5-41
Figure 5-19 GLI Panel............................................................................................. 5-42
Figure 5-20 GLI4 Panel........................................................................................... 5-45
Figure 5-21 Principle of GIPI board ......................................................................... 5-48
Figure 5-22 GIPI Board........................................................................................... 5-49
Figure 5-23 GUIM Principle..................................................................................... 5-52
Figure 5-24 GUIM Board......................................................................................... 5-53
Figure 5-25 GUIM2 Board....................................................................................... 5-58
Figure 5-26 Principle of GUP board ........................................................................ 5-61
III
ZXG10 iBSC Hardware Description
IV
Figures
V
Figures
VII
ZXG10 iBSC Hardware Description
VIII
Tables
IX
ZXG10 iBSC Hardware Description
X
Glossary
APS
- Automatic Protection Switching
Abis
- Abis Interface between BSC and BTS
BCTC
- Backplane of ConTrol Center
BGSN
- Backplane of Giga universal Service Network
BPSN
- Backplane of Packet Switch Network
BSSAP
- Base Station System Application Part
BSSGP
- Base Station System GPRS Protocol
BTS
- Base Transceiver Station
BUSN
- Backplane Of Universal Service Network
CAS
- Channel Associated Signaling
CCS
- Common Channel Signaling
CHUB
- Control plane HUB
CLKG
- CLOCK Generator
CMP
- Calling Main Processor
CS
- Circuit Switched
DTB
- Digital Trunk Board
FE
- Fast Ethernet
XI
ZXG10 iBSC Hardware Description
GE
- Gigabit Ethernet
GLI
- Gigabit Line Interface
GLI4
- Gigabit Line Interface 4
GPRS
- General Packet Radio Service
GPS
- Global Positioning System
GUIM
- Gigabit Universal Interface Module
GUIM2
- GE Universal Interface Module 2
GUP
- Generic User Profile
ICM
- Integrated Clock Module
IP
- Internet Protocol
MGW
- Media GateWay
MSC
- Mobile Switching Center
OMM
- Operation & Maintenance Module
OMP
- Operation Main Processor
PCU
- Packet Control Unit
PS
- Packet Switched
PSN
- Packet Switched Network
PWRD
- PoWeR Distributor
QoS
- Quality of Service
XII
Glossary
RCHB1
- Rear Board 1 of CHUB
RCHB2
- Rear Board 2 of CHUB
RCKG1
- Rear Board 1 of CLKG
RCKG2
- Rear Board 2 of CLKG
RDTB
- Rear Board of DTB
RGER
- Rear Giga Ethernet Board of Resource
RGIM1
- General Rear Interface Module 1
RMNIC
- Rear Board of MNIC
RMPB
- Rear Board of MP
RSPB
- Rear Board of SPB
RSVB
- Rearcard of SerVe Board
RTP
- Real-time Transport Protocol
RUIM2
- Rear board of UIM (type2)
RUIM3
- Rear board of UIM (type3)
SBCX
- X86 Single Board Computer
SDTB
- Sonet Digital Trunk Board
SGSN
- Service GPRS Supporting Node
SPB
- Signaling Processing Board
STM
- Synchronous Transfer Mode
XIII
ZXG10 iBSC Hardware Description
TC
- TransCoder
TCU
- TransCoder Unit
UIMC
- Universal Interface Module for Control plane (BCTC or BPSN)
UIMU
- Universal Interface Module for User Plane
XIV