Introduction
The Blast Chip design system uses a unique constant delay methodology in which delays
through the cells of a design are fixed initially. The optimization process used by Blast
Chip then performs buffer or inverter insertion, gate sizing, and other logic restructuring
operations to meet timing goals.
Optimization is performed using SuperCell models, which characterize the timing
behavior of library cells. In well designed libraries, where the delay of SuperCell models
scales linearly with the load and assuming that every SuperCell model is continuously
sizable, it is theoretically possible to meet the delays computed by the constant delay
methodology regardless of the actual load after placement.
Real libraries frequently do not have cells with sizes that can drive all possible loads.
Therefore, it is possible that the largest available cell in the library is not capable of driving
a load that is necessary to meet timing objectives. Situations like this are referred to as
“load violations.”
This document describes how to use the report that is produced when you execute the
report clone command to identify load violations and how to interpret the report.
Methodology
The SuperCell model allows you to reason about delay in the absence of knowledge
about capacitance. Before placement, nothing is known about the actual wire lengths.
In this stage, (fix time) you use the SuperCell model to get an estimate of the timing.
Because this model is both simpler and more accurate than using wire load models, the
use of SuperCell models speeds the timing optimization. Furthermore, as the SuperCell
models are continuous models, rather than discrete models, they lend themselves to
continuous optimization methods. Due to the relative smoothness of the state space,
such methods are less prone to getting caught in local minima.
After placement, the estimates of the wire capacitances become more accurate.
The accuracy of the SuperCell model is now increasingly dependent on the ability to find
the right size for each cell for the given load. Obviously, the continuous sizing assumption
is optimistic, and in real libraries there are only a limited number of sizes available.
Clone Report
To aid in identifying these situations, Blast Chip has the clone report. The reason that it is
called the clone report is that cloning is one of the main methods of increasing drive
strengths. However, unlike sizing and creating parallel cells, this method has a large
number of different circumstantial constraints. The clone report lists the size of the load
violation for each cell and the reason it cannot be cloned. The clone report lists all load
violations sorted by size.
Table 1 lists the column names that can be added to the clone report.
Problems
problem violation cause total load slack model pin
------------- --------- ---------- ---------- ----- --------- -----------------
Primary In 3.053 Cap Limit 243 167 * fa_ct_c_prefix_1
Too Much Wire 2.245 Overload 184 -49 SC_ND3B C43194_2/Z
Primary In 2.220 Cap Limit 193 97 * x86_inst_rot_ctl
Primary In 1.752 Cap Limit 165 -49 * w_profile_en
Too Much Wire 1.595 Overload 631 52 SC_O22AIH C43348/Z
May Clone 1.576 Overload 417 -45 SC_NR3H taxi_U514.C1_2/Z
Single Fanout 1.202 Overload 67 320 SC_NR3A C42293_3/Z
May Clone 1.154 Overload 367 96 SC_NR3H dec_U851.C1_3/Z
Single Fanout 1.108 Overload 61 74 SC_A2O1IA C41663_2/Z
May Clone 1.103 Overload 221 17 SC_INVA BW1_INV1695_7/Z
May Clone 1.085 Rise Limit 704 2524 SC_NR2B fp_smu_U338.C2/Z
Single Fanout 0.959 Overload 251 38 SC_ND2B gen_U1132.C1/Z
Primary In 0.898 Cap Limit 114 75 * c_misc_mark
Single Fanout 0.813 Overload 66 437 SC_NR3A C42299_3/Z
May Clone 0.793 Overload 373 313 SC_ND3H dec_U881.C1_2/Z
Too Much Wire 0.724 Overload 342 353 SC_ND3D C42856_2/Z
May Clone 0.693 Overload 162 163 SC_INR2B gen_U1081.C2/Z
May Clone 0.682 Overload 2027 64 SC_INVP C51540/Z
May Clone 0.679 Overload 465 192 SC_INR2H info_U109.C1/Z
May Clone 0.669 Overload 60 148 SC_A2O1IA C43378/Z
Too Much Wire 0.666 Overload 285 -49 SC_NR3H taxi_U580.C2_6/Z
Single Fanout 0.629 Overload 288 38 SC_NR3H C41051_12/Z
May Clone 0.622 Overload 105 255 SC_ND2A dec2_U263.C1/Z
May Clone 0.607 Overload 127 381 SC_INR2A reg_U253.C2_1/Z
Single Fanout 0.578 Overload 62 121 SC_ND2A C41666_4/Z
May Clone 0.569 Overload 217 189 SC_IND2B C41027/Z
Total wire length 1.36607 meter
Total wire load 292.851 pf
Total area 0.735351 sq mm
* * * Overload Summary * * *
Problem Count Average(%) Worst(%)
------------------ ----- ---------- --------
May Clone 782 20.9 157.6
Single Fanout 295 22.0 120.2
Don't Clone Entity 14 15.6 32.5
Primary Out 37 21.6 39.5
Primary In 469 22.3 305.3
Too Much Wire 160 23.7 224.5
------------------ ----- ---------- --------
Total 1757 21.7 305.3
Don’t Clone Cell Cannot clone because of a noclone Use clear noclone on cell.
directive on cell.
Don’t Clone Model Cannot clone because of noclone Use clear noclone on model.
directive on the model.
Don’t Clone Entity Cannot clone because of noclone Use clear noclone on entity.
directive on the entity.
Cell has InOut Cannot clone because cell has Rearchitect the design to
bidirectional in-out pins. eliminate bidirectional pins.
Net has InOut Cannot clone because net has In Rearchitect the design to
Out (bi-directional) pins. eliminate bidirectional pins.
Multisource Cannot clone because the net has Rearchitect the design to
multiple sources. eliminate multisource nets.
Primary output Cannot clone primary output. Reduce loading on primary output.
Relax timing constraint on primary
output.
Primary input Cannot clone primary input. Relax timing constraint on primary
input. Increase driving cell
strength on input. Relax
capacitance limit on input.
Too Much Wire Cloning results in duplication of large Increase drive by using parallel
amount of wire. This cell is not cells. Increase force limit parallel
suitable for driving long wires. on the model.
Output Net Kept Output net topology may not be Use clear keep of output net.
modified.
Not Bound Cell is not bound to a model master. Read in missing models and bind
using the run bind logical
command.
Overload Summary
The overload summary at the end of the report lists the total number of overloads and the
cause of them. Similar tables are also printed by various optimization commands and are
primarily intended to monitor the performance of various algorithms. Each line shows the
number of overloaded cells, the average overload, and the worst overload.
Gain Table
The following table is printed by the run gate trim command:
* Output Gain Distribution *
Gain Range Count Pct
------------------------------
0.52...1.00 580 5.5%
------------------------------
1.00...2.00 3229 30.6%
2.00...4.00 3974 37.7%
4.00...8.00 2693 25.5%
8.00..10.00 69 0.7%
You can use this table to estimate how timing critical the entire design is. It divides the
cells into ranges by gain. The ranges each occupy a 2x range in gain. The boundaries of
the ranges are 0.25, 0.5, 1, 2, 4, 8—each an increasing factor of 2, except for the first and
the last range. The low end of the first range shows the actual smallest output gain
anywhere in the design, and the high end of the last range shows the actual highest
output gain anywhere in the system.
The Count column is the number of outputs with gain falling in this range, and the Pct
column shows this number as a percentage of the total number of outputs. You can
consider the ranges above the bar critical, and below the bar as non-critical.
In the previous example, there are no critical pins. The smallest gain is 1.20, which is not
considered critical. You can expect meeting the timing on this design to be easy.
* Output Gain Distribution *
Gain Range Count Pct
------------------------------
0.20...0.25 1436 13.6%
0.25...0.50 1136 10.8%
0.50...1.00 2239 21.2%
------------------------------
1.00...2.00 3039 28.8%
2.00...4.00 1797 17.0%
4.00...8.00 829 7.9%
8.00..10.00 69 0.7%
In the previous example, the smallest gain is 0.2, which is an extremely small value (0.2 is
a hard limit in trim). Moreover, there are a large number of outputs in the smallest ranges.
This indicates an over constrained design that will not meet timing after placement. You
might have an error in your timing constraints.
Cloning
Cloning is usually enabled for combinational cells, but is turned off for sequential cells.
The no clone restriction can be turned off by the clear noclone command. Cloning
sequential cells can eliminate load violations, but can pose function verification
challenges. Depending on the methodology for formal verification, such copies can cause
a problem. Modern formal verification tools can handle this simple sequential verification
issue, older tools, however, report a functional mismatch due to the mismatch in the
number of sequential elements. Cloning sequential cells can also pose a problem for the
initialization of the design. Depending on the initialization methodology, there might be a
problem. Cloning sequential elements is safe if the initialization is based on one of the
following methods:
1. Set or reset signal to sequential elements.
2. Scan in initial state using scan chain.
3. Verify initialization using three valued (0, 1, X) simulation.