UVM Registers Abstraction

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ClueLogic > UVM > UVM Tutorial for Candy Lovers – 9. Register Abstraction
UVM Tutorial for Candy Lovers – 9. Register Abstraction

 October 29, 2012  Keisuke Shimizu
Last Updated on June 7, 2015
This post will explain how to use the UVM Register Abstraction Layer (RAL) to generate register transactions. The figure
below shows the verification platform used for this post. Among other things, the jelly_bean_reg_block, the
jelly_bean_reg_adapter, and the jelly_bean_reg_predictor are the classes used for the register abstraction.
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Verification Platform
The figure below shows the diagram of the RAL-related classes. The standard UVM classes are shown in pink, while the
jelly-bean classes are shown in light blue. The diagram looks busy, but bear in mind that I will explain each jelly-bean
class one by one.
Diagram of the Jelly-Bean-Register Related Classes
Register Definitions
In the previous posts, the DUT had no accessible registers. We are going to add the registers that hold jelly-bean recipe
information and its taste. We will also add a command input port to the DUT so that we can write a jelly-bean recipe to the
register and read its taste. The figure below shows the register definition of the DUT.
DUT Registers
The source code of the DUT (jelly_bean_taster) is shown below. When the command input is WRITE, the values of flavor
color, sugar_free, and sour input ports are written to the RECIPE register (line 22 to 25). When the command input is READ
the TASTE register is read out and the taste output is driven accordingly (line 27).
1 module jelly_bean_taster( jelly_bean_if.slave_mp jb_slave_if );

2 import jelly_bean_pkg::*;
3
4 reg [2:0] flavor;
5 reg [1:0] color;
6 reg sugar_free;
7 reg sour;
8 reg [1:0] command;
9 reg [1:0] taste;
10
11 initial begin
12 flavor = 0;
13 color = 0;
14 sugar_free = 0;
15 sour = 0;
16 command = 0;
17 taste = 0;
18 end
19
20 always @ ( posedge jb_slave_if.clk ) begin
21 if ( jb_slave_if.command == jelly_bean_types::WRITE ) begin
22 flavor < = jb_slave_if.flavor;
23 color <= jb_slave_if.color;
24 sugar_free <= jb_slave_if.sugar_free;
25 sour <= jb_slave_if.sour;
26 end else if ( jb_slave_if.command == jelly_bean_types::READ ) begin
27 jb_slave_if.taste <= taste;
28 end
29 end
30
31 always @ ( posedge jb_slave_if.clk ) begin
32 if ( jb_slave_if.flavor == jelly_bean_types::CHOCOLATE &&
33 jb_slave_if.sour ) begin
34 taste <= jelly_bean_types::YUCKY;
35 end else if ( jb_slave_if.flavor != jelly_bean_types::NO_FLAVOR ) begin
36 taste <= jelly_bean_types::YUMMY;
37 end
38 end
39 endmodule: jelly_bean_taster
Register Model
The model of the RECIPE register is defined by extending the uvm_reg class. Each field of the register is defined as a
uvm_reg_field (line 4 to 7). The fields are configured in the build function. Note that the name, build, is used for
convenience. Do not confuse it with the build_phase of the uvm_component because the uvm_reg is not a uvm_component
1 class jelly_bean_recipe_reg extends uvm_reg;

2 ùvm_object_utils( jelly_bean_recipe_reg )
3
4 rand uvm_reg_field flavor;
5 rand uvm_reg_field color;
6 rand uvm_reg_field sugar_free;
7 rand uvm_reg_field sour;
8
9 constraint flavor_color_con {
10 flavor.value != jelly_bean_types::NO_FLAVOR;
11 flavor.value == jelly_bean_types::APPLE
12 -> color.value != jelly_bean_types::BLUE;
13 flavor.value == jelly_bean_types::BLUEBERRY
14 -> color.value == jelly_bean_types::BLUE;
15 flavor.value < = jelly_bean_types::CHOCOLATE;
16 }
17
18 function new( string name = "jelly_bean_recipe_reg" );
19 super.new( .name( name ), .n_bits( 7 ), .has_coverage( UVM_NO_COVERAGE ) );
20 endfunction: new
21
22 virtual function void build();
23 flavor = uvm_reg_field::type_id::create( "flavor" );
24 flavor.configure( .parent ( this ),
25 .size ( 3 ),
26 .lsb_pos ( 0 ),
27 .access ( "WO" ),
28 .volatile ( 0 ),
29 .reset ( 0 ),
30 .has_reset ( 1 ),
31 .is_rand ( 1 ),
32 .individually_accessible( 0 ) );
33
34 color = uvm_reg_field::type_id::create( "color" );
35 color.configure( .parent ( this ),
36 .size ( 2 ),
37 .lsb_pos ( 3 ),
39 .volatile ( 0 ),
40 .reset ( 0 ),
42 .is_rand ( 1 ),
44
45 sugar_free = uvm_reg_field::type_id::create( "sugar_free" );
46 sugar_free.configure( .parent ( this ),
47 .size ( 1 ),
48 .lsb_pos ( 5 ),
50 .volatile ( 0 ),
51 .reset ( 0 ),
53 .is_rand ( 1 ),
55
56 sour = uvm_reg_field::type_id::create( "sour" );
57 sour.configure( .parent ( this ),
58 .size ( 1 ),
59 .lsb_pos ( 6 ),
61 .volatile ( 0 ),
62 .reset ( 0 ),
64 .is_rand ( 1 ),
66 endfunction: build
67 endclass: jelly_bean_recipe_reg
The model of the TASTE register is similarly defined.
1 class jelly_bean_taste_reg extends uvm_reg;

2 ùvm_object_utils( jelly_bean_taste_reg )
3
4 rand uvm_reg_field taste;
5
6 function new( string name = "jelly_bean_taste_reg" );
7 super.new( .name( name ), .n_bits( 2 ), .has_coverage( UVM_NO_COVERAGE ) );
8 endfunction: new
9
11 taste = uvm_reg_field::type_id::create("taste");
12 taste.configure( .parent ( this ),
13 .size ( 2 ),
14 .lsb_pos ( 0 ),
15 .access ( "RO" ),
16 .volatile ( 1 ),
17 .reset ( 0 ),
19 .is_rand ( 1 ),
22 endclass: jelly_bean_taste_reg
Register Block
The jelly_bean_reg_block contains the two registers created above and defines a register map.
1 class jelly_bean_reg_block extends uvm_reg_block;

2 ùvm_object_utils( jelly_bean_reg_block )
3
4 rand jelly_bean_recipe_reg jb_recipe_reg;
5 rand jelly_bean_taste_reg jb_taste_reg;
6 uvm_reg_map reg_map;
7
8 function new( string name = "jelly_bean_reg_block" );
9 super.new( .name( name ), .has_coverage( UVM_NO_COVERAGE ) );
10 endfunction: new
11
13 jb_recipe_reg = jelly_bean_recipe_reg::type_id::create( "jb_recipe_reg" );
14 jb_recipe_reg.configure( .blk_parent( this ) );
15 jb_recipe_reg.build();
16
17 jb_taste_reg = jelly_bean_taste_reg::type_id::create( "jb_taste_reg" );
18 jb_taste_reg.configure( .blk_parent( this ) );
19 jb_taste_reg.build();
20
21 reg_map = create_map( .name( "reg_map" ), .base_addr( 8'h00 ),
22 .n_bytes( 1 ), .endian( UVM_LITTLE_ENDIAN ) );
23 reg_map.add_reg( .rg( jb_recipe_reg ), .offset( 8'h00 ), .rights( "WO" ) );
24 reg_map.add_reg( .rg( jb_taste_reg ), .offset( 8'h01 ), .rights( "RO" ) );
25 lock_model(); // finalize the address mapping
27
28 endclass: jelly_bean_reg_block
Register Adapter
The jelly_bean_reg_adapter class provides two functions to convert between a uvm_reg_bus_op and a
jelly_bean_transaction. The reg2bus function converts a uvm_reg_bus_op into a jelly_bean_transaction, whereas
the bus2reg function converts a jelly_bean_transaction back to a uvm_reg_bus_op.
The uvm_reg_adapter is a uvm_object, not a uvm_component.
Advanced Topic: Even though a uvm_sequence is a uvm_sequence_item, you cannot let the reg2bus() function create a
uvm_sequence and return it. This is because when a register is read/written, the uvm_reg_map calls
uvm_sequence_base::start_item() passing the object returned by the reg2bus(), but the start_item() does not
expect a uvm_sequence. This will cause a fatal error. For more details, please see Register Access Methods.
1 class jelly_bean_reg_adapter extends uvm_reg_adapter;

2 ùvm_object_utils( jelly_bean_reg_adapter )
3
4 function new( string name = "" );
5 super.new( name );
6 supports_byte_enable = 0;
7 provides_responses = 0;
8 endfunction: new
9
10 virtual function uvm_sequence_item reg2bus( const ref uvm_reg_bus_op rw );
11 jelly_bean_transaction jb_tx
12 = jelly_bean_transaction::type_id::create("jb_tx");
13
14 if ( rw.kind == UVM_READ ) jb_tx.command = jelly_bean_types::READ;
15 else if ( rw.kind == UVM_WRITE ) jb_tx.command = jelly_bean_types::WRITE;
16 else jb_tx.command = jelly_bean_types::NO_OP;
17 if ( rw.kind == UVM_WRITE )
18 { jb_tx.sour, jb_tx.sugar_free, jb_tx.color, jb_tx.flavor } = rw.data;
19 return jb_tx;
20 endfunction: reg2bus
21
22 virtual function void bus2reg( uvm_sequence_item bus_item,
23 ref uvm_reg_bus_op rw );
24 jelly_bean_transaction jb_tx;
25
26 if ( ! $cast( jb_tx, bus_item ) ) begin
27 ùvm_fatal( get_name(),
28 "bus_item is not of the jelly_bean_transaction type." )
29 return;
30 end
31
32 rw.kind = ( jb_tx.command == jelly_bean_types::READ ) ? UVM_READ : UVM_WRITE;
33 if ( jb_tx.command == jelly_bean_types::READ )
34 rw.data = jb_tx.taste;
35 else if ( jb_tx.command == jelly_bean_types::WRITE )
36 rw.data = { jb_tx.sour, jb_tx.sugar_free, jb_tx.color, jb_tx.flavor };
37 rw.status = UVM_IS_OK;
38 endfunction: bus2reg
39
40 endclass: jelly_bean_reg_adapter
Register Predictor
The register predictor updates the values of the register model based on observed bus transactions. As the jelly-bean
register predictor is not involved with any kind of extended features, the uvm_reg_predictor is used as is.
typedef uvm_reg_predictor#( jelly_bean_transaction ) jelly_bean_reg_predictor;
Agent
The jelly_bean_agent instantiates the jelly_bean_reg_adapter (line 35).
1 class jelly_bean_agent extends uvm_agent;

2 ùvm_component_utils( jelly_bean_agent )
3
4 uvm_analysis_port#( jelly_bean_transaction ) jb_ap;
5
6 jelly_bean_agent_config jb_agent_cfg;
7 jelly_bean_sequencer jb_seqr;
8 jelly_bean_driver jb_drvr;
9 jelly_bean_monitor jb_mon;
10 jelly_bean_reg_adapter jb_reg_adapter;
11
12 function new( string name, uvm_component parent );
13 super.new( name, parent );
14 endfunction: new
15
16 function void build_phase( uvm_phase phase );
17 super.build_phase( phase );
18
19 if ( ! uvm_config_db#( jelly_bean_agent_config )::get( .cntxt( this ),
20 .inst_name ( "" ),
21 .field_name( "jb_agent_cfg" ),
22 .value( jb_agent_cfg ))) begin
23 ùvm_error( "jelly_bean_agent", "jb_agent_cfg not found" )
24 end
25
26 jb_ap = new( .name( "jb_ap" ), .parent( this ) );
27 if ( jb_agent_cfg.active == UVM_ACTIVE ) begin
28 jb_seqr = jelly_bean_sequencer::type_id::create( .name( "jb_seqr" ),
29 .parent( this ) );
30 jb_drvr = jelly_bean_driver::type_id::create( .name( "jb_drvr" ),
32 end
33 jb_mon = jelly_bean_monitor::type_id::create( .name( "jb_mon" ),
35 jb_reg_adapter = jelly_bean_reg_adapter::type_id::create( .name( "jb_reg_adapter" ) );
36 endfunction: build_phase
37
38 function void connect_phase( uvm_phase phase );
39 super.connect_phase( phase );
40
41 jb_mon.jb_if = jb_agent_cfg.jb_if;
42 if ( jb_agent_cfg.active == UVM_ACTIVE ) begin
43 jb_drvr.seq_item_port.connect( jb_seqr.seq_item_export );
44 jb_drvr.jb_if = jb_agent_cfg.jb_if;
45 end
46 jb_mon.jb_ap.connect( jb_ap );
47 endfunction: connect_phase
48 endclass: jelly_bean_agent
Environment Configuration
The jelly_bean_env_config has a handle to the jelly_bean_reg_block so that the jelly_bean_env can access the
register model.
1 class jelly_bean_env_config extends uvm_object;

2 ùvm_object_utils( jelly_bean_env_config )
3
4 bit has_jb_agent = 1;
5 bit has_jb_sb = 1;
6
8 jelly_bean_reg_block jb_reg_block;
9
12 endfunction: new
13 endclass: jelly_bean_env_config
Environment
The jelly_bean_env instantiates the jelly_bean_agent and the jelly_bean_reg_predictor (line 28 to 31), then
connects register-related objects:
Firstly, in the connect_phase(), the set_sequencer() function associates the jelly-bean sequencer and the register
adapter with the register map (line 45 and 46). The set_sequencer() must be called before starting the sequence based
on a uvm_reg_sequence. A register block may have more than one register map.
Secondly, the register map and the register adapter are associated with the register predictor (line 49 and 50). The
register predictor will use the register map and the register adapter to convert a jelly_bean_transaction back to a
register operation.
Lastly, the register predictor is connected to the agent to subscribe the jelly_bean_transactions from the agent (line
51).
1 class jelly_bean_env extends uvm_env;

2 ùvm_component_utils( jelly_bean_env )
3
4 jelly_bean_env_config jb_env_cfg;
5 jelly_bean_agent jb_agent;
6 jelly_bean_fc_subscriber jb_fc_sub;
7 jelly_bean_scoreboard jb_sb;
8 jelly_bean_reg_predictor jb_reg_predictor;
9
12 endfunction: new
13
14 function void build_phase( uvm_phase phase );
15 super.build_phase( phase );
16 if ( ! uvm_config_db#( jelly_bean_env_config )::get
17 ( .cntxt( this ),
18 .inst_name( "" ),
19 .field_name( "jb_env_cfg" ),
20 .value( jb_env_cfg ) ) ) begin
21 ùvm_fatal( get_name(), "jb_env_cfg not found" )
22 end
23
24 uvm_config_db#( jelly_bean_agent_config )::set( .cntxt( this ),
25 .inst_name( "jb_agent*" ),
26 .field_name( "jb_agent_cfg" ),
27 .value( jb_env_cfg.jb_agent_cfg ) );
28 jb_agent = jelly_bean_agent::type_id::create( .name( "jb_agent" ),
30 jb_reg_predictor = jelly_bean_reg_predictor::type_id::create( .name( "jb_reg_predictor" ),
32 if ( jb_env_cfg.has_jb_sb ) begin
33 jb_sb = jelly_bean_scoreboard::type_id::create( .name( "jb_sb" ),
35 end
36 jb_fc_sub = jelly_bean_fc_subscriber::type_id::create( .name( "jb_fc_sub" ),
39
40 function void connect_phase( uvm_phase phase );
41 super.connect_phase( phase );
42 jb_agent.jb_ap.connect( jb_fc_sub.analysis_export );
43 jb_agent.jb_ap.connect( jb_sb.jb_analysis_export );
44 if ( jb_env_cfg.jb_reg_block.get_parent() == null ) begin // if the top-level env
45 jb_env_cfg.jb_reg_block.reg_map.set_sequencer( .sequencer( jb_agent.jb_seqr ),
46 .adapter( jb_agent.jb_reg_adapter ) );
47 end
48 jb_env_cfg.jb_reg_block.reg_map.set_auto_predict( .on( 0 ) );
49 jb_reg_predictor.map = jb_env_cfg.jb_reg_block.reg_map;
50 jb_reg_predictor.adapter = jb_agent.jb_reg_adapter;
51 jb_agent.jb_ap.connect( jb_reg_predictor.bus_in );
52 endfunction: connect_phase
53
54 endclass: jelly_bean_env
Base Test
The base test instantiates a jelly_bean_reg_block (line 16 and 17) and stores its handle in the jelly_bean_env_config
(line 19 and 20).
1 class jelly_bean_base_test extends uvm_test;

2 ùvm_component_utils( jelly_bean_base_test )
3
4 jelly_bean_env jb_env;
5 jelly_bean_env_config jb_env_cfg;
8
11 endfunction: new
12
13 function void build_phase(uvm_phase phase);
14 super.build_phase(phase);
15
16 jb_reg_block = jelly_bean_reg_block::type_id::create( "jb_reg_block" );
17 jb_reg_block.build();
18
19 jb_env_cfg = jelly_bean_env_config::type_id::create( "jb_env_cfg" );
20 jb_env_cfg.jb_reg_block = jb_reg_block;
21
22 jb_agent_cfg = jelly_bean_agent_config::type_id::create( "jb_agent_cfg" );
23
24 if ( ! uvm_config_db#( virtual jelly_bean_if )::get( .cntxt( this ),
25 .inst_name( "" ),
26 .field_name( "jb_if" ),
27 .value( jb_agent_cfg.jb_if ))) begin
28 ùvm_error( "jelly_bean_test", "jb_if not found" )
29 end
30
31 jb_env_cfg.jb_agent_cfg = jb_agent_cfg;
32
33 uvm_config_db#(jelly_bean_env_config)::set( .cntxt( null ),
34 .inst_name( "*" ),
35 .field_name( "jb_env_cfg" ),
36 .value( jb_env_cfg ) );
37 jb_env = jelly_bean_env::type_id::create( .name( "jb_env" ),
40
41 virtual function void start_of_simulation_phase( uvm_phase phase );
42 super.start_of_simulation_phase( phase );
43 uvm_top.print_topology();
44 endfunction: start_of_simulation_phase
45
46 endclass: jelly_bean_base_test
Sequence without Register Abstraction

We have created all the components by now and we are ready to create a register sequence. But before doing that, let’s
create a “regular” sequence without using the register abstraction for comparison. The jelly_bean_sequence is a
sequence to generate a sour-green-apple jelly bean. The body of the sequence creates a jelly_bean_transaction, which
will be used by the driver to do pin wiggling.
1 class jelly_bean_sequence extends uvm_sequence#( jelly_bean_transaction );

2 ùvm_object_utils( jelly_bean_sequence )
3
6 endfunction: new
7
8 task body();
9 jelly_bean_transaction jb_tx;
10 jb_tx = jelly_bean_transaction::type_id::create( .name( "jb_tx" ),
11 .contxt( get_full_name()));
12 start_item( jb_tx );
13 jb_tx.flavor = jelly_bean_types::APPLE;
14 jb_tx.color = jelly_bean_types::GREEN;
15 jb_tx.sugar_free = 0;
16 jb_tx.sour = 1;
17 finish_item(jb_tx);
18 endtask: body
19 endclass: jelly_bean_sequence
Sequence Using Register Abstraction

The jelly_bean_reg_sequence is another sequence to generate a sour-green-apple jelly bean, but using the register
abstraction. This sequence is extended from the uvm_reg_sequence class so that we can use the convenience functions
such as write_reg() and read_reg(). The body of the sequence writes a recipe (line 23) to the RECIPE register, then
reads back its taste from the TASTE register (line 24). Note that we do not create a jelly_bean_transaction in the
sequence. The register adapter will convert the register operations into the corresponding jelly_bean_transactions.
1 class jelly_bean_reg_sequence extends uvm_reg_sequence;

2 ùvm_object_utils( jelly_bean_reg_sequence )
3
6 endfunction: new
7
8 virtual task body();
10 jelly_bean_types::flavor_e flavor;
11 jelly_bean_types::color_e color;
12 bit sugar_free;
13 bit sour;
14 uvm_status_e status;
15 uvm_reg_data_t value;
16
17 $cast( jb_reg_block, model );
18 flavor = jelly_bean_types::APPLE;
19 color = jelly_bean_types::GREEN;
20 sugar_free = 0;
21 sour = 1;
22
23 write_reg( jb_reg_block.jb_recipe_reg, status, { sour, sugar_free, color, flavor } );
24 read_reg ( jb_reg_block.jb_taste_reg, status, value );
25 endtask: body
26
27 endclass: jelly_bean_reg_sequence
Register Test
The jelly_bean_reg_test creates a jelly_bean_reg_sequence we have just created and starts the sequence (line 12 to
15).
1 class jelly_bean_reg_test extends jelly_bean_base_test;

2 ùvm_component_utils( jelly_bean_reg_test )
3
6 endfunction: new
7
8 task main_phase( uvm_phase phase );
9 jelly_bean_reg_sequence jb_reg_seq;
10
11 phase.raise_objection( .obj( this ) );
12 jb_reg_seq = jelly_bean_reg_sequence::type_id::create( .name( "jb_reg_seq" ),
13 .contxt( get_full_name()));
14 jb_reg_seq.model = jb_reg_block;
15 jb_reg_seq.start( .sequencer( jb_env.jb_agent.jb_seqr ) );
16
17 #100ns;
18 phase.drop_objection( .obj( this ) );
19
20 endtask: main_phase
21 endclass: jelly_bean_reg_test
Simulation
Let’s look at a simulation result. The simulation successfully generated a sour-green apple and read back its taste from the
DUT.
1 UVM_INFO jb3.sv(727) @ 30: uvm_test_top.jb_env.jb_sb [jelly_bean_scoreboard] You have a good sense of taste.
2 ---------------------------------------------------------
3 Name Type Size Value
4 ---------------------------------------------------------
5 jb_tx jelly_bean_transaction - @7929
6 flavor jelly_bean_types::flavor_e 3 APPLE
7 color jelly_bean_types::color_e 2 GREEN
8 sugar_free integral 1 'h0
9 sour integral 1 'h1
10 command jelly_bean_types::command_e 2 WRITE
11 taste jelly_bean_types::taste_e 2 NO_TASTE
12 ---------------------------------------------------------
13
14 UVM_INFO jb3.sv(727) @ 60: uvm_test_top.jb_env.jb_sb [jelly_bean_scoreboard] You have a good sense of taste.
15 ----------------------------------------------------------
16 Name Type Size Value
17 ----------------------------------------------------------
18 jb_tx jelly_bean_transaction - @7928
19 flavor jelly_bean_types::flavor_e 3 NO_FLAVOR
20 color jelly_bean_types::color_e 2 NO_COLOR
21 sugar_free integral 1 'h0
22 sour integral 1 'h0
23 command jelly_bean_types::command_e 2 READ
24 taste jelly_bean_types::taste_e 2 YUMMY
25 ----------------------------------------------------------
I hope this tutorial helped you to understand the UVM Register Abstraction.
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 UVM  uvm_reg, uvm_reg_adapter, uvm_reg_block, uvm_reg_field, uvm_reg_predictor, uvm_reg_sequence
UVM Tutorial for Candy Lovers – 8. Configurations UVM Tutorial for Candy Lovers – 10. Inside Candy
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UVM Tutorial for Candy Lovers – 9. Register Abstraction

Last Updated on June 7, 2015

1 module jelly_bean_taster( jelly_bean_if.slave_mp jb_slave_if );

1 class jelly_bean_recipe_reg extends uvm_reg;

The model of the TASTE register is similarly defined.

1 class jelly_bean_taste_reg extends uvm_reg;

1 class jelly_bean_reg_block extends uvm_reg_block;

The uvm_reg_adapter is a uvm_object, not a uvm_component.

1 class jelly_bean_reg_adapter extends uvm_reg_adapter;

typedef uvm_reg_predictor#( jelly_bean_transaction ) jelly_bean_reg_predictor;

1 class jelly_bean_agent extends uvm_agent;

1 class jelly_bean_env_config extends uvm_object;

1 class jelly_bean_env extends uvm_env;

1 class jelly_bean_base_test extends uvm_test;

Sequence without Register Abstraction

1 class jelly_bean_sequence extends uvm_sequence#( jelly_bean_transaction );

Sequence Using Register Abstraction

1 class jelly_bean_reg_sequence extends uvm_reg_sequence;

1 class jelly_bean_reg_test extends jelly_bean_base_test;

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