ICICTES 2013, Samutsongkhram, Thailand 24-26 January 2013
A Simplified Low-Rate Low-Cost PLC Device:
Simulation and Implementation Issues
Luis Carlos Mathias, Leonimer Flávio de Melo
Taufik Abrão, Felipe Andrade Allemand Borges
Department of Electrical Engineering
State University of Londrina
Londrina, Paraná, Brazil
Email: {luis.mathias, leonimer, taufik}@uel.br
fborges22@gmail.com
Abstract—In this contribution an complete design and imple-
mentation based on a single-chip device integration suitable for
narrowband grid power communication supported by the KNX
PL-132 physical layer standard are developed. The integration
allows a reduction in circuit dimensions and cost, and conse-
quently increasing the range of applications. The entire proposed
system is designed, simulated and implemented in hardware.
Furthermore, the standard X10 and KNX PL-132, witch are
extensively deployed in low-speed power line communication
(PLC) for home automation applications are briefly reviewed.
I. I NTRODUCTION
Power Line Communication (PLC) technology designed for
automation systems, has shown promise primarily due to the
capillarity of the electrical system and the increasing scarcity
of bandwidth for devices that operate on radio frequency
bands. The simple fact of not requiring additional cabling or
antennas contributes to a more economical solution compared
to other technologies. For discrete control applications, the
most widespread standard protocols are X10 and KNX PL-
132. Both operate in half-duplex and are in accordance with
the European norm CENELEC EN 50065-1, with signaling on
low-voltage electrical installations in the frequency range of
3.0kHz to 148.5kHz.
The X10 communication protocol is based on the timing
of bursts from 120kHz, with a duration of 1 ms, close to
the zero volts crossing. The bursts are repeated twice more
respecting to the lag of 120 degrees. Hence, those devices
connected to different phases of the electrical grid network
also are able to receive the signal [1]. A datagram X-10 has 13
bits and is composed of start code (4 bits), house code (4 bits),
command or code device (4 bits), and a bit flag that datagram
command or device. The one bit of the datagram is represented
by the presence of burst and zero for the absence. For the
house code and command code or device, then the next half
cycle is transmitted one bit symbol serving as complementary
error detection mechanism. So a datagram network takes 11
cycles to be transmitted. In order to ensure the transmission,
each set is transmitted twice, and the receiver X-10 now
operates to receive a command. The datagram of a typical full
command consists of two datagrams from the device code, a
196
João Maurício Rosário
Faculty of Mechanical Engineering
Department of Mechanical Design
State University of Campinas
Campinas, São Paulo
Email: rosario@fem.unicamp.br
space of three cycles of the power grid, and two command
datagrams. This results in a total of 47 cycles of power
grid, implying in a relative transmission delay. Furthermore,
in order to operate just simple functions, such "on/off" and
dimming of lights, there is a limited number of 16 codes and
residential addresses related to 16 code devices. However, the
main inconvenient consists in many of the devices are designed
to be only transmitters or receivers, not supporting command
recognition (ACK), i.e., the device that sent the command does
not receive a confirmation of receipt of another device, causing
eventually some communication failures. A full analog circuit
implementation of X10 protocol, as well as one version based
on microcontroller are reported in [2] and [3], respectively.
The EHS/KNX PL-132 protocol achieves the rate of 2400
bps and is specified in the KNX Handbook [4]. The physical
layer modulation uses binary frequency shift keying (BFSK),
with a center frequency of fc = (132.5 ± 0.25)kHz and
minimum frequency deviation of ∆fc = ±600Hz ± 1%.
This protocol supports ACK and besides the datagram being
protected by 16-bit Cyclic Redundancy Check (CRC), the
protocol supports a system of Forward Error Correction (FEC)
capable of correcting up to three bit errors for each block of
14 bits of the datagram. According to [4], this corresponds
to a protection against the noise bursts lasting up 1.25ms
every 5.84ms; as a result, the protocol becomes more robust
and reliable face to harmful and hostility of PLC channel.
An example of application of this protocol is discussed
in [5]. Devices operating under this protocol generally use
the chip ST7537 or ST7540, which performs power grid
transceiver function. The main manufacturer for this chip is
SGS-Thomson Microelectronics [6] [7]. This integrated circuit
requires a microcontroller, power source and various discrete
components, making the complete PLC circuit with large
dimensions, which can hinder some applications.
The KNX PL-132 presents the following advantages over
the X10: a) high data rate, b) higher immunity against im-
pulsive noise, c) greater assurance of integrity, and d) the ack
of information reception. Under this background, the present
work proposes to increase the integration level, deploying a
single chip microcontroller and other simple discrete com-
 ICICTES 2013, Samutsongkhram, Thailand 24-26 January 2013
AWGN
ponents in order to simplify the design an implementation,
PLC e(t) f(t) g(t) l(t)
by decreasing circuit dimensions and device costs as well. CHANNEL
Thus, several functions of modulation and demodulation at
the physical layer level are executed by the peripherals of the BAND PASS LOW PASS
AMPLIFIER
FILTER FILTER
microcontroller, while hold available processing resources of
the microcontroller for further application in the management
of a discrete device for home automation.

II. M ETHODOLOGY
Vref _

ANALOG
COMPARATOR
m(t)

TIMER
n(k)

CAPTURE ACCUMULATOR SUMMATION

} p(k)
Σ
CONST _

r(k)
+
DATA OUT
(PTA3)

Adopted modulation was adapted from [3]. In this pro-

Microcontroller
cess, the microcontroller generates a square wave with the
same frequency of the symbol rate to be transmitted. With Fig. 2. Block diagram of the receiver.
the intention of maintaining the continuous phase transitions
between symbols, the number of cycles representing a bit is
approximated by the value n = 132500 Hz presents the implemented prototype version for the low-speed
2400 bps = 55 cycles. This
signal must be filtered in order to attenuate the remaining low-cost PLC devices (transmitter and receiver boards).
harmonics, and then amplified to be coupled with the power a)
grid. The transmitter block diagram is depicted in Fig. 1, while
the transmitter hardware is described in subsection III-B.
Microcontroller

1 131900Hz

DATA LOGIC PWM a(t) b(t) c(t) d(t) PLC

IN LEVEL (50% duty-cycle) CHANNEL b)
0 BAND PASS
AMPLIFIER BAND PASS
FILTER
133100Hz FILTER
(COUPLING)

Fig. 1. Block diagram of the transmitter.

The non-coherent receiver scheme is shown in Fig. 2.

According this schematic, the first step of the demodulation
process consists in select and amplify the signal in the
frequency band of interest. Further details of this stage of
the receiver hardware are described in subsection III-C. Alter
low-pass filter, the signal is inserted into the microcontroller
through one inner analog comparator module configured as
R
reference voltage, also internal operation performed by the
microcontroller board. The analog comparator output m(t) is
connected to a counter module. Thus, the counter captures
the period between the signal rise ramp. Each capture of
count value is stored into a 8 bits last input first output
(LIFO) memory buffer of size 16. For each new capture,
it is performed a summation of the elements of this buffer
and compared to a threshold constant value. The value of
this constant is the period of capture of the center frequency
modulation multiplied by the buffer size. As a result, the
demodulated signal is the boolean result of the comparison.
Finally, the information bytes are recovered in a datagram
format by software. For this purpose, we decided to convert
the demodulated signal at the microcontroller’s output pin
PTA3 in order to externally connect its to the RX pin of the
R
serial communication module. Hence, this peripheral performs
decoding byte, generating an interrupt when complete, without
burden the microcontroller processing. As disadvantage, this
technique expend completely two microcontroller pins. Fig. 3
Fig. 3. Implemented prototype version for the low-speed low-cost PLC
devices: a) transmitter breadboard; b) receiver breadboard.
A. Simulation Environment
Simulations of the communication system were performed
using the MatLab
scripts, according to the diagrams of
Fig. 1 and 2. It was considered a bus speed BU SCLK =
16.777M Hz, which is the real frequency generated by PLL
clock generator, while the deployed crystal of the micro-
controller board has a nominal frequency of fcrystal =
32.768kHz.
The filters were modelled first in its frequency response
format, then the impulse response was obtained by inverse
fast Fourier transform (IFFT). Therefore, the signal xfilter (t)
passing through a filter is convolved with the impulse response
hfilter (t), resulting the input received signal [8]:
yfilter (t) = hfilter (t) ∗ xfilter (t) (1)
where ∗ is the convolution operator.
The fig. 4 displays the main graphical signal outputs for
the PLC transmitter generated from the MatLab
simulation
environment. It shows a predictable attenuation in the signal
d(t) caused by the low impedance of of the adopted power
grid channel model. Were admitted, the minimum impedance
of the power grid of approximately 4.7Ω measure statistical

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 ICICTES 2013, Samutsongkhram, Thailand 24-26 January 2013

form at work [9] and path loss of −7dB canal 110m from the
work [10].
0.1

e(t) .[V]
0
1 −0.1
a(t) .[V]

0 0 20 40 60 80 100 120 140 160 180 200

t .[ns]
−1
1.4
0 50 100 150 200
t .[ns]

l(t) .[V]
1 1.2
b(t) .[V]

0
1
0 20 40 60 80 100 120 140 160 180 200
−1
t .[ns]
0 50 100 150 200
t .[ns]
130
0.2 128
d(t) .[V]

n(k)
0
126
124
−0.2 122
0 50 100 150 200 0 20 40 60 80 100 120 140 160
t .[ns] k

Fig. 4. Simulated signals relating to a portion of one symbol. Square 2040

wave a(t), sine wave after the first filter b(t) and injected signal under low r(k) 2030
impedance of the power grid d(t). Const = 2026
2020

2010
In order to emulate the non-coherent BFSK PLC receiver, 0 50 100 150
an additive white Gaussian noise (AWGN) was added to k

the received signal e(t), resulting in a signal-to-noise ratio
SN R = 10dB. As a illustrative example of simulated re-
ceiving signals, in Fig. 5 demodulation steps for a binary
data vector [101] is performed. Signals shape changing can be
observed in the simulation signals at the receiver side, showing
Fig. 5. Simulated BFSK signals at the receiver side. e(t) represents the
received signal after addition of noise, l(t) is the signal after RLC filter and
amplification, while n(k) is the capture of periods at each cycle. r(k) is the
sum of the 16 elements of the capture buffer.
+5Vcc

the correct demodulation of information vector after compared CN201

C201
BDM
with reference level Const, which is determined by: 1
10nF

2 ACMP-
3 0 U201
16 ∗ BUSCLK 16 ∗ 16.777MHz 4 1 20
Const = = ≃ 2026 (2) 2 PTA5/IRQ/RESET
PTA4/BKGD
PTA0/TPM1CH0
PTA1/ACMP-
19
fc 132.500kHz 3
4 VDD PTA2/SDA
18
17
0 5 VSS PTA3/SCL 16
6 PTB7/EXTAL PTB0/RxD 15
It is evident that under SN R = 10dB the signal r(k) R201 10M
7 PTB6/XTAL
PTB5/TPM1CH1
PTB1/TxD
PTB2/ADP6
14
8 13
represents the recovered binary data vector [101] with no PTB4/TPM2CH1 PTB3/ADP7
32768Hz

X201 9 12
10 PTC3/ADP11 PTC0/ADP8 11
PTC2/ADP10 PTC1/ADP9
errors. C202 C203 MC9S08SH4
C204 C205
47pF 47pF EN_TX 10nF 10nF
SW201 SW202
III. H ARDWARE D ESIGN LIGA DESLIGA
0 0 PWM

A. Microcontroller and Peripherical Circuits 0 0

A low cost microcontroller with Von Neumman architecture
has been used. The Freescale Semiconductor MC9S08SH4CTJ
microcontroller has 8 bits, 4 Kbyte Flash memory, 256 Bytes
of RAM, maximum bus clock and CPU clock of 20 and
40MHz, respectively [11]. Furthermore, an analog comparator
module (ACMP), a serial communications interface (SCI)
module, and a timer module with function of the PWM
fixed duty cycle generation and capture of the period signal
in free running mode have been included as peripherals.
Diagram in Fig. 6 shows connections with the pinouts of the
microcontroller. The choose in adopting this microcontrollers
family, is also due to the fact that this microcontrollers family
is compatible with microcontroller MC9S08PA8 programming
language, allowing us to integrate the peripheral touch sensing
interface (TSI); as a consequence, rapid implementation of
capacitive touch buttons was enabled.
Fig. 6. Connection diagram for the microcontroller.
The adopted power source topology is depicted in Fig.
7. As one can see, the PLC DC power source has not
been completely isolated from the power grid. A capacitive
transformerless power supply type has been adopted [12]. The
reactance of the capacitor C101 limits the current supplied
to the source. In a positive half cycle occurs the loading of
capacitor C102 via diode D102. The voltage is limited by the
diode zener D101 which is reversely biased and operating in
its zener region. In the negative half cycle the diode zener
D101 restricts in voltage of the barrier diode and diode D102
is reversely biased; as a consequence, capacitor C102 holds
its charge. Voltage regulator U101 estabilizes the voltage
delivered to the PLC circuits. The fuse F101 has the function

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 ICICTES 2013, Samutsongkhram, Thailand 24-26 January 2013

of protecting against over current due to a failure in the with the diodes D1 and D2 [14]. Thus the effect of thermal
circuit, while in conjunction with the varistor RV101 provides collapse is mitigated, which could destroy the transistor due
transient protection. The R101 resistor limits the inrush current to excessive bias current generated by the difference in bias
when the device is connected to the power line network. voltages between base and emitter caused by differential heat-
According to [12], the maximum current IOUT = 29.7mA can ing of the junction of transistors and diodes. Hence, for design
be supplied by this power source, been determined by: purpose, this effect was taken into account by simulation only.
√ When the transmission signal is enable, the amplifier should
2VRMS − VZ
IOUT ≤ IIN = −1 (3) have a low impedance signal to the power grid channel. Note
2 (2πf C101 + R101) that while the PLC device is not transmitting, in the case the
where: IIN is the input current, VZ = 10V is the zener voltage of the amplifier remains active cause severe signal attenuation
of the diode D101, f = 60Hz and VRMS = 127V is the from a remote transmitter due to its lower impedance would
frequency and the effective voltage of the Brazilian power further reduce the power grid impedance. To solve this prob-
grid, respectively. lem, a binary signal EN_TX generated by the microcontroller
PHASE_PROT
places the amplifier in high impedance (HI) while there is
R102 1M
+5Vcc no transmission, through the circuit composed by Q1-Q2
U101
PHASE F1 100mA R101 10 C101 1uF D102
1
LM78L05
2
transistors and R2-R3 resistors.
GND

IN OUT
D1N4148
Finally, the amplified signal is coupled to the electric power
2

RV101 grid network by another filter composed by inductor L2

3

D101 C102 C103

S10K150V 1N4740
1N47 1mF 10uF
and capacitor C4. The zener diode D3 protects the amplifier
1

NEUTRAL
voltage surges, eventually generated by the power grid.
0 C. Receiver Hardware
According to Fig. 9, the first stage of the non-coherent
Fig. 7. Circuit diagram of the power supply.
BFSK receiver is composed by a three-stages band pass filter
in cascade coupled through capacitor C14 to an solid-state
B. Transmitter Hardware amplifier. Before the amplified received filtered signal reaching
Fig 8 shows the circuit diagram of the PLC transmitter. The the pin of the microcontroller’s comparator module, it passes
modulated signal is generated starting from a square wave through a low pass RC filter of the first order consists of
with the same frequency of the information symbol to be R11 resistor and C15 capacitor, with 3 dB cutoff frequency of
transmitted, which is generated by the microcontroller. When fc = 338.6 kHz.
passing through the bandpass filter consisting of L1, C1 and PHASE_PROT
R1, odd harmonic components are attenuated [13], resulting
L3
in a sinusoidal signal at the fundamental frequency, which is 1mH

coupled to the amplification stage through capacitors C2 and C5 220pF C8 220pF C11 220pF +5Vcc
C3.
C6 220pF C9 220pF C12 220pF
+5Vcc R10
10k
C7 1nF L4 1mH C10 1nF L5 1mH C13 1nF C14 10nF R11 10k
ACMP
EN_TX R2 47
Q1
2N3904
R6 R7 R8 R9 C15
47 47 47 10k 47pF

Q8
R4 2N3904 0
470
0 0 0
C2 10nF
Q3
2N3904 0

D1
D1N4148 L2 15uH PHASE_PROT Fig. 9. Circuit diagram for the first stage of the non-coherent BFSK receiver.
2

D2 C4 100nF
PWM L1 1mH C1 1.5nF C3 10nF D1N4148
Q4
D3
1N4737
The cascade RLC filter has the function of attenuate the
2N3906
outband spectral components of other signals present in the
1

R1 R5
47 470 electrical network, including the 60Hz grid frequency. The
0
0
RLC filter selects the band of interest composed by two
EN_TX
Q2
2N3904
different frequencies associated to the bit information 0,
R3 470
fbit0 = 133.1kHz, while the bit information 1 is represented
0 by fbit1 = 131.9 kHz. The filter is dimensioned [13] for
a resonant frequency of f0 = fbit0 +f 2
bit1
= 132.5kHz,
Fig. 8. Circuit diagram for the PLC transmitter stage. bandwidth of 3dB equals to BW ≈ 3.8kHz and a gain at
the f = 60Hz of |H(60Hz)| ≤ −275.6 dB.
The output amplifier is an class AB with crossover distortion The input amplifier composed bythe NPN junction transistor
compensation for polarization of the transistors Q3 and Q4 Q8 is biased in a negative feedback mode through resistor R9

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 ICICTES 2013, Samutsongkhram, Thailand 24-26 January 2013
between base and collector. This type of polarisation ensures
higher gain stability compared to the base constant-current
polarisation mode[15].
Next demodulation stage is performed by the microntroller.
Since the module ACMP of the microcontroller performs
the comparison with a fixed internal reference threshold of
Vref_int ≃ 1.2V , a possible saturation of the amplifier signal
does not interfere with the signal capture and decision. This is
due to the fact that the counting period between interruptions
is generated by the ramp rise and compared with the signal
reference voltage which is programmable via microcontroller
ACMP module. In doing so, allow us to eliminate the need for
a more complex circuit topology with automatic gain control
(AGC).
IV. M EASUREMENT S ETUP AND R ESULTS
Two PLC devices were mounted and connected to the
same phase of the grid network, and separated 3 meters far
from each other by wall socket. The transmitter and receive
signals were captured by an four channel oscilloscope with
BW = 100M Hz bandwidth. The main signals at the receiver
side regarding the demodulation of the transmitted stream
information 0X01 are depicted in Fig. 10. The channel consists
R Home Automation Using the PIC16F877A, Mi-
of distinct and insulated conductors with copper section of
2.5mm2 . The conductors are protected by conduit of the
polyvinyl chloride (PVC), the same insulating material of the
conductors.
Fig. 10. Time domain signals Bursts for the proposed low-cost PLC system:
CH 1 – square wave a(t). CH 2 – sinusoidal signal after AB-class amplifier at
transmitter side, c(t). CH 3 – signal after amplifier and RC filter at the receiver
side; CH 4: demodulated data, l(t).
V. C ONCLUSION
In this contribution, it was demonstrated by both simulation
and implementation the design, simulation and implementation
of a low-cost, low-speed power line devices based on the
physical layer protocol KNX-PL132 specifications. The micro-
controller deployed in this cost-effective PLC project presents
an average cost five times less than the ST7540 chip modem,
200
while the latter still needs a microcontroller to perform a PLC
system. Combining this low-cost feature with reduced size of
the circuit because of decreased component number, enable us
to adopt the proposed solution for an increase range of low-
rate communication applications. The implementation of the
protocol data layer, as well as encryption capability are remain
as a suggestion for future work.
ACKNOWLEDGMENTS
Part of this work was supported by the Coordination of
Improvement of Higher Education Personnel (CAPES), for
resources Support Program Graduate (PROAP), the National
Council for Scientific and Technological Development (Con-
tract 202340/2011-2 and 303426/2009-8) and in part by
funds from the State University of Londrina (FAEPE / UEL
02/2011), Government of the State of Paraná.
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