FAMILIARIZATION WITH DSP KIT

The Code Composer Studio IDE is a development environment that tightly integrates
the tools needed to create winning DSP applications. It is designed for the Texas Instruments
(TI) high performance TMS320C6000 (C6000) and digital signal processor (DSP) platforms.
The Key components of the Code Composer Studio IDE include:
o Tuning tools for optimizing applications
o C/C++ Compiler, Assembly Optimizer and Linker (Code Generation Tools)
o Real-Time Operating System (DSP/BIOS)
o Ability to dynamically connect and disconnect from targets
o Real-Time Data Exchange between host and target (RTDX)
o Update Advisor
o Instruction Set Simulator
o Advanced Event Triggering
o Data Visualization
The Code Composer Studio IDE Version 3.0 (Tuning Edition) integrates all host and
target tools in a unified environment. It also simplifies DSP system configuration and
application design to help designers get started faster than ever before.
The Code Composer Studio IDE, an integral component of TI.s software strategy,
includes the features necessary to take you through each step of the application development
flow. All of these features are provided in an integrated product allowing developers to focus
their energy on innovation.
Code Composer Studio Setup is a utility that is used to define the target board or
simulator the user will use with the Code Composer Studio IDE. This information is called the
system configuration and consists of a device driver that handles communication with the
target plus other information and files that describe the characteristics of your target, such
as the default memory map. The Code Composer Studio IDE needs this information to
establish communication with your target system and to determine which tools are
applicable for the given target.

As DSP applications become more complex, it is important to structure them in an

efficient, maintainable manner. This requires use of a real-time kernel that enables system
functions to be allocated to different threads. The DSP/BIOS kernel provides an efficient set
of kernel, real-time analysis, and peripheral configuration services, eliminating the need to
develop and maintain custom DSP operating systems. DSP/BIOS is an integral part of the
Code Composer Studio IDE. The kernel object browser displays the state of operating system
objects (such as tasks and semaphores), and provides data on stack usage and stack
overflow/underflow. These capabilities make it easier to debug applications and optimize
usage of OS and system resources. DSP/BIOS consists of four parts: a real-time kernel, real-
time analysis services, peripheral configuration libraries, and a graphical configuration tool.
For each supported processor, DSP/BIOS includes a set of peripheral management functions
and macros known as the Chip Support Library (CSL). The CSL supports on-chip peripherals
for all TMS320C5000 and TMS320C6000 devices and is fully integrated into the DSP/BIOS
Configuration tool. The CSL supports both graphical and programmatic peripheral
configuration and control, eliminating the need to remember individual register flags
settings or painstakingly calculate bitmaps.
Code Composer Studio IDE’s open plug-in architecture (called “TMS320 DSP
Algorithm Standard” or “XDAIS”) reduces time-consuming system integration for anyone
trying to include algorithms into their DSP system. XDAIS defines common programming
rules and guidelines with a set of programming interfaces that are used consistently by
algorithms across a wide variety of applications.
Source Code Editor
The Code Composer Studio IDE includes fully integrated code editing environment
tuned for writing C, C++ and DSP assembly code. The editor provides standard editing
features such as: keyword highlighting, printing, cut and paste, drag and drop, etc. The
maximum number of lines per file is 2,147,483,648 and the maximum number of characters
per line is 3500.

The Code Composer Studio compile tools shifts the burden of optimization from hand-coded
assembly to the C Compiler. With these tools it is possible to exploit the high performance of
TI’s DSP platforms without ever writing hand-coded assembly.
Debugger
The Code Composer Studio debugger makes it easy to find and fix errors in real−time
embedded applications. For example, debugger commands enable you to control program
execution. Debugger windows and dialogs allow you to view source code and track the
values of program variables in memory and registers. Breakpoints enable you to stop
execution at a specified location and examine the current state of the program.
Real-Time Data Exchange (RTDX)
RTDX allows designers to monitor continuously their systems and gain real−time
insights into running applications. It also allows data to be streamed with ActiveX−compliant
application such as Excel, LabVIEW or MATLAB. When displaying RTDX data, host
applications can read either live or saved data. The IDE also supports RTDX with multiple
processors on either the same or different scan paths.
Application Code Tuning
The Code Composer Studio IDE now offers a series of tools (called Tuning Tools) to
help developers to optimize applications. These tools allow users to set goals and track
progress towards goals by collecting different sets of data. A new Advice Window provides
on-the-fly recommendations about how to make code meet user goals.
The IDE has two Layouts, (tuning layout and standard layout), which can be toggled
from the main toolbar. Standard layout is the default, while tuning layout (represented by a
tuning fork icon on the toolbar) opens advice windows on the left side. The tuning layout
focuses attention on the optimization needs of the user’s program. The advice window walks
the user through the optimization/tuning process specific to the DSP device and a selected
goal.
Data Visualization
Code Composer Studio IDE incorporates an advanced signal analysis interface that
enables developers to monitor signal data critically and thoroughly. The new features are
useful in developing applications for communications, wireless, and image processing, as
well as general DSP applications. Time/frequency, Constellation plot, Eye diagram, Image
display etc are the various graphs that can be drawn.

Real-Time Analysis
Real-time analysis tools help developers to see time-related interactions between
code sections. They can reveal subtle real-time problems that otherwise might go
undetected. Code Composer Studio IDE allows developers to probe, trace and monitor a DSP
application while it runs. Even after the program has halted, information already captured
through real-time analysis tools can provide invaluable insight into the sequence of events
that led up to the current point of execution.
General Extension Language (GEL)
The General Extension Language (GEL) is an interpretive language similar to C that
lets you create functions to extend Code Composer Studio IDE’s usefulness. After creating
GEL functions using the GEL grammar, you can load them into Code Composer Studio IDE.
With GEL, you can access actual/simulated target memory locations and add options to the
IDE’s GEL menu. GEL is particularly useful for automated testing.
Conclusion
Code Composer Studio IDE v3.0 represents the evolution of the DSP development
environment. It contains functionality needed by today’s larger, distributed, global project
teams. By reducing time spent on repetitive tasks and tool development, the IDE gives the
developer more time to focus on innovation.
 SOFTWARE DEVELOPMENT FLOW IN TMS PROCESSORS

Tools Descriptions
The following list describes the tools that are shown in Figure 1-1:
 The C/C++ compiler translates C/C++ source code into assembly language source
code. The compiler package includes the library-buildutility, with which you can
build your own runtime libraries.
 The assembler translates assembly language source files into machine language
COFF object files. Source files can contain instructions, assembler directives, and
macro directives. You can use assembler directives to control various aspects of the
assembly process, such as the source listing format, data alignment, and section
content. The assembler translates assembly language source files into machine
language COFF object files. The TMS320C54x, 55x tools include two assemblers. The
mnemonic assembler accepts mnemonic assembly source files. The algebraic
assembler accepts algebraic assembly source files. Source files can contain
instructions, assembler directives, and macro directives. You can use assembler
directives to control various aspects of the assembly process, such as the source
listing format, data alignment, and section content.
  The linker combines relocatable COFF object files (created by the assembler) into a
single executable COFF object module. As it creates the executable module, it binds
symbols to memory locations and resolves all references to those symbols. It also
accepts archiver library members and output modules created by a previous linker
run. Linker directives allow you to combine object file sections, bind sections or
symbols to addresses or within memory ranges, and define or redefine global
symbols.
 The archiver collects a group of files into a single archive file. For example, you can
collect several macros into a macro library. The assembler searches the library and
uses the members that are called as macros by the source file. You can also use the
archiver to collect a group of object files into an object library. The linker includes in
the library the members that resolve external references during the link.
 The mnemonic-to-algebraic assembly translator utility converts an assembly
language source file containing mnemonic instructions to an assembly language
source file containing algebraic instructions.
 The library-build utility builds your own customized C/C++ runtime-support
library. Standard runtime-support library functions are provided as source code in
rts.src and as object code in rts.lib.
 The TMS320C54x,55x Code Composer Studio debugger accepts COFF files as input,
but most EPROM programmers do not.
 The hex conversion utility converts a COFF object file into TI-tagged, Intel, Motorola,
or Tektronix object format. The converted file can be downloaded to an EPROM
programmer.
 The absolute lister accepts linked object files as input and creates .abs files as output.
You assemble .abs files to produce a listing that contains absolute rather than relative
addresses. Without the absolute lister, producing such a listing would be tedious and
require many manual operations.
 The cross-reference lister uses object files to produce a cross-reference listing
showing symbols, their definitions, and their references in the linked source files.
 The COFF disassembler(only in c55x) accepts object files and executable files as
input and produces an assembly listing as output. This listing shows assembly
instructions, their opcodes, and the section program counter values. The disassembly
listing is useful for viewing the:
Assembly instructions and their size
Encoding of assembly instructions
Output of a linked executable file
 The object file display utility prints the contents of object files, executable files,
and/or archive libraries in both human readable and XML formats.
 The name utility (only in c55x) prints a list of names defined and referenced in a
COFF object or an executable file.
 The strip utility removes symbol table and debugging information from object and
executable files.
The purpose of this development process is to produce a module that can be executed in a
C54x target system. You can use one of several debugging tools to refine and correct your
code. Available products include:
  An instruction-accurate software simulator
 An evaluation module (EVM)
 An XDS emulator
These debugging tools are accessed within Code Composer Studio.

TMS 320 DSP PROCESSORS

TMS320DSP family consists of fixed-point, floating-point, and multiprocessor digital
signal processors (DSPs). The TMS320 DSP architecture is designed specifically for real-time
signal processing. The following characteristics make this family the ideal choice for a wide
range of processing applications:
- Very flexible instruction set
- Inherent operational flexibility
- High-speed performance
- Innovative parallel architecture
- Cost-effectiveness
- C-friendly architecture
Today, the TMS320 DSP family consists of three supported DSP platforms:
TMS320C2000, TMS320C5000, and TMS320C6000. Within the C5000, DSP platform there
are three generations, the TMS320C5x, TMS320C54x, and TMS320C55x.
The C54x DSP has a high degree of operational flexibility and speed. It combines an
advanced modified Harvard architecture (with one program memory bus, three data
memory buses, and four address buses), a CPU with application-specific hardware logic, on-
chip memory, on-chip peripherals, and a highly specialized instruction set. Spinoff devices
that combine the C54x CPU with customized on-chip memory and peripheral configurations
have been, and continue to be, developed for specialized areas of the electronics market.
The C54x devices offer these advantages:
 Enhanced Harvard architecture built around one program bus, three data buses, and
four address buses for increased performance and versatility
 Advanced CPU design with a high degree of parallelism and application specific
hardware logic for increased performance
 A highly specialized instruction set for faster algorithms and for optimized high-level
language operation
 Modular architecture design for fast development of spinoff devices
 Advanced IC processing technology for increased performance and low power
consumption
 Low power consumption and increased radiation hardness because of new static
design techniques
1.3 TMS320C54x DSP Key Features
This section lists the key features of the C54x DSPs.
CPU
 Advanced multi-bus architecture with one program bus, three databuses, and four
address buses
 40-bit arithmetic logic unit (ALU), including a 40-bit barrel shifter and two
independent 40-bit accumulators
  17-bit x 17-bit parallel multiplier coupled to a 40-bit dedicated adder for
nonpipelined single-cycle multiply/accumulate (MAC) operation
 Compare, select, store unit (CSSU) for the add/compare selection of the Viterbi
operator
 Exponent encoder to compute the exponent of a 40-bit accumulator value in a single
cycle
 Two address generators, including eight auxiliary registers and two auxiliary register
arithmetic units
 Multiple-CPU/core architecture on some devices
Memory
 192K words x 16-bit addressable memory space (64K-words program, 64K-words
data, and 64K-words I/O), with extended program memory in the C548, C549, C5402,
C5410, and C5420.
Instruction set
 Single-instruction repeat and block repeat operations
 Block memory move instructions for better program and data management
 Instructions with a 32-bit long operand
 Instructions with 2- or 3-operand simultaneous reads
 Arithmetic instructions with parallel store and parallel load
 Conditional-store instructions
 Fast return from interrupt
 On-chip peripherals
 Software-programmable wait-state generator
 Programmable bank-switching logic
 On-chip phase-locked loop (PLL) clock generator with internal oscillator or external
clock source. With the external clock source, there are several multiplier values
available from one of the device
Speed: 25/20/15/12.5/10-ns execution time for a single-cycle, fixed-pointb instruction (40
MIPS/50 MIPS/66 MIPS/80 MIPS/100 MIPS):
Power
 Power consumption control with IDLE 1, IDLE 2, and IDLE 3 instructions for power-
down modes
 Control to disable the CLKOUT signal
Emulation: IEEE Standard 1149.1 boundary scan logic interfaced to on-chip scan-based
emulation logic
Introduction to the TMS320C55x
The TMS320C55x digital signal processor (DSP) represents the latest generation of
’C5000 DSPs from Texas Instruments. The ’C55x is built on the proven legacy of the ’C54x
and is source code compatible with the ’C54x, protecting the customer’s software
investment. Following the trends set by the’C54x, the ’C55x is optimized for power efficiency,
low system cost, and best-in-class performance for tight power budgets. The TMS320C55x is
a low-power, general-purpose signal processing architecture with an instruction set
optimized for efficiency, ease of use, and compactness. Although the ’C55x instruction set is
much more powerful and flexible than that of previous generations, the architecture is
completely compatible with TMS320C54x instructions. This allows programs developed on
the ’C54x to be re-assembled and executed on the ’C55x with bit-exact results. A highly
parallel architecture complements the ’C55x instruction set and enables increased code
density while reducing the number of cycles required per operation. The union of an
efficient, compact instruction set with a highly parallel architecture provides a high-
performance signal processing engine while minimizing code size and power consumption.
The key features of TMS320C55x are
 A 32 x 16-bit Instruction buffer queue
 Two 17-bit x17-bit MAC units
 One 40-bit ALU
 One 40-bit Barrel Shifter
 One 16-bit ALU
 Four 40-bit accumulators
 Twelve independent buses:
– Three data read buses
– Two data write buses
– Five data address buses
– One program read bus
– One program address bus
 User-configurable IDLE Domains
The TMS320C6000 digital signal processor (DSP) platform is part of the TMS320 DSP
family. The TMS320C62xx DSP generation and the TMS320C64x DSP generation comprise
fixed-point devices in the C6000 DSP platform, and the TMS320C67x DSP generation
comprises floating point devices in the C6000 DSP platform. The TMS320C62x and
TMS320C64x DSPs are code-compatible. The TMS320C62x and TMS320C67x DSPs are
code-compatible. All three use the VelociTI architecture, a high-performance, advanced
VLIW (very long instruction word) architecture, making these DSPs excellent choices for
multichannel and multifunction applications.
1-5 Introduction
The C6000 devices execute up to eight 32-bit instructions per cycle. The C62x/C67x
device’s core CPU consists of 32 general-purpose registers of 32-bit word length and eight
functional units. The C64x core CPU consists of 64 general-purpose 32-bit registers and eight
functional units. These eight functional units contain:
 Two multipliers
 Six ALUs
The C6000 generation has a complete set of optimized development tools, including
an efficient C compiler, an assembly optimizer for simplified assembly language
programming and scheduling, and a Windows based debugger interface for visibility into
source code execution characteristics. A hardware emulation board, compatible with the TI
XDS510 emulator interface, is also available. This tool complies with IEEE Standard
1149.1–1990, IEEE Standard Test Access Port and Boundary-Scan Architecture.
Features of the C6000 devices include:
 Advanced VLIW CPU with eight functional units, including two multipliers and six
arithmetic units
 Executes up to eight instructions per cycle for up to ten times the performance of
typical DSPs
  Allows designers to develop highly effective RISC-like code for fast development time
 Instruction packing
 Gives code size equivalence for eight instructions executed serially or in parallel
 Reduces code size, program fetches, and power consumption
 Conditional execution of all instructions
 Reduces costly branching
 Increases parallelism for higher sustained performance
 Efficient code execution on independent functional units
 Industry’s most efficient C compiler on DSP benchmark suite
 Industry’s first assembly optimizer for fast development and improved parallelization
 8/16/32-bit data support, providing efficient memory support for a variety of
applications
 40-bit arithmetic options add extra precision for vocoders and other computationally
intensive applications
Features and Options of the TMS320C62x/C64x/C67x

TMS3206713 CPU and Peripheral Connectivity

 Block diagram of TMS320C6713 DSK

Simplified block diagram of TMS320C67xx family

  Saturation and normalization provide support for key arithmetic operations
 Field manipulation and instruction extract, set, clear, and bit counting support
common operation found in control and data manipulation applications.
The C67x has these additional features:
 Hardware support for single-precision (32-bit) and double-precision (64-bit) IEEE
floating-point operations
 32 x 32-bit integer multiply with 32- or 64-bit result.
The C64x additional features include:
 Each multiplier can perform two 16 x 16-bit or four 8 x 8 bit multiplies every clock
cycle.
 Quad 8-bit and dual 16-bit instruction set extensions with data flow support
 Support for non-aligned 32-bit (word) and 64-bit (double word) memory accesses
 Special communication-specific instructions have been added to address common
operations in error-correcting codes.
 Bit count and rotate hardware extends support for bit-level algorithms.

Result: