NTD20N06L, NTDV20N06L

Power MOSFET
20 A, 60 V, Logic Level, N−Channel
DPAK/IPAK
Designed for low voltage, high speed switching applications in
power supplies, converters and power motor controls and bridge www.onsemi.com
circuits.
V(BR)DSS RDS(on) TYP ID MAX
Features 20 A
• AEC Q101 Qualified − NTDV20N06L 60 V 39 mW@5.0 V
(Note 1)
• These Devices are Pb−Free and are RoHS Compliant
D
Typical Applications
• Power Supplies
• Converters
G
N−Channel

• Power Motor Controls

• Bridge Circuits S

MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) 4

Rating Symbol Value Unit

4
Drain−to−Source Voltage VDSS 60 Vdc
Drain−to−Gate Voltage (RGS = 10 MW) VDGR 60 Vdc 1
1 2 2
Gate−to−Source Voltage Vdc 3 3
− Continuous VGS ±15 DPAK IPAK
− Non−repetitive (tpv10 ms) VGS ±20 CASE 369C CASE 369D
Drain Current STYLE 2 STYLE 2
− Continuous @ TA = 25°C ID 20 Adc
− Continuous @ TA = 100°C ID 10 MARKING DIAGRAMS
− Single Pulse (tpv10 ms) IDM 60 Apk & PIN ASSIGNMENTS
Total Power Dissipation @ TA = 25°C PD 60 W 4 4
Derate above 25°C 0.40 W/°C Drain Drain
Total Power Dissipation @ TA = 25°C (Note 1) 1.88 W
Total Power Dissipation @ TA = 25°C (Note 2) 1.36 W
AYWW
AYWW

N6LG
N6LG

20

°C
20

Operating and Storage Temperature Range TJ, Tstg −55 to

+175
Single Pulse Drain−to−Source Avalanche EAS 128 mJ
2
Energy − Starting TJ = 25°C 1 3
(VDD = 25 Vdc, VGS = 5.0 Vdc, Drain
Gate Source
L = 1.0 mH, IL(pk) = 16 A, VDS = 60 Vdc) 1 2 3
Gate Drain Source
Thermal Resistance °C/W
− Junction−to−Case RqJC 2.5 A = Assembly Location*
− Junction−to−Ambient (Note 1) RqJA 80 Y = Year
− Junction−to−Ambient (Note 2) RqJA 110 WW = Work Week
20N6L = Device Code
Maximum Lead Temperature for Soldering TL 260 °C G = Pb−Free Package
Purposes, 1/8 in from case for 10 seconds
Stresses exceeding those listed in the Maximum Ratings table may damage the * The Assembly Location code (A) is front side
device. If any of these limits are exceeded, device functionality should not be optional. In cases where the Assembly Location is
assumed, damage may occur and reliability may be affected. stamped in the package, the front side assembly
1. When surface mounted to an FR4 board using 1 in pad size, (Cu Area 1.127 in2). code may be blank.
2. When surface mounted to an FR4 board using recommended pad size,
(Cu Area 0.412 in2).
ORDERING INFORMATION
See detailed ordering and shipping information on page 2 of
this data sheet.

© Semiconductor Components Industries, LLC, 2014 1 Publication Order Number:

August, 2017 − Rev. 5 NTD20N06L/D
 NTD20N06L, NTDV20N06L

ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)

Characteristic Symbol Min Typ Max Unit
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage (Note 3) V(BR)DSS Vdc
(VGS = 0 Vdc, ID = 250 mAdc) 60 71.3 −
Temperature Coefficient (Positive) − 71.2 − mV/°C
Zero Gate Voltage Drain Current IDSS mAdc
(VDS = 60 Vdc, VGS = 0 Vdc) − − 1.0
(VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150°C) − − 10
Gate−Body Leakage Current (VGS = ± 15 Vdc, VDS = 0 Vdc) IGSS − − ±100 nAdc
ON CHARACTERISTICS (Note 3)
Gate Threshold Voltage (Note 3) VGS(th) Vdc
(VDS = VGS, ID = 250 mAdc) 1.0 1.6 2.0
Threshold Temperature Coefficient (Negative) − 4.6 − mV/°C
Static Drain−to−Source On−Resistance (Note 3) RDS(on) mW
(VGS = 5.0 Vdc, ID = 10 Adc) − 39 48
Static Drain−to−Source On−Resistance (Note 3) VDS(on) Vdc
(VGS = 5.0 Vdc, ID = 20 Adc) − 0.81 1.66
(VGS = 5.0 Vdc, ID = 10 Adc, TJ = 150°C) − 0.72 −
Forward Transconductance (Note 3) (VDS = 4.0 Vdc, ID = 10 Adc) gFS − 17.5 − mhos
DYNAMIC CHARACTERISTICS
Input Capacitance Ciss − 707 990 pF
(VDS = 25 Vdc, VGS = 0 Vdc,
Output Capacitance Coss − 224 320
f = 1.0 MHz)
Transfer Capacitance Crss − 72 105
SWITCHING CHARACTERISTICS (Note 4)
Turn−On Delay Time td(on) − 9.6 20 ns
Rise Time (VDD = 30 Vdc, ID = 20 Adc, tr − 98 200
VGS = 5.0 Vdc,
Turn−Off Delay Time RG = 9.1 W) (Note 3) td(off) − 25 50
Fall Time tf − 62 120
Gate Charge QT − 16.6 32 nC
(VDS = 48 Vdc, ID = 20 Adc,
Q1 − 5.5 −
VGS = 5.0 Vdc) (Note 3)
Q2 − 8.5 −
SOURCE−DRAIN DIODE CHARACTERISTICS
Forward On−Voltage (IS = 20 Adc, VGS = 0 Vdc) (Note 3) VSD − 0.97 1.2 Vdc
(IS = 20 Adc, VGS = 0 Vdc, TJ = 150°C) − 0.85 −
Reverse Recovery Time trr − 42 − ns
(IS = 20 Adc, VGS = 0 Vdc,
ta − 30 −
dIS/dt = 100 A/ms) (Note 3)
tb − 12 −
Reverse Recovery Stored Charge QRR − 0.066 − mC
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
3. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%.
4. Switching characteristics are independent of operating junction temperatures.

ORDERING INFORMATION
Device Package Shipping†
NTD20N06LG DPAK 75 Units / Rail
(Pb−Free)
NTD20N06L−1G IPAK (Straight Lead) 75 Units / Rail
(Pb−Free)
NTD20N06LT4G DPAK 2500 / Tape & Reel
(Pb−Free)
NTDV20N06LT4G DPAK 2500 / Tape & Reel
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.

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2
 NTD20N06L, NTDV20N06L

40 40
VGS = 10 V VDS ≥ 10 V
ID, DRAIN CURRENT (AMPS)

ID, DRAIN CURRENT (AMPS)

8V 4.5 V
30 5V 30
6V
4V
20 20

3.5 V TJ = 25°C
10 10
TJ = 100°C
3V TJ = −55°C
0 0
0 1 2 3 4 5 1.6 2.4 3.2 4 4.8 5.6
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)

Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics

RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)

RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)

0.085 0.085
VGS = 5 V
VGS = 10 V
0.075 0.075
TJ = 100°C
0.065 0.065

0.055 0.055 TJ = 100°C

TJ = 25°C 0.045
0.045

0.035 0.035 TJ = 25°C

TJ = −55°C
0.025 0.025 TJ = −55°C

0.015 0.015
0 10 20 30 40 0 10 20 30 40
ID, DRAIN CURRENT (AMPS) ID, DRAIN CURRENT (AMPS)
Figure 3. On−Resistance versus Figure 4. On−Resistance versus Drain Current
Gate−to−Source Voltage and Gate Voltage
RDS(on), DRAIN−TO−SOURCE RESISTANCE

2 10000
ID = 10 A VGS = 0 V
1.8 VGS = 5 V
TJ = 150°C
IDSS, LEAKAGE (nA)

1.6
1000
(NORMALIZED)

1.4

1.2
100
1

TJ = 100°C
0.8

0.6 10
−50 −25 0 25 50 75 100 125 150 175 0 10 20 30 40 50 60
TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

Figure 5. On−Resistance Variation with Figure 6. Drain−to−Source Leakage Current

Temperature versus Voltage

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3

Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (Dt)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The published capacitance data is difficult to use for
calculating rise and fall because drain−gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (IG(AV)) can be made from a
rudimentary analysis of the drive circuit so that
t = Q/IG(AV)
During the rise and fall time interval when switching a
resistive load, VGS remains virtually constant at a level
known as the plateau voltage, VSGP. Therefore, rise and fall
times may be approximated by the following:
tr = Q2 x RG/(VGG − VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turn−on and turn−off delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG − VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
2400
VDS = 0 V
2000
C, CAPACITANCE (pF)
Ciss
1600
1200
Crss
800
400
0
10
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
NTD20N06L, NTDV20N06L
POWER MOSFET SWITCHING
The capacitance (Ciss) is read from the capacitance curve at
a voltage corresponding to the off−state condition when
calculating td(on) and is read at a voltage corresponding to the
on−state when calculating td(off).
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load. Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.
VGS = 0 V
TJ = 25°C
Ciss
Coss
Crss
5 0 5 10 15 20 25
VGS VDS
Figure 7. Capacitance Variation
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 NTD20N06L, NTDV20N06L

6 1000
VGS , GATE−TO−SOURCE VOLTAGE (VOLTS) VDS = 30 V
QT ID = 20 A
5
VGS = 5 V

4 Q2 VGS 100 tr
Q1

t, TIME (ns)
tf
3
td(off)
2 10 td(on)

1 ID = 20 A
TJ = 25°C
0 1
0 4 8 12 16 20 1 10 100
QG, TOTAL GATE CHARGE (nC) RG, GATE RESISTANCE (OHMS)

Figure 8. Gate−To−Source and Drain−To−Source Figure 9. Resistive Switching Time

Voltage versus Total Charge Variation versus Gate Resistance

DRAIN−TO−SOURCE DIODE CHARACTERISTICS

20
VGS = 0 V
IS, SOURCE CURRENT (AMPS)

TJ = 25°C
16

12

0
0.6 0.68 0.76 0.84 0.92 1
VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA

The Forward Biased Safe Operating Area curves define reliable operation, the stored energy from circuit inductance
the maximum simultaneous drain−to−source voltage and dissipated in the transistor while in avalanche must be less
drain current that a transistor can handle safely when it is than the rated limit and adjusted for operating conditions
forward biased. Curves are based upon maximum peak differing from those specified. Although industry practice is
junction temperature and a case temperature (TC) of 25°C. to rate in terms of energy, avalanche energy capability is not
Peak repetitive pulsed power limits are determined by using a constant. The energy rating decreases non−linearly with an
the thermal response data in conjunction with the procedures increase of peak current in avalanche and peak junction
discussed in AN569, “Transient Thermal Resistance − temperature.
General Data and Its Use.” Although many E−FETs can withstand the stress of
Switching between the off−state and the on−state may drain−to−source avalanche at currents up to rated pulsed
traverse any load line provided neither rated peak current current (IDM), the energy rating is specified at rated
(IDM) nor rated voltage (VDSS) is exceeded and the continuous current (ID), in accordance with industry custom.
transition time (tr,tf) do not exceed 10 ms. In addition the total The energy rating must be derated for temperature as shown
power averaged over a complete switching cycle must not in the accompanying graph (Figure 12). Maximum energy at
exceed (TJ(MAX) − TC)/(RqJC). currents below rated continuous ID can safely be assumed to
A Power MOSFET designated E−FET can be safely used equal the values indicated.
in switching circuits with unclamped inductive loads. For

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 NTD20N06L, NTDV20N06L

SAFE OPERATING AREA

100

EAS , SINGLE PULSE DRAIN−TO−SOURCE

140
VGS = 15 V ID = 16 A
I D, DRAIN CURRENT (AMPS)

SINGLE PULSE 10 ms 120

TC = 25°C

AVALANCHE ENERGY (mJ)

100
10
100 ms
80
1 ms
60
10 ms
1 dc
40
RDS(on) LIMIT
THERMAL LIMIT 20
PACKAGE LIMIT
0.1 0
0.1 1 10 100 25 50 75 100 125 150 175
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) TJ, STARTING JUNCTION TEMPERATURE (°C)

Figure 11. Maximum Rated Forward Biased Figure 12. Maximum Avalanche Energy versus
Safe Operating Area Starting Junction Temperature

10

50% Duty Cycle

1
R(t) (°C/W)

20%
10%
5%
0.1 2%
1%

Single Pulse

0.01
0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000
PULSE TIME (sec)

Figure 13. Thermal Response

di/dt
IS
trr
ta tb
TIME

tp 0.25 IS

IS

Figure 14. Diode Reverse Recovery Waveform

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 NTD20N06L, NTDV20N06L

PACKAGE DIMENSIONS

DPAK (SINGLE GAUGE)

CASE 369C
ISSUE F
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
A Y14.5M, 1994.
E C 2. CONTROLLING DIMENSION: INCHES.
A 3. THERMAL PAD CONTOUR OPTIONAL WITHIN DI-
b3 MENSIONS b3, L3 and Z.
B c2 4. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR BURRS. MOLD
FLASH, PROTRUSIONS, OR GATE BURRS SHALL
4 NOT EXCEED 0.006 INCHES PER SIDE.
L3 Z 5. DIMENSIONS D AND E ARE DETERMINED AT THE
D OUTERMOST EXTREMES OF THE PLASTIC BODY.
DETAIL A H 6. DATUMS A AND B ARE DETERMINED AT DATUM
1 2 3 PLANE H.
7. OPTIONAL MOLD FEATURE.

L4 INCHES MILLIMETERS
NOTE 7
DIM MIN MAX MIN MAX
b2 c BOTTOM VIEW A 0.086 0.094 2.18 2.38
e SIDE VIEW A1 0.000 0.005 0.00 0.13
b b 0.025 0.035 0.63 0.89
0.005 (0.13) M C b2 0.028 0.045 0.72 1.14
TOP VIEW b3 0.180 0.215 4.57 5.46
c 0.018 0.024 0.46 0.61
c2 0.018 0.024 0.46 0.61
H Z Z D 0.235 0.245 5.97 6.22
E 0.250 0.265 6.35 6.73
e 0.090 BSC 2.29 BSC
GAUGE SEATING
L2 PLANE C PLANE
H 0.370 0.410 9.40 10.41
L 0.055 0.070 1.40 1.78
L1 0.114 REF 2.90 REF
L2 0.020 BSC 0.51 BSC
L BOTTOM VIEW L3 0.035 0.050 0.89 1.27
A1 L4 −−− 0.040 −−− 1.01
L1 ALTERNATE
Z 0.155 −−− 3.93 −−−
CONSTRUCTIONS
DETAIL A
ROTATED 905 CW STYLE 2:
PIN 1. GATE
SOLDERING FOOTPRINT* 2. DRAIN
3. SOURCE
6.20 3.00 4. DRAIN
0.244 0.118
2.58
0.102

5.80 1.60 6.17

0.228 0.063 0.243

SCALE 3:1 ǒinches

mm Ǔ

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.

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 NTD20N06L, NTDV20N06L

PACKAGE DIMENSIONS

IPAK
CASE 369D
ISSUE C

B C NOTES:
1. DIMENSIONING AND TOLERANCING PER
V R E ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.

INCHES MILLIMETERS
4 DIM MIN MAX MIN MAX
Z A 0.235 0.245 5.97 6.35
A B 0.250 0.265 6.35 6.73
S C 0.086 0.094 2.19 2.38
1 2 3
D 0.027 0.035 0.69 0.88
E 0.018 0.023 0.46 0.58
−T− F 0.037 0.045 0.94 1.14
SEATING G 0.090 BSC 2.29 BSC
PLANE K H 0.034 0.040 0.87 1.01
J 0.018 0.023 0.46 0.58
K 0.350 0.380 8.89 9.65
R 0.180 0.215 4.45 5.45
J S 0.025 0.040 0.63 1.01
F V 0.035 0.050 0.89 1.27
H
Z 0.155 −−− 3.93 −−−
D 3 PL
STYLE 2:
G 0.13 (0.005) M T PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN

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