(Top View)
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and
advise customers to obtain the latest version of relevant information to verify before placing orders.
Pin Configuration(Cont.)
23 ROUTN
27 LOUTN
28 PGND
22 PGND
24 RBSN
26 LBSN
25 NC
LOUTP 1 21 ROUTP
LBSP 2 20 RBSP
LPVDD 3 19 RPVDD
APA2614 18 MONO
SD 4
QFN4x4-28
FLAG 5 17 NC
LINP 6 16 RINP
LINN 7 15 RINN
AVDD 11
NC 8
GAIN0 9
GAIN1 10
AGND 12
PLIMIT 14
VCLAMP 13
(Top View)
Note : ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which
are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for
MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen
free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by
weight).
Note1: Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are
stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recom-
mended operating conditions" is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
Thermal Characteristics
Symbol Parameter Typical Value Unit
Thermal Resistance -Junction to Ambient (Note 2)
θJA TSSOP-28P 45
QFN4x4-28 40 ο
C/W
Thermal Resistance -Junction to Case (Note 3)
θJC TSSOP-28P 8
QFN4x4-28 7
Note 2: θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. The exposed pad
of TSSOP-28P is soldered directly on the PCB.
Note 3: The case temperature is measured at the center of the exposed pad on the underside of the TSSOP-28P package.
Electrical Characteristics
VDD=12V, GND=0V, AV=36dB, TA= 25οC (unless otherwise noted).
APA2614
Symbol Parameter Test Conditions Unit
Min. Typ. Max.
IO=2mA, VDD=8~26V
VCLAMP Regulated Voltage 4.5 5 5.5 V
TJ = -40oC ~ 125oC
Maximum Output Voltage
VO VPLIMIT = 1V, Vl = 1Vrms - 5.5 -
Under PLIMIT Control
TSD(ON) Shutdown Turn-On Time SD =2.2V - 16 - ms
TSD(OFF) Shutdown Turn-Off Time SD =0.8V - 2 - µs
IDD Quiescent Supply Current No Load - 20 35 mA
Quiescent Supply Current in
ISD SD = 0V - 10 100
shutdown mode µA
II Input Current SD , GAIN0, GAIN1, MONO - 5 50
FOSC Internal Oscillator Frequency 400 500 600 kHz
Static Drain-Source On-State
RDSON VDD = 12V, IL= 0.5A - 240 - mΩ
Resistance
Gain 0 = 0, Gain 1 = 0 - 20 -
Gain 0 = 1, Gain 1 = 0 - 26 -
AV Gain dB
Gain 0 = 0, Gain 1 = 1 - 32 -
Gain 0 = 1, Gain 1 = 1 - 36 -
tDCDET DC Derect Time VINP=5V, VINN=0V - 500 - ms
Stereo Mode
VDD=12V, GND=0V, AV=36dB, TA= 25οC (unless otherwise noted).
APA2614
Symbol Parameter Test Conditions Unit
Min. Typ. Max.
VDD = 24V, TA = 25°
C
VDD=16V
Po Output Power - 12 - W
THD+N=1%, FIN=1kHz
RL=8Ω
Total Harmonic Distortion Pulse VDD=16V
THD+N - 0.1 - %
Noise FIN=1kHz, Po=7.5W
Crosstalk Channel Separation VO=1Vrms, FIN =1kHz, Gain=20dB - -85 -
PSRR Power Supply Rejection Ratio RL=4Ω, input AC-Ground, fin=1kHz - -65 -
Maximum output at THD+N<1%, dB
SNR Signal-To-Noise Ratio - 95 -
FIN=1kHz, Gain = 20dB, A-weighted
Attshutdown Shutdown Attenuation FIN=1kHz, RL = 8Ω, Vin = 1VPP - -100 -
I VOS I Offset Voltage AV=20dB - - 15 mV
µV
Vn Noise Output Voltage With A-weighted Filter (AV = 20dB) - 160 -
(rms)
VDD = 12V TA = 25°
C
VDD=13V
THD+N = 1% RL=8Ω - 8 -
FIN=1kHz
PO Output Power W
VDD=13V
THD+N = 10% RL=8Ω - 10 -
FIN=1kHz
VDD=13V RL = 8Ω
THD+N Total Harmonic Distortion Plus Noise - 0.1 - %
FIN=1kHz PO = 5W
APA2614
Symbol Parameter Test Conditions Unit
Min. Typ. Max.
VDD = 12V TA = 25°
C
Crosstalk Channel Separation VO=1Vrms, FIN =1kHz, Gain=20dB - -90 -
PSRR Power Supply Rejection Ratio RL=4Ω, input AC-Ground, fin=1kHz - -65 -
Maximum output at THD+N<1%, dB
SNR Signal-To-Noise Ratio FIN=1kHz, Gain = 20dB, - 95 -
A-weighted
Attshutdown Shutdown Attenuation FIN=1kHz, RL = 8Ω, Vin = 1VPP - -100 -
I VOS I Offset Voltage AV=20dB - - 15 mV
Vn Noise Output Voltage With A-weighted Filter (AV = 20dB) - 160 - µV (rms)
Mono Mode
VDD=12V, GND=0V, AV=36dB, TA= 25οC (unless otherwise noted).
APA2614
Symbol Parameter Test Conditions Unit
Min. Typ. Max.
VDD = 12V TA = 25°
C
VDD=16V
THD+N = 1% RL = 4Ω - 24 -
FIN=1kHz
PO Output Power W
VDD=16V
THD+N = 10% RL = 4Ω - 30 -
FIN=1kHz
VDD=16V RL = 4Ω
THD+N Total Harmonic Distortion Plus Noise - 0.1 - %
FIN=1kHz PO = 6W
PSRR Power Supply Rejection Ratio RL=4Ω, input AC-Ground, fin=1kHz - -65 -
Maximum output at THD+N<1%,
SNR Signal-To-Noise Ratio - 95 - dB
FIN=1kHz, Gain = 20dB, A-weighted
Attshutdown Shutdown Attenuation FIN=1kHz, RL = 8Ω, Vin = 1Vrms - -100 -
VOS Offset Voltage AV = 20dB - - 15 mV
Vn Noise Output Voltage With A-weighted Filter (AV = 20dB) - 160 - µV (rms)
THD+N (%)
VDD=24V
Fin=1kHz
0.1 Fin=1kHz 0.1 RL=4Ω
RL=8Ω
AV=20dB
AV=20dB AUX-0025
AUX-0025 AES-17(20kHz)
AES-17(20kHz)
0.01 0.01
0 5 10 15 20 25 30 35 40 0 5 10 15 20 25 30 35 40 45
Output Power (W) Output Power (W)
0.1
Fin=1kHz PO=1W
0.1 RL=4Ω
AV=20dB
AUX-0025 0.01
AES-17(20kHz)
MONO mode
0.01 0.001
0 10 20 30 40 50 20 100 1k 10k 20k
Output Power (W) Frequency (Hz)
THD+N (%)
0.1 0.1
PO=1W
PO=1W
0.01 0.01
0.001 0.001
20 100 1k 10k 20k 20 100 1k 10k 20k
Frequency (Hz) Frequency (Hz)
Efficiency (%)
MONO mode VDD=12V
THD+N (%)
60
0.1 VDD=8V
50
Fin=1kHz
40 RL=8Ω
PO=1W THD+N≦10%
30 AV=20dB
0.01
20 AUX-0025
AES-17(20kHz)
10 stereo mode
0.001 0
20 100 1k 10k 20k 0 2 4 6 8 10 12 14 16 18 20 22 24
Frequency (Hz) Output Power (W)
90 VDD=12V
10.0 RL=8Ω
80 AV=20dB
70
Output Power (W)
8.0
Efficiency (%)
60
VDD=8V VDD=12V
50 6.0
Fin=1kHz
40 RL=4Ω
THD+N≦10% 4.0
30
AV=20dB
20
AUX-0025
AES-17(20kHz) 2.0
10 MONO mode
0 0.0
0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
Output Power (W) VPLIMT (V)
Crosstalk (dB)
-70 AUX-0025
AES-17(20kHz)
16.0
-80
Left channel to Right channel
12.0
-90
8.0 -100
Right channel to Left channel
4.0 -110
0.0 -120
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 20 100 1k 10k 20k
VPLIMT (V) Frequency (Hz)
-70
AES-17(20kHz)
-80 Right channel to Left channel 300
-90 AV=32dB
250
-100
Left channel to Right channel
AV=20dB AV=26dB
200
-110
-120 150
20 100 1k 10k 20k 20 100 1k 10k 20k
Frequency (Hz) Frequency (Hz)
-20 AV=20dB
AES-17(20kHz)
A-Weighting AV=36dB Vrr=0.2Vrms
350 -30 AUX-0025
AES-17(20kHz)
PSRR (dB)
-40
300 L-channel
AV=32dB
-50
250 -60
AV=26dB
-70
200 R-channel
AV=20dB -80
150 -90
20 100 1k 10k 20k 20 100 1k 10k 20k
Gain,
AES-17(20kHz) AV=20dB +50
PSRR (dB)
Gain (dB)
+36 VDD=12V
+150 -60
Gain, RL=8Ω
Phase (Degree)
+50 -80 AES-17(20kHz)
Gain (dB)
+30
+0 -90
+28
Phase, -50 -100
+26 VDD=12V AV=36dB
RL=8Ω -100 L-channel R-channel
+24 Phase, -110
Ci=1µF AV=32dB
AUX-0025 -150 -120
+22
AES-17(20kHz)
+20 -200 -130
20 100 1k 10k 20k 100k 20 100 1k 10k 20k
Frequency (Hz) Frequency (Hz)
0.7
20
0.6
15 0.5
0.4
10
0.3
0.2
5
0.1
0 0.0
0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30
Supply Voltage (V) Supply Voltage (V)
Pin Description
PIN
I/O/P FUNCTION
NO.
TSSOP QFN4x4 NAME
-28P -28
Shutdown logic input for audio amp (Low=outputs disabled, High=output
1 4 SD I
enabled). TTL logic levels with compliance to AVDD.
Protection flag output (open drain). Connecting FLAG and SD can be set to
2 5 FLAG O
auto-recovery. Otherwise need to reset by cyding AVDD
3 6 LINP I Positive audio input for left channel. Biased at VCLAMP/2.
4 7 LINN I Negative audio input for left channel. Biased at VCLAMP/2.
5 9 GAIN0 I Gain select least significant bit. TTL logic levels with compliance to AVDD.
6 10 GAIN1 I Gain select least significant bit. TTL logic levels with compliance to AVDD.
7 11 AVDD P Analog supply.
8 12 AGND P Analog signal ground. Connect to the thermal pad.
9 13 VCLAMP O Regulated voltage, Nominal voltage is 5V.
Power limit level adjust. Connect a resistor divider from VCLAMP to GND to
10 14 PLIMIT I
set power limit. Connect directly to VCLAMP for no power limit.
11 15 RINN I Negative audio input for right channel. Biased at VCLAMP/2.
12 16 RINP I Positive audio input for right channel. Biased at VCLAMP/2.
13 8, 17, 25 NC Not connected.
14 18 MONO I Parallel BTL mode switch.
Power supply for right channel H-bridge. Right channel and left channel power
15,16 19 RPVDD P
supply inputs are connected internally.
17 20 RBSP I Bootstrap I/O for right channel, positive high-side FET.
18 21 ROUTP O Class-D H-bridge positive output for right channel.
19, 24 22, 28 PGND P Power ground for the H-bridges.
20 23 ROUTN O Class-D H-bridge negative output for right channel.
21 24 RBSN I Bootstrap I/O for right channel, negative high-side FET.
22 26 LBSN I Bootstrap I/O for left channel, negative high-side FET.
23 27 LOUTN O Class-D H-bridge negative output for left channel.
25 1 LOUTP O Class-D H-bridge positive output for left channel.
26 2 LBSP I Bootstrap I/O for left channel, positive high-side FET.
Power supply for left channel H-bridge. Right channel and left channel power
27,28 3 LPVDD P
supply inputs are connected internally.
Block Diagram
VCLAMP LBSP
LPVDD
LPVDD
LOUTP FB
MONO Select
Gate
LOUTP FB LOUTP
Drive
LINP
PWM PGND
Gain VCLAMP
PLIMIT
Control Logic LPVDD
LBSN
LINN LPVDD
LOUTN FB
LOUTN FB
Gate
Drive LOUTN
FLAG
VCLAMP RBSN
AVDD LDO RPVDD
Regulator
RPVDD
VCLAMP
VCLAMP
Gate
ROUTN FB ROUTN
Drive
ROUTN FB
RINN
Gain PWM PGND
VCLAMP
PLIMIT Logic
Control RPVDD RBSP
RINP RPVDD
ROUTP FB
Gate
Drive ROUTP
MONO Select
ROUTP FB
TTL MONO
MONO PGND
Buffer Select
AGND
VDD
10Ω 100kΩ
(Recommmanded)
1kΩ
(Recommmanded) SD 1 28 LPVDD
Shutdown Control
FLAG 2 27 LPVDD
Left Channel 1µF LINP 3 26 LBSP 0.22µF BEAD
29
GND
Stereo VDD
VDD
10Ω 100kΩ
(Recommmanded)
1kΩ
(Recommmanded) SD 1 28 LPVDD
Shutdown Control
FLAG 2 27 LPVDD
LINP 3 26 LBSP
LINN 4 25 LOUTP
GAIN0 5 24 PGND 0.47µF
BEAD
Gain Setting GAIN1 6 23 LOUTN
1000pF
1µF AVDD 7 22 LBSN
AGND 8
APA2614 21 RBSN
BEAD
1µF VCLAMP 9 20 ROUTN 1000pF
PLIMIT 10 19 PGND
0.47µF
1µF RINN 11 18 ROUTP
Right Channel
1µF RINP 12 17 RBSP
Input Signal
NC 13 16 RPVDD
MONO 14 15 RPVDD
100 µF 0. 1µF 1000 pF
29
GND
MONO VDD
Function Description
Class-D Operation the switching period, reducing the switching current, which
reduces any I2R losses in the load.
Output = 0
Gain Setting Operation
VOUTP
GAIN1 GAIN0 Gain Ri(Ω)
0 0 20dB 60k
0 1 26dB 30k
VOUTN
1 0 32dB 15k
VOUT 1 1 36dB 9k
(VOUTP-VOUTN)
Table 1 : The Gain Setting
1.57V 5W 6.3W
1.85V 7W 8.5W Thermal Protection
Table2. PLIMIT Typical Operation Thermal protection on the APA2614 prevents damage to
the device when the internal die temperature exceeds
VCLAMP Supply 150°C. There is a ±15°C tolerance on this trip point from
device to device. Once the die temperature exceeds the
The VCLAMP is used to power the gates of the output full
thermal set point, the device enters into the shutdown
bridge transistors. It can also be used to supply the PLIMIT
state and the outputs are disabled. This is not a latched
voltage divider circuit. Add a 1µF capacitor to ground at
fault. The thermal fault is cleared once the temperature of
this pin.
the die is reduced by 15°C. The device begins normal
Stereo/mono switching Operation operation at this point with no external system interaction.
APA2614 offers the feature of Stereo operation with two Thermal protection faults are NOT reported on the
outputs of each channel connected directly. If the MONO FLAG terminal.
pin (pin 14) is tied high, the positive and negative outputs
of each channel (left and right) are synchronized and in
phase. To operate in this mono mode, apply the input
signal to the RIGHT input and place the speaker between
the LEFT and RIGHT outputs. Connect the positive and
negative output together for best efficiency.
MONO mode can increase more output power compare
to the stereo mode single channel’s output power.
Application Information
Input Resistance, Ri A ferrite bead may need if it’s failing the test for FCC or CE
Changing the gain setting can vary the input resistance tested without the LC filter. The figure 2 is the sample for
of the amplifier from its smallest value, 9 kΩ ±20%, to the added ferrite bead; the ferrite show choosing high im-
largest value, 60 kΩ ±20%. As a result, if a single capaci- pedance in high frequency.
tor is used in the input high-pass filter, the -3 dB or cutoff
frequency may change when changing gain steps.
Ferrite
Input Capacitor, Ci OUTP Bead
1 (2)
Ci =
2πRi fc
33µH
In this example, CI is 0.13 µF; so, one would likely choose OUTP
Layout Recommendation(Cont.)
2.0mm
0.7mm
3.0mm
2.7mm
0.65mm
1.5mm
2.5mm
6.5mm
0.254mm
0.45mm
Via diameter
= 0.3mm x 8
Via diameter
= 0.3mm x 9
6.4mm
Package Information
TSSOP-28P
D SEE VIEW A
D1
E1
E2
EXPOS
E
ED PAD
e b c
0.25
A2
A
GAUGE PLANE
SEATING PLANE
L
A1
0
VIEW A
S TSSOP-28P
Y
M MILLIMETERS INCHES
B
O
L MIN. MAX. MIN. MAX.
A 1.20 0.047
0 0o 8o 0o 8o
Note : 1. Followed from JEDEC MO-153 AET.
2. Dimension "D" does not include mold flash, protrusions
or gate burrs. Mold flash, protrusion or gate burrs shall not
exceed 6 mil per side.
3. Dimension "E1" does not include inter-lead flash or protrusions.
Inter-lead flash and protrusions shall not exceed 10 mil per side.
Package Information
QFN4x4-28
D A
b
Pin 1
A1
A3
D2
Pin 1 Corner
E2
L K
S QFN4x4-28
Y
M MILLIMETERS INCHES
B
O
L MIN. MAX. MIN. MAX.
A 0.80 1.00 0.031 0.039
E1
F
W
B0
K0 A0 OD1 B A
B
SECTION A-A
T
SECTION B-B
d
H
A
T1
Application A H T1 C d D W E1 F
12.4+2.00 13.0+0.50
330.0±2.00 50 MIN. 1.5 MIN. 20.2 MIN. 12.0±0.30 1.75±0.10 5.5±0.05
-0.00 -0.20
QFN4x4-28 P0 P1 P2 D0 D1 T A0 B0 K0
1.5+0.10 0.6+0.00
4.0±0.10 8.0±0.10 2.0±0.05 1.5 MIN. 4.30±0.20 4.30±0.20 1.30±0.20
-0.00 -0.40
(mm)
P2 P0
D0 A
E1
F
W
B0
D1
K0 A0 A
B B
SECTION A-A
SECTION B-B
d
H
A
T1
Application A H T1 C d D W E1 F
16.4+2.00 13.0+0.50
330.0±2.00 50 MIN. 1.5 MIN. 20.2 MIN. 16.0±0.30 1.75±0.10 7.50±0.10
-0.00 -0.20
TSSOP-28P P0 P1 P2 D0 D1 T A0 B0 K0
4.00±0.10 12.00±0.10 2.00±0.10 1.5+0.10 1.5 MIN. 0.6+0.00 6.9±0.20 10.20.±0.20 1.50±0.20
-0.00 -0.40
(mm)
QFN4x4-28
Classification Profile
Customer Service
Taipei Branch :
2F, No. 11, Lane 218, Sec 2 Jhongsing Rd.,
Sindian City, Taipei County 23146, Taiwan
Tel : 886-2-2910-3838
Fax : 886-2-2917-3838