SIMATIC 03/21/2017 05:03:24 PM

TIT-3 TIT-3

1 7

TIT-3
TIT-3
including rights created by patent grant or registration of a utility model or design, reserved.

2
8
The reproduction, transmission or use of this document or its contents is not permitted
without express written authority. Offenders will be liable for damages. All rights,

TIT-3 TIT-3

3 9

TIT-3 TIT-3

4 10

TIT-3 LIT-3

11
5

TIT-3 LIT-3

6 12

G70 Kemira\PLC Acido Acrilico\CPU 412-5 H PN/DP A\S7 Program(4)\Charts\\F_AI Author: modula
G70 - GAA Project Created on:: 16/03/2017 9:45
Last change: 21/03/2017 17:02
Partit.: A Overview Number of pages: 7

Page 1 of 7
SIMATIC 03/21/2017 05:03:24 PM

TIT-31800
F_CH_AI
F_:Fail- CYC_INT5
6/1
@F_(1)(A,1)\FAI6x15Bit_HAR_1 CHADDR PASS_OUT
CHADDRI00 ADDRESS INPUT PROCESS DATA BYTE 16#0 CHADDR_R QBAD
"TIT_31800_D" IW608 VALUE QSIM Loop 1(A,1)\TIT31800_801
including rights created by patent grant or registration of a utility model or design, reserved.

Temperatura di fondo tank Acido Acrilico S3 40.0 VHRANGE QSUBS QBAD1 1=INPUT IN1 INVALID
10.0 VLRANGE V Loop 1(A,1)\TIT31800_801
0 CH_F_ON V_DATA IN1 INPUT 1
0.0 CH_F_HL QUALITY
The reproduction, transmission or use of this document or its contents is not permitted

0.0 CH_F_LL V_MOD

0.0 SIM_V ACK_REQ
without express written authority. Offenders will be liable for damages. All rights,

0 SIM_ON 1
0.0 SUBS_V F_FBO_BO
F_BOOL t CYC_INT5
1 SUBS_ON 27/13
0 PASS_ON IN OUT "Interscambio_Tag".QBAD_TIT_31800 DB30.QBAD
0 ACK_NEC
ACK_REI

TIT-31801
F_CH_AI
F_:Fail- CYC_INT5
6/2
@F_(1)(B,2)\FAI6x15Bit_HAR_3 CHADDR PASS_OUT
CHADDRI10 ADDRESS INPUT PROCESS DATA BYTE 16#0 CHADDR_R QBAD
"TIT_31801_D" IW650 VALUE QSIM Loop 1(A,1)\TIT31800_801
Temperatura di fondo tank Acido Acrilico S3 40.0 VHRANGE QSUBS QBAD2 1=INPUT IN2 INVALID
10.0 VLRANGE V Loop 1(A,1)\TIT31800_801
0 CH_F_ON V_DATA IN2 INPUT 2
0.0 CH_F_HL QUALITY
0.0 CH_F_LL V_MOD
0.0 SIM_V ACK_REQ
0 SIM_ON 2
0.0 SUBS_V F_FBO_BO
F_BOOL t CYC_INT5
1 SUBS_ON 27/14
0 PASS_ON IN OUT "Interscambio_Tag".QBAD_TIT_31801 DB30.QBAD
0 ACK_NEC
F_DO_SPARE(A,2)\Ack_Passivation ACK_REI
OUT OUTPUT

G70 - Kemira - GAA Project

TIT-31800
TIT-31801

G70 Kemira\PLC Acido Acrilico\CPU 412-5 H PN/DP A\S7 Program(4)\Charts\\F_AI Author: modula
G70 - GAA Project Created on:: 16/03/2017 9:45
Last change: 21/03/2017 17:02
Partit.: A Sh.: 1 Number of pages: 7

Page 2 of 7
SIMATIC 03/21/2017 05:03:24 PM

TIT-31802
F_CH_AI
F_:Fail- CYC_INT5
6/3
@F_(1)(A,1)\FAI6x15Bit_HAR_1 CHADDR PASS_OUT
CHADDRI04 ADDRESS INPUT PROCESS DATA BYTE 16#0 CHADDR_R QBAD
"TIT_31802_D" IW612 VALUE QSIM Loop 1(A,2)\14
Temperatura intermedia tank Acido Acrilico 40.0 VHRANGE QSUBS IN1 INPUT 1
10.0 VLRANGE V Loop 1(A,2)\TIT31802_823
including rights created by patent grant or registration of a utility model or design, reserved.

0 CH_F_ON V_DATA IN1 INPUT 1

0.0 CH_F_HL QUALITY
0.0 CH_F_LL V_MOD
25.0 SIM_V ACK_REQ
The reproduction, transmission or use of this document or its contents is not permitted

1 SIM_ON 3
0.0 SUBS_V F_FBO_BO
without express written authority. Offenders will be liable for damages. All rights,

F_BOOL t CYC_INT5
1 SUBS_ON 27/15
0 PASS_ON IN OUT "Interscambio_Tag".QBAD_TIT_31802 DB30.QBAD
0 ACK_NEC
ACK_REI

TIT-31823
F_CH_AI
F_:Fail- CYC_INT5
6/7
@F_(1)(B,2)\FAI6x15Bit_HAR_3 CHADDR PASS_OUT
CHADDRI00 ADDRESS INPUT PROCESS DATA BYTE 16#0 CHADDR_R QBAD
"TIT_31823_D" IW640 VALUE QSIM Loop 1(A,2)\33
Temperatura intermedia tank Acido Acrilico 40.0 VHRANGE QSUBS IN1 INPUT 1
10.0 VLRANGE V Loop 1(A,2)\TIT31802_823
0 CH_F_ON V_DATA IN2 INPUT 2
0.0 CH_F_HL QUALITY
0.0 CH_F_LL V_MOD
5.0 SIM_V ACK_REQ
1 SIM_ON 4
0.0 SUBS_V F_FBO_BO
F_BOOL t CYC_INT5
1 SUBS_ON 27/16
0 PASS_ON IN OUT "Interscambio_Tag".QBAD_TIT_31823 DB30.QBAD
0 ACK_NEC
F_DO_SPARE(A,2)\Ack_Passivation ACK_REI
OUT OUTPUT

G70 - Kemira - GAA Project

TIT-31802
TIT-31823

G70 Kemira\PLC Acido Acrilico\CPU 412-5 H PN/DP A\S7 Program(4)\Charts\\F_AI Author: modula
G70 - GAA Project Created on:: 16/03/2017 9:45
Last change: 21/03/2017 17:02
Partit.: A Sh.: 2 Number of pages: 7

Page 3 of 7
SIMATIC 03/21/2017 05:03:24 PM

TIT-31811
F_CH_AI
F_:Fail- CYC_INT5
6/6
@F_(1)(A,1)\FAI6x15Bit_HAR_1 CHADDR PASS_OUT
CHADDRI10 ADDRESS INPUT PROCESS DATA BYTE 16#0 CHADDR_R QBAD
"TIT_31811_D" IW618 VALUE QSIM Loop 2(A,1)\TIT31811_824
Temperatura Acido Acrilico in ritorno loop 100.0 VHRANGE QSUBS QBAD1 1=INPUT IN1 INVALID
0.0 VLRANGE V Loop 2(A,1)\TIT31811_824
including rights created by patent grant or registration of a utility model or design, reserved.

0 CH_F_ON V_DATA IN1 INPUT 1

0.0 CH_F_HL QUALITY
0.0 CH_F_LL V_MOD
0.0 SIM_V ACK_REQ
The reproduction, transmission or use of this document or its contents is not permitted

0 SIM_ON 5
0.0 SUBS_V F_FBO_BO
without express written authority. Offenders will be liable for damages. All rights,

F_BOOL t CYC_INT5
1 SUBS_ON 27/17
0 PASS_ON IN OUT "Interscambio_Tag".QBAD_TIT_31811 DB30.QBAD
0 ACK_NEC
ACK_REI

TIT-31824
F_CH_AI
F_:Fail- CYC_INT5
6/8
@F_(1)(B,2)\FAI6x15Bit_HAR_3 CHADDR PASS_OUT
CHADDRI02 ADDRESS INPUT PROCESS DATA BYTE 16#0 CHADDR_R QBAD
"TIT_31824_D" IW642 VALUE QSIM Loop 2(A,1)\TIT31811_824
Temperatura Acido Acrilico in ritorno loop 100.0 VHRANGE QSUBS QBAD2 1=INPUT IN2 INVALID
0.0 VLRANGE V Loop 2(A,1)\TIT31811_824
0 CH_F_ON V_DATA IN2 INPUT 2
0.0 CH_F_HL QUALITY
0.0 CH_F_LL V_MOD
0.0 SIM_V ACK_REQ
0 SIM_ON 6
0.0 SUBS_V F_FBO_BO
F_BOOL t CYC_INT5
1 SUBS_ON 27/18
0 PASS_ON IN OUT "Interscambio_Tag".QBAD_TIT_31824 DB30.QBAD
0 ACK_NEC
F_DO_SPARE(A,2)\Ack_Passivation ACK_REI
OUT OUTPUT

G70 - Kemira - GAA Project

TIT-31811
TIT-31824

G70 Kemira\PLC Acido Acrilico\CPU 412-5 H PN/DP A\S7 Program(4)\Charts\\F_AI Author: modula
G70 - GAA Project Created on:: 16/03/2017 9:45
Last change: 21/03/2017 17:02
Partit.: A Sh.: 3 Number of pages: 7

Page 4 of 7
SIMATIC 03/21/2017 05:03:24 PM

TIT-31806
F_CH_AI
F_:Fail- CYC_INT5
6/4
@F_(1)(A,1)\FAI6x15Bit_HAR_1 CHADDR PASS_OUT
CHADDRI06 ADDRESS INPUT PROCESS DATA BYTE 16#0 CHADDR_R QBAD
"TIT_31806_D" IW614 VALUE QSIM Loop 3(A,1)\TIT31806_825
including rights created by patent grant or registration of a utility model or design, reserved.

Temperatura acqua termostatazione mandata p 100.0 VHRANGE QSUBS QBAD1 1=INPUT IN1 INVALID
0.0 VLRANGE V Loop 3(A,1)\TIT31806_825
0 CH_F_ON V_DATA IN1 INPUT 1
0.0 CH_F_HL QUALITY
The reproduction, transmission or use of this document or its contents is not permitted

0.0 CH_F_LL V_MOD

0.0 SIM_V ACK_REQ
without express written authority. Offenders will be liable for damages. All rights,

0 SIM_ON 7
0.0 SUBS_V F_FBO_BO
F_BOOL t CYC_INT5
1 SUBS_ON 27/19
0 PASS_ON IN OUT "Interscambio_Tag".QBAD_TIT_31806 DB30.QBAD
0 ACK_NEC
ACK_REI

TIT-31825
F_CH_AI
F_:Fail- CYC_INT5
6/9
@F_(1)(B,2)\FAI6x15Bit_HAR_3 CHADDR PASS_OUT
CHADDRI04 ADDRESS INPUT PROCESS DATA BYTE 16#0 CHADDR_R QBAD
"TIT_31825_D" IW644 VALUE QSIM Loop 3(A,1)\TIT31806_825
Temperatura acqua termostatazione mandata p 100.0 VHRANGE QSUBS QBAD2 1=INPUT IN2 INVALID
0.0 VLRANGE V Loop 3(A,1)\TIT31806_825
0 CH_F_ON V_DATA IN2 INPUT 2
0.0 CH_F_HL QUALITY
0.0 CH_F_LL V_MOD
0.0 SIM_V ACK_REQ
0 SIM_ON 8
0.0 SUBS_V F_FBO_BO
F_BOOL t CYC_INT5
1 SUBS_ON 27/20
0 PASS_ON IN OUT "Interscambio_Tag".QBAD_TIT_31825 DB30.QBAD
0 ACK_NEC
F_DO_SPARE(A,2)\Ack_Passivation ACK_REI
OUT OUTPUT

G70 - Kemira - GAA Project

TIT-31806
TIT-31825

G70 Kemira\PLC Acido Acrilico\CPU 412-5 H PN/DP A\S7 Program(4)\Charts\\F_AI Author: modula
G70 - GAA Project Created on:: 16/03/2017 9:45
Last change: 21/03/2017 17:02
Partit.: A Sh.: 4 Number of pages: 7

Page 5 of 7
SIMATIC 03/21/2017 05:03:24 PM

TIT-31808
F_CH_AI
F_:Fail- CYC_INT5
6/5
@F_(1)(A,1)\FAI6x15Bit_HAR_1 CHADDR PASS_OUT
CHADDRI08 ADDRESS INPUT PROCESS DATA BYTE 16#0 CHADDR_R QBAD
"TIT_31808_D" IW616 VALUE QSIM Loop 4(A,1)\TIT31808_826
Temperatura Acido Acrilico in carico da tan 100.0 VHRANGE QSUBS QBAD1 1=INPUT IN1 INVALID
0.0 VLRANGE V Loop 4(A,1)\TIT31808_826
including rights created by patent grant or registration of a utility model or design, reserved.

0 CH_F_ON V_DATA IN1 INPUT 1

0.0 CH_F_HL QUALITY
0.0 CH_F_LL V_MOD
0.0 SIM_V ACK_REQ
The reproduction, transmission or use of this document or its contents is not permitted

0 SIM_ON 9
0.0 SUBS_V F_FBO_BO
without express written authority. Offenders will be liable for damages. All rights,

F_BOOL t CYC_INT5
1 SUBS_ON 27/21
0 PASS_ON IN OUT "Interscambio_Tag".QBAD_TIT_31808 DB30.QBAD
0 ACK_NEC
F_DO_SPARE(A,2)\Ack_Passivation ACK_REI
OUT OUTPUT

TIT-31826
F_CH_AI
F_:Fail- CYC_INT5
6/10
@F_(1)(B,2)\FAI6x15Bit_HAR_3 CHADDR PASS_OUT
CHADDRI06 ADDRESS INPUT PROCESS DATA BYTE 16#0 CHADDR_R QBAD
"TIT_31826_D" IW646 VALUE QSIM Loop 4(A,1)\TIT31808_826
Temperatura Acido Acrilico in carico da tan 100.0 VHRANGE QSUBS QBAD2 1=INPUT IN2 INVALID
0.0 VLRANGE V Loop 4(A,1)\TIT31808_826
0 CH_F_ON V_DATA IN2 INPUT 2
0.0 CH_F_HL QUALITY
0.0 CH_F_LL V_MOD
0.0 SIM_V ACK_REQ
0 SIM_ON 10
0.0 SUBS_V F_FBO_BO
F_BOOL t CYC_INT5
1 SUBS_ON 27/22
0 PASS_ON IN OUT "Interscambio_Tag".QBAD_TIT_31826 DB30.QBAD
0 ACK_NEC
ACK_REI

G70 - Kemira - GAA Project

TIT-31808
TIT-31826

G70 Kemira\PLC Acido Acrilico\CPU 412-5 H PN/DP A\S7 Program(4)\Charts\\F_AI Author: modula
G70 - GAA Project Created on:: 16/03/2017 9:45
Last change: 21/03/2017 17:02
Partit.: A Sh.: 5 Number of pages: 7

Page 6 of 7
SIMATIC 03/21/2017 05:03:25 PM

LIT-30800
F_CH_AI
F_:Fail- CYC_INT5
6/11
@F_(1)(A,4)\FAI6x15Bit_HAR_2 CHADDR PASS_OUT
CHADDRI00 ADDRESS INPUT PROCESS DATA BYTE 16#0 CHADDR_R QBAD
"LIT_30800_D" IW624 VALUE QSIM Loop 1(A,4)\LIT30800_801
Livello tank Acido Acrilico S392 9000.0 VHRANGE QSUBS QBAD1 1=INPUT IN1 INVALID
0.0 VLRANGE V Loop 1(A,4)\LIT30800_801
including rights created by patent grant or registration of a utility model or design, reserved.

0 CH_F_ON V_DATA IN1 INPUT 1

0.0 CH_F_HL QUALITY
0.0 CH_F_LL V_MOD 11
3100.0 SIM_V ACK_REQ F_FBO_BO
F_BOOL t CYC_INT5
The reproduction, transmission or use of this document or its contents is not permitted

1 SIM_ON 27/23
0.0 SUBS_V IN OUT "Interscambio_Tag".QBAD_LIT_30800 DB30.QBAD
without express written authority. Offenders will be liable for damages. All rights,

1 SUBS_ON
0 PASS_ON
0 ACK_NEC
F_DO_SPARE(A,2)\Ack_Passivation ACK_REI
OUT OUTPUT

LIT-30801
F_CH_AI
F_:Fail- CYC_INT5
6/12
@F_(1)(B,2)\FAI6x15Bit_HAR_3 CHADDR PASS_OUT
CHADDRI08 ADDRESS INPUT PROCESS DATA BYTE 16#0 CHADDR_R QBAD
"LIT_30801_D" IW648 VALUE QSIM Loop 1(A,4)\LIT30800_801
Livello tank Acido Acrilico S392 9000.0 VHRANGE QSUBS QBAD2 1=INPUT IN2 INVALID
0.0 VLRANGE V Loop 1(A,4)\LIT30800_801
0 CH_F_ON V_DATA IN2 INPUT 2
0.0 CH_F_HL QUALITY
0.0 CH_F_LL V_MOD
8000.0 SIM_V ACK_REQ
1 SIM_ON 12
0.0 SUBS_V F_FBO_BO
F_BOOL t CYC_INT5
1 SUBS_ON 27/24
0 PASS_ON IN OUT "Interscambio_Tag".QBAD_LIT_30801 DB30.QBAD
0 ACK_NEC
ACK_REI

G70 - Kemira - GAA Project

LIT-30800
LIT-30801

G70 Kemira\PLC Acido Acrilico\CPU 412-5 H PN/DP A\S7 Program(4)\Charts\\F_AI Author: modula
G70 - GAA Project Created on:: 16/03/2017 9:45
Last change: 21/03/2017 17:02
Partit.: A Sh.: 6 Number of pages: 7

Page 7 of 7
SIMATIC 03/21/2017 05:09:31 PM

TIT31 I6

I5 LIT30
TIT31
including rights created by patent grant or registration of a utility model or design, reserved.

1 TIT31

2
LALL
The reproduction, transmission or use of this document or its contents is not permitted
without express written authority. Offenders will be liable for damages. All rights,

TIT31
I8

I7

14

13 7
33

17 8

18 9

All_1

All_2

All_3

All_4

G70 Kemira\PLC Acido Acrilico\CPU 412-5 H PN/DP A\S7 Program(4)\Charts\\Loop 1 Author: modula
G70 - GAA Project Created on:: 28/02/2017 17:59
Last change: 21/03/2017 17:05
Partit.: A Overview Number of pages: 5

Page 1 of 5
SIMATIC 03/21/2017 05:09:31 PM

TIT31800_801
F_1oo2AI I6
F_:1oo2 CYC_INT5
F_LIM_HL
8/1 CYC_INT5
0.5 DELTA OUT_AVG F_:Limit
8/6
1s DIS_TIME OUT_MAX U QH
F_AI(A,1)\TIT-31800 IN1 OUT_MIN 26.0 U_HL QHN F_DO_EFLA(A,1)\Cond_ON
including rights created by patent grant or registration of a utility model or design, reserved.

V PROCESS VALUE IN2 QBAD_1CH 0.0 HYS U_HL_O IN1 INPUT 1

F_AI(A,1)\TIT-31801 QBAD1 QBAD_ALL 0 SUBS_IN HYS_O F_DO_ESA(A,1)\7
V PROCESS VALUE QBAD2 DIS IN INPUT
F_AI(A,1)\TIT-31800 21.5 SUBS_V DIS_D F_DO_ESA(A,1)\10
The reproduction, transmission or use of this document or its contents is not permitted

QBAD 1=PROCESS VALUE INVALID 0 ACK_NEC ACK_REQ S SET

F_AI(A,1)\TIT-31801 0 ACK F_DO_VALVOLE(A,6)\Close_TV31800
without express written authority. Offenders will be liable for damages. All rights,

QBAD 1=PROCESS VALUE INVALID IN1 INPUT 1

I5 F_DO_VALVOLE(A,1)\Loop1_5_6_7_8
F_LIM_LL IN1 INPUT 1
F_:Limit CYC_INT5
8/7
U QL
17.0 U_LL QLN F_DO_EFLA(A,1)\Cond_ON
0.0 HYS U_LL_O IN2 INPUT 2
0 SUBS_IN HYS_O F_DO_ESA(A,1)\16
S SET
F_DO_ESA(A,1)\14
IN INPUT
F_DO_VALVOLE(A,6)\Close_TV31801
1 IN1 INPUT 1
F_FBO_BO F_DO_VALVOLE(A,1)\Loop1_5_6_7_8
F_BOOL t CYC_INT5
27/7 IN2 INPUT 2
IN OUT "Interscambio_Tag".QBAD_1CH_BL_I5_6 DB30.QB

2
F_FBO_BO
F_BOOL t CYC_INT5
27/12
IN OUT "Interscambio_Tag".QBAD_ALL_BL_I5_6 DB30.QB

3
F_FBO_BO
F_BOOL t CYC_INT5
27/11
IN OUT "Interscambio_Tag".DIS_BL_I5_6 DB30.DIS_BL_

G70 - Kemira - GAA Project

LOOP 1 (1/2)
Blocchi: I5, I6

G70 Kemira\PLC Acido Acrilico\CPU 412-5 H PN/DP A\S7 Program(4)\Charts\\Loop 1 Author: modula
G70 - GAA Project Created on:: 28/02/2017 17:59
Last change: 21/03/2017 17:05
Partit.: A Sh.: 1 Number of pages: 5

Page 2 of 5
SIMATIC 03/21/2017 05:09:31 PM

TIT31802_823
F_1oo2AI
F_:1oo2 CYC_INT5
8/2 I8
0.5 DELTA OUT_AVG F_LIM_HL
F_:Limit CYC_INT5
1s DIS_TIME OUT_MAX 8/8
F_AI(A,2)\TIT-31802 IN1 OUT_MIN U QH F_DO_EFLA(A,1)\Cond_ON
V PROCESS VALUE IN2 QBAD_1CH 26.0 U_HL QHN IN3 INPUT 3
F_AI(A,2)\TIT-31823 QBAD1 QBAD_ALL 0.0 HYS U_HL_O F_DO_ESA(A,2)\21
including rights created by patent grant or registration of a utility model or design, reserved.

V PROCESS VALUE QBAD2 DIS 0 SUBS_IN HYS_O S SET

21.5 SUBS_V DIS_D F_DO_ESA(A,2)\19
0 ACK_NEC ACK_REQ IN INPUT
0 ACK I7 F_DO_VALVOLE(A,6)\Close_TV31800
F_LIM_LL
The reproduction, transmission or use of this document or its contents is not permitted

CYC_INT5 IN2 INPUT 2

F_:Limit F_DO_VALVOLE(A,1)\Loop1_5_6_7_8
without express written authority. Offenders will be liable for damages. All rights,

8/9
U QL IN3 INPUT 3
17.0 U_LL QLN F_DO_EFLA(A,1)\Cond_ON
0.0 HYS U_LL_O IN4 INPUT 4
0 SUBS_IN HYS_O F_DO_ESA(A,1)\28
14 S SET
F_OR4 F_DO_ESA(A,1)\22
F_:OR 4 CYC_INT5
8/16 IN INPUT
F_AI(A,2)\TIT-31802 IN1 OUT F_DO_VALVOLE(A,6)\Close_TV31801
QBAD 1=PROCESS VALUE INVALID IN2 OUTN IN2 INPUT 2
Loop 1(A,4)\TIT31802_OUT 0 IN3 F_DO_VALVOLE(A,1)\Loop1_5_6_7_8
QL OUTPUT 0 IN4 13 7 IN4 INPUT 4
F_AND4 F_FBO_BO
F_:AND 4 CYC_INT5 F_BOOL t CYC_INT5
8/10 27/8
IN1 OUT IN OUT "Interscambio_Tag".QBAD_1CH_BL_I7_8 DB30.QB
33 IN2 OUTN
F_OR4 IN3
F_:OR 4 CYC_INT5
8/19 1 IN4
F_AI(A,2)\TIT-31823 IN1 OUT
QBAD 1=PROCESS VALUE INVALID IN2 OUTN
Loop 1(A,4)\TIT31823_OUT 0 IN3
QL OUTPUT 0 IN4 17 8
F_AND4 F_FBO_BO
F_:AND 4 CYC_INT5 F_BOOL t CYC_INT5
8/18 27/10
IN1 OUT IN OUT "Interscambio_Tag".QBAD_ALL_BL_I7_8 DB30.QB
IN2 OUTN
IN3
1 IN4

18 9
F_AND4 F_FBO_BO
F_:AND 4 CYC_INT5 F_BOOL t CYC_INT5
8/17 27/9
IN1 OUT IN OUT "Interscambio_Tag".DIS_BL_I7_8 DB30.DIS_BL_
IN2 OUTN
Loop 1(A,4)\TIT31823_OUT IN3
QLN NEGATED OUTPUT 1 IN4
Loop 1(A,4)\TIT31802_OUT
QLN NEGATED OUTPUT

G70 - Kemira - GAA Project

LOOP 1 (2/2)
Blocchi: I7, I8

G70 Kemira\PLC Acido Acrilico\CPU 412-5 H PN/DP A\S7 Program(4)\Charts\\Loop 1 Author: modula
G70 - GAA Project Created on:: 28/02/2017 17:59
Last change: 21/03/2017 17:05
Partit.: A Sh.: 2 Number of pages: 5

Page 3 of 5
SIMATIC 03/21/2017 05:09:31 PM

All_1
F_LIM_HL
F_:Limit CYC_INT5
8/13
0.0 U QH F_DO_EFLA(A,1)\Cond_ON1
27.0 U_HL QHN IN1 INPUT 1
0.0 HYS U_HL_O F_DO_ESA(A,6)\Con_ON_NOT_ACK
including rights created by patent grant or registration of a utility model or design, reserved.

0 SUBS_IN HYS_O IN1 INPUT 1

The reproduction, transmission or use of this document or its contents is not permitted

All_2
F_LIM_LL
without express written authority. Offenders will be liable for damages. All rights,

F_:Limit CYC_INT5
8/14
0.0 U QL F_DO_EFLA(A,1)\Cond_ON1
16.0 U_LL QLN IN2 INPUT 2
0.0 HYS U_LL_O F_DO_ESA(A,6)\Con_ON_NOT_ACK
0 SUBS_IN HYS_O IN2 INPUT 2

All_3
F_LIM_HL
F_:Limit CYC_INT5
8/11
0.0 U QH F_DO_EFLA(A,1)\Cond_ON1
27.0 U_HL QHN IN3 INPUT 3
0.0 HYS U_HL_O F_DO_ESA(A,6)\Con_ON_NOT_ACK
0 SUBS_IN HYS_O IN3 INPUT 3

All_4
F_LIM_LL
F_:Limit CYC_INT5
8/12
0.0 U QL F_DO_EFLA(A,1)\Cond_ON1
16.0 U_LL QLN IN4 INPUT 4
0.0 HYS U_LL_O F_DO_ESA(A,6)\Con_ON_NOT_ACK
0 SUBS_IN HYS_O IN4 INPUT 4

G70 Kemira\PLC Acido Acrilico\CPU 412-5 H PN/DP A\S7 Program(4)\Charts\\Loop 1 Author: modula
G70 - GAA Project Created on:: 28/02/2017 17:59
Last change: 21/03/2017 17:05
Partit.: A Sh.: 3 Number of pages: 5

Page 4 of 5
SIMATIC
including rights created by patent grant or registration of a utility model or design, reserved. 03/21/2017 05:09:31 PM
The reproduction, transmission or use of this document or its contents is not permitted
without express written authority. Offenders will be liable for damages. All rights,

LIT30800_801
F_1oo2AI
F_:1oo2 CYC_INT5
8/3 TIT31802_OUT
0.5 DELTA OUT_AVG F_LIM_LL
1s DIS_TIME OUT_MAX F_:Limit CYC_INT5
8/5
F_AI(A,6)\LIT-30800 IN1 OUT_MIN U QL Loop 1(A,2)\14
V PROCESS VALUE IN2 QBAD_1CH 3000.0 U_LL QLN IN2 INPUT 2
F_AI(A,6)\LIT-30801 QBAD1 QBAD_ALL 0.0 HYS U_LL_O Loop 1(A,2)\18
V PROCESS VALUE QBAD2 DIS 0 SUBS_IN HYS_O IN2 INPUT 2
F_AI(A,6)\LIT-30800 0.0 SUBS_V DIS_D Loop 1(A,2)\17
QBAD 1=PROCESS VALUE INVALID 0 ACK_NEC ACK_REQ IN2 INPUT 2
F_AI(A,6)\LIT-30801 0 ACK Loop 1(A,2)\13
QBAD 1=PROCESS VALUE INVALID TIT31823_OUT IN2 INPUT 2
F_LIM_LL
F_:Limit CYC_INT5
8/4
U QL Loop 1(A,2)\33
6750.0 U_LL QLN IN2 INPUT 2
0.0 HYS U_LL_O Loop 1(A,2)\18
0 SUBS_IN HYS_O IN3 INPUT 3
Loop 1(A,2)\17
IN3 INPUT 3
Loop 1(A,2)\13
LALL 30800_1 IN3 INPUT 3
F_LIM_LL
F_:Limit CYC_INT5
8/15
U QL
990.0 U_LL QLN
0.0 HYS U_LL_O F_DO_MOTORI(A,1)\StopCond_P392
0 SUBS_IN HYS_O IN2 INPUT 2

G70 Kemira\PLC Acido Acrilico\CPU 412-5 H PN/DP A\S7 Program(4)\Charts\\Loop 1 Author: modula
G70 - GAA Project Created on:: 28/02/2017 17:59
Last change: 21/03/2017 17:05
Partit.: A Sh.: 4 Number of pages: 5

Page 5 of 5
SIMATIC 03/21/2017 05:09:47 PM

TIT31

1
including rights created by patent grant or registration of a utility model or design, reserved.

3
The reproduction, transmission or use of this document or its contents is not permitted
without express written authority. Offenders will be liable for damages. All rights,

I10

I9

I12

I11

All1

All2

G70 Kemira\PLC Acido Acrilico\CPU 412-5 H PN/DP A\S7 Program(4)\Charts\\Loop 2 Author: modula
G70 - GAA Project Created on:: 16/03/2017 12:03
Last change: 21/03/2017 17:05
Partit.: A Overview Number of pages: 3

Page 1 of 3
SIMATIC 03/21/2017 05:09:47 PM

TIT31811_824
F_1oo2AI
F_:1oo2 CYC_INT5
9/1
0.5 DELTA OUT_AVG
1s DIS_TIME OUT_MAX Loop 2(A,2)\I12
including rights created by patent grant or registration of a utility model or design, reserved.

IN1 OUT_MIN U INPUT

F_AI(A,3)\TIT-31811 IN2 QBAD_1CH Loop 2(A,2)\All1
V PROCESS VALUE QBAD1 QBAD_ALL U INPUT
F_AI(A,3)\TIT-31824 QBAD2 DIS Loop 2(A,2)\I10
The reproduction, transmission or use of this document or its contents is not permitted

V PROCESS VALUE 21.5 SUBS_V DIS_D U INPUT

F_AI(A,3)\TIT-31811 0 ACK_NEC ACK_REQ Loop 2(A,2)\All2
without express written authority. Offenders will be liable for damages. All rights,

QBAD 1=PROCESS VALUE INVALID 0 ACK U INPUT

F_AI(A,3)\TIT-31824 Loop 2(A,2)\I11
QBAD 1=PROCESS VALUE INVALID U INPUT
Loop 2(A,2)\I9
U INPUT

1
F_FBO_BO
F_BOOL t CYC_INT5
27/4
IN OUT "Interscambio_Tag".QBAD_1CH_BL_I9_10_11_12

2
F_FBO_BO
F_BOOL t CYC_INT5
27/6
IN OUT "Interscambio_Tag".QBAD_ALL_BL_I9_10_11_12

3
F_FBO_BO
F_BOOL t CYC_INT5
27/5
IN OUT "Interscambio_Tag".DIS_BL_I9_10_11_12 DB30.

G70 - Kemira - GAA Project

LOOP 2
Blocchi:I9, I10, I11 e I12

G70 Kemira\PLC Acido Acrilico\CPU 412-5 H PN/DP A\S7 Program(4)\Charts\\Loop 2 Author: modula
G70 - GAA Project Created on:: 16/03/2017 12:03
Last change: 21/03/2017 17:05
Partit.: A Sh.: 1 Number of pages: 3

Page 2 of 3
SIMATIC 03/21/2017 05:09:48 PM

I10
F_LIM_HL
F_:Limit CYC_INT5
9/6
U QH F_DO_EFLA(A,1)\Cond_ON2
25.0 U_HL QHN IN1 INPUT 1
0.0 HYS U_HL_O F_DO_ESA(A,2)\38
0 SUBS_IN HYS_O S SET
F_DO_ESA(A,2)\34
including rights created by patent grant or registration of a utility model or design, reserved.

IN INPUT
F_DO_VALVOLE(A,1)\Loop2_9_10
I9 IN1 INPUT 1
F_LIM_LL F_DO_MOTORI(A,2)\Loop2_09_10
F_:Limit CYC_INT5
The reproduction, transmission or use of this document or its contents is not permitted

9/7 IN1 INPUT 1

U QL F_DO_EFLA(A,1)\Cond_ON2
without express written authority. Offenders will be liable for damages. All rights,

19.0 U_LL QLN IN2 INPUT 2

0.0 HYS U_LL_O F_DO_ESA(A,2)\33
0 SUBS_IN HYS_O S SET
F_DO_ESA(A,2)\39
IN INPUT
F_DO_VALVOLE(A,1)\Loop2_9_10
I12 IN2 INPUT 2
F_LIM_HL F_DO_MOTORI(A,2)\Loop2_09_10
F_:Limit CYC_INT5
9/4 IN2 INPUT 2
Loop 2(A,1)\TIT31811_824 U QH F_DO_EFLA(A,1)\Cond_ON2
OUT_MAX MAXIMUM VALUE OF INx 26.0 U_HL QHN IN3 INPUT 3
0.0 HYS U_HL_O F_DO_ESA(A,3)\30
0 SUBS_IN HYS_O S SET
F_DO_ESA(A,3)\26
IN INPUT
F_DO_MOTORI(A,2)\Loop2_11_12
I11 IN1 INPUT 1
F_LIM_LL F_DO_VALVOLE(A,1)\Loop2_11_12
F_:Limit CYC_INT5
9/3 IN1 INPUT 1
U QL F_DO_EFLA(A,1)\Cond_ON2
17.0 U_LL QLN IN4 INPUT 4
0.0 HYS U_LL_O F_DO_ESA(A,3)\24
0 SUBS_IN HYS_O S SET
F_DO_ESA(A,3)\32
IN INPUT
F_DO_MOTORI(A,2)\Loop2_11_12
All1 IN2 INPUT 2
F_LIM_HL F_DO_VALVOLE(A,1)\Loop2_11_12
F_:Limit CYC_INT5
9/5 IN2 INPUT 2
U QH F_DO_EFLA(A,1)\Cond_ON3
27.0 U_HL QHN IN1 INPUT 1
0.0 HYS U_HL_O F_DO_ESA(A,6)\Con_ON_NOT_ACK1
0 SUBS_IN HYS_O IN1 INPUT 1

All2
F_LIM_LL
F_:Limit CYC_INT5
9/2
Loop 2(A,1)\TIT31811_824 U QL F_DO_EFLA(A,1)\Cond_ON3
OUT_MIN MINIMUM VALUE OF INx 16.0 U_LL QLN IN2 INPUT 2
0.0 HYS U_LL_O F_DO_ESA(A,6)\Con_ON_NOT_ACK1
0 SUBS_IN HYS_O G70 - Kemira - GAA Project IN2 INPUT 2
LOOP 2
Blocchi:I9, I10, I11 e I12
G70 Kemira\PLC Acido Acrilico\CPU 412-5 H PN/DP A\S7 Program(4)\Charts\\Loop 2 Author: modula
G70 - GAA Project Created on:: 16/03/2017 12:03
Last change: 21/03/2017 17:05
Partit.: A Sh.: 2 Number of pages: 3

Page 3 of 3
SIMATIC 03/21/2017 05:10:00 PM

TIT31

1
including rights created by patent grant or registration of a utility model or design, reserved.

2
The reproduction, transmission or use of this document or its contents is not permitted

3
without express written authority. Offenders will be liable for damages. All rights,

All1

All2

All3

All4

I14

I13

G70 Kemira\PLC Acido Acrilico\CPU 412-5 H PN/DP A\S7 Program(4)\Charts\\Loop 3 Author: modula
G70 - GAA Project Created on:: 16/03/2017 12:03
Last change: 21/03/2017 17:06
Partit.: A Overview Number of pages: 3

Page 1 of 3
SIMATIC 03/21/2017 05:10:00 PM

TIT31806_825
F_1oo2AI
F_:1oo2 CYC_INT5
10/1
0.5 DELTA OUT_AVG
1s DIS_TIME OUT_MAX Loop 3(A,2)\All3
IN1 OUT_MIN U INPUT
F_AI(A,4)\TIT-31806 IN2 QBAD_1CH Loop 3(A,2)\I14
including rights created by patent grant or registration of a utility model or design, reserved.

V PROCESS VALUE QBAD1 QBAD_ALL U INPUT

F_AI(A,4)\TIT-31825 QBAD2 DIS Loop 3(A,2)\All1
V PROCESS VALUE 21.5 SUBS_V DIS_D U INPUT
F_AI(A,4)\TIT-31806 0 ACK_NEC ACK_REQ Loop 3(A,2)\I13
The reproduction, transmission or use of this document or its contents is not permitted

QBAD 1=PROCESS VALUE INVALID 0 ACK U INPUT

F_AI(A,4)\TIT-31825 Loop 3(A,2)\All2
without express written authority. Offenders will be liable for damages. All rights,

QBAD 1=PROCESS VALUE INVALID U INPUT

Loop 3(A,2)\All4
U INPUT

1
F_FBO_BO
F_BOOL t CYC_INT5
11/-
IN OUT "Interscambio_Tag".QBAD_1CH_BL_I13_14 DB30.

2
F_FBO_BO
F_BOOL t CYC_INT5
13/-
IN OUT "Interscambio_Tag".QBAD_ALL_BL_I13_14 DB30.

3
F_FBO_BO
F_BOOL t CYC_INT5
12/-
IN OUT "Interscambio_Tag".DIS_BL_I13_14 DB30.DIS_B

G70 - Kemira - GAA Project

LOOP 3
Blocchi: I13, I14

G70 Kemira\PLC Acido Acrilico\CPU 412-5 H PN/DP A\S7 Program(4)\Charts\\Loop 3 Author: modula
G70 - GAA Project Created on:: 16/03/2017 12:03
Last change: 21/03/2017 17:06
Partit.: A Sh.: 1 Number of pages: 3

Page 2 of 3
SIMATIC 03/21/2017 05:10:00 PM

All1
F_LIM_HL
F_:Limit CYC_INT5
10/5
U QH F_DO_EFLA(A,1)\Cond_ON3
23.0 U_HL QHN IN3 INPUT 3
0.0 HYS U_HL_O F_DO_ESA(A,3)\42
0 SUBS_IN HYS_O S SET
F_DO_ESA(A,3)\44
including rights created by patent grant or registration of a utility model or design, reserved.

IN INPUT

All2
F_LIM_LL
The reproduction, transmission or use of this document or its contents is not permitted

F_:Limit CYC_INT5
without express written authority. Offenders will be liable for damages. All rights,

10/2
U QL
20.0 U_LL QLN F_DO_EFLA(A,1)\Cond_ON3
0.0 HYS U_LL_O IN4 INPUT 4
0 SUBS_IN HYS_O F_DO_ESA(A,4)\50
S SET
F_DO_ESA(A,4)\46
IN INPUT
All3
F_LIM_HL
F_:Limit CYC_INT5
10/6
U QH
Loop 3(A,1)\TIT31806_825 25.0 U_HL QHN F_DO_EFLA(A,1)\Cond_ON4
OUT_MAX MAXIMUM VALUE OF INx 0.0 HYS U_HL_O IN1 INPUT 1
0 SUBS_IN HYS_O F_DO_ESA(A,4)\59
S SET
F_DO_ESA(A,4)\57
IN INPUT
All4
F_LIM_LL
F_:Limit CYC_INT5
10/7
U QL
18.0 U_LL QLN F_DO_EFLA(A,1)\Cond_ON4
0.0 HYS U_LL_O IN2 INPUT 2
0 SUBS_IN HYS_O F_DO_ESA(A,4)\63
S SET
F_DO_ESA(A,4)\61
IN INPUT
I14
F_LIM_HL
F_:Limit CYC_INT5
10/4
U QH
26.0 U_HL QHN F_DO_EFLA(A,1)\Cond_ON4
0.0 HYS U_HL_O IN3 INPUT 3
0 SUBS_IN HYS_O F_DO_ESA(A,6)\Con_ON_NOT_ACK1
IN4 INPUT 4
F_DO_VALVOLE(A,1)\Loop3_13_14
IN1 INPUT 1
I13
F_LIM_LL
F_:Limit CYC_INT5
10/3 F_DO_EFLA(A,1)\Cond_ON4
U QL IN4 INPUT 4
Loop 3(A,1)\TIT31806_825 17.0 U_LL QLN G70 - Kemira - GAA Project F_DO_ESA(A,6)\Con_ON_NOT_ACK1
OUT_MIN MINIMUM VALUE OF INx 0.0 HYS U_LL_O LOOP 3 IN3 INPUT 3
Blocchi: I13, I14
0 SUBS_IN HYS_O F_DO_VALVOLE(A,1)\Loop3_13_14
IN2 INPUT 2
G70 Kemira\PLC Acido Acrilico\CPU 412-5 H PN/DP A\S7 Program(4)\Charts\\Loop 3 Author: modula
G70 - GAA Project Created on:: 16/03/2017 12:03
Last change: 21/03/2017 17:06
Partit.: A Sh.: 2 Number of pages: 3

Page 3 of 3
 The reproduction, transmission or use of this document or its contents is not permitted
without express written authority. Offenders will be liable for damages. All rights,
including rights created by patent grant or registration of a utility model or design, reserved. SIMATIC

Partit.: A
G70 - GAA Project

Overview
TIT31

3
2
1

I15
I16
All2
All1

Author: modula G70 Kemira\PLC Acido Acrilico\CPU 412-5 H PN/DP A\S7 Program(4)\Charts\\Loop 4

Number of pages: 3
Last change: 21/03/2017 17:06
Created on:: 16/03/2017 12:03

Page 1 of 3
03/21/2017 05:10:13 PM
SIMATIC 03/21/2017 05:10:13 PM

TIT31808_826
F_1oo2AI
F_:1oo2 CYC_INT5
14/1
0.5 DELTA OUT_AVG
1s DIS_TIME OUT_MAX Loop 4(A,2)\All1
including rights created by patent grant or registration of a utility model or design, reserved.

IN1 OUT_MIN U INPUT

F_AI(A,5)\TIT-31808 IN2 QBAD_1CH Loop 4(A,2)\I16
V PROCESS VALUE QBAD1 QBAD_ALL U INPUT
F_AI(A,5)\TIT-31826 QBAD2 DIS Loop 4(A,2)\All2
The reproduction, transmission or use of this document or its contents is not permitted

V PROCESS VALUE 21.5 SUBS_V DIS_D U INPUT

F_AI(A,5)\TIT-31808 0 ACK_NEC ACK_REQ Loop 4(A,2)\I15
without express written authority. Offenders will be liable for damages. All rights,

QBAD 1=PROCESS VALUE INVALID 0 ACK U INPUT

F_AI(A,5)\TIT-31826
QBAD 1=PROCESS VALUE INVALID

1
F_FBO_BO
F_BOOL t CYC_INT5
15/-
IN OUT "Interscambio_Tag".QBAD_1CH_BL_I15_16 DB30.

2
F_FBO_BO
F_BOOL t CYC_INT5
17/-
IN OUT "Interscambio_Tag".QBAD_ALL_BL_I15_16 DB30.

3
F_FBO_BO
F_BOOL t CYC_INT5
16/-
IN OUT "Interscambio_Tag".DIS_BL_I15_16 DB30.DIS_B

G70 - Kemira - GAA Project

LOOP 4
Blocchi: I15, I16

G70 Kemira\PLC Acido Acrilico\CPU 412-5 H PN/DP A\S7 Program(4)\Charts\\Loop 4 Author: modula
G70 - GAA Project Created on:: 16/03/2017 12:03
Last change: 21/03/2017 17:06
Partit.: A Sh.: 1 Number of pages: 3

Page 2 of 3
SIMATIC 03/21/2017 05:10:13 PM

All1
F_LIM_HL
F_:Limit CYC_INT5
14/4
Loop 4(A,1)\TIT31808_826 U QH F_DO_EFLA(A,1)\Cond_ON5
OUT_MAX MAXIMUM VALUE OF INx 25.0 U_HL QHN IN1 INPUT 1
0.0 HYS U_HL_O F_DO_ESA(A,5)\66
including rights created by patent grant or registration of a utility model or design, reserved.

0 SUBS_IN HYS_O S SET

F_DO_ESA(A,5)\68
IN INPUT
All2
F_LIM_LL
The reproduction, transmission or use of this document or its contents is not permitted

F_:Limit CYC_INT5
without express written authority. Offenders will be liable for damages. All rights,

14/5
U QL
Loop 4(A,1)\TIT31808_826 19.0 U_LL QLN F_DO_EFLA(A,1)\Cond_ON5
OUT_MIN MINIMUM VALUE OF INx 0.0 HYS U_LL_O IN2 INPUT 2
0 SUBS_IN HYS_O F_DO_ESA(A,6)\71
S SET
F_DO_ESA(A,6)\69
I16 IN INPUT
F_LIM_HL
F_:Limit CYC_INT5
14/3
U QH F_DO_EFLA(A,1)\Cond_ON5
26.0 U_HL QHN IN3 INPUT 3
0.0 HYS U_HL_O F_DO_ESA(A,5)\55
0 SUBS_IN HYS_O S SET
F_DO_ESA(A,5)\53
IN INPUT
I15 F_DO_MOTORI(A,4)\Loop4_15_16
F_LIM_LL IN1 INPUT 1
F_:Limit CYC_INT5
14/2 F_DO_VALVOLE(A,2)\Loop4_15_16
U QL IN1 INPUT 1
17.0 U_LL QLN F_DO_EFLA(A,1)\Cond_ON5
0.0 HYS U_LL_O IN4 INPUT 4
0 SUBS_IN HYS_O F_DO_ESA(A,5)\45
S SET
F_DO_ESA(A,5)\51
IN INPUT
F_DO_MOTORI(A,4)\Loop4_15_16
IN2 INPUT 2
F_DO_VALVOLE(A,2)\Loop4_15_16
IN2 INPUT 2

G70 - Kemira - GAA Project

LOOP 4
Blocchi: I15, I16

G70 Kemira\PLC Acido Acrilico\CPU 412-5 H PN/DP A\S7 Program(4)\Charts\\Loop 4 Author: modula
G70 - GAA Project Created on:: 16/03/2017 12:03
Last change: 21/03/2017 17:06
Partit.: A Sh.: 2 Number of pages: 3

Page 3 of 3
SIMATIC 03/21/2017 05:08:54 PM

CV-38 CV-38

11 OpenC ClosC

Loop1
including rights created by patent grant or registration of a utility model or design, reserved.

14
OpenC
Loop2
ClosC
The reproduction, transmission or use of this document or its contents is not permitted
without express written authority. Offenders will be liable for damages. All rights,

Loop2

Loop3

CV-38 FV-33

12 OpenC ClosC

Loop4

CV-38
SET_F 6

Close 10

Close 9
13

OpenC

ClosC

G70 Kemira\PLC Acido Acrilico\CPU 412-5 H PN/DP A\S7 Program(4)\Charts\\F_DO_VALVOLE Author: modula
G70 - GAA Project Created on:: 8/03/2017 15:50
Last change: 21/03/2017 17:05
Partit.: A Overview Number of pages: 7

Page 1 of 7
SIMATIC 03/21/2017 05:08:54 PM

CV-38800
F_CH_DO
F_:Fail- CYC_INT5
18/20
CHADDR PASS_OUT
@F_(1)(A,2)\FDO10xDC24V_2A_1 CHADDR_R QBAD
CHADDRO00 ADDRESS OUTPUT PROCESS DATA BYTE CH_INF QSIM
@F_(1)(A,3)\FDO10xDC24V_2A_2 CH_INF_R VALUE "EV-38800/D" Q8.0
including rights created by patent grant or registration of a utility model or design, reserved.

CHADDRO00 ADDRESS OUTPUT PROCESS DATA BYTE I QUALITY Cmd. valvola CV-38800/D intercetto acqua te
@F_(1)(A,2)\FDO10xDC24V_2A_1 0 SIM_I ACK_REQ
CHADDRI00 ADDRESS INPUT PROCESS DATA BYTE 0 SIM_MOD
@F_(1)(A,3)\FDO10xDC24V_2A_2 0 SIM_ON
The reproduction, transmission or use of this document or its contents is not permitted

CHADDRI00 ADDRESS INPUT PROCESS DATA BYTE 0 PASS_ON

0 ACK_NEC
without express written authority. Offenders will be liable for damages. All rights,

ACK_REI
F_DO_SPARE(A,2)\Ack_Passivation
OUT OUTPUT 11 OpenCond_CV38800 ClosCond_CV38800
F_BO_FBO F_OR4 F_AND4
F_:BOOL CYC_INT5 F_:OR 4 CYC_INT5 F_:AND 4 CYC_INT5
5/5 18/7 18/16
"Interscambio_Tag".Open_CV38800 DB30.Open_C IN OUT IN1 OUT IN1 OUT
IN2 OUTN IN2 OUTN
0 IN3 IN3
0 IN4 IN4

Loop1_5_6_7_8
F_OR4
F_:OR 4 CYC_INT5
18/10
Loop 1(A,1)\I6 IN1 OUT F_DO_VALVOLE(A,3)\OpenCond_CV38811
QH OUTPUT IN2 OUTN IN2 INPUT 2
Loop 1(A,1)\I5 IN3 F_DO_VALVOLE(A,6)\SET_FIC
QL OUTPUT IN4 IN1 INPUT 1
Loop 1(A,2)\I8
QH OUTPUT
Loop 1(A,2)\I7 Loop2_9_10
QL OUTPUT F_OR4
F_:OR 4 CYC_INT5
18/11
IN1 OUT
Loop 2(A,2)\I10 IN2 OUTN F_DO_VALVOLE(A,3)\OpenCond_CV38811
QH OUTPUT 0 IN3 IN3 INPUT 3
Loop 2(A,2)\I9 0 IN4 F_DO_VALVOLE(A,6)\SET_FIC
QL OUTPUT IN2 INPUT 2

Loop2_11_12
F_OR4
F_:OR 4 CYC_INT5
18/14
Loop 2(A,2)\I12 IN1 OUT F_DO_VALVOLE(A,3)\OpenCond_CV38811
QH OUTPUT IN2 OUTN IN4 INPUT 4
Loop 2(A,2)\I11 0 IN3
QL OUTPUT 0 IN4

Loop3_13_14
F_OR4
F_:OR 4 CYC_INT5
18/15
IN1 OUT
Loop 3(A,2)\I14 IN2 OUTN F_DO_VALVOLE(A,4)\ClosCond_CV38813
QH OUTPUT 0 IN3 IN2 INPUT 2
Loop 3(A,2)\I13 0 IN4 F_DO_VALVOLE(A,3)\ClosCond_CV38811
QL OUTPUT IN2 INPUT 2
G70 Kemira\PLC Acido Acrilico\CPU 412-5 H PN/DP A\S7 Program(4)\Charts\\F_DO_VALVOLE Author: modula
G70 - GAA Project Created on:: 8/03/2017 15:50
Last change: 21/03/2017 17:05
Partit.: A Sh.: 1 Number of pages: 7

Page 2 of 7
SIMATIC 03/21/2017 05:08:55 PM

CV-38809
F_CH_DO
F_:Fail- CYC_INT5
18/19
@F_(1)(A,2)\FDO10xDC24V_2A_1 CHADDR PASS_OUT
CHADDRO00 ADDRESS OUTPUT PROCESS DATA BYTE CHADDR_R QBAD
@F_(1)(A,3)\FDO10xDC24V_2A_2 CH_INF QSIM
including rights created by patent grant or registration of a utility model or design, reserved.

CHADDRO00 ADDRESS OUTPUT PROCESS DATA BYTE CH_INF_R VALUE

@F_(1)(A,2)\FDO10xDC24V_2A_1 I QUALITY "EV-38809/D" Q8.1
CHADDRI00 ADDRESS INPUT PROCESS DATA BYTE 0 SIM_I ACK_REQ Cmd. valvola CV-38809/D intercetto mandata
@F_(1)(A,3)\FDO10xDC24V_2A_2 0 SIM_MOD
The reproduction, transmission or use of this document or its contents is not permitted

CHADDRI00 ADDRESS INPUT PROCESS DATA BYTE 0 SIM_ON

0 PASS_ON
without express written authority. Offenders will be liable for damages. All rights,

0 ACK_NEC
F_DO_SPARE(A,2)\Ack_Passivation ACK_REI
OUT OUTPUT

12 OpenCond_CV38809 ClosCond_CV38809
F_BO_FBO F_OR4 F_AND4
F_:BOOL CYC_INT5 F_:OR 4 CYC_INT5 F_:AND 4 CYC_INT5
5/2 18/4 18/3
"Interscambio_Tag".Open_CV38809 DB30.Open_C IN OUT IN1 OUT IN1 OUT
0 IN2 OUTN IN2 OUTN
0 IN3 1 IN3
0 IN4 1 IN4

Loop4_15_16
F_OR4
F_:OR 4 CYC_INT5
18/12
Loop 4(A,2)\I16 IN1 OUT
QH OUTPUT IN2 OUTN
Loop 4(A,2)\I15 0 IN3
QL OUTPUT 0 IN4

G70 Kemira\PLC Acido Acrilico\CPU 412-5 H PN/DP A\S7 Program(4)\Charts\\F_DO_VALVOLE Author: modula
G70 - GAA Project Created on:: 8/03/2017 15:50
Last change: 21/03/2017 17:05
Partit.: A Sh.: 2 Number of pages: 7

Page 3 of 7
SIMATIC 03/21/2017 05:08:55 PM

CV-38811
F_CH_DO
F_:Fail- CYC_INT5
18/21
@F_(1)(A,2)\FDO10xDC24V_2A_1 CHADDR PASS_OUT
CHADDRO00 ADDRESS OUTPUT PROCESS DATA BYTE CHADDR_R QBAD
@F_(1)(A,3)\FDO10xDC24V_2A_2 CH_INF QSIM
CHADDRO00 ADDRESS OUTPUT PROCESS DATA BYTE CH_INF_R VALUE
@F_(1)(A,2)\FDO10xDC24V_2A_1 I QUALITY "EV-38811/D" Q8.2
including rights created by patent grant or registration of a utility model or design, reserved.

CHADDRI00 ADDRESS INPUT PROCESS DATA BYTE 0 SIM_I ACK_REQ Cmd. valvola CV-38811/D intercetto acqua te
@F_(1)(A,3)\FDO10xDC24V_2A_2 0 SIM_MOD
CHADDRI00 ADDRESS INPUT PROCESS DATA BYTE 0 SIM_ON
0 PASS_ON
The reproduction, transmission or use of this document or its contents is not permitted

0 ACK_NEC
F_DO_SPARE(A,2)\Ack_Passivation ACK_REI
without express written authority. Offenders will be liable for damages. All rights,

OUT OUTPUT

13
F_BO_FBO
F_:BOOL CYC_INT5
5/4
"Interscambio_Tag".Open_CV38811 DB30.Open_C IN OUT

OpenCond_CV38811
F_OR4
F_:OR 4 CYC_INT5
18/9
IN1 OUT
F_DO_VALVOLE(A,1)\Loop1_5_6_7_8 IN2 OUTN
OUT OUTPUT IN3
F_DO_VALVOLE(A,1)\Loop2_11_12 IN4
OUT OUTPUT
F_DO_VALVOLE(A,1)\Loop2_9_10 ClosCond_CV38811
OUT OUTPUT F_AND4
F_:AND 4 CYC_INT5
18/8
IN1 OUT
F_DO_VALVOLE(A,1)\Loop3_13_14 IN2 OUTN
OUTN NEGATING OUTPUT 1 IN3
1 IN4

G70 Kemira\PLC Acido Acrilico\CPU 412-5 H PN/DP A\S7 Program(4)\Charts\\F_DO_VALVOLE Author: modula
G70 - GAA Project Created on:: 8/03/2017 15:50
Last change: 21/03/2017 17:05
Partit.: A Sh.: 3 Number of pages: 7

Page 4 of 7
SIMATIC 03/21/2017 05:08:55 PM

CV-38813
F_CH_DO
F_:Fail- CYC_INT5
18/17
CHADDR PASS_OUT
@F_(1)(A,2)\FDO10xDC24V_2A_1 CHADDR_R QBAD
CHADDRO00 ADDRESS OUTPUT PROCESS DATA BYTE CH_INF QSIM
@F_(1)(A,3)\FDO10xDC24V_2A_2 CH_INF_R VALUE "EV-38813/D" Q8.3
including rights created by patent grant or registration of a utility model or design, reserved.

CHADDRO00 ADDRESS OUTPUT PROCESS DATA BYTE I QUALITY Cmd. valvola CV-38813/D intercetto ricircol
@F_(1)(A,2)\FDO10xDC24V_2A_1 0 SIM_I ACK_REQ
CHADDRI00 ADDRESS INPUT PROCESS DATA BYTE 0 SIM_MOD
@F_(1)(A,3)\FDO10xDC24V_2A_2 0 SIM_ON
The reproduction, transmission or use of this document or its contents is not permitted

CHADDRI00 ADDRESS INPUT PROCESS DATA BYTE 0 PASS_ON

0 ACK_NEC
without express written authority. Offenders will be liable for damages. All rights,

ACK_REI
F_DO_SPARE(A,2)\Ack_Passivation
OUT OUTPUT

14
F_BO_FBO
F_:BOOL CYC_INT5
5/3
"Interscambio_Tag".Open_CV38811 DB30.Open_C IN OUT OpenCond_CV38813
F_OR4
F_:OR 4 CYC_INT5
18/2
IN1 OUT
0 IN2 OUTN ClosCond_CV38813
0 IN3 F_AND4
0 IN4 F_:AND 4 CYC_INT5
18/1
IN1 OUT
F_DO_VALVOLE(A,1)\Loop3_13_14 IN2 OUTN
OUT OUTPUT 1 IN3
1 IN4

G70 Kemira\PLC Acido Acrilico\CPU 412-5 H PN/DP A\S7 Program(4)\Charts\\F_DO_VALVOLE Author: modula
G70 - GAA Project Created on:: 8/03/2017 15:50
Last change: 21/03/2017 17:05
Partit.: A Sh.: 4 Number of pages: 7

Page 5 of 7
SIMATIC 03/21/2017 05:08:55 PM

FV-33800
F_CH_DO
F_:Fail- CYC_INT5
18/18
@F_(1)(A,2)\FDO10xDC24V_2A_1 CHADDR PASS_OUT
CHADDRO00 ADDRESS OUTPUT PROCESS DATA BYTE CHADDR_R QBAD
@F_(1)(A,3)\FDO10xDC24V_2A_2 CH_INF QSIM
including rights created by patent grant or registration of a utility model or design, reserved.

CHADDRO00 ADDRESS OUTPUT PROCESS DATA BYTE CH_INF_R VALUE

@F_(1)(A,2)\FDO10xDC24V_2A_1 0 I QUALITY "EV-33800/D" Q8.4
CHADDRI00 ADDRESS INPUT PROCESS DATA BYTE 0 SIM_I ACK_REQ Cmd. apertura fissa valvola di regolazione
@F_(1)(A,3)\FDO10xDC24V_2A_2 0 SIM_MOD
The reproduction, transmission or use of this document or its contents is not permitted

CHADDRI00 ADDRESS INPUT PROCESS DATA BYTE 0 SIM_ON

0 PASS_ON
without express written authority. Offenders will be liable for damages. All rights,

0 ACK_NEC
F_DO_SPARE(A,2)\Ack_Passivation ACK_REI
OUT OUTPUT

G70 Kemira\PLC Acido Acrilico\CPU 412-5 H PN/DP A\S7 Program(4)\Charts\\F_DO_VALVOLE Author: modula
G70 - GAA Project Created on:: 8/03/2017 15:50
Last change: 21/03/2017 17:05
Partit.: A Sh.: 5 Number of pages: 7

Page 6 of 7
SIMATIC 03/21/2017 05:08:55 PM

SET_FIC 6
F_OR4 F_FBO_BO
F_:OR 4 CYC_INT5 F_BOOL t CYC_INT5
18/13 27/1
F_DO_VALVOLE(A,1)\Loop1_5_6_7_8 IN1 OUT IN OUT "Interscambio_Tag".FIC33800_SET_DIFF_10m3h
OUT OUTPUT IN2 OUTN
F_DO_VALVOLE(A,1)\Loop2_9_10 0 IN3
including rights created by patent grant or registration of a utility model or design, reserved.

OUT OUTPUT 0 IN4

The reproduction, transmission or use of this document or its contents is not permitted
without express written authority. Offenders will be liable for damages. All rights,

Close_TV31800 10
F_OR4 F_FBO_BO
F_:OR 4 CYC_INT5 F_BOOL t CYC_INT5
18/6 27/2
Loop 1(A,1)\I6 IN1 OUT IN OUT "Interscambio_Tag".Close_TV31800 DB30.Close
QH OUTPUT IN2 OUTN
Loop 1(A,2)\I8 0 IN3
QH OUTPUT 0 IN4

Close_TV31801 9
F_OR4 F_FBO_BO
F_:OR 4 CYC_INT5 F_BOOL t CYC_INT5
18/5 27/3
Loop 1(A,1)\I5 IN1 OUT IN OUT "Interscambio_Tag".Close_TV31801 DB30.Close
QL OUTPUT IN2 OUTN
Loop 1(A,2)\I7 0 IN3
QL OUTPUT 0 IN4

G70 Kemira\PLC Acido Acrilico\CPU 412-5 H PN/DP A\S7 Program(4)\Charts\\F_DO_VALVOLE Author: modula
G70 - GAA Project Created on:: 8/03/2017 15:50
Last change: 21/03/2017 17:05
Partit.: A Sh.: 6 Number of pages: 7

Page 7 of 7
SIMATIC 03/21/2017 05:08:27 PM

P392_ P394_
START Start StopC

5 Start Loop4
P392_
P394_
StopC
including rights created by patent grant or registration of a utility model or design, reserved.

8
The reproduction, transmission or use of this document or its contents is not permitted

P392_
10
without express written authority. Offenders will be liable for damages. All rights,

Loop2 9 Start

Loop2

START

START Start

P392A

P392A

P392B

P392B

G70 Kemira\PLC Acido Acrilico\CPU 412-5 H PN/DP A\S7 Program(4)\Charts\\F_DO_MOTORI Author: modula
G70 - GAA Project Created on:: 16/03/2017 14:56
Last change: 21/03/2017 17:05
Partit.: A Overview Number of pages: 5

Page 1 of 5
SIMATIC 03/21/2017 05:08:27 PM

P392_1
F_CH_DO
F_:Fail- CYC_INT5
19/16
CHADDR PASS_OUT
@F_(1)(A,2)\FDO10xDC24V_2A_1 CHADDR_R QBAD
CHADDRO00 ADDRESS OUTPUT PROCESS DATA BYTE CH_INF QSIM
@F_(1)(A,3)\FDO10xDC24V_2A_2 CH_INF_R VALUE "HC-P392-1" Q8.7
including rights created by patent grant or registration of a utility model or design, reserved.

CHADDRO00 ADDRESS OUTPUT PROCESS DATA BYTE I QUALITY Pompa P392 - Cmd. START KM1
@F_(1)(A,2)\FDO10xDC24V_2A_1 0 SIM_I ACK_REQ
CHADDRI00 ADDRESS INPUT PROCESS DATA BYTE 0 SIM_MOD
@F_(1)(A,3)\FDO10xDC24V_2A_2 0 SIM_ON
The reproduction, transmission or use of this document or its contents is not permitted

CHADDRI00 ADDRESS INPUT PROCESS DATA BYTE 0 PASS_ON

0 ACK_NEC
without express written authority. Offenders will be liable for damages. All rights,

5 StartCond_P392 ACK_REI
F_BO_FBO F_OR4
F_:BOOL CYC_INT5 F_:OR 4 CYC_INT5
5/8 5/16
"Interscambio_Tag".P392_START DB30.P392_STA IN OUT IN1 OUT P392_2
0 IN2 OUTN F_CH_DO
F_:Fail- CYC_INT5
0 IN3 19/8
0 IN4 CHADDR PASS_OUT
StopCond_P392 CHADDR_R QBAD
F_AND4 CH_INF QSIM
F_:AND 4 CYC_INT5 CH_INF_R VALUE "HC-P392-2" Q9.0
5/18
IN1 OUT I QUALITY Pompa P392 - Cmd. START KM2
Loop 1(A,4)\LALL 30800_1 IN2 OUTN 0 SIM_I ACK_REQ
QLN NEGATED OUTPUT 1 IN3 0 SIM_MOD
1 IN4 0 SIM_ON
0 PASS_ON
0 ACK_NEC
ACK_REI

P392_VFD
F_CH_DO
F_:Fail- CYC_INT5
19/9
CHADDR PASS_OUT
@F_(1)(A,2)\FDO10xDC24V_2A_1 CHADDR_R QBAD
CHADDRO01 ADDRESS OUTPUT PROCESS DATA BYTE CH_INF QSIM
@F_(1)(A,3)\FDO10xDC24V_2A_2 CH_INF_R VALUE "HC-P392-3" Q9.1
CHADDRO01 ADDRESS OUTPUT PROCESS DATA BYTE I QUALITY Pompa P392 - Cmd. START VFD
@F_(1)(A,2)\FDO10xDC24V_2A_1 0 SIM_I ACK_REQ
CHADDRI01 ADDRESS INPUT PROCESS DATA BYTE 0 SIM_MOD
@F_(1)(A,3)\FDO10xDC24V_2A_2 0 SIM_ON
CHADDRI01 ADDRESS INPUT PROCESS DATA BYTE 0 PASS_ON
0 ACK_NEC
ACK_REI
F_DO_SPARE(A,2)\Ack_Passivation
OUT OUTPUT
G70 - Kemira - GAA Project
- P392

G70 Kemira\PLC Acido Acrilico\CPU 412-5 H PN/DP A\S7 Program(4)\Charts\\F_DO_MOTORI Author: modula
G70 - GAA Project Created on:: 16/03/2017 14:56
Last change: 21/03/2017 17:05
Partit.: A Sh.: 1 Number of pages: 5

Page 2 of 5
SIMATIC 03/21/2017 05:08:27 PM

Loop2_11_12 9 StartCond_P392A
F_OR4 F_SR_FF F_OR4
F_:OR 4 CYC_INT5 F_:SR-Fl CYC_INT5 F_:OR 4 CYC_INT5
19/1 19/2 19/7
Loop 2(A,2)\I12 IN1 OUT S Q IN1 OUT F_DO_MOTORI(A,3)\P392A_2
QH OUTPUT IN2 OUTN R QN IN2 OUTN I PROCESS VALUE
Loop 2(A,2)\I11 0 IN3 0 IN3 F_DO_MOTORI(A,3)\P392A_1
QL OUTPUT 0 IN4 0 IN4 I PROCESS VALUE
including rights created by patent grant or registration of a utility model or design, reserved.

Loop2_09_10
F_OR4
F_:OR 4 CYC_INT5
The reproduction, transmission or use of this document or its contents is not permitted

19/6
Loop 2(A,2)\I10 IN1 OUT
without express written authority. Offenders will be liable for damages. All rights,

QHN NEGATED OUTPUT IN2 OUTN

Loop 2(A,2)\I9 0 IN3
QLN NEGATED OUTPUT 0 IN4

START_P392A
F_BO_FBO
F_:BOOL CYC_INT5
5/7
"Interscambio_Tag".P392A_START DB30.P392A_S IN OUT

StartCond_P392B
START_P392B F_OR4
F_:OR 4 CYC_INT5
F_BO_FBO
CYC_INT5 19/5
F_:BOOL IN1 OUT
5/6
"Interscambio_Tag".P392B_START DB30.P392B_S IN OUT IN2 OUTN F_DO_MOTORI(A,3)\P392B_2
0 IN3 I PROCESS VALUE
0 IN4 F_DO_MOTORI(A,3)\P392B_1
I PROCESS VALUE

G70 - Kemira - GAA Project

- P392A/B

G70 Kemira\PLC Acido Acrilico\CPU 412-5 H PN/DP A\S7 Program(4)\Charts\\F_DO_MOTORI Author: modula
G70 - GAA Project Created on:: 16/03/2017 14:56
Last change: 21/03/2017 17:05
Partit.: A Sh.: 2 Number of pages: 5

Page 3 of 5
SIMATIC 03/21/2017 05:08:27 PM

P392A_1
F_CH_DO
F_:Fail- CYC_INT5
19/15
CHADDR PASS_OUT
CHADDR_R QBAD
CH_INF QSIM
CH_INF_R VALUE "HC-P392A-1" Q14.0
including rights created by patent grant or registration of a utility model or design, reserved.

I QUALITY Pompa P392A - Cmd. START KM1

0 SIM_I ACK_REQ
0 SIM_MOD
0 SIM_ON
The reproduction, transmission or use of this document or its contents is not permitted

0 PASS_ON
0 ACK_NEC
without express written authority. Offenders will be liable for damages. All rights,

ACK_REI P392A_2
F_CH_DO
F_:Fail- CYC_INT5
19/10
CHADDR PASS_OUT
CHADDR_R QBAD
CH_INF QSIM
CH_INF_R VALUE
F_DO_MOTORI(A,2)\StartCond_P392A I QUALITY "HC-P392A-2" Q14.1
OUT OUTPUT 0 SIM_I ACK_REQ Pompa P392A - Cmd. START KM2
0 SIM_MOD
0 SIM_ON
0 PASS_ON
0 ACK_NEC
ACK_REI
P392B_1
F_CH_DO
F_:Fail- CYC_INT5
19/17
@F_(1)(A,5)\FDO10xDC24V_2A_3 CHADDR PASS_OUT
CHADDRO00 ADDRESS OUTPUT PROCESS DATA BYTE CHADDR_R QBAD
@F_(1)(A,6)\FDO10xDC24V_2A_4 CH_INF QSIM
CHADDRO00 ADDRESS OUTPUT PROCESS DATA BYTE CH_INF_R VALUE
@F_(1)(A,5)\FDO10xDC24V_2A_3 I QUALITY "HC-P392B-1" Q14.2
CHADDRI00 ADDRESS INPUT PROCESS DATA BYTE 0 SIM_I ACK_REQ Pompa P392B - Cmd. START KM1
@F_(1)(A,6)\FDO10xDC24V_2A_4 0 SIM_MOD
CHADDRI00 ADDRESS INPUT PROCESS DATA BYTE 0 SIM_ON
0 PASS_ON
0 ACK_NEC
F_DO_SPARE(A,2)\Ack_Passivation ACK_REI
OUT OUTPUT
P392B_2
F_CH_DO
F_:Fail- CYC_INT5
19/14
CHADDR PASS_OUT
CHADDR_R QBAD
CH_INF QSIM
CH_INF_R VALUE "HC-P392B-2" Q14.3
I QUALITY Pompa P392B - Cmd. START KM2
F_DO_MOTORI(A,2)\StartCond_P392B 0 SIM_I ACK_REQ
OUT OUTPUT 0 SIM_MOD
0 SIM_ON
0 PASS_ON
G70 - Kemira - GAA Project 0 ACK_NEC
- P392A/B ACK_REI

G70 Kemira\PLC Acido Acrilico\CPU 412-5 H PN/DP A\S7 Program(4)\Charts\\F_DO_MOTORI Author: modula
G70 - GAA Project Created on:: 16/03/2017 14:56
Last change: 21/03/2017 17:05
Partit.: A Sh.: 3 Number of pages: 5

Page 4 of 5
SIMATIC 03/21/2017 05:08:27 PM

P394_1
F_CH_DO
F_:Fail- CYC_INT5
19/13
CHADDR PASS_OUT
START_P394 StartCond_P394 StopCond_394 CHADDR_R QBAD
F_BO_FBO F_OR4 F_AND4 CH_INF QSIM
F_:BOOL CYC_INT5 F_:OR 4 CYC_INT5 F_:AND 4 CYC_INT5
5/9 5/17 19/3 CH_INF_R VALUE "HC-P394-1" Q14.4
including rights created by patent grant or registration of a utility model or design, reserved.

IN OUT IN1 OUT IN1 OUT I QUALITY Pompa P394 - Cmd. START KM1
"Interscambio_Tag".P394_START DB30.P394_STA 0 IN2 OUTN IN2 OUTN 0 SIM_I ACK_REQ
0 IN3 1 IN3 0 SIM_MOD
0 IN4 1 IN4 0 SIM_ON
The reproduction, transmission or use of this document or its contents is not permitted

0 PASS_ON
Loop4_15_16 0 ACK_NEC
without express written authority. Offenders will be liable for damages. All rights,

F_OR4 ACK_REI
F_:OR 4 CYC_INT5
19/4
IN1 OUT
Loop 4(A,2)\I16 IN2 OUTN
QH OUTPUT 0 IN3
Loop 4(A,2)\I15 0 IN4 P394_2
QL OUTPUT F_CH_DO
F_:Fail- CYC_INT5
19/11
CHADDR PASS_OUT
@F_(1)(A,5)\FDO10xDC24V_2A_3 CHADDR_R QBAD
CHADDRO00 ADDRESS OUTPUT PROCESS DATA BYTE CH_INF QSIM
@F_(1)(A,6)\FDO10xDC24V_2A_4 CH_INF_R VALUE "HC-P394-2" Q14.5
CHADDRO00 ADDRESS OUTPUT PROCESS DATA BYTE I QUALITY Pompa P394 - Cmd. START KM2
@F_(1)(A,5)\FDO10xDC24V_2A_3 0 SIM_I ACK_REQ
CHADDRI00 ADDRESS INPUT PROCESS DATA BYTE 0 SIM_MOD
@F_(1)(A,6)\FDO10xDC24V_2A_4 0 SIM_ON
CHADDRI00 ADDRESS INPUT PROCESS DATA BYTE 0 PASS_ON
0 ACK_NEC
ACK_REI
F_DO_SPARE(A,2)\Ack_Passivation
OUT OUTPUT

8
F_CH_DO
F_:Fail- CYC_INT5
19/12
CHADDR PASS_OUT
10 CHADDR_R QBAD
F_BO_FBO CH_INF QSIM
F_:BOOL CYC_INT5
5/10 CH_INF_R VALUE "ZC-P394" Q14.6
IN OUT I QUALITY Pompa P394 - Consenso all’avviamento pompa
"HS-38400/D" I7.0 0 SIM_I ACK_REQ
Verifica di connessione di messa a terra ta 0 SIM_MOD
0 SIM_ON
0 PASS_ON
0 ACK_NEC
ACK_REI

G70 - Kemira - GAA Project

- P394

G70 Kemira\PLC Acido Acrilico\CPU 412-5 H PN/DP A\S7 Program(4)\Charts\\F_DO_MOTORI Author: modula
G70 - GAA Project Created on:: 16/03/2017 14:56
Last change: 21/03/2017 17:05
Partit.: A Sh.: 4 Number of pages: 5

Page 5 of 5
SIMATIC 03/21/2017 05:07:05 PM

Cond_ Cond_ Cond_

Cond_

Cond_
including rights created by patent grant or registration of a utility model or design, reserved.

Cond_

Cond_
The reproduction, transmission or use of this document or its contents is not permitted
without express written authority. Offenders will be liable for damages. All rights,

Cond_

EFLA-

G70 Kemira\PLC Acido Acrilico\CPU 412-5 H PN/DP A\S7 Program(4)\Charts\\F_DO_EFLA Author: modula
G70 - GAA Project Created on:: 21/03/2017 15:00
Last change: 21/03/2017 17:06
Partit.: A Overview Number of pages: 3

Page 1 of 3
SIMATIC 03/21/2017 05:07:05 PM

Cond_ON Cond_ON6 Cond_ON7

F_OR4 F_OR4 F_OR4
F_:OR 4 CYC_INT5 F_:OR 4 CYC_INT5 F_:OR 4 CYC_INT5
21/2 21/4 21/3
IN1 OUT IN1 OUT IN1 OUT
Loop 1(A,1)\I6 IN2 OUTN IN2 OUTN IN2 OUTN F_DO_EFLA(A,2)\EFLA-3980-1
QH OUTPUT IN3 IN3 IN3 I PROCESS VALUE
Loop 1(A,1)\I5 IN4 IN4 0 IN4
including rights created by patent grant or registration of a utility model or design, reserved.

QL OUTPUT
Loop 1(A,2)\I8
QH OUTPUT Cond_ON1
Loop 1(A,2)\I7 F_OR4
F_:OR 4 CYC_INT5
The reproduction, transmission or use of this document or its contents is not permitted

QL OUTPUT 21/9
Loop 1(A,3)\All_1 IN1 OUT
without express written authority. Offenders will be liable for damages. All rights,

QH OUTPUT IN2 OUTN

Loop 1(A,3)\All_2 IN3
QL OUTPUT IN4
Loop 1(A,3)\All_3
QH OUTPUT
Loop 1(A,3)\All_4 Cond_ON2
QL OUTPUT F_OR4
F_:OR 4 CYC_INT5
21/8
IN1 OUT
Loop 2(A,2)\I10 IN2 OUTN
QH OUTPUT IN3
Loop 2(A,2)\I9 IN4
QL OUTPUT
Loop 2(A,2)\I12
QH OUTPUT Cond_ON3
Loop 2(A,2)\I11 F_OR4
F_:OR 4 CYC_INT5
QL OUTPUT 21/7
Loop 2(A,2)\All1 IN1 OUT
QH OUTPUT IN2 OUTN
Loop 2(A,2)\All2 IN3
QL OUTPUT IN4
Loop 3(A,2)\All1
QH OUTPUT
Loop 3(A,2)\All2 Cond_ON4
QL OUTPUT F_OR4
F_:OR 4 CYC_INT5
21/6
IN1 OUT
Loop 3(A,2)\All3 IN2 OUTN
QH OUTPUT IN3
Loop 3(A,2)\All4 IN4
QL OUTPUT
Loop 3(A,2)\I14
QH OUTPUT Cond_ON5
Loop 3(A,2)\I13 F_OR4
F_:OR 4 CYC_INT5
QLN NEGATED OUTPUT 21/5
Loop 4(A,2)\All1 IN1 OUT
QH OUTPUT IN2 OUTN
Loop 4(A,2)\All2 IN3
QL OUTPUT IN4
Loop 4(A,2)\I16
QH OUTPUT
Loop 4(A,2)\I15
QL OUTPUT

G70 Kemira\PLC Acido Acrilico\CPU 412-5 H PN/DP A\S7 Program(4)\Charts\\F_DO_EFLA Author: modula
G70 - GAA Project Created on:: 21/03/2017 15:00
Last change: 21/03/2017 17:06
Partit.: A Sh.: 1 Number of pages: 3

Page 2 of 3
SIMATIC 03/21/2017 05:07:05 PM

EFLA-3980-1
F_CH_DO
F_:Fail- CYC_INT5
21/1
@F_(1)(A,5)\FDO10xDC24V_2A_3 CHADDR PASS_OUT
CHADDRO01 ADDRESS OUTPUT PROCESS DATA BYTE CHADDR_R QBAD
@F_(1)(A,6)\FDO10xDC24V_2A_4 CH_INF QSIM
CHADDRO01 ADDRESS OUTPUT PROCESS DATA BYTE CH_INF_R VALUE
F_DO_EFLA(A,1)\Cond_ON7 I QUALITY "EFLA-3980-1/D" Q15.0
including rights created by patent grant or registration of a utility model or design, reserved.

OUT OUTPUT 0 SIM_I ACK_REQ Allarme luminoso 1 e 2 sala controllo

@F_(1)(A,5)\FDO10xDC24V_2A_3 0 SIM_MOD
CHADDRI01 ADDRESS INPUT PROCESS DATA BYTE 0 SIM_ON
@F_(1)(A,6)\FDO10xDC24V_2A_4 0 PASS_ON
The reproduction, transmission or use of this document or its contents is not permitted

CHADDRI01 ADDRESS INPUT PROCESS DATA BYTE 0 ACK_NEC

F_DO_SPARE(A,2)\Ack_Passivation ACK_REI
without express written authority. Offenders will be liable for damages. All rights,

OUT OUTPUT

G70 - Kemira - GAA Project

- Allarme luminoso

G70 Kemira\PLC Acido Acrilico\CPU 412-5 H PN/DP A\S7 Program(4)\Charts\\F_DO_EFLA Author: modula
G70 - GAA Project Created on:: 21/03/2017 15:00
Last change: 21/03/2017 17:06
Partit.: A Sh.: 2 Number of pages: 3

Page 3 of 3
SIMATIC 03/21/2017 05:07:32 PM

ACK 46 49 Con_O
50
14 12
16 52

15
57 60
59
7 9
including rights created by patent grant or registration of a utility model or design, reserved.

10 58

11
61 64
The reproduction, transmission or use of this document or its contents is not permitted

63
22 13
without express written authority. Offenders will be liable for damages. All rights,

28 62

23
Con_O

19 17 51 47
21 45

20 48

39 35
33 53 54
55
36
56

34 37
38 68 67
66
40
65
Con_O Con_O

69 70
32 29 71
24
72
25
ESA-3

26 31
30

27 Con_O Con_O

44 43 Con_O
42

41 Con_O

G70 Kemira\PLC Acido Acrilico\CPU 412-5 H PN/DP A\S7 Program(4)\Charts\\F_DO_ESA Author: modula
G70 - GAA Project Created on:: 16/03/2017 14:58
Last change: 21/03/2017 17:05
Partit.: A Overview Number of pages: 7

Page 1 of 7
SIMATIC 03/21/2017 05:07:32 PM

ACK
F_BO_FBO
F_:BOOL CYC_INT5
5/1
"HS-GPAL-GAL" I42.4 IN OUT F_DO_ESA(A,6)\72
Pulsante tacitazione allarmi da sala contro IN1 INPUT 1
14 12 F_DO_ESA(A,5)\65
including rights created by patent grant or registration of a utility model or design, reserved.

F_NOT F_RS_FF IN1 INPUT 1

F_:Inver CYC_INT5 F_:RS-Fl CYC_INT5
20/69 20/67 F_DO_ESA(A,5)\56
IN OUT R Q 16 IN1 INPUT 1
S QN F_RS_FF F_DO_ESA(A,5)\48
F_:RS-Fl CYC_INT5
The reproduction, transmission or use of this document or its contents is not permitted

20/66 IN1 INPUT 1

R Q F_DO_ESA(A,4)\52
without express written authority. Offenders will be liable for damages. All rights,

S QN IN1 INPUT 1
Loop 1(A,1)\I5 15 F_DO_ESA(A,3)\41
QL OUTPUT F_AND4 IN1 INPUT 1
F_:AND 4 CYC_INT5
20/68 F_DO_ESA(A,2)\40
IN1 OUT IN1 INPUT 1
IN2 OUTN F_DO_ESA(A,2)\36
1 IN3 IN1 INPUT 1
1 IN4 F_DO_ESA(A,3)\25
IN1 INPUT 1
F_DO_ESA(A,3)\27
7 9 IN1 INPUT 1
F_NOT F_RS_FF F_DO_ESA(A,2)\20
F_:Inver CYC_INT5 F_:RS-Fl CYC_INT5
20/73 20/71 IN1 INPUT 1
Loop 1(A,1)\I6 IN OUT R Q 10
QH OUTPUT S QN F_RS_FF
F_:RS-Fl CYC_INT5
20/70
R Q
S QN
11
F_AND4
F_:AND 4 CYC_INT5
20/72
IN1 OUT
IN2 OUTN
1 IN3
1 IN4

22 13
F_NOT F_RS_FF
F_:Inver CYC_INT5 F_:RS-Fl CYC_INT5
20/61 20/59
IN OUT R Q 28
S QN F_RS_FF
F_:RS-Fl CYC_INT5
20/58
R Q
S QN
Loop 1(A,2)\I7 23
QL OUTPUT F_AND4
F_:AND 4 CYC_INT5
20/60 Con_ON_ACK
IN1 OUT F_OR4
F_:OR 4 CYC_INT5
IN2 OUTN 20/2
1 IN3 IN1 OUT
1 IN4 IN2 OUTN F_DO_ESA(A,6)\Con_ON
IN3 IN1 INPUT 1
F_DO_ESA(A,2)\21 IN4
Q OUTPUT
G70 Kemira\PLC Acido Acrilico\CPU 412-5 H PN/DP A\S7 Program(4)\Charts\\F_DO_ESA Author: modula
G70 - GAA Project Created on:: 16/03/2017 14:58
Last change: 21/03/2017 17:05
Partit.: A Sh.: 1 Number of pages: 7

Page 2 of 7
SIMATIC 03/21/2017 05:07:32 PM

19 17
F_NOT F_RS_FF
F_:Inver CYC_INT5 F_:RS-Fl CYC_INT5
20/65 20/63
IN OUT R Q 21
S QN F_RS_FF
F_:RS-Fl CYC_INT5
20/62
including rights created by patent grant or registration of a utility model or design, reserved.

R Q
Loop 1(A,2)\I8 S QN F_DO_ESA(A,1)\Con_ON_ACK
QH OUTPUT 20 IN4 INPUT 4
F_AND4
F_:AND 4 CYC_INT5
The reproduction, transmission or use of this document or its contents is not permitted

20/64
IN1 OUT
without express written authority. Offenders will be liable for damages. All rights,

IN2 OUTN
1 IN3
1 IN4

39 35
F_NOT F_RS_FF
F_:Inver CYC_INT5 F_:RS-Fl CYC_INT5
20/48 20/46
Loop 2(A,2)\I9 IN OUT R Q 33
QL OUTPUT S QN F_RS_FF
F_:RS-Fl CYC_INT5
20/45
R Q
S QN
36
F_AND4
F_:AND 4 CYC_INT5
20/47
IN1 OUT
IN2 OUTN
1 IN3
1 IN4

34 37
F_NOT F_RS_FF
F_:Inver CYC_INT5 F_:RS-Fl CYC_INT5
20/44 20/42
IN OUT R Q 38
S QN F_RS_FF
F_:RS-Fl CYC_INT5
20/41
R Q
Loop 2(A,2)\I10 S QN
QH OUTPUT 40
F_AND4
F_:AND 4 CYC_INT5
20/43
F_DO_ESA(A,1)\ACK IN1 OUT
OUT OUTPUT IN2 OUTN Con_ON_ACK1
1 IN3 F_OR4
F_:OR 4 CYC_INT5
1 IN4 20/49
IN1 OUT F_DO_ESA(A,6)\Con_ON
IN2 OUTN IN2 INPUT 2
F_DO_ESA(A,3)\30 IN3
Q OUTPUT IN4
F_DO_ESA(A,3)\24
Q OUTPUT
G70 Kemira\PLC Acido Acrilico\CPU 412-5 H PN/DP A\S7 Program(4)\Charts\\F_DO_ESA Author: modula
G70 - GAA Project Created on:: 16/03/2017 14:58
Last change: 21/03/2017 17:05
Partit.: A Sh.: 2 Number of pages: 7

Page 3 of 7
SIMATIC 03/21/2017 05:07:32 PM

32 29
F_NOT F_RS_FF
F_:Inver CYC_INT5 F_:RS-Fl CYC_INT5
20/53 20/51
Loop 2(A,2)\I11 IN OUT R Q 24
QL OUTPUT S QN F_RS_FF
F_:RS-Fl CYC_INT5
20/50
including rights created by patent grant or registration of a utility model or design, reserved.

R Q
S QN F_DO_ESA(A,2)\Con_ON_ACK1
25 IN4 INPUT 4
F_AND4
F_:AND 4 CYC_INT5
The reproduction, transmission or use of this document or its contents is not permitted

20/52
IN1 OUT
without express written authority. Offenders will be liable for damages. All rights,

IN2 OUTN
1 IN3
1 IN4

26 31
F_NOT F_RS_FF
F_:Inver CYC_INT5 F_:RS-Fl CYC_INT5
20/57 20/55
IN OUT R Q 30
S QN F_RS_FF
F_:RS-Fl CYC_INT5
20/54
R Q
Loop 2(A,2)\I12 S QN F_DO_ESA(A,2)\Con_ON_ACK1
QH OUTPUT 27 IN3 INPUT 3
F_AND4
F_:AND 4 CYC_INT5
20/56
IN1 OUT
IN2 OUTN
1 IN3
1 IN4

44 43
F_NOT F_RS_FF
F_:Inver CYC_INT5 F_:RS-Fl CYC_INT5
20/38 20/36
IN OUT R Q 42
Loop 3(A,2)\All1 S QN F_RS_FF
F_:RS-Fl CYC_INT5
QH OUTPUT 20/35
R Q F_DO_ESA(A,4)\Con_ON_ACK2
S QN IN1 INPUT 1
41
F_AND4
F_:AND 4 CYC_INT5
20/37
IN1 OUT
F_DO_ESA(A,1)\ACK IN2 OUTN
OUT OUTPUT 1 IN3
1 IN4

G70 Kemira\PLC Acido Acrilico\CPU 412-5 H PN/DP A\S7 Program(4)\Charts\\F_DO_ESA Author: modula
G70 - GAA Project Created on:: 16/03/2017 14:58
Last change: 21/03/2017 17:05
Partit.: A Sh.: 3 Number of pages: 7

Page 4 of 7
SIMATIC 03/21/2017 05:07:32 PM

F_DO_ESA(A,3)\42 Con_ON_ACK2
Q OUTPUT 46 49 F_OR4
F_:OR 4 CYC_INT5
F_NOT F_RS_FF
CYC_INT5 CYC_INT5 20/22
F_:Inver F_:RS-Fl IN1 OUT
20/30 20/28
IN OUT R Q 50 IN2 OUTN F_DO_ESA(A,6)\Con_ON
S QN F_RS_FF IN3 IN3 INPUT 3
F_:RS-Fl CYC_INT5
20/27 IN4
including rights created by patent grant or registration of a utility model or design, reserved.

R Q
Loop 3(A,2)\All2 S QN
QL OUTPUT 52
F_AND4
F_:AND 4 CYC_INT5
The reproduction, transmission or use of this document or its contents is not permitted

20/29
F_DO_ESA(A,1)\ACK IN1 OUT
without express written authority. Offenders will be liable for damages. All rights,

OUT OUTPUT IN2 OUTN

1 IN3
1 IN4

57 60
F_NOT F_RS_FF
F_:Inver CYC_INT5 F_:RS-Fl CYC_INT5
20/21 20/19
IN OUT R Q 59
S QN F_RS_FF
F_:RS-Fl CYC_INT5
20/18
R Q
S QN
Loop 3(A,2)\All3 58
QH OUTPUT F_AND4
F_:AND 4 CYC_INT5
20/20
1 IN1 OUT
IN2 OUTN
1 IN3
1 IN4

61 64
F_NOT F_RS_FF
F_:Inver CYC_INT5 F_:RS-Fl CYC_INT5
20/17 20/15
IN OUT R Q 63
S QN F_RS_FF
F_:RS-Fl CYC_INT5
20/14
R Q
Loop 3(A,2)\All4 S QN
QL OUTPUT 62
F_AND4
F_:AND 4 CYC_INT5
20/16
1 IN1 OUT
IN2 OUTN
1 IN3
1 IN4

G70 Kemira\PLC Acido Acrilico\CPU 412-5 H PN/DP A\S7 Program(4)\Charts\\F_DO_ESA Author: modula
G70 - GAA Project Created on:: 16/03/2017 14:58
Last change: 21/03/2017 17:05
Partit.: A Sh.: 4 Number of pages: 7

Page 5 of 7
SIMATIC 03/21/2017 05:07:32 PM

51 47
F_NOT F_RS_FF
F_:Inver CYC_INT5 F_:RS-Fl CYC_INT5
20/34 20/32
Loop 4(A,2)\I15 IN OUT R Q 45
QL OUTPUT S QN F_RS_FF
F_:RS-Fl CYC_INT5
20/31
including rights created by patent grant or registration of a utility model or design, reserved.

R Q
S QN
48
F_AND4
F_:AND 4 CYC_INT5
The reproduction, transmission or use of this document or its contents is not permitted

20/33
IN1 OUT
without express written authority. Offenders will be liable for damages. All rights,

IN2 OUTN
1 IN3
1 IN4

53 54
F_NOT F_RS_FF
F_:Inver CYC_INT5 F_:RS-Fl CYC_INT5
20/26 20/24
IN OUT R Q 55
S QN F_RS_FF
F_:RS-Fl CYC_INT5
20/23
R Q
Loop 4(A,2)\I16 S QN
QH OUTPUT 56
F_AND4
F_:AND 4 CYC_INT5
20/25
IN1 OUT
IN2 OUTN
1 IN3
1 IN4

68 67
F_NOT F_RS_FF
F_:Inver CYC_INT5 F_:RS-Fl CYC_INT5
20/12 20/10
Loop 4(A,2)\All1 IN OUT R Q 66
QH OUTPUT S QN F_RS_FF
F_:RS-Fl CYC_INT5
20/9
R Q
S QN
65
F_AND4
F_:AND 4 CYC_INT5
20/11 Con_ON_ACK3
F_DO_ESA(A,1)\ACK IN1 OUT F_OR4
F_:OR 4 CYC_INT5
OUT OUTPUT IN2 OUTN 20/13
1 IN3 IN1 OUT F_DO_ESA(A,6)\Con_ON
1 IN4 IN2 OUTN IN4 INPUT 4
IN3
IN4
F_DO_ESA(A,6)\71
Q OUTPUT
G70 Kemira\PLC Acido Acrilico\CPU 412-5 H PN/DP A\S7 Program(4)\Charts\\F_DO_ESA Author: modula
G70 - GAA Project Created on:: 16/03/2017 14:58
Last change: 21/03/2017 17:05
Partit.: A Sh.: 5 Number of pages: 7

Page 6 of 7
SIMATIC 03/21/2017 05:07:32 PM

69 70
F_NOT F_RS_FF
F_:Inver CYC_INT5 F_:RS-Fl CYC_INT5
20/8 20/6
IN OUT R Q 71
S QN F_RS_FF
F_:RS-Fl CYC_INT5
20/5
R Q
Loop 4(A,2)\All2 S QN F_DO_ESA(A,5)\Con_ON_ACK3
including rights created by patent grant or registration of a utility model or design, reserved.

QL OUTPUT 72 IN4 INPUT 4

F_AND4
F_:AND 4 CYC_INT5
20/7
F_DO_ESA(A,1)\ACK IN1 OUT
The reproduction, transmission or use of this document or its contents is not permitted

OUT OUTPUT IN2 OUTN

1 IN3 ESA-39800-1
without express written authority. Offenders will be liable for damages. All rights,

1 IN4 F_CH_DO
F_:Fail- CYC_INT5
20/1
CHADDR PASS_OUT
@F_(1)(A,5)\FDO10xDC24V_2A_3 CHADDR_R QBAD
CHADDRO00 ADDRESS OUTPUT PROCESS DATA BYTE CH_INF QSIM
@F_(1)(A,6)\FDO10xDC24V_2A_4 CH_INF_R VALUE "ESA-39800-1/D" Q14.7
CHADDRO00 ADDRESS OUTPUT PROCESS DATA BYTE I QUALITY Allarme acustico 1 e 2 sala controllo
@F_(1)(A,5)\FDO10xDC24V_2A_3 0 SIM_I ACK_REQ
CHADDRI00 ADDRESS INPUT PROCESS DATA BYTE 0 SIM_MOD
@F_(1)(A,6)\FDO10xDC24V_2A_4 0 SIM_ON
CHADDRI00 ADDRESS INPUT PROCESS DATA BYTE 0 PASS_ON
0 ACK_NEC
ACK_REI
F_DO_SPARE(A,2)\Ack_Passivation
OUT OUTPUT
Con_ON Con_ON1
F_OR4 F_OR4
F_:OR 4 CYC_INT5 F_:OR 4 CYC_INT5
20/4 20/3
IN1 OUT IN1 OUT
F_DO_ESA(A,1)\Con_ON_ACK IN2 OUTN IN2 OUTN
OUT OUTPUT IN3 IN3
F_DO_ESA(A,4)\Con_ON_ACK2 IN4 0 IN4
OUT OUTPUT
F_DO_ESA(A,5)\Con_ON_ACK3
OUT OUTPUT Con_ON_NOT_ACK
F_DO_ESA(A,2)\Con_ON_ACK1 F_OR4
F_:OR 4 CYC_INT5
OUT OUTPUT 20/40
Loop 1(A,3)\All_1 IN1 OUT
QH OUTPUT IN2 OUTN
Loop 1(A,3)\All_2 IN3
QL OUTPUT IN4
Loop 1(A,3)\All_3
QH OUTPUT
Loop 1(A,3)\All_4 Con_ON_NOT_ACK1
QL OUTPUT F_OR4
F_:OR 4 CYC_INT5
20/39
IN1 OUT
Loop 2(A,2)\All1 IN2 OUTN
QH OUTPUT IN3
Loop 2(A,2)\All2 IN4
QL OUTPUT
Loop 3(A,2)\I13 G70 - Kemira - GAA Project
QL OUTPUT - Allarme acustico
Loop 3(A,2)\I14
QH OUTPUT
G70 Kemira\PLC Acido Acrilico\CPU 412-5 H PN/DP A\S7 Program(4)\Charts\\F_DO_ESA Author: modula
G70 - GAA Project Created on:: 16/03/2017 14:58
Last change: 21/03/2017 17:05
Partit.: A Sh.: 6 Number of pages: 7

Page 7 of 7