CM508 Ri02 P05T00

®
Preliminary CM508 RI02
Programmable Power Management IC for LCD Panels

General Description Features
The CM508 RI02 offers a compact power supply solution 8V to 14V Input Supply Voltage
to provide all voltages required by a TFT LCD panel. With Boost Regulator for AVDD
its high current capabilities, the device is ideal for large ` 13.5V to 19.8V Programmable Output
screen LCD monitors panels and TV applications with 12V ` Isolation Switch
supply voltage. ` Current Limit Protection
Buck Regulator for VI/O

The CM508 RI02 is available in a VQFN-40L 6x6 package.
` 2.2V to 3.7V Programmable Output
Sync. Buck Regulator for VCORE

Ordering and Marking Information
` 0.8V to 3.3V Programmable Output
Part No. Marking Information Package Type
Sync. Buck Regulator for HAVDD
CMI VQFN-40L 6x6 ` 4.8V to 11.1V Programmable Output
CM508 RI02
CM508 RI02 (V-Type)
Positive Charge Pump Regulator for VGH
` 20V to 40V Programmable Output
` 0V to 15V Gate Shaping Voltage

Pin Configurations
` Temperature Compensation
(TOP VIEW)
Negative Charge Pump Regulator for VGL
OUTBK1
OUTBK2
BSTBK1
GVOFF
` −5.5V to −14.5V Programmable Output

LXBK1
LXBK1
LXBK2
INBK2
PGND
EN
Programmable Sequencing
40 39 38 37 36 35 34 33 32 31 Fixed Switching Frequency 750kHz
INBK1 1 30 OUTBK3 Over Temperature Protection
INBK1 2 29 PGND
NC 3 28 LXBK3 I2C Compatible Interface for Register Control
SDA 4 27 BST3 Thin 40-Lead
SCL 5 26 INBK3
A0 6
PGND 25 RE RoHS Compliant and Halogen Free
HVS 7 24 VGHM
INVL 8 23 VGHP
AGND 9
41
22 DRVP
Applications
COMP 10 21 DRVN TFT LCD Monitor Panel
11 12 13 14 15 16 17 18 19 20
TFT LCD Panel
VL
LX1
LX1
VGL
NTC
PGND
PGND
SWI
NC
SWO
VQFN-40L 6x6
Copyright © 2012 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.
CM508 RI02-P05T00 July 2012 www.richtek.com

1
CM508 RI02 Preliminary
Typical Application Circuit

L1
6.8µH D1
VIN
12V C3
C1 10µF
10µF x 2 C2
0.1µF
8 15, 16 17
INVL LX1 SWI
1, 2 INBK1 SWO 18 VAVDD
C4 16.8V
C6 CM508 RI02 10µF x 5 R5
10µF 1k
VI/O
36 INBK2
VI/O
C12 SDA 4 SDA
10µF R6
26 INBK3 1k
VI/O
C19 SCL 5 SCL
10µF
11 VL 6
A0 A0
C5 R4 C14
1µF 115k 470pF
Chip Enable 31 EN COMP 10
R7
7 100k
HVS HVS VAVDD
37 OUTBK1 C15
DRVP 22 0.1µF
40 BSTBK1
C7 VLX1
L2 0.1µF
6.8µH 38,39 C16
VI/O LXBK1 0.1µF D5 C17 R8
0
3V C8 0.47µF
10µF D2
20 VGL D6
23 VGH
D3 D4 VGHP
VGL 28V
VL C18
-10.3V
C11 C9 C10 RTCOMP1 2.2µFx 2
10µFx 2 0.47µF 47nF 21 DRVN 51k
NTC 12
R1 RTCOMP2
0 NTC
22k NCP18XH103F03RB
LXB1
R3 25
RE BST3 27
C20
0.1µF
VGHM 24 VGHM L4
35 GVOFF LXBK3 28 VHAVDD
GVOFF 6.8µH 8.1V
C21
L3 OUTBK3 30 10µFx 2
6.8/4.7µH
VCORE 33 LXBK2
1.2V C13 13, 14, 29, 32,
10µFx 2 34 OUTBK2
41 (Exposed Pad)
PGND
AGND
9
www.richtek.com CM508 RI02-P05T00 July 2012

2
Timing Diagram
UVLO
VIN
3ms Buck1 (VI/O)
Buck1 (3.3V) 350µs
3ms
Buck2 (2.5V/1.2V)
Buck2 (VCORE)
VGL
3ms
EN
(From TCON)
10ms AVDD
AVDD Soft-Start 10ms or 20ms
AVDD Buck3 (HAVDD)
1
Buck3 ( x AVDD)
2 3ms
VGHP
GVOFF
VGH
VGHM
Figure 1. Power Sequence Timing Diagram

3
Functional Pin Description

Pin No. Pin Name Pin Function
Power Supply Pin for V I/O Buck Converter. INBK1 is internally connected to
1, 2 INBK1
INBK3.
3, 19 NC No Internal Connection.
2
4 SDA I C Compatible Serial Data Input/Output.
2
5 SCL I C Compatible Serial Clock Input.
2
6 A0 I C Compatible Device Address Bit 0.
7 HVS Boost HVS Enable.
Analog Input. This is the input for the analog circuits. Connect this pin with a
8 INVL
decoupling capacitor.
9 AGND Analog Ground.
10 COMP Compensation Pin for Boost Converter.
11 VL Internal Logic Regulator Output. Connect this pin with a decoupling capacitor.
12 NTC Temperature Compensation Pin for VGH.
13, 14, 29, 32, Power Ground. The exposed pad must be soldered to a large PCB and
PGND
41 (Exposed Pad) connected to PGND for maximum thermal dissipation.
15, 16 LX1 Switch Node of Boost Converter.
17 SWI Isolation Switch Input.
Isolation Switch Output. This pin is also used as the feedback of the boost
18 SWO
converter.
20 VGL Output Sensing Pin of VGL Negative Charge Pump.
21 DRVN Base Drive of External NPN Transistor for VGL Negative Charge Pump.
22 DRVP Base Drive of External PNP Transistor for VGH Positive Charge Pump.
Output Sensing Pin for VGH Positive Charge Pump and Power Supply Pin for
23 VGHP
GPM.
24 VGHM Switch Output for Gate Shaping Function.
25 RE Discharge Pin for Gate Shaping Function.
Power Supply Pin for HAVDD Buck Converter. INBK3 is internally connected
26 INBK3
INBK1.
N-MOSFET Gate Drive Voltage for HAVDD Buck Converter. Connect a
27 BST3
capacitor from LXBK3 to this pin.
28 LXBK3 Switch Node of HAVDD Buck Converter.
30 OUTBK3 Output Sensing Pin for HAVDD Buck Converter.
31 EN Chip Enable (Active High).
33 LXBK2 Switch Node of VCORE Buck Converter.
34 OUTBK2 Output Sensing Pin of V CORE Buck Converter.
Gate Shaping Control Input. When GVOFF is high, the switch between VGHP
and VGHM is on and the switch between VGHM and RE is off. When GVOFF is
35 GVOFF
low, the switch between VGHP and VGHM is off and the switch between VGHM
and RE is on.
36 INBK2 Power Supply Pin for VCORE Buck Converter.
37 OUTBK1 Output Sensing Pin of V I/O Buck Converter.

4
Pin No. Pin Name Pin Function
38, 39 LXBK1 Switch Node of VI/O Buck Converter.
N-MOSFET Gate Drive Voltage for VI/O Buck Converter. Connect a capacitor
40 BSTBK1
from LXBK1 to this pin.
Function Block Diagram
INVL LX1 SWI SWO
Internal
VL
Regulator
BOOST
COMP
HVS
BSTBK1
INBK1
EN
Buck1 Sequence SDA
LXBK1 Control I2C Interface SDL
A0
OUTBK1 Thermal
UVLO EEPROM DAC
Shutdown
VL
VL BST3
VGL INBK3
DRVN
Regulator
100k
Buck3 LXBK3
VGL
INBK2
OUTBK3
LXBK2 Buck2
DRVP
VGH
OUTBK2 Regulator
VGH
VGHP
NTC
VGHM GPM
AGND
RE PGND
GVOFF

5
Absolute Maximum Ratings (Note 1)

EN, INVL, INBK1, INBK3, SWI, SWO, OUTBK3, LX1 to PGND ---------------------------------------- −0.3V to 24V
VL, NTC, COMP, SDA, SCL, A0, HVS, OUTBK1, OUTBK2,
INBK2, GVOFF, DRVN to PGND ------------------------------------------------------------------------------- −0.3V to 6V
LXBKx to PGND ---------------------------------------------------------------------------------------------------- −0.3 to (VINBKx + 0.3V)
LXBKx to PGND
<20ns ----------------------------------------------------------------------------------------------------------------- −2 to (VINBKx + 0.3V)
BSTBK1 to LXBK1 ------------------------------------------------------------------------------------------------- −0.3 to 6V
BST3 to LXBK3 ----------------------------------------------------------------------------------------------------- −0.3 to 6V
SWI to SWO -------------------------------------------------------------------------------------------------------- −0.3 to 24V
VGHP, VGHM, RE, DRVP to PGND --------------------------------------------------------------------------- −0.3 to 40V
VGL to VL ------------------------------------------------------------------------------------------------------------ −24 to 0.3V
PGND to AGND ----------------------------------------------------------------------------------------------------- ±0.3V
Power Dissipation, PD @ TA = 25°C
VQFN-40L 6x6 ------------------------------------------------------------------------------------------------------ 3.7W
Package Thermal Resistance (Note 2)
VQFN-40L 6x6, θJA ------------------------------------------------------------------------------------------------- 27°C/W
VQFN-40L 6x6, θJC ------------------------------------------------------------------------------------------------ 6.5°C/W
Lead Temperature (Soldering, 10 sec.) ------------------------------------------------------------------------ 260°C
Junction Temperature ---------------------------------------------------------------------------------------------- 150°C
Storage Temperature Range ------------------------------------------------------------------------------------- −65°C to 150°C
ESD Susceptibility (Note 3)
HBM (Human Body Model) --------------------------------------------------------------------------------------- 2kV
MM (Machine Model) ---------------------------------------------------------------------------------------------- 200V
Recommended Operating Conditions (Note 4)

Supply Input Voltage, VIN ---------------------------------------------------------------------------------------- 8V to 14V
Junction Temperature Range ------------------------------------------------------------------------------------- −40°C to 125°C
Ambient Temperature Range ------------------------------------------------------------------------------------- −40°C to 85°C
Electrical Characteristics
(VIN = 12V, EN = High, VAVDD = 16V, VI/O = 3.3V, VCORE = 1.2V, VHAVDD = 8V, VGH = 26V, VGL = −5V, TA = 25°C, unless otherwise
specified)
Parameter Symbol Test Conditions Min Typ Max Unit
Supply Current
Quiescent Current into INVL LX1, LXBKx Switching -- 7 --
IQIN mA
Quiescent Current into INBKx LX1, LXBKx Not Switching -- 0.2 --
Under Voltage Lockout Threshold V UVLO VIN Falling -- 7 -- V
Under Voltage Lockout Threshold
ΔVUVLO -- 400 -- mV
Hysteresis
VL Output Voltage VL -- 5 -- V
VL Output Voltage Tolerance ΔVL −1 -- 1 %

6
Fault Detection
Fault Trigger Duration -- 50 -- ms
Thermal Shutdown Threshold T SD Temperature Rising -- 150 -- °C
Thermal Shutdown Hysteresis ΔT SD -- 30 -- °C
Logic Inputs (SDA, SCL, HVS, EN, GVOFF)
Input Threshold Logic-High V IH 1.7 -- --
V
Voltage Logic-Low V IL -- -- 0.6
Input Leakage Current IIH, IIL V IN = 0V or 3.3V −1 0.01 1 μA
Input Capacitance -- 5 -- pF
SDA Output Low Voltage V OL ISINK = 6mA -- 0.3 -- V
2
I C Timing Characteristics
Serial-Clock Frequency fSCL 0 -- 1 MHz
Bus Free Time Between STOP and
tBUF 1.3 -- -- μs
START Conditions
Hold Time (Repeated) START
tHD, DAT 0.6 -- -- μs
Condition
SCL Pulse-Width Low tLOW 1.3 -- -- μs
SCL Pulse-Width High tHIGH 0.6 -- -- μs
Setup Time for a Repeated START
tSU, STA 0.6 -- -- μs
Condition
Data Hold Time tHD, DAT 0 -- 800 ns
Data Setup Time tSU, DAT 100 -- -- ns
20 +
SDA and SCL Receiving Rise Time tR -- 300 ns
0.1CB
20 +
SDA and SCL Receiving Fall Time tF -- 300 ns
0.1CB
20 +
SDA Transmitting Fall Time tFF -- 250 ns
0.1CB
Setup Time for STOP Condition tSU, STO 0.6 -- -- μs
Bus Capacitance CB -- -- 400 pF
Pulse Width of Suppressed Spike tSP -- -- 50 ns
Internal Oscillator
Oscillator Frequency fOSC 600 750 900 kHz
Maximum Duty Cycle DMAX -- 90 -- %
Boost Converter (AVDD)
V HVS = 0V, Programmable
SWO Regulation Voltage Range V SWO 13.5 -- 19.8 V
Step 0.1V
SWO Regulation Voltage
−1 -- 1 %
Tolerance
HVS Voltage V HVS Programmable Step 0.2V 0 -- 3 V
N-MOSFET On-Resistance RDS(ON) ILX1 = 500mA -- 100 -- mΩ
N-MOSFET Switch Current Limit ILIM 4.25 5 5.75 A

7

N-MOSFET Switch Current Limit
0 -- 2.8 A
Negative Offset
Switch Leakage Current ILEAK V LX1 = 16.5V -- 1 10 μA
Soft-Start Period -- 10 20 ms
SWI Over Voltage Protection VOVP V SWI Rising 20.5 21.5 22.5 V
SWI Over Voltage Protection
ΔVOVP -- 1.5 -- V
Hysteresis
SWO Line Regulation 8V ≤ VIN ≤ 14V, IOUT = 1mA -- 0.008 -- %/V
SWO Load Regulation 1mA ≤ IOUT ≤ 2A -- ±1 -- %/A
Transconductance of Error Amplifier gm -- 240 -- μA/V
SWO Fault Trip Level V SWO Falling 76 80 84 %
Gain of Error Amplifier AV -- 1000 -- V/V
Isolation Switch
P-MOSFET On-Resistance RDS(ON) ISWI = 0.2A -- 100 200 mΩ
Switch Current -- -- 3 A
ISWI ≥ 2.5A -- 1.5 -- ms
Short Circuit Trigger Duration
ISWI ≥ 4.5A -- 100 -- μs
Buck1 Converter (VI/O)
OUTBK1 Regulation Voltage Range VOUTB1 Programmable Step 0.1V 2.2 -- 3.7 V
OUTBK1 Regulation Voltage
ILOAD = 10mA −2 -- 2 %
Tolerance
LXBK1 to INBK1 N-MOSFET
RDS(ON) ILXBK1 = 500mA -- 150 -- mΩ
On-Resistance
LXBK1 Positive Current Limit ILIM 3 3.5 4 A
LXBK1 to PGND N-MOSFET
-- 6 -- Ω
On-Resistance
OUTBK1 Line Regulation 8V ≤ VIN ≤ 14V, IOUT = 1mA -- 0.005 -- %/V
OUTBK1 Load Regulation 1mA ≤ IOUT ≤ 2.5A -- 0.25 -- %/A
Soft-Start Period tSS -- 3 -- ms
OUTBK1 Fault Trip Level V OUTBK1 Falling 76 80 84 %
Buck2 Converter (VCORE )
Operating Frequency fOSC -- 2 -- MHz
Maximum Duty Cycle DMAX -- -- 100 %
OUTBK2 Regulation Voltage Range VOUTBK2 Programmable Step 0.1V 0.8 -- 3.3 V
ILOAD = 10mA −2 -- 2 %
Tolerance
OUTBK2 to LXBK2 P-MOSFET V OUTBK1 = 3.3V,
RDS(ON) -- 160 -- mΩ
On-Resistance ILXBK2 = 500mA
LXBK2 Positive Current Limit ILIM 2.5 3.0 3.5 A
Switch Leakage Current ILEAK V LXBK2 = 0V -- 1 10 μA

8
VOUTBK1 = 3.3V -- 160 -- mΩ
On-Resistance
Line Regulation 8V ≤ V IN ≤ 14V, IOUT = 1mA -- 0.1 -- %/V
Load Regulation 1mA ≤ IOUT ≤ 1A -- 0.1 -- %/A
OUTBK2 Fault Trip Level VOUTBK2 Falling 70 75 80 %
Buck3 Converter (HAVDD)
V OUTBK3 Programmable Step 0.1V 4.8 -- 11.1 V
Range
Regulation Voltage Tolerance V OUTBK3 ILOAD = 10mA −1 -- 1 %
INBK3 to LXBK3 N-MOSFET
R DS(ON) ILXBK3 = 500mA -- 200 -- mΩ
On-Resistance
LXBK3 Positive Current Limit
ILIM 1.7 2.0 2.3 A
Tolerance
Switch Leakage Current ILEAK VLXBK3 = 0V -- 1 10 μA
-- 200 -- mΩ
On-Resistance
LXBK3 Negative Current Limit
ILIM 1.7 2.0 2.3 A
Tolerance
Line Regulation 8V ≤ V IN ≤ 14V, IOUT = 1mA -- 0.1 -- %/V
Load Regulation 1mA ≤ IOUT ≤ 1.5A -- 0.25 -- %/A
OUTBK3 Fault Trip Level VOUTBK3 Falling 75 80 85 %
OUTBK3 Over Voltage Threshold VOUTBK3 Rising 115 120 125 %
Negative Charge Pump Controller (VGL)
VGL Output Voltage V GL Programmable Step 0.5V −14.5 -- −5.5 V
VDRVN = 0.6V,
DRVN Source Current IDRVN 5 8 -- mA
VGL= VGL(nominal) + 0.05V
Regulation Voltage Tolerance VDRVN = 0.6V, IDRVN = −100μA −1 -- 1 %
VDRVN = 0.6V,
VGL Load Regulation Error -- 11 25 mV/mA
−50μA < IDRVN < −1mA
VGL VGL
VGL Fault Trip Level VGL Rising -- V
+ 1.5 + 2.5
Positive Charge Pump Controller (VGH)
VGH_L Regulation Voltage Range V GH_L Programmable Step 1V 20 -- 35 V
VGH_H = VGH_L + VGH_OS ,
VGH_H Offset Voltage V GH_OS 0 -- 15 V
Programmable Step 1V
VGH_H Regulation Voltage Range V GH_H 20 -- 40 V
IDRVP VGH = VGH(nominal) − 5% 5 -- -- mA
DRVP Sink Current
VGH < 20% -- 80 -- μA
Regulation Voltage Tolerance VDRVP = 16V, IDRVP = 100μA −2 -- 2 %

9

V DRVP = 16V,
VGH Load Regulation Error -- 11 25 mV/mA
50μA < IDRVP < 1mA
VGH Fault Trip Level VGH Falling 75 80 85 %
Gate Pulse Modulation(GPM)
Gate Shaping Lower Limit Voltage Programmable Step 5V 0 -- 15 V
VGHP-to-VGHM Switch
GVOFF = High -- 3 5 Ω
On-Resistance
VGHM-to-RE Switch
GVOFF = Low -- 3 5 Ω
On-Resistance
GVOFF to VGHM Delay Time 0.15 0.25 0.35 μs
Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in
the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may
affect device reliability.
Note 2. θJA is measured at TA = 25°C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. θJC is
measured at the exposed pad of the package.
Note 3. Devices are ESD sensitive. Handling precaution is recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.

10
Typical Operating Characteristics
AVDD Efficiency vs. Load Current VI/O Efficiency vs. Load Current
100 100
90 90
80 80
70 70
Efficiency (%)
Efficiency (%)
60 60
50 50
40 40
30 30
20 20
10 10
VIN = 12V, VAVDD = 16.8V VIN = 12V, VI/O = 3V
0 0
0 0.5 1 1.5 2 0 0.5 1 1.5 2
Load Current (A) Load Current (A)
VCORE Efficiency vs. Load Current HAVDD Efficiency vs. Load Current
100 100
90 90
80 80
70 70
Efficiency (%)
Efficiency (%)
60 60
50 50
40 40
30 30
20 20
10 10
VIN = 12V, VI/O = 3V, VCORE = 1.2V VIN = 12V, VHAVDD = 8.1V
0 0
0 0.2 0.4 0.6 0.8 0 0.25 0.5 0.75 1
AVDD Output Voltage vs. Load Current VI/O Output Voltage vs. Load Current
17.0 3.3
16.9 3.2
Output Voltage (V)
Output Voltage (V)
16.8 3.1
16.7 3.0
16.6 2.9
VIN = 12V, VAVDD = 16.8V VIN = 12V, VI/O = 3V

16.5 2.8
0 0.5 1 1.5 2 0 0.5 1 1.5 2

11
VCORE Output Voltage vs. Load Current HAVDD Output Voltage vs. Load Current
1.5 8.3
1.4 8.2
Output Voltage (V)

Output Voltage (V)
1.3 8.1
1.2 8.0
1.1 7.9
VIN = 12V, VI/O = 3V, VCORE = 1.2V VIN = 12V, VHAVDD = 8.1V
1.0 7.8
0 0.25 0.5 0.75 1 0 0.25 0.5 0.75 1
VGH Output Voltage vs. Load Current VGL Output Voltage vs. Load Current
29.0 -9.0
28.5 -9.5
Output Voltage (V)
Output Voltage (V)
28.0 -10.0
27.5 -10.5
VIN = 12V, VGH = 28V VIN = 12V

27.0 -11.0
0 10 20 30 40 50 60 0 10 20 30 40 50 60
Load Current (mA) Load Current (mA)
AVDD Operating Frequency vs. Input Voltage VCORE Operating Frequency vs. Input Voltage
780 2.030
Operating Frequency (MHz)1
Operating Frequency (kHz)1
770 2.020
760 2.010
750 2.000
740 1.990
VAVDD = 16.8V, IAVDD = 0.1A VCORE = 1.2V, IVCORE = 0.1A

730 1.980
8 9 10 11 12 13 14 8 9 10 11 12 13 14
Input Voltage (V) Input Voltage (V)

12
AVDD INL Error vs. DAC Setting VI/O INL Error vs. DAC Setting
1.0 1.0
Integral Nonlinearity (LSB)1

0.5 0.5
0.0 0.0
-0.5 -0.5
-1.0 -1.0
0 7 14 21 28 35 42 49 56 63 0 3 6 9 12 15
DAC Setting (Step) DAC Setting (Step)
VCORE INL Error vs. DAC Setting HAVDD INL Error vs. DAC Setting
1.0 1.0
0.5 0.5
0.0 0.0
-0.5 -0.5
-1.0 -1.0
0 5 10 15 20 25 0 7 14 21 28 35 42 49 56 63
VGH INL Error vs. DAC Setting VGL INL Error vs. DAC Setting
1.0 1.0
0.5 0.5
0.0 0.0
-0.5 -0.5
-1.0 -1.0
0 3 6 9 12 15 0 3 6 9 12 15

13
AVDD OCP INL Error vs. DAC Setting Power On Sequence

1.0
0.5
VIN
(5V/Div)
VI/O
0.0 (2V/Div)
V CORE
(1V/Div)
VGL
-0.5 (10V/Div)
VIN = 12V, VI/O = 3V, VCORE = 1.2V, VGL = −10.3V

-1.0
0 1 2 3 4 5 6 7 Time (2.5ms/Div)
DAC Setting (Step)
Enable Sequence (Normal) Enable Sequence (VGL with LX1)
VGL
(5V/Div)
VEN
(2V/Div)
AVDD
(10V/Div)
AVDD
(10V/Div)
HAVDD HAVDD
(5V/Div) (5V/Div)
VGH VGH
VEN = 3.3V, VGH = 28V, VEN = 3.3V, VGH = 28V,
(20V/Div) (20V/Div)
VAVDD = 16.8V, VHAVDD = 8.1V VAVDD = 16.8V, VHAVDD = 8.1V, VGL = −10.3V
Time (5ms/Div) Time (5ms/Div)

14
Applications Information
The CM508 RI02 is a multi-functional power solution for Over Temperature Protection
LCD panel. The CM508 RI02 contains a step-up converter The CM508 RI02 equips an Over Temperature Protection
for main power, two synchronous buck converters, one (OTP) circuitry to prevent overheating due to excessive
voltage detector, and one step-down converter. It also power dissipation. The OTP will shut down switching
includes a positive charge pump with temperature operation when junction temperature exceeds 150°C, and
compensation for positive voltage. Moreover, the charge must re-power on again, the CM508 RI02 can be release
pump circuit is utilized to generate gate high and gate form shut down state. To maintain continuous operation
low voltages. maximum, the junction temperature should be prevented
from rising above 125°C.
Boost Converter
The main boost converter has a programmable soft-start Boost Inductor Selection
function to reduce the input inrush current and the soft- The inductor value depends on the maximum input current.
start time can be set to 10 or 20ms. As a result, VAVDD As a general rule the inductor ripple current is 20% to
rises up smoothly while the input current stays limited for 40% of maximum input current. If 40% is selected as an
the entire soft-start duration. example, the inductor ripple current can be calculated
according to the following equation :
Boost Over Voltage Protection VOUT × IOUT(MAX)
The main boost converter has an over voltage protection IIN(MAX) =
η × VIN
to protect the main switch at the SWI pin. When the SWO
IRIPPLE = 0.4 × IIN(MAX)
pin voltage rises above 21.5V, the boost converter turns
the MOSFET switch off. As soon as the output voltage where η is the efficiency of the boost converter, IIN(MAX) is
falls below the over voltage threshold, the converter will the maximum input current, and IRIPPLE is the inductor
resume operation. ripple current. The input peak current can be obtained by
adding the maximum input current with half of the inductor
Boost Over Current Protection ripple current as shown in the following equation :
The CM508 RI02 senses the inductor current that is flowing IRIPPLE = 0.2 × IIN(MAX)
into the LX1 pin. The internal N-MOSFET will be turned off Note that the saturated current of inductor must be greater
if the peak inductor current reaches 3.4A (typ.). The current than IPEAK. The inductance can eventually be determined
limit level can programmable by AVDD OCP register (03h), according to the following equation :
and the level is 6A minus AVDD OCP register setting value.
η × ( VIN ) × ( VOUT − VIN )
2
Thus, the output current at the current limit boundary, L=
0.4 × ( VOUT ) × I OUT(MAX)×fOSC
2
denoted as IOUT(LIM), can be calculated according to the
following equation :
⎛ where fOSC is the switching frequency. For better system
V 1 V × (VOUT − VIN ) t S ⎞
IOUT(LIM) = η × IN × ⎜ ILIM − × IN × ⎟ performance, a shielded inductor is preferred to avoid EMI
VOUT ⎝ 2 VOUT L ⎠
problems.
where η is the efficiency of the boost converter, ILIM is the
value of the current limit, and tS is the switching period. Boost Diode Selection
The Schottky diode is a good choice for any asynchronous
Boost Fault Protection
boost converter due to the small forward voltage. However,
The main boost converter has a fault protection. This
when selecting a Schottky diode, important parameters
function disables the boost converter if SWO is detected
such as power dissipation, reverse voltage rating, and
to be below 80%. The IC will shut down if SWO remains
pulsating peak current must all be taken into
below 80% after 50ms.

15
consideration. A suitable Schottky diode's reverse voltage Loop Compensation

rating must be greater than the maximum output voltage, The voltage feedback loop can be compensated with an
and its average current rating must exceed the average external compensation network consisting of RCOMP1,
output current. CCOMP2 and CCOMP1. Choose RCOMP1 to set high frequency
integrator gain for fast transient response and CCOMP2 to
Boost Output Capacitor Selection
set the integrator zero to maintain stability.
Output ripple voltage is an important index for estimating
the performance. This portion consists of two parts, one VI/O Buck Converter
is the product of IIN and ESR of output capacitor, another The buck converter is a high efficiency PWM architecture
part is formed by charging and discharging process of with 750kHz operation frequency and fast transient
output capacitor. As shown in Figure 2, ΔVOUT1 can be response. The converter drives an internal N-MOSFET,
evaluated based on the ideal energy equalization. connected between the VINB1 and LXBK1 pins
According to the definition of Q, the Q value can be respectively. Connect a 100nF low ESR ceramic capacitor
calculated as following equation : between the BSTBK1 pin and LXBK1 pin to provide gate
1 ⎡⎛ 1 ⎞ ⎛ 1 ⎞⎤ driver voltage for the high side MOSFET.
Q= × ⎢⎜ IIN + ΔIL − IOUT ⎟ + ⎜ IIN − ΔIL − IOUT ⎟ ⎥ ×
2 ⎣⎝ 2 ⎠ ⎝ 2 ⎠⎦
VIN VI/O Buck Soft-Start
1
× = COUT × ΔVOUT1
VOUT fOSC The step-down converter has an internal soft-start to reduce
the input inrush current. When the buck converter is
where fOSC is the switching frequency and ΔIL is the enabled, the output voltage rises slowly from 0 to 3.3V.
inductor ripple current. Move COUT to left side to estimate The typical soft-start time is around 3ms.
the value of ΔVOUT1 as following equation :
D × IOUT VI/O Buck Over Current Protection
ΔVOUT1 =
η × COUT × fOSC The CM508 RI02 senses the inductor current that is flowing
out the LXBK1 pin. The internal MOSFET will be turned
Finally, the output ripple voltage can be determined as
off if the peak inductor current reaches 3.5A (typ.)
following equation :
D × IOUT
ΔVOUT = IIN × ESR + VI/O Buck Short Circuit Protection
η × COUT × fOSC
To limit the short circuit current, the device has a cycle-
by-cycle current limit. To avoid the short circuit current
from rising above the internal current limit when the output
ΔIL
is shorted to GND, the switching frequency is reduced as
Input Current Inductor Current well. The switching frequency is reduced to one-half of
original frequency when the OUTBK1 voltage is below 80%
and to one-fourth of the original frequency when the
Output Current OUTBK1 voltage is below 20%. If the short is removed,
Time the buck converter will restart operation. If the voltage
(1-D)TS remains below 80% after 50ms, the IC will shut down.
Output Ripple
Voltage (ac)
VI/O Buck Fault Protection
Time
ΔVOUT1 The buck converter has two fault protections. One is output
UVP and the other is OVP. This function disables the
buck converter if the OUTBK1 voltage is detected to be
Figure 2. The Output Ripple Voltage without the
below 80%. If the OUTBK1 voltage remains below 80%
Contribution of ESR
after 50ms, the IC will shut down.

16
VI/O Over Voltage Protection sized for the maximum RMS current should be used. The
When the OUTBK1 voltage rises above 110%, the buck RMS current is given by :
converter turns the MOSFET switch off. As soon as the VOUT VIN
IRMS = IOUT(MAX) × × −1
feedback voltage falls below the over voltage threshold, VIN VOUT
the converter will resume operation. This formula has a maximum at VIN = 2VOUT, where
IRMS = IOUT / 2. This simple worst-case condition is
Buck Inductor Selection
commonly used for design because even significant
The inductor value and operating frequency determine the deviations do not offer much relief. Choose a capacitor
ripple current according to a specific input and output rated at a higher temperature than required. Several
voltage. The ripple current, ΔIL, will increase with higher capacitors may also be paralleled to meet size or height
VIN and decrease with higher inductance, as shown in requirements in the design. For the input capacitor, a 10μF
below equation : low ESR ceramic capacitor is recommended.
⎛ V ⎞ ⎛ V ⎞
ΔIL = ⎜ OUT ⎟ × ⎜ 1− OUT ⎟
⎝ fOSC × L ⎠ ⎝ VIN ⎠ Buck Output Capacitor Selection
The selection of COUT is determined by the required ESR
Having a lower ripple current reduces not only the ESR
to minimize voltage ripple. Moreover, the amount of bulk
losses in the output capacitors but also the output voltage
capacitance is also a key for COUT selection to ensure
ripple. High frequency with small ripple current can achieve
that the control loop is stable. Loop stability can be
the highest efficiency operation. However, it requires a
checked by viewing the load transient response as
large inductor to achieve this goal. For the ripple current
described in a later section. The output ripple, VOUT, is
selection, the value of IL(MAX) = 0.4 is a reasonable starting
determined by :
point. The largest ripple current occurs at the highest VIN.
⎛ 1 ⎞
To guarantee that the ripple current stays below the ΔVOUT = ΔIL × ⎜ ESR + ⎟
⎝ 8 × fOSC × COUT ⎠
specified maximum, the inductor value should be chosen
according to the following equation : The output ripple will be highest at the maximum input
⎛ VOUT ⎞ ⎛ V ⎞ voltage since IL increases with input voltage. Multiple
L= ⎜ ⎟ × ⎜ 1− OUT ⎟
⎜ fOSC × ΔIL(MAX) ⎟ ⎜ VIN(MAX) ⎟ capacitors placed in parallel may be needed to meet the
⎝ ⎠ ⎝ ⎠
ESR and RMS current handling requirement. Suitable
Buck Diode Selection candidates such as dry tantalum, special polymer,
When the power switch turns off, the path of the current aluminum electrolytic and ceramic capacitors are all
is through the diode connected between the switch output available in surface mount packages. Special polymer
and ground. This forward biased diode must have minimum capacitors offer very low ESR value. However, it provides
voltage drop and quick recovery time. The Schottky diode lower capacitance density than other types. Although
is a preferred choice and is able to handle typical operation tantalum capacitors have the highest capacitance density,
currents. Care should be given, however, to make sure it is important to only use types that pass the surge test
that the reverse voltage rating of the diode is greater than for use in switching power supplies. Aluminum electrolytic
the maximum input voltage and the current rating is greater capacitors have significantly higher ESR. However, it can
than the maximum load current. be used in cost-sensitive applications requiring high ripple
current rating and long term reliability. Ceramic capacitors
Buck Input Capacitor Selection have excellent low ESR characteristics but can have a
The input capacitance, C IN, is needed to filter the high voltage coefficient and audible piezoelectric effects.
trapezoidal current at the source of the high side MOSFET. The high Q of ceramic capacitors with trace inductance
To prevent large ripple current, a low ESR input capacitor can also lead to significant ringing. Nevertheless, higher

17
value, lower cost ceramic capacitors are now becoming Positive Linear Regulator Controller
available in smaller case sizes. Their high ripple current, The positive linear controller provides high level voltage to
high voltage rating and low ESR make them ideal for the level shifter. The linear regulator can provide a
switching regulator applications. However, care must be programmable output voltage. The output voltage is
taken when these capacitors are used at the input and regulated by the I2C controller.
output. When a ceramic capacitor is used at the input,
VIN, and the power is supplied by a wall adapter through Positive Linear Regulator Controller Short Circuit
long wires, a load step at the output can induce ringing at Protection
the input. At best, this ringing can couple to the output The positive linear regulator controller has a short circuit
and be mistaken as loop instability. At worst, a sudden protection. This function limits the current of the positive
inrush of current through the long wires can potentially linear regulator controller to 80μA if the VGH voltage is
cause a voltage spike at VIN large enough to damage the detected to be below 20%.
part.
Positive Linear Regulator Controller Fault
VCORE Synchronous Buck Over Current Protection Protection
The CM508 RI02 senses the inductor current that is flowing The positive linear regulator controller has a fault protection.
out the LXBK2 pin. The internal MOSFET will be turned This function disables the positive linear regulator
off if the peak inductor current reaches 3A (typ.). controller if the VGH voltage is detected to be below 80%.
The IC will shutdown if the VGH voltage remains below
VCORE Synchronous Buck Fault Protection 80% after 50ms.
The buck converter has a fault protection. This function
disables the buck converter if the OUTBK2 voltage is Positive Linear Regulator Controller, Temperature
detected to be below 75%. If the OUTBK2 voltage remains Compensation
below 75% after 50ms, the IC will shut down. The output voltage is temperature compensated and fully
adjustable from 20V to 40V. VTCOMP allows programming
HAVDD Synchronous Buck Over Current Protection between high and low voltage levels. Keep in mind that
The CM508 RI02 senses the inductor current that is flowing VTCOMP has a positive value and can be determined as
out the LXBK3 pin. The internal MOSFET will be turned below equation :
off if the peak inductor current reaches 2A (typ.). (RNTC // RTCOMP2 )
VTCOMP = VL ×
(RNTC // RTCOMP2 ) + RTCOMP1
HAVDD Synchronous Buck Short Circuit Protection
To limit the short circuit current, the device has a cycle- VGH = VTCOMP × 2 × 21
by-cycle current limit. To avoid the short circuit current
VL
from rising above the internal current limit when the output
is shorted to GND, the switching frequency is reduced as RTCOMP1
VTCOMP
well. The switching frequency is reduced to one-half of
original frequency when the HAVDD voltage is below 80% RNTC1 RTCOMP2
and to one fourth of the original frequency when the HAVDD
voltage is below 20%. If the short is removed, the buck
converter will restart operation. If the output voltage Figure 3. NTC Application Circuit
remains below 80% after 50ms, the IC will shut down.

18
The resistance of the NTC thermistor decreases nonlinearly Negative Linear Regulator Controller
with rising temperature Operation of the negative linear regulator is similar to the
1 1
−B ×( − ) positive linear regulator. The negative linear regulator
T0 T
RNTC (T) = RT0 × e provides low level voltage to the level shifter. The linear
where RT0 is the resistance at absolute temperature, T0 is regulator can provide a programmable output voltage.
the absolute temperature in Kelvin, and B is the material Similar to the positive linear regulator, the output voltage
constant. is also regulated by the I2C controller.
Figure 4 shows the VGH Temperature Compensation Under Voltage Lockout

curve. When VTCOMP under 1V, the VGH voltage will be
To prevent abnormal device operation caused by low input
equal VGH_L register (08h) setting voltage, and VTCOMP
voltages, an under voltage lockout is included which shuts
large than 2V, the VGH voltage will be equal VGH_L register
down the device at voltages lower than 8V. All functions
(08h) add VGH_H Offset register (09h) setting voltage.
will be turned off in this state.
VGH
VGHL + VGH_H Offset Power On Sequence
40V (MAX)
The CM508 RI02 provides six supply voltages, VAVDD,
VGH_L 20V (MIN) VI/O, VCORE, VHAVDD, VGH and VGL, with power on sequence
as shown below. The VI/O buck converter, VCORE buck
Temperature
converter, and negative charge pump driver are turned on
VTCOMP
when the supply voltage becomes larger than UVLO and
EN is in logic-high. The VGH positive charge pump is only
2V
1V enabled after the AVDD converter and VGL negative charge
pump are ready. The output voltages are all regulated by
Temperature the I2C controller.
T2 T1
Figure 4. VGH Temperature Compensation
VCORE
VIN VI/O Soft- VI/O Buck
Soft-Start
Power On Start Time Converter
Time
VGL VGL Negative

VCORE EN Pull
Soft-Start Charge Pump High
Buck Converter
Time Controller
AVDD Boost AVDD Boost

Isolation Switch Converter and HAVDD Converter and
Soft-Start Time Sync. Buck Converter HAVDD Sync. Buck
Soft-Start Time Converter
VGH VGH Positive

Soft-Start Charge Pump
Time Controller
Figure 5. Power On Sequence and Function Block

19
UVLO
VIN
3ms Buck1 (VI/O)
Buck1 (3.3V) 350µs
3ms
Buck2 (2.5V/1.2V)
Buck2 (VCORE)
VGL
3ms
EN
(From TCON)
10ms AVDD
AVDD Soft-Start 10ms or 20ms
AVDD Buck3 (HAVDD)
1
Buck3 ( x AVDD)
2 3ms
VGHP
GVOFF
VGH
VGHM
Figure 6. Timing Diagram
Register Description : DAC Register and EEPROM

Writes and reads can be made directly to the DAC register
to control and monitor the position without any nonvolatile
memory changes. This is done by setting address 00h to
0Bh and then writing the data. The nonvolatile memory
stores the power on value. When power on, the contents
of the Memory are transferred to the DAC register. To write
to the memory, first program all data registers (00h to
0Bh). Then, set the write data bit once all desired data
are addressed after power on. To write a new value to the
memory, set a new power on position and load the same
value into the DAC register. When write address FFh and
data register 80h, I2C interface will write all DAC register
data into EEPROM. Reading from the memory will not
change the DAC register if its contents are different.

20
I2C Command
Slave Address
7 6 5 4 3 2 1 = A0 0 = R/W
0 1 0 0 0 0 0 0 A0 = GND Write
0 1 0 0 0 0 1 0 A0 = DVDD Write
0 1 0 0 0 0 0 1 A0 = GND Read
0 1 0 0 0 0 1 1 A0 = DVDD Read
Write Command
(a) Write Single Byte to DAC Register
Example : Writing 29h to DAC Address 07h (BK3_OUT)
Start 0 1 0 0 0 0 A0 0 Slave 0 0 0 0 0 1 1 1 Slave 0 0 1 0 1 0 0 1 Slave Stop
ACK ACK ACK
(b) Write Multi Byte to DAC Register

Example : Writing 29h, 2Ah, 2Bh to DAC address 06h, 07h, 08h
Start 0 1 0 0 0 0 A0 0 Slave 0 0 0 0 0 1 1 0 Slave 0 0 1 0 1 0 0 1 Slave
ACK ACK ACK
0 0 1 0 1 0 1 0 Slave 0 0 1 0 1 0 1 1 Slave Stop

ACK ACK
(c) Write All DAC Register into EEPROM

Example : Write All DAC Register into EEPROM
ACK ACK ACK
Read Command
(a) Read data from DAC Register
Example : Reading Data from DAC Register Address 08h, 09h, 0Ah, 0Bh
ACK ACK ACK
Start 0 1 0 0 0 0 A0 0 Slave 0 0 0 0 0 0 0 1 Slave
ACK ACK
Start 0 1 0 0 0 0 A0 1 Slave D D D D D D D Master
D N-ACK D D D D D D D Master
D N-ACK
ACK
D D D D D D D D Master D D D D D D D Master Stop

D N-ACK
ACK
(b) Read Data from EEPROM

Example : Reading Data from EFPROM Address 03h, 04h, 05h, 06h
ACK ACK ACK
Start 0 1 0 0 0 0 A0 0 Slave 0 0 0 0 0 0 1 1 Slave
ACK ACK
Start 0 1 0 0 0 0 A0 1 Slave D D D D D D D Master
D N-ACK D D D D D D D Master
D N-ACK
ACK
D D D D D D D D Master D D D D D D D Master Stop

D N-ACK
ACK

21
VGH Temperature Compensation
VGH
VGHL + VGH_H Offset
40V (MAX)
VGH_L 20V (MIN)
Temperature
VTCOMP
2V
1V
Temperature
T2 T1
Register Map
MTP Factory
Channel Address Range Resolution Initialization Bit (Step)
Value
Channel Register 00h 00h to 3Fh -- 00h 8bits
13.5V (00h) to 19.8V
AVDD 01h 0.1V 16.8V (21h) 6bits (64 steps)
(3Fh)
HVS 02h 0 (0h) to 3V (Fh) 0.2V 1.6V (08h) 4bits (16 steps)
AVDD OCP
03h 0A (0h) to 2.8A (7h) 0.4A 1.6A (04h) 3bits (8 steps)
(Negative Offset)
AVDD Soft-Start
04h 10ms (0h) to 20ms (1h) 10ms 10ms (0h) 1bits (2 steps)
Time
Buck1 (VI/O) 05h 2.2V (0h) to 3.7V (Fh) 0.1V 3V (08h) 4bits (16 steps)
Buck2 (VCORE ) 06h 0.8V (00h) to 3.3V (19h) 0.1V 1.2 (04h) 5bits (32 steps)
Buck3 (HAVDD) 07h 4.8V (00h) to 11.1V (3Fh) 0.1V 8.1V (21h) 6bits (64 steps)
VGH_L 08h 20V (0h) to 35V (Fh) 1V 28V (08h) 4bits (16 steps)
VGH_H Offset 09h 0V (0h) to 15V (Fh) 1V 8V (08h) 4bits (16 steps)
GPM Stop Level 0Ah 0V (0h) to 15V (3h) 5V 5V (01h) 2bits (4 steps)
VGL 0Bh −14.5V (Fh) to −5.5V (0h) 0.6V −10.3V (08h) 4bits
Write Remain Time FEh Fh (fixed) -- 0Fh 4bits
Control Register FFh 0h to 81h -- 00h 8bits

22
Thermal Considerations Layout Consideration
For continuous operation, do not exceed absolute ` The power components must be placed as close to the
maximum junction temperature. The maximum power IC as possible to reduce current loop. The connections
dissipation depends on the thermal resistance of the IC between power components must be as short and wide
package, PCB layout, rate of surrounding airflow, and as possible due to large current flowing through these
difference between junction and ambient temperature. The traces during operation.
maximum power dissipation can be calculated by the ` The compensation circuit should be kept away from
following formula : the power loops and shielded with a ground trace to
PD(MAX) = (TJ(MAX) − TA) / θJA prevent any noise coupling.
where TJ(MAX) is the maximum junction temperature, TA is ` Minimize the size of the switching node and keep it
the ambient temperature, and θJA is the junction to ambient wide and short. Keep the switching node away from the
thermal resistance. feedback and analog ground.
For recommended operating condition specifications, the ` The exposed pad of the chip should be connected to
maximum junction temperature is 125°C. The junction to ground plane for maximum thermal consideration.
ambient thermal resistance, θJA, is layout dependent. For ` The power ground (PGND) consists of input and output
VQFN-40L 6x6 package, the thermal resistance, θJA, is capacitor grounds.
27°C/W on a standard JEDEC 51-7 four-layer thermal test
` The analog ground (AGND) consists of the grounds of
board. The maximum power dissipation at TA = 25°C can
compensation and soft-start capacitor.
be calculated by the following formula :
` Separate power ground (PGND) and analog ground
P D(MAX) = (125°C − 25°C) / (27°C/W) = 3.7W for
(AGND). Connect the AGND and PGND islands at a
VQFN-40L 6x6 package
single end. Make sure that there are no other
The maximum power dissipation depends on the operating connections between these separate ground planes.
ambient temperature for fixed T J(MAX) and thermal
resistance, θJA. The derating curve in Figure 7 allows the
designer to see the effect of rising ambient temperature
on the maximum power dissipation.
4.0
Maximum Power Dissipation (W)1
Four-Layer PCB
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
0 25 50 75 100 125
Ambient Temperature (°C)
Figure 7. Derating Curve of Maximum Power Dissipation

23
Add a ground trace to prevent PGND consists of input and output

any noise between the switching capacitor grounds and should be wide and
node (SWBK1) and OUTB1 pin. short enough to connect to a ground plane.
PGND
VI/O VCORE
OUTBK1
OUTBK2
The exposed pad of the chip BSTBK1
SWBK1
SWBK1
SWBK2
GVOFF
INBK2
PGND
should be connected to ground
plane for thermal consideration.
EN
40 39 38 37 36 35 34 33 32 31 HAVDD
PGND INBK1 1 30 OUTBK3

VIN
INBK1 2 29 PGND
NC 3 28 SWBK3
SDA 4 27 BST3 PGND
Connect this pin with a SCL 5 26 INBK3

PGND
decoupling capacitor. A0 6 25 RE
HVS 7 24 VGHM
VIN
INVL 8 23 VGHP
AGND AGND 9 22 DRVP
COMP 10 21 DRVN
11 12 13 14 15 16 17 18 19 20
SWI
VL
SW1
SW1
VGL
NTC
PGND
PGND
NC
SWO
Connect this pin with a

The compensation circuit should decoupling capacitor.
be kept away from the power
loops and shielded with a ground Minimize the size of the LX1 node and keep
trace to prevent noise coupling. AGND PGND its traces as wide and short as possible.
VIN AVDD Keep the switching node away from the
analog ground, SWI and SWO pins.
Add a ground trace to
PGND prevent any noise between
Place the power components as close to the the LX1 node and SWI pin.
IC as possible. The traces should be wide
and short especially for the high current loop.
Figure 8. PCB Layout Guide

24
Outline Dimension
D D2 SEE DETAIL A
L
1
E E2
e b 1 1
2 2
A
A3 DETAIL A
A1
Pin #1 ID and Tie Bar Mark Options
Note : The configuration of the Pin #1 identifier is optional,

but must be located within the zone indicated.
Dimensions In Millimeters Dimensions In Inches

Symbol
Min Max Min Max
A 0.800 1.000 0.031 0.039
A1 0.000 0.050 0.000 0.002
A3 0.175 0.250 0.007 0.010
b 0.180 0.300 0.007 0.012
D 5.950 6.050 0.234 0.238
D2 4.000 4.750 0.157 0.187
E 5.950 6.050 0.234 0.238
E2 4.000 4.750 0.157 0.187
e 0.500 0.020
L 0.350 0.450 0.014 0.018
V-Type 40L QFN 6x6 Package
Richtek Technology Corporation

5F, No. 20, Taiyuen Street, Chupei City
Hsinchu, Taiwan, R.O.C.
Tel: (8863)5526789
Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should
obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot
assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be
accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.

25
Datasheet Revision History

Version Data Page No. Item Description
P00 2010/11/24 First Edition
Ordering and Marking Information
Pin Configurations
P01 2011/5/6 Functional Pin Description Modify
Application Information
Pin Configurations
Timing Diagram
Functional Pin Description
P02 2011/7/26 Modify
Absolute Maximum Ratings
P03 2011/12/15 Application Information Modify
New Format (some item)
Part Number
Typical Application Circuit Modify
P04 2012/5/2
Typical Operating Characteristics CM508 to CM508-RI01
Part Number
Typical Application Circuit Modify
P05 2012/7/13
Typical Operating Characteristics CM508-RI01 to CM508-RI02
Application

26

CM508 Ri02 P05T00

Diunggah oleh

Informasi Dokumen

Judul Asli

Hak Cipta

Format Tersedia

Bagikan dokumen Ini

Bagikan atau Tanam Dokumen

Opsi Berbagi

Apakah menurut Anda dokumen ini bermanfaat?

Apakah konten ini tidak pantas?

Hak Cipta:

Format Tersedia

CM508 Ri02 P05T00

Diunggah oleh

Hak Cipta:

Format Tersedia

®

Preliminary CM508 RI02

Programmable Power Management IC for LCD Panels

supply voltage. ` Current Limit Protection

Buck Regulator for VI/O

Sync. Buck Regulator for VCORE

` 0V to 15V Gate Shaping Voltage

` −5.5V to −14.5V Programmable Output

CM508 RI02-P05T00 July 2012 www.richtek.com

Typical Application Circuit

www.richtek.com CM508 RI02-P05T00 July 2012

Figure 1. Power Sequence Timing Diagram

CM508 RI02-P05T00 July 2012 www.richtek.com

Functional Pin Description

www.richtek.com CM508 RI02-P05T00 July 2012

Function Block Diagram

INVL LX1 SWI SWO

CM508 RI02-P05T00 July 2012 www.richtek.com

Absolute Maximum Ratings (Note 1)

Recommended Operating Conditions (Note 4)

www.richtek.com CM508 RI02-P05T00 July 2012

CM508 RI02-P05T00 July 2012 www.richtek.com

Parameter Symbol Test Conditions Min Typ Max Unit

www.richtek.com CM508 RI02-P05T00 July 2012

CM508 RI02-P05T00 July 2012 www.richtek.com

Parameter Symbol Test Conditions Min Typ Max Unit

www.richtek.com CM508 RI02-P05T00 July 2012

VIN = 12V, VAVDD = 16.8V VIN = 12V, VI/O = 3V

CM508 RI02-P05T00 July 2012 www.richtek.com

Output Voltage (V)

Output Voltage (V)

VIN = 12V, VGH = 28V VIN = 12V

VAVDD = 16.8V, IAVDD = 0.1A VCORE = 1.2V, IVCORE = 0.1A

www.richtek.com CM508 RI02-P05T00 July 2012

Integral Nonlinearity (LSB)1

Integral Nonlinearity (LSB)1

Integral Nonlinearity (LSB)1

CM508 RI02-P05T00 July 2012 www.richtek.com

AVDD OCP INL Error vs. DAC Setting Power On Sequence

VIN = 12V, VI/O = 3V, VCORE = 1.2V, VGL = −10.3V

Enable Sequence (Normal) Enable Sequence (VGL with LX1)

Time (5ms/Div) Time (5ms/Div)

www.richtek.com CM508 RI02-P05T00 July 2012

CM508 RI02-P05T00 July 2012 www.richtek.com

consideration. A suitable Schottky diode's reverse voltage Loop Compensation

www.richtek.com CM508 RI02-P05T00 July 2012

CM508 RI02-P05T00 July 2012 www.richtek.com

www.richtek.com CM508 RI02-P05T00 July 2012

Figure 4 shows the VGH Temperature Compensation Under Voltage Lockout

Figure 4. VGH Temperature Compensation

VGL VGL Negative

AVDD Boost AVDD Boost

VGH VGH Positive

Figure 5. Power On Sequence and Function Block

CM508 RI02-P05T00 July 2012 www.richtek.com

Figure 6. Timing Diagram

Register Description : DAC Register and EEPROM

www.richtek.com CM508 RI02-P05T00 July 2012

(b) Write Multi Byte to DAC Register

0 0 1 0 1 0 1 0 Slave 0 0 1 0 1 0 1 1 Slave Stop

(c) Write All DAC Register into EEPROM

D D D D D D D D Master D D D D D D D Master Stop

(b) Read Data from EEPROM