SVE-504P

A lab report on

Double Gate (DG) MOSFET using TCAD

By-
R.Siva (31811207)
T.Sarath Chandra (31811208)
Atul Kumar Singh (31811209)

SCHOOL OF VLSI DESIGN & EMBEDDED SYSYTEM

NATIONAL INSTITUTE OF TECHNOLOGY
KURUKSHETRA

SUBMITED TO:
Dr. Gaurav Saini

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 List of Content

1. Abstract
2. Introduction
3. Operation of DGMOSFET
4. Types of DGMOSFET
5. Features of DGMOSFET
6. Structure and materials used
7. Results and simulations images
8. Steps for TCAD implementations
9. Conclusion
10. Precautions

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 List of Figures

1. Basic block diagram of DGMOSFET

2. Symmetric DGMOSFET
3. Asymmetric DGMOSFET
4. Dimensions
5. DGMOSFET TCAD image
6. DGMOSFET with mesh
7. Conduction band diagram of DGMOSFET in saturation region
8. Conduction band diagram of DGMOSFET in linear region
9. ID vs VGS graph
10. DIBL graph
11. Sub-threshold graph

List of Tables

1. Types of materials and concentration

2. Dimensions of the regions

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 1. ABSTRACT

Scaling the MOSFET below 50nm, there is an increase in DIBL, Channel length
modulation, gate leakage. Increase in sub threshold slope will attribute to decrease in gate
coupling to the channel. Traditional technique is reducing the oxide thickness but this will
result in leakages and increase of power consumption, suggested solution is use high K
material for oxide but there is compatibility issues with the silicon. Hence one of the
suggested method is use of two gates, Double Gate (DG) MOSFET. Threshold voltages,
Ion and Ioff current, DIBL, Sub Threshold conditions are simulated using TCAD.

2. INTRODUCTION

If the MOSFET technology is reduced below 50nm there will be increase in DIBL, Channel
length modulation, and gate leakage. As the gate length decreases the capacitive control of
the channel potential by the gate will become difficult. This results in the short channel
effects, such as increase in I off leakage current, roll off in threshold voltage, DIBL.
For suppressing the SCE in bulk devices other parameters have been scaled down together
with gate length, for oxide thickness, channel depletion width and source/drain junction
capacitance. Thin oxide thickness increases the capacitive control of gate over channel, but
will result in leakages.
For selection or designing of a device that has high control over the channel and other
effects many methods are introduced. One of the technique is Double Gate MOSFET. This
device have control of Silicon channel very effectively by choosing the width of silicon

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channel to be very small and applying the gate voltage both sides. This idea is favorable
for scaling the CMOS below 50nm gate length.
There are two types of MOSFET technologies they are normal structure and underlap
structure, which will be discussed later.
In section 2 the operation of the DG MOSFET is described, like modes of operation. In
section 3 types of DGMOSFETS. In section 4 features of the MOSFET is discussed. In
section 5 DG MOSFET structure, material used and types of doping is discussed. In section
6 results are shown for the defined structure. Section 7 will conclude the topic.

3. OPERATION OF DGMOSFET

A basic block diagram of the DGMOSFET is shown below. The other gate is kept exactly
opposite to the first gate as shown in the fig1.1.

MOSFET device can be of types based on the length of the gate

 Normal MOSFET- in which gate length and channel length are same
 Underlap MOSFET- in which gate length is smaller than channel length

As we can see, due to the two gates the MOSFET can be used in two types of operations,
like
 Both the gate can be used with same voltages.
 Both are used at different voltages.
 Both can of same material
 both can be different materials

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 Fig: 1.1 Basic Block Diagram of DGMOSFET [1]

The most common mode of operation of the DG MOSFET is to modify the 2 gates at
the same time. Another use of the 2 gates is to modify only 1 gate and apply a bias to
the second gate to dynamically alter the VTH (Threshold voltage) of the field-effect
transistor. During this mode of operation, also called as “Ground Plane” (GP) or Back
Gate (BG).The sub threshold slope is determined by the magnitude relation of the
switching gate capacitance and the series combination of the channel capacitance and
the non-switching gate capacitance. A thin oxide dielectric at the non-switching gate
reduces the voltage needed to regulate the VTH and preserves the drain-field shielding
advantage of the double-gate device structure. Because of the presence of 2 gates every
gates management the 1/2 the device and the operation is totally freelance of the
opposite. Then the overall current of the device is equal to the sum of the 2 channels.
The relative scaling advantage of Double Gate MOSFET is regarding two occasions.
The performance of isosceles version of Double Gate MOSFET is increase by the upper
channel quality as compared to bulk MOSFET. Since the common force field of the
channel that is made within the device is lower that decrease the interference roughness
scattering per universal quality model.

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 4. TYPES OF DG MOSFET

DG MOSFET can be design in two ways they are

 Symmetric DG MOSFET (SDG)

Fig: 1.2 Symmetric DGMOSFET [1]

In Symmetric DG MOSFET both the gates have identical material and work perform as
shown in fig 1.3. The each gate tied with same bias. At ON-state, the 2 channels (inversion
layers) are formed on the 2 sides of silicon body of the SDG device. These channels
conduct at identical time. In addition the SDG device shows higher carrier quality thanks
to its lower cross force field as compared to the ADG device. The structure of symmetric
DG MOSFET is as shown in fig 1.3.

 Asymmetric DG MOSFET (ADG)

Fig: 1.3 Asymmetric DGMOSFET [1]

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In Asymmetric DG MOSFET both the gates have completely different material or work
functions as shown in fig three. These have 2 completely different work functions of each
the gates. DG MOSFET switch may be obtained by applying completely different voltage
at each the gate. Only 1 channel is created for the ADG device unless the operation
voltage is very high to make the opposite inversion layer close to the P+ gate. The edge
voltage of Associate in Nursing ADG MOSFET may be adjusted by ever-changing the
body thickness (Tsi) and/or the gate-oxide thickness (Tox), while not the requirement for
exotic gate materials.

5. FEATURES OF DG MOSFET
 The Control of short-channel effects by device geometry as compared to bulk
MOSFET, where the short-channel effects are controlled by doping.
 A thin silicon channel leading to tight coupling of the gate potential with the
channel potential.

These features provide potential DG MOSFET advantages that include

 Reduced 2D short-channel effects leading to a shorter allowable channel length.

 A sharper sub threshold slope which allows for a larger gate overdrive for the same
power supply and the same off current.
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𝑆 = 2.3
𝑞 𝜕𝑉𝑔𝑠
 Better carrier transport as the channel doping is reduced or the channel can be
undoped.
 The potential advantages in Double Gate MOSFETs allows for higher current
derive capability.
 The gate capacitance is also double due to the presence of double gate in device
(per device areas).

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 6. STRUCTURE AND MATERIAL USED

Basic structure of the designed DG MOSFET is given below.

1.4 Dimensions of DG MOSFET

Materials and required concentration used in the DG MOSFET are given below
N-type Silicon (phosphorous)
Source/Drain
Concentration = 1x 1020 cm-3
Gate Metal (work function 4.72eV)
Oxide SiO2
Spacer Si3N4
P-type silicon (boron)
Channel
Concentration = 1x 1017 cm-3
Table 1.1 Type of Materials and Concentration

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Dimensions of the regions in DGMOSFET
SN Parameter Values
1 Channel length 30 nm
2 Channel width 20 nm
3 Gate length 20 nm
4 Spacer length 20 nm
5 Spacer width 20 nm
6 Oxide thickness 2 nm
7 Source and drain length 50 nm
8 Source and drain width 60 nm
Table 1.2 Dimensions of the Regions

The DG-MOSFET is designed with above specifications. The threshold voltage of 0.233
V is considered for its performance analysis. A metal (gate) work function used is 4.72 eV.
The material used for source, channel and drain is silicon. Si3N4 is used as spacer between
gate and source/drain. SiO2 is used as an oxide between the gate and channel. Here we have
considered an underlap structure (gate length is less than channel length). The n-type
material used for doping is phosphorus and the p type material used is boron.

Here two types of doping are done 1. Constant doping profile and 2. Analytical doping
profile. In constant doping profile the doping will be constant and uniform overall the
region for the given concentration. In analytical doping profile the doping will non-uniform
like at one place there will be high doping(1020) and in one place there will be low(10 17).
As the device is underlap MOSFET the gate length is smaller than the channel length. We
implement the design using the TCAD and there are some steps to be followed for
eliminating the wrong design procedure. In the TCAD there is a feature called meshing
which helps in selecting the point of interest where the equations should be performed. If

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the mesh concentration if high then it will take more time to calculate and less
concentration takes less time.

7. RESULTS AND GRAPHS

7.1 TCAD implementation of the DG MOSFET.

Fig 1.5 DGMOSFET TCAD Image

Fig 1.6 DG MOSFET (with mesh)

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7.2 Conduction band diagrams of the DGMOSFET in linear region and saturation regions
are given below.

Fig 1.7 Conduction Band diagram of DGMOSFET in Saturation Region

Fig 1.8 Conduction Band diagram of DGMOSFET in Linear Region

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7.3 Output Graphs

Fig 1.9 ID vs VGS Graph

Fig 1.10 DIBL Graph

Fig 1.11 Sub-Threshold Swing

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 8. STEPS FOR TCAD SIMULATION
Step 1: Create a folder- right click - open the terminal → type “sde”-synopsis TCAD tool
will open.
Step 2: Go to File → Journal → On → <name of file>.jrl → Open
Step 3: Go to Draw → Uncheck “Auto region naming” (so that we can name the regions)
Step 4: Go to Draw → Check “Exact coordinates” (for defining exact coordinates)
Step 5: Select rectangle in toolbar → Select Silicon material in → Draw the silicon
region → Name the region → Ok
Step 6: Select Si3N4 material → Draw the spacer region → Name the region → Ok
Step 7: Select SiO2 material → Draw the oxide region → Name the region → Ok
Step 8: Select Metal material → Draw the gate region → Name the region → Ok
Step 9: Contacts → Contact sets → Contact name<source, drain, gate> (use different
color combinations for each contact) → Set
Step 10: Select any of the Defined contact sets → Activate →Close (Can be done
alternatively by selecting any defined contact sets from the drop down menu in the
toolbar)
Step 11: in tool bar select “Select Edge” → right click on corresponding edge → go to
Contacts → Set contact (after this the contact will set if the set contact is not clicked then
the contact will not set )
Step 12: Device → Constant profile placement → Give placement name → Select
Region → Give constant profile definition name → Select doping species → Enter
doping concentration → Add placement → Close
Step 13: Mesh → Define Rel/Eval Window → Line(Draw line where there should
be peak concentration) → Name the line → Ok
Step 16: Device → Analytical profile placement → Give placement name → Select
Ref/Win (line where there has to be peak concentration) → Give profile definition name
→ Select species → Select profile type as Gaussian → Enter peak doping concentration
→ Enter peak position(0 in this case as the line is drawn at the peak position) → Select
Junction → Enter doping concentration at junction → Enter depth of junction from the
line → Select needed Eval Direction → Add placement → Close
Step 17: File → Save Model As → Give File Name → Click on Save

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Step 18: Mesh → Define Rel/Eval Window → Rectangle(select different regions for
analysis)
Step 19: Mesh → Refinement placement → Give Placement Name → Select Rel/Eval
Window → Give Refinement definition Name → Give the maximum and minimum
element size → Create refinement → Close
Step 20: Mesh → Build Mesh → Build Mesh
Step 21: Open folder → Right click to open terminal → type “sdevice –P:Metal”
Step 22: Open “models.par” file in the folder that is in the folder and change the work
function of the metal to 4.72 eV → Save the file
Step 23: Copy the following files to the folder: lin_des.cmd, sat_des.cmd (edit the
voltage and current values for the linear and saturation regions) → Open the terminal
→ sdevice <X>_des.cmd (edit the voltage and current values for the linear and
saturation regions)
Step 24: Copy the following files to the folder: Vti_ins.cmd, ionioff_ins.cmd,
dibl_ins.cmd, SS_ins.cmd
Step 25: Set proper current level in the above files.
Step 26: Open terminal → type “inspect –f <X>_ins.cmd” → save the graphs →
Record the values

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 9. CONCLUSION
 Double gate MOSFET has been designed with following parameters:
 On current (Ion) = 8.431×10-4 A/µm
 Off current (Ioff) = 1.447×10-9 A/µm
Ion
 = 5.83 × 105
Ioff
 Sub threshold swing = 84.094 mV/decade
 DIBL = 127 mV/V

10. PRECAUTIONS
 Take all measurements in µm
 Do proper meshing, meshing should be dense at critical areas
 Check the log file if the Newton method is converged properly or not before
calculating the parameters
 Set proper work function to get the desired threshold voltage
 Set the current level before calculating SS and DIBL

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