Manual Parte-1 PDF

Operations & Maintenance Manual
Manual P/N 572100-0001
MODEL 2100
SINGLE FREQUENCY
LOCALIZER SYSTEM
Equipment Part Number 002100-0103 (Single),-0104 (Dual)
THIS DOCUMENT CONTAINS PROPRIETARY INFORMATION AND SUCH

INFORMATION MAY NOT BE DISCLOSED TO OTHERS FOR ANY
PURPOSES WITHOUT WRITTEN PERMISSION FROM
AIRPORT SYSTEMS INTERNATIONAL, INC.
Original Issue June, 1999

Rev. A September, 1999
Rev. B September, 1999
Rev. C July, 2000
Copyright, Airport Systems International, Inc., 1999 - 2000

11300 West 89th Street
Overland Park, KS U.S.A. 66214
THIS PAGE INTENTIONALLY BLANK
Airport Systems International, Inc.
LIST OF EFFECTIVE PAGES
REVISION A
Page No. Issue Page No. Issue
Title Page thru Warranty September 1999
i thru xviii September 1999
1-1 thru 1-16 September 1999
REVISION B
Title thru Record of Revisions September 1999
7-2 September, 1999
REVISION C
Title Page thru Warranty July 2000
i thru xx July 2000
1-1 thru 1-18 July 2000
2-1 thru 2-102 July 2000
3-1 thru 3-100 July 2000
4-1 thru 4-10 July 2000
5-1 thru 5-6 July 2000
6-1 thru 6-58 July 2000
7-1 thru 7-10 July 2000
8-1 thru 8-16 July 2000
9-1 thru 9-42 July 2000
10-1 thru 10-4 July 2000
11-1 thru 11-151 July 2000

Overland Park, KS U.S.A. 66214
Rev. C July, 2000 Effective Pages 1

This document contains proprietary information and such information may
not be disclosed to others for any purposes without written permission from
Effective Pages 2 Rev. C July, 2000

RECORD OF REVISIONS
Page Revision Insertion Page Revision Insertion
Number Date Number Date
Level Date Level Date
Title Page C 7/2000
thru Warranty
i thru xx C 7/2000
1-1 thru 1-18 C 7/2000
2-1 thru C 7/2000
2-102
3-1 thru C 7/2000
3-100
4-1 thru 4-10 C 7/2000
5-1 thru 5-6 C 7/2000
6-1 thru 6-58 C 7/2000
7-3 thru 7-10 C 7/2000
8-1 thru 8-16 C 7/2000
9-1 thru 9-42 C 7/2000
10-1 thru C 7/2000
10-4
11-1 thru C 7/2000
11-151
Rev. C July, 2000 Effective Pages 3

Effective Pages 4 Rev. C July, 2000

MODEL 2100 SINGLE FREQUENCY LOCALIZER
SAFETY SUMMARY
The following are general safety precautions that are not related to any specific procedures and therefore do
not appear elsewhere in this publication. These are recommended precautions that personnel must understand
and apply them during many phases of operation and maintenance.
ELECTROSTATIC SENSITIVE DEVICES PRECAUTIONS
Since most modules used in all models of equipment have Electrostatic Discharge (ESD) sensitive devices
included in them, all modules should be considered sensitive to electrostatic discharge. Handling in the field
shall be the same as in the factory. Each system is shipped with a wrist strap that must be worn while
maintaining the equipment. The wrist strap shall be fastened to the equipment chassis either in the designated
plug-in or attached to the equipment chassis with the alligator clip. The wrist strap must be used before any
modules are removed from the equipment and at all times while handling the modules until they are placed
in a protective environment such as an anti-static bag. Modules or boards must not be placed on any non-
conducting surface such as wooden work benches, painted metal work benches, plastics, or technical
manuals. Any work surface to be used must have a conducting mat placed on it and attached to earth
ground. The mat and additional wrist straps can be obtained from Airport Systems International, Inc.
KEEP AWAY FROM LIVE CIRCUITS
Operating personnel must at all times observe all safety regulations. Under no circumstances should any
person remove any protective covers that expose lethal voltages. Do not replace components or make
adjustments inside the equipment with primary power supply turned on. Under certain conditions, dangerous
potentials may exist when the power is in the off position, due to charges retained by capacitors. To avoid
casualties, always remove power and allow time for the capacitors to discharge before touching it.
DO NOT SERVICE OR ADJUST ALONE
Under no circumstances should any person reach into or enter the enclosure for the purpose of servicing or
adjusting the equipment except in the presence of someone who is capable of rendering aid.
RESUSCITATION
Personnel working with or near high voltages should be familiar with modern methods of resuscitation.
The equipment is supplied by Airport Systems International, Inc. For replacement parts and repair service,
contact Airport Systems International, Inc.
HOW TO ORDER REPLACEMENT PARTS
When ordering replacement parts, you should direct your order as indicated below and furnish the following
information insofar as applicable. To enable us to give better replacement service, please be sure to give us
complete information.
INFORMATION REQUIRED
1. Airport Systems International, Inc. model number, type and serial number of equipment.
2. Unit sub-assembly number (where applicable).
3. Item or reference symbol number from parts list or schematic.
4. Airport Systems International, Inc. part number and description.
5. Manufacturer's code, name and part number (where applicable).
6. Quantity of each replacement part required.
CORRESPONDENCE/SHIPPING ADDRESS

Overland Park, Kansas 66214
U.S.A.
COMMUNICATIONS
Telephone: 913/492-0861
Telex: 49610240 Airport Sys Int
Fax: 913/492-0870

MANUFACTURER'S WARRANTY
A. The Manufacturer warrants to the original purchaser, subject to the limitations and exclusions stated
below, that all mechanical and electrical parts of products which it manufactures (the "Products") will be free
of defects in materials and workmanship for a period of (i) one year from the date of installation or (ii) eighteen
(18) months from the date of shipment, whichever first occurs (the "Warranty Period").
B. If the Customer believes a Product is defective, notice thereof shall be provided to the Manufacturer's
Customer Service Department at the address provided on the cover page and (if applicable) to the selling
Distributor. A defect in materials and workmanship covered by this warranty shall be deemed to have occurred
only if, and as of the time when, the Manufacturer is notified in writing by the Customer, within the Warranty
Period, that the Product has become defective, and the Manufacturer's personnel verify that the said Product,
in fact, does not comply with the warranty provided hereunder and it is determined that:
(i) The Products, during the entire Warranty Period, have been operated within normal service conditions
recommended by the Manufacturer and recognized in the industry, and
(ii) The Products have been installed and adjusted according the Manufacturer's procedures as stated
in the Instruction Manual or other instructions supplied in writing by the Manufacturer.
C. Failures caused by lightning or other acts of God, or power surges, are not considered to be defects
in materials and workmanship and are not covered under this warranty. Routine maintenance and calibration
are also not considered to be defects in materials and workmanship and are not covered under this warranty,
Any change, modification or alteration of the Manufacturer's Products not specifically authorized by the
Manufacturer will void this warranty.
D. Any circuit board or module returned to the factory for warranty coverage, must be enclosed in an
electrostatic sensitive device (ESD) protective wrapping. If circuit board or module is not received in an ESD
protective wrap, any and all warranty will be null and void.
E. If it is determined that the conditions for warranty coverage, as described above, have been satisfied,
the Manufacturer shall repair or replace the defective Products or parts thereof in accordance with the following
procedures:
(i) Customer will contact the Manufacturer's Customer Service Department which will issue the Customer
a Return Authorization (RA) number.
(ii) The component, defective part, or Product, as appropriate, shall be returned to the Manufacturer
for inspection, freight prepaid by the Customer. The RA number must be clearly displayed on the exterior
of the shipping container. No shipments will be accepted without a RA number. All customs duties,
fees, etc. will be paid by the Customer.

MANUFACTURER'S WARRANTY
(Cont)
(iii) If, upon inspection, it is determined by Manufacturer's personnel that the Product or component
thereof is indeed defective and covered by this warranty, then Manufacturer, at its option, may either
repair the Product or defective component thereof and return the same to the Customer or ship a
replacement for the defective Product or part thereof, freight paid. All customs duties, fees, etc. will
be paid by the Customer. The Product or component thereof will be returned to the customer utilizing
a shipping mode similar to that used by Customer to ship the same to the Manufacturer.
(iv) If, upon inspection by Manufacturer, it is determined that the Product or component thereof was
not defective or was not covered by this warranty, then the cost of all of Manufacturer's inspections
and the return shipping charges will be charged to Customer.
F. The Manufacturer reserves the right to make modifications and alterations to Products without obligation
to install such improvements on, in, or in place of theretofore manufactured Products of Manufacturer.
G. Manufacturer does not warranty any Products, components, subassemblies, or parts not of its own
manufacture. Manufacturer hereby transfers to Customer any and all warranties (if any) which it receives
from its suppliers.
H. This warranty applies only to the original purchaser and, unless Customer receives the express written
consent of an officer of Manufacturer, this warranty may not be assigned, transferred, or conveyed to any
third party, even if the third party is a bona a fide purchaser of the Products.
I. THIS WARRANTY IS EXPRESSLY IN LIEU OF ALL OTHER WARRANTIES, EXPRESSED

OR IMPLIED, WHETHER STATUTORY OR OTHERWISE, INCLUDING AND IMPLIED WARRANTY
OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL
THE MANUFACTURER BE LIABLE FOR INDIRECT, INCIDENTAL, COLLATERAL, PUNITIVE,
OR CONSEQUENTIAL DAMAGES OF ANY KIND, WHETHER ARISING OUT OF CONTRACT,
TORT, NEGLIGENCE, STRICT LIABILITY, OR OTHER PRODUCTS LIABILITY THEORY.
J. CUSTOMER'S SOLE REMEDY FOR ANY BREACH OF THE WARRANTY SHALL BE

THE REPAIR OR REPLACEMENT OF THE PRODUCTS BY THE MANUFACTURER AS PROVIDED
HEREIN, AND IN NO EVENT SHALL THE MANUFACTURER BE REQUIRED TO INCUR COSTS
FOR THE REPAIR OR REPLACEMENT OF ANY PRODUCT IN EXCESS OF THE PURCHASE
PRICE OF SUCH PRODUCT, PLUS ANY TRANSPORTATION CHARGES ACTUALLY PAID
ATTRIBUTABLE TO SUCH PRODUCTS.
TABLE OF CONTENTS
SECTION 1. GENERAL INFORMATION AND REQUIREMENTS
Paragraph Description Page
1.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

1.2 EQUIPMENT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
1.2.1 General Design Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
1.2.1.1 Localizer Electronic Subsystem. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
1.2.1.2 Localizer Antenna System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
1.2.2 Monitoring System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
1.2.3 Localizer Far Field Monitor System (Optional) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
1.2.4 Localizer Near Field Monitor (Optional) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
1.2.5 Station Control System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
1.2.5.1 Control System Features Provided . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
1.2.6 Remote Maintenance Monitoring System (RMM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
1.2.6.1 RMM Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
1.2.6.2 RMM Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9
1.3 ELECTRONIC EQUIPMENT CABINET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10
1.3.1 Local Control Unit (1A1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11
1.3.2 Local Control CCA (1A1A1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12
1.3.3 Synthesizer Assembly CCA (1A2/1A14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12
1.3.4 Power Amplifier Assembly (1A22/1A24) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12
1.3.5 Battery Charging Power Supply (BCPS) CCA (1A6/1A10) . . . . . . . . . . . . . . . . . . . 1-12
1.3.6 RMS Processor CCA (1A8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13
1.3.7 Cabinet Interface CCA (1A18) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13
1.3.8 AC Power Monitor CCA (1A17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13
1.3.9 Main Power Supply Assembly (1A20/1A21) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13
1.4 EQUIPMENT SPECIFICATION DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14
1.5 EQUIPMENT AND ACCESSORIES SUPPLIED . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16
1.6 EQUIPMENT REQUIRED BUT NOT SUPPLIED . . . . . . . . . . . . . . . . . . . . . . . . . 1-17
1.7 OPTIONAL EQUIPMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17
Rev. C July, 2000 i

TABLE OF CONTENTS
SECTION 2. TECHNICAL DESCRIPTION
2.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

2.2 SINGLE FREQUENCY LOCALIZER OPERATION . . . . . . . . . . . . . . . . . . . . . . . . 2-1
2.3 2100 ILS LOCALIZER TRANSMITTER THEORY OF OPERATION . . . . . . . . . . . 2-4
2.3.1 Synthesizer Assembly (012012) (1A2/1A14) Theory of Operation . . . . . . . . . . . . . . . 2-8
2.3.1.1 Synthesizer CCA (1A2/1A14) Block Diagram Theory . . . . . . . . . . . . . . . . . . . . . . . . 2-9
2.3.1.2 Synthesizer CCA (1A2/1A14) Detailed Circuit Theory . . . . . . . . . . . . . . . . . . . . . . . 2-10
2.3.1.2.1 RF Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
2.3.1.2.2 Audio Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12
2.3.2 Power Amplifier (030676) (1A22/1A23/1A24/1A25) Theory of Operation . . . . . . . 2-17
2.3.2.1 Operation of the CSB AM Modulator and Power Amplifier. . . . . . . . . . . . . . . . . . . . 2-17
2.3.2.2 Operation of the AM Modulation Feedback Loop. . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18
2.3.2.3 CSB Phase Feedback Loop Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20
2.3.2.4 Transmitter Enable/Disable Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21
2.3.2.5 SBO Modulator and Power Amplifier Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21
2.3.2.6 Operation of the SBO Channel Bi-Phase Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23
2.3.2.7 Operation of the SBO Channel Phase Lock Loop. . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23
2.3.3 Monitor CCA (1A3/1A13) Theory of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25
2.3.3.1 Monitor CCA (1A3/1A13) Block Diagram Theory. . . . . . . . . . . . . . . . . . . . . . . . . . 2-25
2.3.3.2 Monitor CCA (1A3/1A13) Detailed Circuit Theory. . . . . . . . . . . . . . . . . . . . . . . . . . 2-26
2.3.3.2.1 Audio Signal Conditioning. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-26
2.3.3.2.2 Digital Signal Processing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-30
2.3.4 RMS CCA Theory of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-36
2.3.4.1 RMS CCA (012015)(1A8) Block Diagram Theory . . . . . . . . . . . . . . . . . . . . . . . . . . 2-36
2.3.4.1.1 Test Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-36
2.3.4.1.2 Microprocessor and Associated Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-38
2.3.4.1.3 Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-38
2.3.4.1.4 Parallel Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-38
2.3.4.1.5 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-38
2.3.4.2 RMS CCA (012015)(1A8) Detailed Theory of Operation. . . . . . . . . . . . . . . . . . . . . 2-39
2.3.4.2.1 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-39
2.3.4.2.2 Microprocessor and Associated Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-39
2.3.4.2.2.1 Address Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-40
2.3.4.2.2.2 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-41
2.3.4.2.2.3 Power Fail, Reset, and Watchdog Functions (U3) . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-41
2.3.4.2.2.4 Real Time Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-42
ii Rev. C July, 2000

TABLE OF CONTENTS
2.3.4.2.3 ILS Test Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-43

2.3.4.2.5 Station Configuration Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-45
2.3.4.2.6 Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-46
2.3.4.2.7 SVD Modem. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-47
2.3.4.2.8 BCPS Control and Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-49
2.3.5 AC Power Monitor CCA (012017) (1A17) Theory of Operation. . . . . . . . . . . . . . . . 2-49
2.3.6 Cabinet Interface CCA (012013) (1A18) Theory of Operation. . . . . . . . . . . . . . . . . . 2-51
2.3.7 Local Control Unit (1A1) Simplified Theory of Operation . . . . . . . . . . . . . . . . . . . . 2-61
2.3.7.1 Local Control Unit (1A1) Block Diagram Theory . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-62
2.3.7.1.1 DC to DC Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-62
2.3.7.1.2 Power Fail Detectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-62
2.3.7.1.3 Key Switch Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-62
2.3.7.1.5 1.8432MHz Oscillator/Divider Chains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-62
2.3.7.1.6 Positive Alarm Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-63
2.3.7.1.7 Negative Alarm Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-63
2.3.7.1.8 20 Second Delay Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-63
2.3.7.1.9 LCU Transfer Control State machine #1 & #2 & Discrete Controls . . . . . . . . . . . . . 2-63
2.3.7.1.10 LED Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-65
2.3.7.1.11 Audible Alarm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-65
2.3.7.1.12 Wattmeter State machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-65
2.3.7.2 Local Control Unit CCA (1A1A1) Detailed Theory of Operation . . . . . . . . . . . . . . . 2-65
2.3.7.2.1 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-65
2.3.7.2.2 Pushbutton Switches and LED Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-66
2.3.7.2.4 Monitor Alarm Interface Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-69
2.3.7.2.5 Station Control Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-70
2.3.7.2.6 Aural Alarm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-71
2.3.7.2.7 RF Wattmeter Selection Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-71
2.3.7.2.8 System Configuration Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-72
2.3.7.2.9 Clock Oscillator and Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-72
2.3.7.2.10 Reset and Watchdog Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-72
2.3.8 Battery Charging Power Supply CCA (012014) (1A6/1A10) Theory of Operation . . 2-73
2.3.8.1 Battery Charging Power Supply CCA (012014) (1A6/1A10)
Block Diagram Theory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-74
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2.3.8.2 Battery Charging Power Supply CCA ( 012014) (1A6/1A10)

Detailed Circuit Theory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-76
2.3.9 Monitor Recombining Unit CCA (012027-0003) (1A15A1) Theory of Operation. . . 2-81
2.3.9.1 Monitor Recombining Unit CCA (012027-0003) (1A15A1) Block Diagram Theory. 2-81
2.3.9.2 Monitor Recombining Unit (MRU) (1A15A1) Detailed Circuit Theory . . . . . . . . . . . 2-89
2.3.10 Transmitter Recombining Unit CCA (TRU) (012025) (1A15A3).
Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-93
2.3.10.1 Transmitter Recombining Unit CCA (TRU) (012025) (1A15A3).
Block Diagram Theory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-94
2.3.10.2 Transmitter Recombining Unit (TRU) (1A15A3) Detailed Circuit Theory. . . . . . . . . 2-95
2.3.11 Transfer Relay Driver Board (012044) (1A15A2). Theory of Operation. . . . . . . . . . 2-96
2.3.11.1 Signal Interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-97
2.3.11.2 Relay Driver and Timing Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-97
2.3.11.3 Power On Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-99
2.3.11.4 Indicator Status Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-100
2.3.12 Environmental Sensors. - Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-100
2.3.12.1 Shelter Temperature Sensor Assembly Circuit Theory . . . . . . . . . . . . . . . . . . . . . . 2-101
2.3.12.2 Outside Temperature Sensor Assembly Circuit Theory. . . . . . . . . . . . . . . . . . . . . . 2-101
2.3.12.3 Fire/Smoke Detector Assembly Theory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-101
2.3.12.4 Intrusion Sensor Assembly Theory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-101
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SECTION 3. OPERATION
3.1 INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

3.2 REMOTE CONTROL STATUS UNIT (RCSU). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
3.3 REMOTE STATUS UNIT (RSU). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
3.4 PORTABLE MAINTENANCE DATA TERMINAL (PMDT). . . . . . . . . . . . . . . . . . 3-1
3.4.1 Equipment Turn On & Shutdown. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
3.4.1.1 Equipment Turn On. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
3.4.1.1.1 Connecting the PMDT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
3.4.1.1.2 Starting the PMDT Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
3.4.1.1.3 Turning On the ILS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
3.4.1.2 Equipment Shutdown. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
3.4.1.2.1 Equipment Turn Off. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
3.4.1.2.2 PMDT PC Turn Off. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
3.4.2 PMDT Screens. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
3.4.2.1 General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
3.4.2.1.1 Menus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
3.4.2.1.2 System Status at a Glance; Sidebar Status and Control . . . . . . . . . . . . . . . . . . . . . . . 3-6
3.4.2.1.3 Screen Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
3.4.2.2 Configuring the PMDT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
3.4.2.3 Connecting to the ILS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
3.4.2.3.1 Security Levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
3.4.2.3.2 PMDT Logon via Direct or Modem Connection. . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
3.4.2.4 RMS Status Screens . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13
3.4.2.5 RMS Data Screens . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15
3.4.2.5.1 RMS Maintenance Alerts Screen. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15
3.4.2.5.2 Analog-to-Digital Data Screen. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16
3.4.2.5.3 Digital Inputs Screen. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17
3.4.2.5.4 RMS Antenna Fault Screen. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18
3.4.2.6 RMS Logs Screen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19
3.4.2.6.1 Operational Summary Screen. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19
3.4.2.6.2 Alarms Log Screen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20
3.4.2.6.3 Maintenance Alerts Log Screen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21
3.4.2.6.4 Command Activity Screen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-22
3.4.2.6.5 Parameter Change Log Screen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23
3.4.2.7 RMS Configuration Screen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-24
3.4.2.7.1 General RMS Configuration Screen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-25
3.4.2.7.1.1 General Configuration of the Localizer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-26
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3.4.2.7.2 Station Configuration Screen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-28

3.4.2.7.3 A/D Limits Configuration Screen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-30
3.4.2.7.4 Security Codes Configuration Screen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-31
3.4.2.7.4.1 User Account Maintenance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-32
3.4.2.7.4.1.1 Add a User Account. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-32
3.4.2.7.4.1.2 Change a User’s Password. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-33
3.4.2.7.4.1.3 Delete a User’s Account. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-34
3.4.2.8 RMS Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-35
3.4.2.9 Monitor Configuration Screens . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-38
3.4.2.9.1 General Monitor Configuration Screen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-38
3.4.2.9.2 Integral/Standby Monitor Configuration Screens. . . . . . . . . . . . . . . . . . . . . . . . . . . 3-39
3.4.2.9.3 Near Field Monitor Configuration Screen. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-40
3.4.2.9.4 Far Field Monitor Configuration Screen. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-41
3.4.2.10 Monitor Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-42
3.4.2.11 Monitors 1 - 4 Screens . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-43
3.4.2.11.1 Monitor Data Screens . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-43
3.4.2.11.1.1 Integral/Standby Monitor Data Screens. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-43
3.4.2.11.1.2 Field Monitor Data Screen. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-44
3.4.2.11.1.3 Monitor Certification Test Results Screen. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-45
3.4.2.11.1.4 Monitor Maintenance Alerts Screen. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-48
3.4.2.11.1.5 Monitor Status Screen. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-49
3.4.2.11.2 Monitor Fault History Screens . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-50
3.4.2.11.2.1 Integral/Standby Monitor Fault History Screens . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-50
3.4.2.11.2.2 Field Monitors Fault History Screens . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-51
3.4.2.11.2.3 LCU Fault History Screens . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-52
3.4.2.11.3 Monitor Offsets & Scale Factors Screens . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-53
3.4.2.11.3.1 Integral/Standby Monitor Offsets & Scale Factors Screens . . . . . . . . . . . . . . . . . . . . 3-54
3.4.2.11.3.2 Near Field Monitor Offsets & Scale Factors Screen . . . . . . . . . . . . . . . . . . . . . . . . . 3-55
3.4.2.11.3.3 Far Field Monitor Offsets & Scale Factors Screen . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-56
3.4.2.11.3.4 Monitor Certification Offsets & Scale Factors Screen . . . . . . . . . . . . . . . . . . . . . . . . 3-57
3.4.2.12 Transmitters Data Screens . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-58
3.4.2.12.1 Wattmeter Data Screen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-58
3.4.2.12.2 Tx 1 & 2 Synthesizer & PA Data Screens . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-59
3.4.2.13 Transmitters Configuration Screens . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-60
3.4.2.13.1 Wattmeter Limits & Offsets Data Screen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-61
3.4.2.13.2 Tx 1 & 2 Offsets & Scale Factors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-62
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3.4.2.14 Transmitters Waveform Screens . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-63

3.4.2.15 Transmitter Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-65
3.4.2.16 Controlling the Transmitter via the PMDT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-68
3.4.2.16.1 General Transmitter Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-68
3.4.2.16.2 Changing the Waveform Data Name. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-68
3.4.2.16.3 Change the Modulation Balance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-68
3.4.2.16.4 Change the Total Depth of Modulation (SDM). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-69
3.4.2.16.5 Change the CSB Power Level. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-69
3.4.2.16.6 Change the SBO Power Level. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-69
3.4.2.16.7 Change the Course Identification Depth of Modulation. . . . . . . . . . . . . . . . . . . . . . . 3-70
3.4.2.17 Diagnostics Screen. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-71
3.4.2.17.1 Power-Up Diagnostics Results. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-71
3.4.2.17.2 Fault Isolation Test Results. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-72
3.5 RMM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-73
3.6 LOCAL CONTROL UNIT (LCU). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-74
3.7 REMOTE MAINTENANCE SUB-SYSTEM (RMS) CCA (1A8). . . . . . . . . . . . . . . 3-88
3.8 MONITOR CCA (1A3, 1A4, 1A12, 1A13). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-90
3.9 SYNTHESIZER CCA (1A2, 1A14). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-92
3.10 BATTERY CHARGING POWER SUPPLY (BCPS) CCA (1A6, 1A10). . . . . . . . . . 3-94
3.11 CABINET INTERFACE ASSEMBLY (1A18). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-96
3.12 DUAL TRANSFER/RECOMBINER ASSEMBLY (1A15). . . . . . . . . . . . . . . . . . . . 3-97
3.13 SINGLE RECOMBINER ASSEMBLY (1A15). . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-99
SECTION 4. STANDARDS AND TOLERANCES
4.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1

4.2 STANDARDS AND TOLERANCES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
SECTION 5. PERIODIC MAINTENANCE
5.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1

5.2 PERFORMANCE CHECKS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
5.3 OTHER ON-SITE MAINTENANCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
5.4 OFFSITE MAINTENANCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
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SECTION 6. MAINTENANCE PROCEDURES
6.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1

6.2 PERFORMANCE CHECK PROCEDURES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1
6.2.1 Remote Maintenance Monitor Performance Checks. . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1
6.2.2 Remote Maintenance Monitor Operation Performance Check. . . . . . . . . . . . . . . . . . . 6-2
6.2.3 Monitor Certification Check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3
6.2.4 Standby Transmitter Check (Dual Equipment only). . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3
6.2.5 Voltage and Current Performance Check. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4
6.2.6 Transmitter RF Frequency Check. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4
6.2.7 Integral Monitor Performance Checks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6
6.2.7.1 Read/Calibrate Course Monitor Offset - Course System. . . . . . . . . . . . . . . . . . . . . . . . 6-6
6.2.7.2 Read/Calibrate Width Monitor Offset - Course System. . . . . . . . . . . . . . . . . . . . . . . . 6-8
6.2.7.3 CSB Modulation Percentage Performance Check. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9
6.2.8 Internal Test Equipment Calibration Checks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-11
6.2.9 Voltage Performance Check. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-11
6.2.9.1 AC Voltmeter Performance Check. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-11
6.2.9.2 DC Voltmeter Performance Check. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-11
6.2.10 Battery Performance Check. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-12
6.2.11 Verify Monitor Alarm Points. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-12
6.2.12 Check Transfer from Main to Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-13
6.2.13 Check Dual Transmitter Auto Restart Time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14
6.2.14 Check Single Transmitter Auto Restart Time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-16
6.2.15 VSWR (Voltage Standing Wave Ratio) Measurement. . . . . . . . . . . . . . . . . . . . . . . . 6-17
6.3 OTHER MAINTENANCE PROCEDURES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-18
6.3.1 Ground Check Procedure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-18
6.3.2 Sideband Null Check. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-21
6.3.3 Cable Fault Alarm Performance Check. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-22
6.3.4 Antenna Misalignment Alert Performance Check. . . . . . . . . . . . . . . . . . . . . . . . . . . 6-23
6.4 SPECIAL MAINTENANCE PROCEDURES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-24
6.4.1 Calibration Checks of Internal Test Equipment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-24
6.4.2 Zero the Watt Meter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-24
6.4.3 Setting the CSB Forward Power Scale Factor and Offset. . . . . . . . . . . . . . . . . . . . . . 6-24
6.4.4 Setting the CSB Reflected Power Scale Factor and Offset. . . . . . . . . . . . . . . . . . . . . 6-25
6.4.5 Setting the SBO Forward Power Scale Factor and Offset. . . . . . . . . . . . . . . . . . . . . . 6-27
6.4.6 Setting the SBO Reflected Power Scale Factor and Offset. . . . . . . . . . . . . . . . . . . . . 6-28
6.4.7 Setting the Total Modulation % Scaling Factors. . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-29
viii Rev. C July, 2000

TABLE OF CONTENTS
SECTION 6. MAINTENANCE PROCEDURES
6.4.8 Setting Monitor RF level reference levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-31

6.4.8.1 Integral Monitor Centerline Reference Level Adjustment. . . . . . . . . . . . . . . . . . . . . . 6-31
6.4.8.2 Standby Monitor Centerline RF Reference Level Adjustment. . . . . . . . . . . . . . . . . . . 6-32
6.4.8.3 Near Field Monitor RF Reference Level Adjustment (if installed) . . . . . . . . . . . . . . . 6-33
6.4.8.4 Far Field Monitor RF Reference Level Adjustment (if installed) . . . . . . . . . . . . . . . . 6-34
6.4.8.5 Monitor RF Level Alarm Adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-35
6.4.8.6 Monitor Certification Reference Level Adjustment. . . . . . . . . . . . . . . . . . . . . . . . . . 6-36
6.4.8.7 Monitor Certification Centerline DDM Offset Adjustment. . . . . . . . . . . . . . . . . . . . . 6-37
6.4.8.8 Monitor Certification Width DDM Offset Adjustment. . . . . . . . . . . . . . . . . . . . . . . . 6-38
6.4.8.9 Monitor Certification SDM Offset Adjustment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-39
6.4.9 Standby Transmitter Monitor Adjustments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-40
6.4.9.1 Setting the Standby Transmitter CRS CSB Power Scale Factor and Offset. . . . . . . . 6-40
6.4.9.2 Setting the Standby Transmitter SBO power Scale Factor and Offset. . . . . . . . . . . . . 6-42
6.4.9.3 Setting the Standby Transmitter Total Modulation % Scale Factor. . . . . . . . . . . . . . . 6-43
6.4.9.4 Setting the Standby Transmitter Centerline Offset. . . . . . . . . . . . . . . . . . . . . . . . . . . 6-44
6.4.9.5 Setting the Standby Transmitter Width Offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-45
6.4.9.6 Setting the Standby Transmitter Centerline RF Level Reference Level. . . . . . . . . . . . 6-46
6.4.10 Set Automatic Restart Delay Time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-46
6.4.11 Setting Alarm Delay Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-47
6.4.12 +24.5 Vdc Power Supply (1A20/1A21) Output Adjustment . . . . . . . . . . . . . . . . . . . 6-48
6.4.13 BCPS (1A6/1A10) Output Adjustment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-49
6.4.14 System Phasing Check. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-50
6.4.15 Monitor Phasing Check. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-52
6.4.15.1 Monitor Course System Phasing Check and Adjustmen
t 012027-0001 and -0002 MRU Adjustment (early units) . . . . . . . . . . . . . . . . . . . . 6-52
6.4.15.2 Monitor Course System Phasing Check and Adjustment
012027-0003 Monitor Recombiner Unit Adjustment (later units) . . . . . . . . . . . . . . . 6-53
6.4.15.3 Standby Monitor System Phasing Check and Adjustment
012025-0001 Transmitter Monitor Recombiner Unit Adjustment . . . . . . . . . . . . . . 6-54
6.4.16 Localizer Temperature Sensor Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-55
6.4.17 Automatic Setting of Scale Factors & Offsets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-56
Rev. C July, 2000 ix

TABLE OF CONTENTS
SECTION 7. CORRECTIVE MAINTENANCE
7.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1

7.2 TEST EQUIPMENT REQUIRED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1
7.3 ON-SITE CORRECTIVE MAINTENANCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1
7.3.1 General Troubleshooting Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2
7.4 OFF-SITE REPAIRS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3
7.5 OVERHAUL, MAINTENANCE, AND REPAIR STANDARDS . . . . . . . . . . . . . . . . 7-3
7.6 PACKING INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3
7.7 FAULT ISOLATION FLOWCHARTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3
SECTION 8. PARTS LIST
8.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1
x Rev. C July, 2000

TABLE OF CONTENTS
SECTION 9. INSTALLATION, INTEGRATION, AND CHECKOUT
9.1 INTRODUCTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1

9.2 SITE INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1
9.3 UNPACKING AND RE-PACKING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1
9.3.1 Environmental Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1
9.4 INPUT REQUIREMENT SUMMARY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1
9.5 INSTALLATION PROCEDURES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1
9.5.1 Installation Tools and Test Equipment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1
9.5.2 Installation Kits.- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3
9.5.3 Shelter Foundation Installation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3
9.5.4 Shelter Installation.- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3
9.5.5 Shelter Grounding Installation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4
9.5.6 Exterior Interface Box Installation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4
9.5.7 Air Conditioner Installation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4
9.5.8 Localizer Transmitter Cabinet Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4
9.5.9 Battery Backup Assembly Installation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4
9.5.10 Environmental Sensors Kit Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4
9.5.11 Primary AC Power Kit Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6
9.5.12 LPD Antenna Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6
9.5.13 Heliax RF Cable Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7
9.5.14 Audio Cable Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-8
9.5.15 Localizer to Exterior Interface Ground Plate Connections.- . . . . . . . . . . . . . . . . . . . . 9-9
9.5.16 Localizer Shelter to Antenna Array Electric Power Cable Installation . . . . . . . . . . . . 9-11
9.5.17 Localizer Shelter to Antenna Array Ground Wire Installation . . . . . . . . . . . . . . . . . . 9-11
9.5.18 Localizer/DME Interconnect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-12
9.5.18.1 Localizer/DME Keying Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-12
9.5.18.2 DME Status Monitoring Interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-12
9.5.19 Antenna Cables to Distribution Unit Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-12
9.6 INSPECTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-15
9.7 INITIAL START-UP AND PRELIMINARY TESTING . . . . . . . . . . . . . . . . . . . . . 9-15
9.7.1 Input Voltage Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-15
9.7.2 Installing Modules in Transmitter Cabinet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-17
9.7.2.1 Checking and Setting the Backplane DIP Switches . . . . . . . . . . . . . . . . . . . . . . . . . . 9-18
9.7.3 PMDT Hook-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-24
9.7.4 Initial Turn-On.- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-25
9.7.5 Setting Modulation Percentage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-27
Rev. C July, 2000 xi

TABLE OF CONTENTS
SECTION 9. INSTALLATION, INTEGRATION, AND CHECKOUT
9.7.6 Setting Parameter Offsets/Scale Factors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-28

9.7.6.1 Monitor Certification Centerline DDM Offset Adjustment. . . . . . . . . . . . . . . . . . . . . 9-28
9.7.6.2 Monitor Certification Width DDM Offset Adjustment. . . . . . . . . . . . . . . . . . . . . . . . 9-28
9.7.6.3 Monitor Certification Reference Level Adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . 9-28
9.7.6.4 Monitor Certification Centerline SDM Offset Adjustment. . . . . . . . . . . . . . . . . . . . . 9-28
9.7.7 RF Forward Power, Reflected RF Power, and VSWR Checks . . . . . . . . . . . . . . . . . 9-28
9.7.7.1 CSB Forward Power Scale Factor and Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-28
9.7.7.2 CSB Reflected Power Scale Factor and Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-29
9.7.7.3 SBO Forward Power Scale Factor and Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-29
9.7.7.4 SBO Reflected Power Scale Factor and Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-29
9.7.8 Modulation Percentage and Keying Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-29
9.7.9 Cutting In Antenna Nulls. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-30
9.7.10 System Phasing and Preliminary Course Width Adjustment . . . . . . . . . . . . . . . . . . . . 9-30
9.7.11 Cutting-In The Monitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-31
9.7.12 Monitor Recombining Unit Adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-32
9.7.13 Setting Monitor Alarm Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-35
9.7.13.1 Setting Integral Monitor Alarm Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-35
9.7.13.2 Setting Standby Transmitter Monitor Alarm Parameters . . . . . . . . . . . . . . . . . . . . . . 9-35
9.7.13.3 Setting Field Monitor Alarm Limits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-36
9.7.13.4 Setting Maintenance Alert Limits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-37
9.7.13.4.1 Setting Spare A/D Alert Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-37
9.7.13.4.2 Setting Obstruction Light Current Alert Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-39
9.7.14 Setting/Checking Station Alarm Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-39
9.7.15 Standby Transmitter Recombiner Unit (TRU) Alignment (dual stations only) . . . . . . 9-40
9.7.15.1 Course Transmitter TRU Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-40
9.7.15.2 Standby Monitor Offset Adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-41
9.7.15.3 Alternate Transmitter Check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-41
9.8 INSTALLATION VERIFICATION TESTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-41
xii Rev. C July, 2000

TABLE OF CONTENTS
SECTION 10. SOFTWARE
10.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1

10.2 MONITOR DIGITAL SIGNAL PROCESSOR (MDSP) . . . . . . . . . . . . . . . . . . . . . 10-1
10.3 MONITOR CENTRAL PROCESSING UNIT (MCPU) . . . . . . . . . . . . . . . . . . . . . . 10-2
10.4 REMOTE MONITORING SUBSYSTEM (RMS) . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2
10.5 PORTABLE MAINTENANCE DATA TERMINAL (PMDT) . . . . . . . . . . . . . . . . . 10-3
10.6 REMOTE CONTROL AND STATUS UNIT (RCSU) . . . . . . . . . . . . . . . . . . . . . . . 10-4
SECTION 11. TROUBLESHOOTING SUPPORT DATA
11.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1
Rev. C July, 2000 xiii

LIST OF ILLUSTRATIONS
Figure Description Page
1-1. Model 2100 Single Frequency Localizer Station, Shelter Interior View. . . . . . . . . . . . 1-2
1-2. Localizer Signal Lobes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
1-3. Model 2100 Single Frequency Localizer Cabinet. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11
2-1. Antenna Pattern for a 8 Element SF Localizer Array . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

2-2. Antenna Pattern for a 14 Element SF Localizer Array . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2-3. Transmitter, Distribution Unit, and Antenna Interconnections. . . . . . . . . . . . . . . . . . . 2-3
2-4. Model 2100 Single Frequency Localizer Block Diagram . . . . . . . . . . . . . . . . . . . . . . . 2-5
2-5. Transfer Recombiner Drawer Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . 2-7
2-6. Frequency Synthesizer Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
2-7. Audio Generator Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
2-8. RF Power Amplifier - CSB Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19
2-9. RF Power Amplifier - SBO Channel Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . 2-22
2-10 Monitor CCA Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25
2-11 Monitor Analog Front-End Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-27
2-12 Monitor Detailed Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-31
2-13 MDSP to MCPU Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-35
2-14. RMS CCA Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-37
2-15. AC Power Monitor Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-50
2-16. Cabinet Interface Associative Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-52
2-17. Cabinet Interface Block Diagram (1 of 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-54
2-20 Simplified Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-61
2-21 LCU Detailed Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-64
2-22. BCPS Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-74
2-23. BCPS Voltage Converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-75
2-24. BCPS Battery Charger Control Circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-77
2-25. Generation of the Width Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-82
2-26. Course, Clearance, and LO Spectrum. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-84
2-27. MRU Down Conversion IF Spectrum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-84
2-26A. Single Frequency Course & LO Spectrum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-85
2-27A. Single Frequency MRU IF Spectrum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-86
2-28. MRU Signal Processing Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-87
2-29. MRU Detailed Block Diagram - Single Frequency Operation . . . . . . . . . . . . . . . . . . 2-90
2-30. TRU Course Channel Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-94
xiv Rev. C July, 2000

LIST OF ILLUSTRATIONS (Cont)
3-1. Sidebar Status Panel (Dual Equipment shown) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6

3-2. PMDT Configuration Screen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
3-3. ILS System Directory Screen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
3-4. PMDT Login Screen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
3-5. Initial PMDT Screen (Dual Equipment shown) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12
3-6. RMS/DME Status Screen (Dual Equipment shown) . . . . . . . . . . . . . . . . . . . . . . . . . 3-13
3-7. Monitor/Transmitter Status Screen (Dual Equipment shown) . . . . . . . . . . . . . . . . . . 3-14
3-8. RMS Maintenance Alerts Screen (Dual Equipment shown) . . . . . . . . . . . . . . . . . . . . 3-15
3-9. RMS A/D Data Screen (Dual Equipment shown) . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16
3-10. RMS Digital Inputs Screen (Dual Equipment shown) . . . . . . . . . . . . . . . . . . . . . . . . 3-17
3-11. RMS Antenna Fault Screen (Dual, 14-Element Equipment shown) . . . . . . . . . . . . . . 3-18
3-12. Operational Summary Screen (Dual Equipment shown) . . . . . . . . . . . . . . . . . . . . . . 3-19
3-13. Alarms Log Screen (Dual Equipment shown) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20
3-14. Maintenance Alerts Log Screen (Dual Equipment shown) . . . . . . . . . . . . . . . . . . . . . 3-21
3-15. Command Activity Log Screen (Dual Equipment shown) . . . . . . . . . . . . . . . . . . . . . 3-22
3-16. Parameter Change Log Screen (Dual Equipment shown) . . . . . . . . . . . . . . . . . . . . . 3-23
3-17. General RMS Configuration Screen (Dual Equipment shown) . . . . . . . . . . . . . . . . . 3-25
3-18. Station Configuration Screen (Dual Equipment shown) . . . . . . . . . . . . . . . . . . . . . . 3-28
3-19. DIP Switch Settings Screen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-29
3-20. A/D Limits Configuration Screen (Dual Equipment shown) . . . . . . . . . . . . . . . . . . . 3-30
3-21. Security Codes Configuration Screen (Dual Equipment shown) . . . . . . . . . . . . . . . . 3-31
3-22. RMS Commands Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-35
3-23. Select Audio Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-36
3-24. DME Control Menu (Dual Equipment shown) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-37
3-25. General Monitor Configuration Screen (Dual Equipment shown) . . . . . . . . . . . . . . . 3-38
3-26. Integral/Standby Monitor Configuration Screens (Dual Equipment shown) . . . . . . . . 3-39
3-27. Near Field Monitor Configuration Screen (Dual Equipment shown) . . . . . . . . . . . . . 3-40
3-28. Far Field Monitor Configuration Screen (Dual Equipment shown) . . . . . . . . . . . . . . 3-41
3-29. Monitor Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-42
3-30. Integral & Standby Monitor Data Screens (Dual Equipment shown) . . . . . . . . . . . . . 3-43
3-31. Field Monitor Data Screen (Dual Equipment shown) . . . . . . . . . . . . . . . . . . . . . . . . 3-44
3-32. Monitor Certification Test Results Screen (Dual Equipment shown) . . . . . . . . . . . . . 3-45
3-33. Monitor Maintenance Alert Screen (Dual Equipment shown) . . . . . . . . . . . . . . . . . . 3-48
3-34. Monitor Status Screen (Dual Equipment shown) . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-49
3-35. Integral & Standby Monitor Fault History Screens (Dual Equipment shown) . . . . . . 3-50
3-36. Field Monitors Fault History Screen (Dual Equipment shown) . . . . . . . . . . . . . . . . . 3-51
3-37. Local Control Unit Fault History Screen (Dual Equipment shown) . . . . . . . . . . . . . . 3-52
3-38. Integral & Standby Monitor Offsets & Scale Factors Screens . . . . . . . . . . . . . . . . . . 3-54
Rev. C July, 2000 xv

LIST OF ILLUSTRATIONS (Cont)
3-39. NFM Offsets & Scale Factors Screen (Dual Equipment shown) . . . . . . . . . . . . . . . . 3-55
3-40. FFM Offsets & Scale Factors Screen (Dual Equipment shown) . . . . . . . . . . . . . . . . . 3-56
3-41. Monitor Certification Offsets & Scale Factors Screen (Dual Equipment shown) . . . . 3-57
3-42. Wattmeter Data Screen (Dual Equipment shown) . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-58
3-43. TX 1 & 2 Synthesizer & PA Data Screens (Dual Equipment shown) . . . . . . . . . . . . . 3-59
3-44. Wattmeter Limits and Offsets Screen (Dual Equipment shown) . . . . . . . . . . . . . . . . 3-61
3-45. Tx 1 & 2 Offsets & Scale Factors Screens (Dual Equipment shown) . . . . . . . . . . . . . 3-62
3-46. Waveform Data Names Screen (Dual Equipment shown) . . . . . . . . . . . . . . . . . . . . . 3-63
3-47. Waveform Data Screen (Dual Equipment shown) . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-64
3-48. Tx Commands Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-65
3-49. Transmitter 1 & 2 Command Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-66
3-50. Localizer Ident Commands Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-67
3-51. Power-Up Diagnostics Results Screen (Dual Equipment shown) . . . . . . . . . . . . . . . . 3-71
3-52. Fault Isolation Diagnostics Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-72
3-53. Localizer Local Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-74
3-54. LCU Power Controls and Indicators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-86
3-55. LCU Transmitter Controls and Indicators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-86
3-56. LCU Monitor Controls and Indicators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-87
3-57. LCU System and Wattmeter Controls and Indicators . . . . . . . . . . . . . . . . . . . . . . . . 3-87
3-58. RMS CCA Indicators and Test Points. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-88
3-59. Monitor CCA Indicators and Test Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-90
3-60. Synthesizer Controls, Indicators and Test Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-92
3-61. BCPS Controls and Indicators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-94
3-62. Cabinet Interface - Fuse F1 Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-96
3-63. Dual Equipment Transfer/Recombiner Drawer Assembly . . . . . . . . . . . . . . . . . . . . . 3-97
3-64. Single Equipment Recombiner Drawer Assembly . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-99
7-1. Troubleshooting Flowchart Legend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4

7-2. Full Diagnostics Fault Isolation Flow Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5
7-3. Remote Diagnostics Fault Isolation Flow Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8
7-4. Antenna Sub-System Fault Isolation Flow Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9
9-1. Typical Single Frequency Localizer Siting Dimensions . . . . . . . . . . . . . . . . . . . . . . . . 9-2

9-2. Shelter Grounding Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5
9-3. Typical Trenching Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6
9-4 Dual Single Frequency Localizer Module and CCA Location Diagram . . . . . . . . . . . 9-17
9-5. S1 Selection for Detected Audio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-33
xvi Rev. C July, 2000

LIST OF ILLUSTRATIONS
11-1 Interconnect Diagram, CAT II/III Single Frequency Localizer . . . . . . . . . . . . . . . . . 11-3

11-2 Synthesizer CCA (1A2/1A14) Schematic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . 11-11
11-3 ILS Monitor CCA (1A3.1A13) Schematic Diagram . . . . . . . . . . . . . . . . . . . . . . . . 11-21
11-4 Battery Charge Power Supply CCA (1A6/1A10) Schematic Diagram . . . . . . . . . . 11-37
11-5 RMS Processor CCA (1A8) Schematic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-43
11-6 Local Control Unit CCA (1A1A1)Schematic Diagram . . . . . . . . . . . . . . . . . . . . . . 11-53
11-7 AC Monitor CCA (1A17) Schematic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-63
11-8 Cabinet Interface CCA (1A18) Schematic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . 11-65
11-9 Monitor Recombiner CELOC (1A15A1) (012027-0001 and -0002)
Schematic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-75
11-9a Monitor Recombiner CELOC (1A15A1) (012027-0003) Schematic Diagram . . . . 11-79
11-10 Transfer Relay Driver CCA (1A15A2) Schematic Diagram . . . . . . . . . . . . . . . . . . . 11-83
11-11 Transmitter Recombiner (TRU) CCA (1A15A3) Schematic Diagram . . . . . . . . . . . 11-85
11-12 Backplane CCA (1A19) Schematic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-87
11-13 Power Amplifier CCA (1A22/1A23/1A24/1A25) Schematic Diagram . . . . . . . . . . . 11-95
11-14 Exterior Interface Installation Kit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-107
11-15 Battery Back-Up Installation Kit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-113
11-16 Cabinet Mounting Kit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-117
11-17 AC Power Installation Kit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-121
11-18 Environmental Sensors Kit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-123
11-19 Shelter Internal Grounding Kit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-127
11-20 Shelter Civil Grounding Kit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-131
11-21 VHF Communication Antenna Kit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-133
11-22 Shelter Lightning Protection Kit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-135
11-23 Interconnect Kit, DME to Model 2100 ILS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-137
11-24 Interconnect Diagram CAT I Single Frequency Localizer . . . . . . . . . . . . . . . . . . . 11-143
11-25 Photo Electric Sensor Kit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-151
Rev. C July, 2000 xvii

LIST OF TABLES
Table No. Description Page
1-1. Equipment Specification Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14

1-2. Equipment and Accessories Supplied . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16
1-3. Equipment Required But Not Supplied . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17
1-4. Optional Equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17
2-1 Address Decoding Function of the EPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13

2-2 RMS CCA Serial Communication Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-46
2-3 LCU Interface - J25 Signal Inputs and Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-97
2-4 Transfer Relay Interface - J1 Signal Inputs and Outputs . . . . . . . . . . . . . . . . . . . . . . 2-98
3-1. PMDT Interconnect Cable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2

3-2. Functions Available via PMDT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
3-3. ILS Security Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
3-4. General Configuration Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-26
3-5. Monitor Certification Test Criteria . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-47
3-6a. Dual Equipment Control Panel Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-75
3-6b. Single Equipment Control Panel Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-82
3-7. RMS CCA (1A8) - Controls and Indicators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-89
3-8. Monitor CCA (1A3, 1A4, 1A12, 1A13) - Controls and Indicators . . . . . . . . . . . . . . 3-91
3-9. Synthesizer CCA (1A2, 1A14) - Controls and Indicators . . . . . . . . . . . . . . . . . . . . . 3-93
3-10. Battery Charging Power Supply (BCPS) CCA (1A6, 1A10) -
Controls and Indicators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-95
3-11. Cabinet Interface Assembly (1A18) - Controls and Indicators . . . . . . . . . . . . . . . . . . 3-96
3-12. Dual Transfer/Recombiner Assembly (1A15) - Controls and Indicators . . . . . . . . . . . 3-98
3-13. Single Recombiner Assembly (1A15) - Controls and Indicators . . . . . . . . . . . . . . . . . 3-99
4-1 Standards and Tolerances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
5-1 Performance Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2

5-2 Other On-Site Maintenance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5
8-1. Model 2100 Single Frequency Localizer System Module and CCA List. . . . . . . . . . . . 8-1
8-2. Model 2100 Single Frequency Localizer Accessory Kit Parts List. . . . . . . . . . . . . . . . 8-3
xviii Rev. C July, 2000

LIST OF TABLES
Table No. Description Page
8-3. Test Equipment Kit, LOC/GS Parts List. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4

8-4. Spares, Single Localizer, Recommended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5
8-5. Spares, Dual Localizer, Recommended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6
8-6. Spares, Dual Localizer, Full, 120 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7
8-7 Spares, Dual Localizer, Full, 240 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-8
8-8 Spares, Single Localizer, Full, 120 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-9
8-9. Spares, Single Localizer, Full, 240 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-10
8-10. Single Equipment, Single Frequency Localizer Electronics Cabinet, 002100-0103 . . 8-11
8-11. Dual Equipment, Single Frequency Localizer Electronics Cabinet, 002100-0104 . . . . 8-14
9-1. Special Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1

9-2. Offset Cable Kit 350 ft. (470070-0005) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7
9-3. Audio Cable Color Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10
9-4 2100 ILS to DME Interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-13
9-5 Model 2100 Localizer System Fuses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-15
9-6 Frequency Selection Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-19
9-7 Standard ILS and DME Frequency Pairing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-20
9-8 Switch 2 Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-22
9-9 Switch 3 Settings Positions 1 through 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-23
9-10 Switch 3 Settings Positions 7 and 8 (* = Default) . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-23
9-11 Initial RF Power Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-26
9-12. Equipment Alarm Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-35
9-13. Equipment Alarm Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-36
9-14. Near Field Alarm Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-36
9-15. Far Field Alarm Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-37
9-16. Maintenance Alert Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-38
11-1. Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1
Rev. C July, 2000 xix

xx Rev. C July, 2000

SECTION 1. GENERAL INFORMATION AND REQUIREMENTS
1.1 INTRODUCTION.- This operation and maintenance manual provides the data required to install,
operate, and maintain the Model 2100 Single Frequency Localizer Equipment supplied by Airport Systems
International, Inc., Overland Park, Kansas, U.S.A. The Single Frequency Localizer 8 and 14 antenna arrays
are not covered in this manual. For information on the antenna, refer to Localizer antenna manual part no.
572100-0053 for the 8 and the 14 Element LPD arrays.
In this section there is an equipment description, including illustrations and equipment specification data, a
table of equipment and accessories supplied, a table of equipment required but not supplied, and a table of
optional equipment.
1.2 EQUIPMENT DESCRIPTION.- The Model 2100 Single Frequency Localizer (figure 1-1) is part of
an Instrument Landing System (ILS). The Localizer provides azimuthal (horizontal) guidance to aircraft
during instrument landings.
The Model 2100 Single Frequency Localizer is mounted on a wall, inside a shelter provided by Airport
Systems or provided by the customer. It is self-monitoring, requires low power, has accurate and stable
frequencies, and requires little maintenance. System status can be checked from the control tower through
the Remote Control and Status Unit (RCSU) or other remote facility through the Remote Maintenance
Monitor (RMM). A built-in charging circuit and battery backup extend operation of the Localizer if AC
power should fail. Frequency generation is by synthesis, requiring only one oscillator to produce the 40
Localizer channels.
The Localizer transmits a horizontally polarized signal along the runway as shown in figure 1-2.
The Single Frequency Localizer is typically installed about 1,000 feet from the stop end of the runway with
the antenna array located on the extended runway centerline. The equipment shelter is located off to one
side, approximately 250 ft. from the centerline. The Single Frequency Localizer utilizes a 8 element or 14
element Log Periodic Dipole (LPD) array. This array is directional and provides front course only.
Rev. C July, 2000 1-1

Figure 1-1. Model 2100 Single Frequency Localizer Station, Shelter Interior View.
1-2 Rev. C July, 2000

Figure 1-2. Localizer Signal Lobes.
The radiated patterns provide course guidance in the horizontal plane to approaching aircraft. Frequencies
of 90 Hz and 150 Hz are used to modulate the RF carriers and thus identify the right and left sides of the
runway centerline. The detected signal is predominantly 90 Hz to the left of the runway centerline (as seen
by an approaching aircraft) and predominantly 150 Hz to the right of the runway centerline. The Localizer
signal DDM (Difference in Depth of Modulation) is displayed on aircraft instruments such as a Course
Deviation Indicator (CDI).
1.2.1 General Design Features.- The Localizer is a solid state design and includes an electronics subsystem,
antenna system, shelter-to-antenna system cables, installation and interface kits, no-break battery backup
system (maintenance free design), and necessary accessory items such as extender boards, cables and
wattmeter elements. A Portable Maintenance Data Terminal (PMDT) for operation of the Localizer is
supplied. Optional Near and Far Field Monitors are available for the Localizer system. Additional options
include a Remote Status Control Unit (RCSU), Remote Status Unit (RSU) (typically installed in a control
tower), and environmental sensors for the electronic equipment shelters. All systems feature Remote
Maintenance Monitoring (RMM) as standard equipment.
Rev. C July, 2000 1-3

The system is microprocessor controlled and has been designed for ease of installation, high reliability,
maximum attention to fail safe characteristics in all monitoring systems, enhanced system security, the
minimum number of required control and telephone lines, and maximum attention to equipment and personnel
safety. Fuses on AC and DC power lines and internal circuits provide maximum equipment protection.
Surge suppression devices are installed in all electronic equipment shelters.
1.2.1.1 Localizer Electronic Subsystem.- The Localizer electronic subsystem’s modular design consists of
a Single Frequency single transmitter/ single monitor and a dual transmitter/ dual monitor configuration. The
all solid state system is housed in a single cabinet designed for mounting on an equipment shelter wall. The
cabinet features a two-piece hinged arrangement. This allows the front portion to be easily swung away from
the wall for access to the rear during installation and maintenance. The front portion of the dual transmitter
configuration contains all the major system modules including the Main and Standby Transmitters, Monitors,
Local Control Unit and Antenna Changeover Unit. The front portion of the single equipment configuration
contains all major system modules including the Transmitter, Monitor, and Local Control Unit. The rear
portion contains the main system power supplies and serves as a junction box for all system cabling to and
from the antenna system, remote control and RMM systems, and power. Wattmeter bodies are incorporated
in each of the antenna feedlines and are mounted through the side of the rear portion of the cabinet. This
allows ready access for power and modulation measurements without opening the cabinet. All major system
modules and circuit card assemblies are readily accessible from the front for maintenance and replacement.
Plug-in design printed circuit card assemblies are arranged to allow installation in the correct location only.
A locking glass-front door provides protection for the system and allows easy viewing of the system control
panel.
1.2.1.2 Localizer Antenna System.- The Single Frequency design Localizer antenna system is a Log Periodic
Dipole (LPD) array with 8 or 14 elements. The system is furnished with all antenna elements and frangible
supports, centrally mounted RF distribution/monitor combining unit, cable raceway, all coaxial feed and
monitor cables, obstruction lighting and all civil and grounding kits needed for a complete installation.
Pickup devices in each of the array elements are used for integral monitoring. The system is connected to
the Localizer transmitter by low-loss coaxial underground RF cables and necessary signal and power cables
from the antenna array to the equipment shelter.
1.2.2 Monitoring System.- A high integrity integral monitoring system is incorporated in the Localizer
system. This system provides fault detection by monitoring the transmitted navigation signals and initiating
automatic station transfer/shutdown action in the event of an out-of-tolerance condition.
The dual transmitter configuration features dual monitors with dual parallel monitoring channels for
measurement of important signal parameters for the On-the-Air Transmitter, Standby Transmitter, Near Field
Monitor (when installed) and the Localizer Far Field Monitor (when installed).
1-4 Rev. C July, 2000

The single transmitter configuration features a single monitor with parallel monitoring channels for
measurement of important signal parameters for the On-the-Air Transmitter, Near Field Monitor (when
installed) and the Localizer Far Field Monitor (when installed).
Independently adjustable executive and maintenance alarm indications are included both locally at the station
and remotely through the Remote Maintenance Monitoring (RMM) system.
Independently adjustable pre-alarm (maintenance alert) indications are included for all executive monitoring
parameters.
A built-in Test Generator performs certification testing assuring integrity of the monitors.
When installed, the optional Near Field Monitor can be configured for operation as a voting monitor in
conjunction with the integral monitoring system.
When installed, the Localizer Far Field Monitor operates in conjunction with the Remote Control and Status
system and can be configured for operation as either an executive or a maintenance monitor. Bypass
capability for the Far Field Monitor is included at the Remote Control and Status Unit (RCSU) and Remote
Status Unit (RSU).
The monitoring system includes a bypass capability to disable the automatic station control action during
adjustment and maintenance. Front panel amber "BYPASS" lights are illuminated any time the integral,
standby transmitter or field monitor channels are bypassed. Front panel red "ALARM" lights are illuminated
any time the integral, standby transmitter or field monitor channels are in an alarm condition.
All monitored and internally measured system parameters are available for display via the station RS-232
communications port and the Portable Maintenance Data Terminal (PMDT). The parameters are also
available remotely through the Remote Control and Status System and through the Remote Maintenance
Monitoring system.
1.2.3 Localizer Far Field Monitor System (Optional).- The optional Far Field Monitor for the Localizer is
an all solid state, modular design sensor system. It is suitable for installation either indoors or outdoors at the
opposite end of the runway from the Localizer. The typical installation is in the same equipment shelter as
the Middle or Inner Marker Beacon. The system may also be located along with a Localizer system which
serves the opposite end of the runway.
The Far Field Monitor antennas are of the Yagi design and are supplied with short, 10 ft mounting towers
for installation. Information on the Localizer Course Position, Received signal strength (RF Level) and
Modulation is displayed on the unit and transmitted as digital data via modems and control lines to the
Localizer monitor for processing.
Rev. C July, 2000 1-5

1.2.4 Localizer Near Field Monitor (Optional).- The Localizer Near Field Monitor is intended for those
customers who desire additional redundancy of the high integrity Integral Monitor provided with the
Localizer system. The Near Field Monitor pickup antenna is installed approximately 300 ft in front of the
Localizer transmitting antenna array on the runway centerline. The Near Field Monitor includes an antenna,
filter, detector and amplifier. Audio signals at 8000 Hz with modulated course position signals are fed via
coaxial cable to the Monitors CCAs inside the Localizer equipment shelter. The detected signals feed
channels dedicated to Near Field Monitoring the Localizer monitor.
1.2.5 Station Control System.- The station control system provides manual control of the station during
maintenance operations and automatic control during unattended operation.
1.2.5.1 Control System Features Provided
a) Local On/Off control and status indication of the transmitting equipment.
b) Selection of which transmitter operates as Main and which operates as Standby. (Dual
transmitter configuration only)
c) Monitor bypass capability with indications for the Integral, Standby Transmitter and
Near/Far field monitoring systems.
d) Provisions for either local or remote control of the transmitting equipment.
e) System reset capability for the system microprocessors.
f) Automatic transfer capability from the main to the hot standby transmitting equipment
(following an adjustable preset alarm delay period; 1 sec nominal for CAT III
operation and 2 sec nominal for CAT II operation; 10 sec nominal for CAT I
operation) in response to monitor executive alarm conditions.
g) Automatic station shutdown following transfer to the standby transmitting equipment

(dual equipment only) should the station remain in an alarm condition. System restart
attempts must be made manually.
h) Automatic station transfer to and from the no-break standby battery system in the
event of a primary AC power failure and subsequent restoration, and automatic turn-
on following restoration of primary AC power should the standby battery system be
depleted. Batteries automatically recharge on restoration of primary power.
1-6 Rev. C July, 2000

i) Remote On/Off control and station status indications via modem on a two-wire
dedicated control line from the station to a Remote Control and Status Unit (RCSU)
installed in a control tower equipment room. One or more slave Remote Status Units
(RSU) with status only functions are furnished as required for installation at a
controller's position(s) in the control tower cab. Each RCSU and RSU is equipped
with an optional no-break battery back up system which maintains operation in the
event of primary AC line failure. The station-to-RCSU control line for each station
may be replaced by a radio link if required by local conditions.
j) Provisions for bypassing Near and Far Field Monitor control action from the RCSU.
Provisions for bypassing the Far Field Monitor control action from the RCSU and
RSU.
In addition to the control features and associated switches above, system control and monitoring functions,
as well as verification and adjustment of proper transmitting and monitoring parameters, are available via an
RS-232 communications port on the transmitter cabinet and a Portable Maintenance Data Terminal
(PMDT). The system is password controlled such that system adjustments are possible only with entry of
the proper security codes.
A second RS-232 communications port is connected to a modem for system operation and monitoring via
a dial-up telephone line to a remote location using the PMDT software.
1.2.6 Remote Maintenance Monitoring System (RMM).- The integral Remote Maintenance Monitoring
system operates in conjunction with the Control System above and consists of the various embedded sensors,
internal monitoring points, microcomputers and built-in test equipment to remotely monitor, control, record
and certify proper operation of the Localizer.
Rev. C July, 2000 1-7

1.2.6.1 RMM Functions.- The RMM provides the following key functions:
a) System ON/OFF control.
b) Adjustment of system transmitting parameters on the Localizer system.(Local only)
c) Monitoring of system performance and certification parameters. Compares the

outputs of each of the monitoring devices to determine alarm and alert status by
comparing the monitored values to pre-determined limits.
d) Adjustment of all alarm and alert monitoring limits. (Local only)
e) Monitor certification through the system test generator on Localizer system.
f) Storage of monitor alert and alarm data. (Local only).
g) System Self/Fault Diagnostic routines with result storage and reporting for the
Localizer system.
h) Monitoring of routine maintenance parameters including voltages, currents, and

VSWR.
i) Monitoring of environmental parameters (when optional sensors are installed).
1) Intrusion detector
2) Smoke detector
3) Obstruction Light operation
4) Indoor Temperature
5) Outdoor Temperature
j) Monitoring of primary AC power applied to the system.
k) Monitoring of standby battery voltage and current.
1-8 Rev. C July, 2000

1.2.6.2 RMM Security.- The RMM features a 4-level security system to insure only authorized personnel
have access to the various system functions and commands:
Level 1 - Allows access for display-only of system status, configuration and monitored
system parameters. No control functions are available at this level.
Level 1 access requires a general User ID.
Level 2 - Level 1 access plus the ability to run tests or diagnostics and make
adjustments which do not affect the integrity of the system.
Level 2 access requires a unique User ID and Password.
Level 3 - Level 2 access plus the ability to adjust all system parameters, excluding
assignment of user ID's and Passwords.
Level 3 access requires a unique User ID and Password.
Level 4 - Full system access to all functions available in the system, including
assignment of user ID's and Passwords.
Level 4 access requires a user to be in Level 1, 2, or 3 and enter a second

unprompted password.
Error indication is provided for invalid User ID or Password entry.
Protection against unsuccessful log-on is provided in the system:
Three unsuccessful attempts to enter either a User ID or password results in

automatic disconnection of the terminal port or dial up-modem for three minutes.
No keyboard entry of a User ID or password for fifteen minutes results in automatic

disconnection of the terminal port or dial up modem.
Rev. C July, 2000 1-9

1.3 ELECTRONIC EQUIPMENT CABINET.- Refer to figure 1-3. The Single Frequency Localizer
transmitter provides the standard CSB/SBO transmitter. The transmitter is controlled and monitored by
the Monitor Circuit Card Assembly (CCA) (1A3/1A13). The 1A3 Monitor controls transmitter 1. The 1A13
Monitor controls transmitter 2. The 90 and 150 Hz navigation tones are synchronously generated on the
Synthesizer assembly (1A2/1A14).
The Single Frequency Localizer equipment features a numeric controlled digital frequency synthesizer for
accurate and stable channel spacing. The RF and audio frequencies are derived from a temperature controlled
crystal oscillator and provides all 40 channels of operation. The Localizer transmitter can be controlled and
monitored locally or from remote locations over dedicated or switched telephone lines. Ease of maintenance
is enhanced with built in test equipment consisting of a frequency difference counter, digital voltmeter,
transmitter forward and reflected power metering, and a transmitter voltage and current monitor. Battery
backup extends operation of the station during failure of main ac power.
In the Single Frequency Localizer equipment configuration, a single integrated transmitter consists of one
audio/RF synthesizer assembly, one RF amplifier, a battery charging power supply BCPS, and a monitor.
These assemblies are duplicated for the second transmitter in a dual configuration. Communication between
the two transmitters is accomplished through the Remote Maintenance System (RMS) processor. Hardware
logic on the Local Control Unit CCA monitors the status of each Monitor CCA and controls the CSB and
SBO ON/OFF. This same logic also controls the transfer switches in a dual transmitter configuration.
Either transmitter may be selected as Main with the other as the Standby station. Integral monitor signals are
fed into the Transfer/ Recombiner Drawer. The RF signals are recombined in amplitude and phase to generate
an audio signal feed to each monitor.
1-10 Rev. C July, 2000

Figure 1-3 Model 2100 Single Frequency Localizer Cabinet.
1.3.1 Local Control Unit (1A1).- The Local Control Unit (LCU) is located at the top of the equipment
cabinet. The following visual indicators are provided for each of four monitoring categories. Monitor 1 and
2 NORM (green), Monitor 1 and 2 ALARM (red), and BYPASS (amber). The four monitoring categories
are Integral, Standby Transmitter, Near Field and Far Field alarms.
The Integral Alarms are those parameters measured by sampling the On-Air transmitter using the integral
pickup probes in the transmitting antenna elements and recombined in the Transfer/Recombiner drawer assy.
The Standby Transmitter Alarms are those parameters measured from the hot standby transmitter while
operating into dummy loads. The signals from the standby transmitter are recombined in the Transmitter
Recombiner unit located in the Transfer/Recombiner Drawer Assy.
Rev. C July, 2000 1-11

The Near Field Monitor alarms are those parameters measured from an optional Near Field Monitor antenna
located on the runway centerline directly in front of the antenna array. This signal is connected
to the Monitor Recombiner CCA.
The Far Field Monitor alarms are those parameters measured from a Far Field Monitor antenna located on
the runway centerline past the opposite (stop) end of the runway. This signal is sent as serial data to each
monitor.
The NORM indicator is illuminated when the Localizer transmitter equipment is operating normally. The
BYPASS indicator illuminates when the monitor is in the bypass mode of operation. The system is still being
monitored, but will not shutdown if an alarm is detected. The ALARM indicator illuminates when a fault is
detected in one of the monitored circuits.
1.3.2 Local Control CCA (1A1A1).- The Local Control Unit (LCU) CCA is attached to the rear side of the
Status Panel Assembly. It receives station status information from each Monitor CCA.
The LCU CCA controls the display of status and Station shutdown and Transfer, in reaction to alarm inputs
from the Monitor (s). Transfer and shutdown control occurs in response to alarm inputs from each monitor
after the programmed timeouts expire and the AND/ OR logic is applied.
1.3.3 Synthesizer Assembly CCA (1A2/1A14).- The Synthesizer assembly generates the frequency locked
carrier frequency of 108 to 112 MHZ in 50 KHz increments. The Synthesizer assembly also generates the
Local Oscillator (LO) signal frequency locked to the carrier frequency and 8 KHz lower. This signal is used
to demodulate the Monitored signals. The Synthesizer assembly consists of one circuit card assembly (CCA).
DIP switches on the backplane determine the proper output frequency and configure it for Capture Effect
or single frequency operation. The 90, 150 Hz and1020 Hz identification tone audio signals are generated
and used to create upper and lower sidebands. The identification Keyer is also located on this CCA.
Dimensions are 9 x 9 inches.
1.3.4 Power Amplifier Assembly (1A22/1A24).- The RF Power Amplifier Assemblies amplify the RF signals
from the Synthesizer Assembly (1A2/1A14) to the level necessary for radiation by the antennae. In addition,
the SBO and CSB signals are modulated in this assembly. Dimensions are 2.25 x 8.75 x 11.75 inches less
connectors.
1.3.5 Battery Charging Power Supply (BCPS) CCA (1A6/1A10).- This Power Supply provides regulated
+12, -12, and +5 Vdc for the Localizer transmitter. The BCPS (1A6) is located on the left side of the cabinet
electronics rack and provides regulated voltage for transmitter 1. BCPS (1A10) is located on the on the right
side of the cabinet electronics rack and provides regulated voltages for transmitter 2. Dimensions are 9 x 9
inches.
1-12 Rev. C July, 2000

1.3.6 RMS Processor CCA (1A8).- The RMS Processor CCA controls the transmitter and monitoring
systems. It also provides the user interface for control of the Single Frequency Localizer via a Portable
Maintenance Data Terminal (PMDT) computer, the Remote Control and Status Unit (RCSU) and the Local
Control/ Display panel. The RMS Processor CCA measures 9 x 9 inches and connects to the motherboard
through a ninety-six (96) pin and a sixty (60) pin connector.
1.3.7 Cabinet Interface CCA (1A18).- The Cabinet Interface CCA converts analog signals within the Single
Frequency Localizer transmitter for maintenance monitoring of internal voltages, currents, power levels,
modulation percentages, and environmental conditions. An eight bit parallel bus in the RMS processor
monitors and controls Cabinet Interface CCA conditions. All communications and measurement from outside
the Localizer passes through this circuit. Transient suppression is provided for all lines exiting the shelter.
This prevents high voltage from entering the Localizer equipment and damaging vital circuitry within the
system. Serial data transmission between the RMS Processor CCA and external communication devices is
achieved using signals that conform to EIA standard RS-232-C for the PMDT, or modem signals to the
RCSU. Dimensions are 8 x 13 inches. It connects to the backplane through a sixty (60) pin flat ribbon
connector.
1.3.8 AC Power Monitor CCA (1A17).- The AC Power Monitor CCA isolates and scales the station
voltages and currents for measurement by the Cabinet Interface CCA. A twelve position terminal block
provides connection to the incoming AC line for both the electronics cabinet and the obstruction lights. A
14 pin flat ribbon cable connects the AC Power Monitor to the Cabinet Interface CCA. Dimensions are 4.5
x 7 inches.
1.3.9 Main Power Supply Assembly (1A20/1A21).- The Main Power Supply assembly is located on the
back wall of the equipment cabinet behind the electronics card cage assembly. It converts the input voltage
of 115 or 230 Vac into +24 Vdc.
Rev. C July, 2000 1-13

1.4 EQUIPMENT SPECIFICATION DATA.- The equipment specification data is listed in table 1-1.
Table 1-1. Equipment Specification Data.
Equipment Manufacturer Airport Systems International, Inc.
Equipment Type Single Frequency Localizer Station
Model Number 2100-0103 Single Equipment

2100-0104 Dual Equipment
CSB Power 15 Watts nominal, adjustable
SBO Power 400 mW nominal, adjustable
Channel Spacing 50 KHz
Frequency Control Synthesized/TCXO
Frequency Stability ±0.0005%
Type of Radiation Horizontally polarized
Antenna Array 8 or 14 Element Single Frequency LPD
Modulation Frequencies 90 Hz, 150 Hz, 1020 Hz
Modulation Depth 40% (nominal) (90+150 Hz)
8% (nominal) (1020 Hz)
Remote Status Is used for station control and status monitoring
Dimensions (Cabinet) 61 cmW x 61 cmD x 61 cmH

(24 in.W x 24 in.D x 24 in.H)
Weight 54 kg (120 lbs)
1-14 Rev. C July, 2000

Table 1-1. Equipment Specification Data. (cont.)
Environmental:
Temperature -10E C to 50E C
Relative Humidity 0 to 95%, non-condensing
Altitude 0 to 4500 m MSL (0 to 15,000 ft MSL)
Duty Cycle Continuous, unattended
Primary Power 120/230 Vac, 47-63 Hz, single phase
Standby Power +24 Vdc no-break battery backup system with charger
Power Consumption 534 VA (nominal)
Rev. C July, 2000 1-15

1.5 EQUIPMENT AND ACCESSORIES SUPPLIED.- Table 1-2 is a list of equipment and accessories that
may be supplied with the Model 2100 Single Frequency Localizer.
Table 1-2. Equipment and Accessories Supplied.
Quantity Nomenclature Part Number
1 Accessory Kit 470363-0001

1 (optional) Environmental Sensor Kit 470357-0001
2 Technical Manual 572100-0001
1 (Dual, 2) Battery Backup Kit 470351-0001
or Battery Backup Kit 470483-0001
1 Exterior Interface Kit 470361-0001
1 Offset Cable Kit 470070-0005
1 Cabinet Mounting Kit 470364-0001
1 AC Power Kit 470355-0001
1 Antenna Array Kit (8 element LPD) 470353-0003
or Antenna Array Kit (14 element LPD) 470353-0002
1 Portable Maintenance Terminal (PMDT) 470360-0001
1 Fuse Kit, 120V 480145-0001
or Fuse Kit, 240V 480145-0002
1 Power Kit, Loc, 120V 470281-0001
or Power Kit, Loc, 240V 470281-0002
1 Near Field Monitor Kit 470362-0001
1 Far Field Monitor Kit, 120V 471139-0001
or Far Field Monitor Kit, 240V 471139-0002
1-16 Rev. C July, 2000

1.6 EQUIPMENT REQUIRED BUT NOT SUPPLIED.- Table 1-3 is a list of equipment that is not supplied
but is required to make the station operational. Equipment having equivalent characteristics and accuracy
may be substituted.
Table 1-3. Equipment Required But Not Supplied.
Description Suggested Equipment ASII Part No.
Multimeter Fluke 77 950257-0000

Oscilloscope Tektronix TAS250
Frequency Counter B & K 1855, to 1.2 GHz
Portable ILS Receiver Airport Systems 001137-0104
Vector Voltmeter Hewlett Packard/HP8508A option 001 950505-0000
Vector Voltmeter Accessory Kit Hewlett Packard/HP11570A 950505-0001
Grounding Clip Hewlett Packard/HP85089A 950505-0002
50 Ohm Dummy Loads
1.7 OPTIONAL EQUIPMENT.- Table 1-4 is a list of optional equipment.
Table 1-4. Optional Equipment.

Qty Nomenclature Part Number
1 Remote Status Monitor (Receiver) (120 V) 001134-0102

1 Remote Status Monitor (Receiver) (240 V) 001134-0104
1 Remote Status Unit with battery backup 470358-0001
or Remote Status Unit w/o battery backup 470358-0002
1 RCSU w/o interlock, w/o UPS, 120 VAC 002138-0101
or RCSU w/o interlock, w/o UPS, 240 VAC 002138-0201
or RCSU w/o interlock, with UPS, 120 VAC 002138-0111
or RCSU w/o interlock, with UPS, 240 VAC 002138-0211
or RCSU with interlock, w/o UPS, 120 VAC 002138-0102
or RCSU with interlock, w/o UPS, 240 VAC 002138-0202
or RCSU with interlock, with UPS, 120 VAC 002138-0112
or RCSU with interlock, with UPS, 240 VAC 002138-0212
or RCSU, RF ready, w/o UPS, 120 VAC 002138-0103
or RCSU, RF ready, w/o UPS, 240 VAC 002138-0203
or RCSU, RF ready, with UPS, 120 VAC 002138-0113
or RCSU, RF ready, with UPS, 240 VAC 002138-0213
1 Portable ILS Receiver 001137-0104
1 Test Equipment Kit (Loc/GS) 470359-0001
Rev. C July, 2000 1-17

1-18 Rev. C July, 2000

2.1 INTRODUCTION.- The Theory of Operation for the equipment at the station level, transmitter cabinet
level, and individual module level, is presented in this section.
The theory of operation is presented at the block diagram level (simplified theory of operation) for the station
level and the transmitter cabinet level, while the module level presents a detailed discussion comprising both
block diagram theory and detailed circuit theory.
If the theory of operation for a module is not complex enough to require both block diagram and circuit
theory as separate sections, only one section titled “detailed theory of operation” is given.
2.2 SINGLE FREQUENCY LOCALIZER OPERATION.- The Single Frequency Localizer configuration
was developed for use at sites where buildings, aircraft, or reflecting terrain are not present. These obstacles
produce reflections, resulting in course bends in the approach region.
For sites which are free of reflection problems; the single frequency localizer provides a very cost-effective
solution. Depending upon site characteristics; a single frequency localizer may be configured to operate with
an 8 element LPD array, or a 14 element LPD array.
Figures 2-1 and 2-2 depict the antenna patterns for typical single frequency localizer LPD antenna arrays.
Figure 2-1 is the antenna pattern for an 8 element LPD array, and Figure 2-2 illustrates the narrower beam
width obtained from a 14 element LPD array.
Figure 2-1. Antenna Pattern for a 8 Element SF Localizer Array
Rev. C July, 2000 2-1

Figure 2-2. Antenna Pattern for a 14 Element SF Localizer Array
The Course-forming signals are called the CSB (Carrier plus Sidebands) and SBO (Sideband Only) signals.
The CSB signal is simply the primary RF carrier amplitude modulated with 90 Hz and 150 Hz audio tones.
The SBO signal is a double-sideband, suppressed carrier signal, with 90 and 150 Hz sidebands only.
The operation of the Single Frequency Localizer requires creating very specific amplitude and phase
relationships at the radiating antennas in order to develop the proper radiation patterns for the SBO and CSB
signals. This is a function of the antenna distribution unit or DU. The DU receives the Course CSB and SBO
signals, divides them, and produces the correct amplitude and phase distribution to achieve the desired
antenna patterns as depicted in the examples above.
Figure 2-3 shows the interconnection between the transmitter cabinet assembly, antenna distribution unit, and
Localizer antennas. For clarity only one Localizer antenna is shown, whereas in an actual system there would
be typically 8, or 14, log periodic dipole (LPD) antennas, depending upon the antenna array specified.
2-2 Rev. C July, 2000

Figure 2-3. Transmitter, Distribution Unit, and Antenna Interconnections.
Refer to Figure 2-3. From the transmitter cabinet two coaxial feed lines are routed to the distribution unit
cabinet located at the antenna array. These lines are the CSB and SBO transmitter outputs from the
transmitter. Within the Distribution Unit cabinet, the signals are routed to the DU assembly which apportions
the two signals (CSB and SBO) to the antennas in the proper amplitude and phase relationships to generate
the CSB and SBO patterns depicted above. The signals are then routed to each antenna in the array. In each
antenna a sampling probe recovers a sample of the transmitted amplitude and phase which is then routed to
the combiner unit within the DU cabinet. The Combiner unit separates these return signals into CSB and
SBO samples which are then routed back to the transmitter cabinet via two cables; one for the CSB signals,
and one for the SBO signals. Within the transmitter cabinet the CSB and SBO signals are routed to the
integral monitoring circuitry.
Also located within the DU cabinet is an antenna fault card for the purpose of detecting open circuits or
short circuits in any of the coaxial feed lines, or in any of the Integral Monitor return lines, from each antenna.
The antenna fault card detects an open or short by routing a DC signal through each antenna feed and
monitor line. If a fault is detected, the affected antenna is identified in data returned to the transmitter cabinet
by means of an analog value.
Rev. C July, 2000 2-3

2.3 2100 ILS LOCALIZER TRANSMITTER THEORY OF OPERATION. - In this section the operation
of the Model 2100 Single Frequency Localizer is first explained at the cabinet level. In subsequent
subsections, the operation of each module, and CCA, is explained in detail.
In this discussion, there are occasional references to the function of a module when used in a capture-effect
system. This is due to the high degree of commonality between elements of the Airport Systems Model 2100
ILS Systems and has no effect upon single frequency operation.
The Model 2100 may be configured either as a single or dual equipment Single Frequency Localizer station.
It may also be configured as a dual or single Capture-Effect localizer. For all configurations there are many
elements which are common. These include the cabinet, the local control unit or control panel, a Remote
Monitoring Subsystem (RMS) processor, the Cabinet Interface CCA, an AC Power Monitor CCA, a Transfer
drawer, and Bird Wattmeter bodies which monitor the transmitter power sent to the antenna.
Additionally, a Single Equipment configuration will have a Frequency Synthesizer, a Monitor CCA, a Course
Power Amplifier, A 24 Volt DC Primary Power Supply, and a battery charging power supply or BCPS. The
BCPS provides low voltage DC at +5, +12, and -12 Volts, and also charges the 24 Volt backup batteries.
In a Dual Equipment configuration, a second Frequency Synthesizer, Monitor CCA, Course Power Amplifier,
and power supplies are added to form a fully redundant system. In addition, changeover relays and standby
monitoring assemblies are added to the Transfer drawer, enabling the system to operate either as a hot or a
cold standby transmitter. In hot standby operation the standby transmitter is fully monitored, so it’s status
is known all times.
Refer to Figure 2-4, a block diagram of the complete Model 2100 Dual Equipment Single Frequency
Localizer.
A single set of transmitter components comprises a Single Frequency Localizer station. As depicted in Figure
2-4, a dual station has a standby set of transmitter components which are designed as Monitor 2, Synthesizer
2, Course Transmitter 2. In the Model 2100, either set of equipment in a dual equipment station may be
designated as “Main” and the other as “Standby”. The transmitter operates as follows.
The Synthesizer Assembly generates the Course RF signal in the range 108 MHz to 112 MHz in 50 KHz
increments. It also generates a Local Oscillator (LO) signal which is used in the monitoring system. This LO
frequency is output exactly 8.0 KHz below the Course RF carrier frequency. By convention, and to maintain
consistency with the capture-effect systems, this LO frequency is referred to as the “clearance” LO frequency
throughout this document because it is generated by the same hardware used to generate the clearance carrier
in capture-effect configurations. The Synthesizer Assembly generates the Course Transmitter and Clearance
LO signals from the same crystal oscillator source to ensure an 8.0 KHz frequency difference is maintained
between the course carrier and “clearance” LO RF signals.
2-4 Rev. C July, 2000

Figure 2-4. Model 2100 Single Frequency Localizer Block Diagram
Rev. C July, 2000 2-5
When used in the single frequency configuration, the Synthesizer Assembly is arranged by design to generate
a Course signal centered at the station frequency and a Clearance LO signal offset by - 8 KHz below the
station frequency. Selection of any of the 40 available Localizer channels is made through programmable
switches on the Backplane circuit card assembly (CCA) (1A19). The Synthesizer is automatically set to the
programmed RF channel center frequency, and the -8 KHz Clearance LO frequency, upon application of
power.
The audio modulation signals of 90 Hz and 150 Hz are also generated digitally by the Synthesizer CCA. The
Synthesizer generates the CSB and SBO audio signals from the same clock source by means of a digital audio
generator. Sum and difference 90 and 150 Hz audio signals are programmed into Random Access Memories
(RAM) at the required levels to provide the modulation signals, which are then clocked into D/A converters
to produce the analog audio outputs.
The Synthesizer Assembly provides several outputs. These consist of the Course Transmitter RF drive signal,
Course Transmitter CSB Audio Signal, Course Transmitter SBO Audio Signal, Clearance transmitter RF
drive signal, Clearance Transmitter CSB Audio Signal, Clearance transmitter SBO Audio Signal, and bi-phase
switch drive signals used to suppress the SBO carriers. These signals are applied as appropriate to two
identical Course Power Amplifier Assemblies. The clearance RF Carrier and Audio signals are not used
in the single frequency configuration.
Each RF Power Amplifier Assembly receives the RF Carrier Signal from the Synthesizer, the CSB and SBO
audio signals, and the bi-phase switch drive signal, and produces a modulated CSB output and a modulated
SBO output.
Additionally, the RF Power Amplifier (PA) receives an analog control voltage. This enables adjustment of
the SBO phase relative to the CSB phase at the amplifier output over a range of approximately plus or minus
30 degrees.
The output of the PA is routed to the Transfer Recombiner Drawer which contains the main – standby
transfer relays, terminations and power measurement facilities for the standby transmitter, the Monitor
Recombiner unit or MRU, the Transmitter Recombiner unit or TRU, and a relay driver CCA. Figure 2-5 is
a block diagram showing the functions contained within the Transfer Recombiner drawer. For clarity, only
single RF signal paths are shown for the transmitter outputs and monitor signals.
From the Transfer Recombiner Drawer the two transmitter output (CSB and SBO) signals are routed through
RF wattmeter bodies for forward and reflected power measurement, and for Voltage Standing Wave Ratio
(VSWR) measurement. The signals then exit the transmitter cabinet via 2 coaxial cables which conduct them
to the DU cabinet at the Localizer antenna array.
2-6 Rev. C July, 2000

Figure 2-5. Transfer Recombiner Drawer Functional Block Diagram
As explained above, the Course CSB, and the Course SBO signals are returned to the transmitter cabinet
from the Combiner unit in the DU. and enter the Transfer Recombiner Drawer where they are routed to the
MRU. The MRU processes the CSB and SBO signals to create a centerline course signal and a width signal
for the Course transmitter. These two resulting signals are in the process, down converted to an 8 KHz IF
which is then routed to the monitor CCA’s.
The outputs from the standby Course transmitter are routed through the coaxial transfer relays, to the
Wattmeter bodies for measurement of the standby transmitter RF power output, to high power RF
attenuators (which dissipate most of the transmitter output power), and then to the TRU (standby Transmitter
Recombiner Unit). The TRU enables the power output and modulation characteristics of the standby
equipment to be monitored. As in the case of the MRU, the TRU processes and down converts the standby
transmitter signals to an 8 KHz Intermediate Frequency (IF) which is directed to the monitor CCA’s.
Rev. C July, 2000 2-7

The down conversion LO signals for the MRU and TRU are obtained from the synthesizers associated with
the on-air and standby transmitters. An LO transfer relay located in the Transfer Recombiner Drawer
performs this function as indicated in Figure 2-5.
A near field path monitor input detector is also provided as part of the MRU. This input accepts an 8 KHz
IF from an external Near Field Monitor (NFM) receiver.
The Monitor CCAs compute the integral Course path Difference Depth Measurement (DDM), Course width
DDM, and Course RF and modulation levels. The Monitor performs the appropriate action based on the
monitored levels and alarm limits. The Monitor will generate an Integral Alarm, Near Field Monitor Alarm,
Far Field Monitor Alarm or Standby Transmitter Alarm to the Local Control Unit (LCU) which will initiate
an automatic shutdown of the transmitter at a preprogrammed delay (0-120 seconds) after an out-of-limit
parameter is received. The Remote Monitoring Subsystem (RMS) microprocessor will request transmitter
restart through the LCU at programmed intervals.
The Cabinet Interface CCA (1A18) provides an interface between the RMS Microprocessor CCA (1A8)
and the Wattmeters monitoring the RF output of the Course Power Amplifier Assemblies.
Through the RMS Microprocessor CCA, the Remote Control and Status Unit (RCSU) monitors and controls
the status of the Localizer system. Control signals from the Remote Control and Status Unit (RCSU) are
applied to the RMS CCA though a dedicated modem link and can turn the equipment on or off.
Also using the RMS processor, the RCSU monitors and controls the status of the Localizer. Control signals
from the RCSU, are used to drive the LCU, turning off or turning on the station, or transferring operation
from one Localizer transmitter to another.
The Portable Maintenance Data Terminal (PMDT), provides a Windows based interface to setup the
Localizer Transmitter and to monitor transmitter operation. The PMDT communicates with the system via
the RMS processor. It may be connected directly to a receptacle on the outside of the transmitter cabinet,
or may connect by remote dial-in, or by connection to the RCSU.
In the following paragraphs the operation of each module and CCA comprising the Model 2100 localizer
transmitter is discussed in detail.
2.3.1 Synthesizer Assembly (012012) (1A2/1A14) Theory of Operation - The Synthesizer Assembly consists
of one CCA which generates the Course and Clearance RF frequencies, and the audio waveforms, for both
the Course and Clearance transmitters. The Synthesizer is described in the following paragraphs.
2-8 Rev. C July, 2000

2.3.1.1 Synthesizer CCA (1A2/1A14) Block Diagram Theory - Refer to Figure 2-6. The Synthesizer
generates 2 output frequencies 8 KHz apart. The output frequencies are spaced on the assigned frequency
for the Course and 8 KHz below the assigned frequency for the Clearance (LO). The assigned frequency is
set by the technician using the dip switches on the Backplane CCA. The Monitor CCA reads the value of the
DIP switches and sets the correct frequency by writing control information to the synthesizer via the
Backplane at power on.
Figure 2-6. Frequency Synthesizer Block Diagram
The synthesizer generates the RF frequencies by use of a Voltage Controlled Oscillator (VCO) with feedback
error correction. A Numeric Controlled Oscillator (NCO) creates a reference signal by dividing the oscillator
Y1 output of 19.6608 MHZ by a 32 bit long division ratio computed and stored into the NCO by the Monitor
CCA. The NCO generates a reference signal ranging from 2.7 to 2.8 MHZ. This reference signal is the
desired station frequency divided by either 40 or 41.
This paragraph applies to the Glideslope only. The output of the VCO is applied to a frequency multiplier
for Glideslope stations. The frequency multiplication is performed by saturating an amplifier to generate
harmonics. The amplifier output is then bandpass filtered to accept only the Glideslope frequencies.
The signal is then split to drive the power amplifier and the local oscillator.
Rev. C July, 2000 2-9

2.3.1.2 Synthesizer CCA (1A2/1A14) Detailed Circuit Theory.
2.3.1.2.1 RF Signal Generation. Refer to Figure 11-2. The Course and Clearance frequency synthesizers
on the CCA are identical and only the Course section will be discussed. The Monitor CCA programs the
frequency of operation by reading the switch position from the Backplane CCA and calculating a
programming value. This value is written over the parallel CPU bus to U10. U10 is a numeric controlled
oscillator (NCO) that divides the input frequency of 19.6608 MHZ to a lower reference frequency. This
reference frequency is the result of the desired output frequency divided by either 40 or 41. The division ratio
may be set to 40 or 41 by the Select_40_41_0 control line. Thirty two (32) bits of data representing the
division ratio are loaded into the buffers of the NCO U10 by sending two 16-bit words. Connector P1 also
contains a control line which control Localizer or Glideslope modes of operation.
Temperature Controlled Crystal Oscillator (TCXO) Y1 provides the 19.6608 MHZ to the NCO.
Capacitors C30, R19, R20, R22, C33, C34, C37 and inductors L1 and L2 form a capacitively coupled
bandpass filter to reduce the digital switching noise from the output of the NCO. TP12 is used to verify the
NCO output frequency.
Capacitor C38 is a DC block to amplifier U12 which is a 50 ohm input/output MMIC amplifier with 12.5 dB
of gain. Capacitor C45 is a DC block. Resistors R35, R36 and R37 provide bias to transistor amplifier Q1.
Resistors R41, R42 and R43 provide level translation necessary for phase detector U11.
Phase comparator U11 is used to lock the same phase and frequency of the reference signal at pin 9 to the
signal at pin 13. If the reference input at pin 9 leads the variable signal at pin 13, the ŪP̄ line will generate
a negative pulse with a width equal to the phase difference. The D̄ŌW̄N̄ signal will be a logic high. If the
reference signal at pin 9 lags the variable signal at pin 13, the D̄ŌW̄N̄ signal will generate a negative series
of pulses with a width equal to the phase difference. The ŪP̄ signal will be a logic high. Resistor R26 and
capacitor C36 form a low pass filter for the ŪP̄ pulses. Resistors R27 and capacitor C35 form a low pass
filter for the D̄ŌW̄N̄ pulses.
Operational amplifier U13 operates as an integrator for the ŪP̄ and D̄ŌW̄N̄ pulses. The output at pin 6 is a
DC level that varies as the phase difference between the reference signal and variable signal changes.
TP13 is provided to check the Varactor voltage from U13 pin 6. Inductor L4 couples the DC voltage to
varactor CR3. The varactor diode CR3 is used as an electrically variable capacitor. As DC voltage on the
cathode of CR3 is varied, the capacitance of the device varies. The capacitance of CR3 and C48 set the
oscillation frequency of Q2 and form the Voltage Controlled Oscillator.
2-10 Rev. C July, 2000

The output of the VCO is coupled through C51 to amplifier U14. Resistors R51, R52 and R53 provide
isolation and attenuation from the VCO. Capacitor C55 is a DC block to amplifier U14, a 50 ohm
input/output MMIC amplifier with 12.5 dB of gain. Capacitor C58 is a DC block.
Resistors R48, R49 and R50 provide attenuation and isolation from the VCO. PS1 is a 50 ohm power splitter
that divides the input signal at pin 6, equally to pins 3 and 4 each, with ½ the power of the input. PS1 also
provides up to 30 dB of isolation from the input to the output.
The output of PS1 at pin 3 is connected to capacitor C218. Capacitor C218 is a DC block. Capacitor C218
is connected to prescaler U18 at pin 5. Prescaler U18 divides the frequency of the signal at pin 5 by either
40 or 41. The division ratio is 40 when the input at pin 1 is a logic high and 41 when the input is a logic low.
The output of U18 is shifted in level by R65, R66 and R67. TP15 is a convenient location for checking the
output of U18. The signal then enters the variable input of the phase comparator.
The output of PS1 at pin 4 is connected to resistors R54, R55 and R58, which provide attenuation and
isolation. Resistor R54 is connected to DC block C56 and then to amplifier U15, a 50 ohm input/output
MMIC amplifier with 12.5 dB of gain. Resistor R61, C60, C220 and L7 provide DC power to the circuit.
The output of U15 is connected to DC block capacitor C63. C63 is connected to U17, a 50 ohm input/output
MMIC amplifier. Resistor R63, C67, C219 and L9 provide DC power to the circuit. Pin 3 of the U17
amplifier is connected to J5 and labeled CRS_FREQ. The signal then connects to DC block C110.
The signal enters U29, a single pole double throw RF switch. U29 and U31 are MMIC RF switches used in
signal routing when selecting between Localizer and Glideslope functions. When the signal at U29 pin 4 is
at -5 Vdc, the signal at U29 pin 1 passes through to pin 3. The signal then enters U31 pin 3 and through to
U31 pin 1.
The signal path through U29 and U31 is determined by the LOC/ḠS̄ switch on the backplane. When the
switch is closed, current flows through U33A pins 1 and 2. Current then also flows from U33A pins 7 and
8, causing approximately -5 Vdc at pin 5 of U29 and U31.
When the signal at U29 pin 5 is -5 Vdc, the signal at U29 pin 1 passes through to U29 pin 6. The signal is
then connected to DC block C116. Resistors R126 and R128, inductors L19 and L8, capacitors C120, C118
and C199, and Q6 operate as an amplifier that saturates and creates harmonics of the input signal. Capacitor
C122 is a DC block.
Capacitors C124, C126, C127, C130, C132, C133, C136, C138, C139 and coils RSN1, RSN3 and RSN5
form a bandpass filter that passes only the third harmonic of the input signal (Glideslope frequencies).
Rev. C July, 2000 2-11

The output of the bandpass filter enters U31 at pin 6 and passes through to pin 1. The signal then enters
power splitter PS3 at pin 6. The signal is divided equally in power and exits on pin 3 for the output to the
Power Amplifier at RF connector P2-D. The output at pin 4 is the Course Local oscillator and exits on the
P2-E RF connector. Built-In-Test (BIT) power detector circuitry consists of capacitors C146, C150, diode
CR6, resistors R138 and R139. Capacitor C146 samples part of the output power which is rectified by CR6
and charges C150. Resistor R138 discharges the C150 so that the output passes audio but not RF
frequencies. Resistor R139 couples the output to the U38 amplifier. The gain of the amp is set by R172 and
R173. The output of the amp is available on TP20 and connector P1 as CRS_PWR.
Resistors R134, R136, inductor L21, capacitor C148 and diode CR8 provide a bias to the BIT detector
circuit. Detector diode CR8 is biased at the same conduction voltage as CR6. This provides detection at a
lower signal level than without a DC bias on the diode CR6.
Built-In-Test (BIT) frequency lock indication circuitry consists of voltage comparators U9A, U9B, U9C and
U9D. When the Course phase comparator U11, and VCO are locked (normal condition) the output of U11
pin 6 through R17, C32, and R10 to U9A pin 5 will be below 3.6 volts. If the output rises above 3.6 volts
then the phase comparator is out of lock and the output of U9 pin 2 will go high. This signal exits on the P2
connector to be monitored by the Monitor CCA. This signal also enters U9B and exits on pin 1 inverted.
When the Course Phase Lock Loop (PLL) is locked this output is a logic high.
U9B is connected to the Clearance lock detect at U9C pin 14. When both Course and Clearance signals are
in lock then the open collector outputs of the two comparators, U9B and U9C, will be open circuit and
resistor R38 will provide a logic high.
This logic high will cause current to flow through CR2 and turn on the green LED CR2 to indicate that both
Course and Clearance are in lock. When either Course, or Clearance, are not in lock, the output of either
U9B or U9C is a logic low. This will cause current to flow away from CR2 and the LED CR2 will be off.
2.3.1.2.2 Audio Signal Generation Refer to Figure 2-7 and 11-2. The Synthesizer CCA is designed to
interface to the Monitor CCA via address, data, and control buses. These buses enter the CCA via connector
P1.
Clock oscillator Y1 provides a 19.6608 MHZ system or “master” clock. The clock is split and buffered by
U37 (74HC04) and “dampened” by 33 ohm current-limiting resistors (RN10). TP30 provides an external
monitoring point for the system clock. The five clocks derived from the system clock are 1_SYS_CLK,
ASG_CLK, 3_SYS_CLK, NCO_CLK_0, and NCO_CLK_1.
1_SYS_CLK and 3_SYS_CLK are routed to the Monitor CCA via P1:A10 and P1:B10. NCO_CLK_0 and
NCO_CLK_1 connect to U10-30 and U19-30 respectively, and provide the control clocks for the NCOs.
2-12 Rev. C July, 2000

Figure 2-7. Audio Generator Block Diagram
ASG_CLK is the time base for the EPLD (U2-92) internal Audio RAM counter. The EPLD performs several
functions. The EPLD acts as an address decoder, data bus buffer, parity generator/checker, wait state
generator, Audio RAM interface, NCO interface, and BI-PHASE decoder.
Table 2-1 Address Decoding Function of the EPLD

Function Signal Name EPLD Output Pin Monitor
microprocessor
address range
NCO chip select NCOCSN U2-79 1F00H-1F01H
(active low)
NCO latch select NCOLATN internal 1F02H-1F03H
(active low)
Rev. C July, 2000 2-13

Table 2-1 Address Decoding Function of the EPLD

Function Signal Name EPLD Output Pin Monitor
microprocessor
address range
Audio Mode enable TRANSFERN internal 1F04H-1F05H
(active low)
Course phaser DAC CRSPHZRN U2-87 1F06H-1F07H
(active low)
Clearance phaser CLRPHZRN U2-85 1F08H-1F09H
DAC (active low)
Audio RAM select RAMSELN internal C000H-FFFFH
(active low)
NCO interface signals NCOCSN and NCOLATN select register operations within the NCOs U10 and U19.
The NCOs derive an output frequency (U10,19-2) based on an input frequency (U10,19-30) divided/scaled
by a 32-bit binary number. The 32-bit binary number is written to the NCOs in two 16-bit writes via D0-D15
(U10,19 pins 19-26, 8-15) and controlled by NCOCSN (U10,19-27), NCOWRN (U2-51 & U10,19-18), and
three control lines of NCOLATN. The control lines are LOAD_0 (U2-77, U10-36), LOAD_1 (U2-86, U19-
36), and TC3 (U2-73 & U10,19-35).
The NCOs are initialized by RESET (U2-2 and U10,19-38) and the amplitude of the output frequency
waveform is set by the voltage on VAA (U10,19-3) and the scaling resistor between FS_ADJUST (U10,19-
4) and ground. SEL40_41_0 (U2-81) and SEL40_41_1 (U2-72) from NCOLATN set the synthesizer
prescalers (U18,28-1) to either divide by 40 or 41.
The Audio RAM (U3 & U4) is a shared memory arrangement between the monitor and the EPLD with the
monitor always having priority. The Audio RAM contains two banks of 8 K words of 90 Hz and 150 Hz
navigation tone information calculated and stored by the monitor. The 8 K words of memory are direct
read/write from the monitor with one wait state, and are memory mapped to address range C000H through
FFFFH. The Monitor selects a bank of memory with the SYNTH_BSEL line. The monitor relinquishes
control of the RAM to the internal counter of the EPLD by writing a “0" to TRANSFERN (henceforth
referred to as Audio mode) and regains control by reading/writing to an address in the memory range (same
as writing a “1" to TRANSFERN and henceforth referred to as Monitor Mode).
TRANSFERN steers a 14-bit multiplexer in the EPLD that passes address lines A14 - A1 of the monitor or
internal counter lines CA13 - CA0 of the EPLD, through RA13 - RA0 (U2) to the Audio RAM address lines
A13 - A0 (U3 & U4).
2-14 Rev. C July, 2000

The internal counter of the EPLD is reset and static while in Monitor Mode. Data flow between the monitor
and the audio RAM is controlled by a 15-bit (DB14 - DB0) bi-directional buffer in the EPLD. DB15 is used
as an odd parity bit (logical summation of DB14 - DB0) with a “1" indicating a parity error.
DB15 can only be read via the Parity Error signal (U2-50, P1-C11) and is written only by the internal parity
generator of the EPLD during a RAM write.
DB11 - DB0 are reserved for audio DAC information. DB12 is not used. DB13 is reserved as an ident keying
sync bit and DB14 is utilized as a Course and Clearance bi-phase indicator (more detail in Audio Mode
explanation). DB15 - DB0 are terminated with 33 ohm damping resistors (RN5 and RN6) and 10 K ohm pull-
up resistors (R54 and R17).
Once Audio mode is initiated by the monitor, an internal 13-bit counter (CA12 - CA0) in the EPLD
continuously cycles through an 8K word block of Audio RAM. The counter is clocked by the previously
mentioned ASG_CLK (U2-92) after being internally divided by 80. DACWRN is the least significant bit of
the counter and is not used for RAM access. DACWRN has a rate of 245.76 KHz, CA0 is 122.88 KHz, CA1
is 61.44 KHz, etc. CA11 is 60 Hz and can be used as an external sync for an oscilloscope via TP1.
Four Audio DACs (U6A/B, U7A/B) convert the digital information (D11 - D0 of U3/U4) to analog tones.
CA1 and CA0 of the EPLD counter are also inputs to an internal 2-9 decoder. The decoder outputs (U2-
58,57,56, & 55) act as chip selects for the DACs (CRSCSBN, CRSSBON, CLRCSBN, and CLRSBON).
The EPLD selects a RAM location addressed by the 13-bit counter (CA12-CA0), the RAM dumps a 12-bit
word (DB11-DB0), the 2-9 decoder selects a DAC, and DACWRN latches the data in the DAC. Thus each
DAC is clocked at 61.44KHz (DACWRN / 4) and converts 2K of data, resulting in a repetition rate of 33.3
milliseconds (30 Hz).
The DACs are powered by ±12 Vdc supplies (U6,7-6,7) and have a voltage output determined by Vref
(U6,7-3,10). A precision voltage regulator REF08 (U34) supplies the -10.240 Vdc reference, permitting the
DACs a 0 to +10.2375 Vdc output range. A 100 ohm resistor (R3-R6) and 0.1uF capacitor (C20-C23)
provide a low pass filter at the output of the DAC (U6,7-4,9).
DB13 of the Audio RAM (U4-17) and IDENTN (U2-95) are logically combined and utilized as a bank switch
line (CA13) to select the upper or lower 8K (RA13) of Audio RAM (U3,4-26) for transmission to the Audio
DACs. The upper 8K of memory contains only 90 Hz and 150 Hz tone information while the lower 8K
contains additional 1020 Hz information for carrier sideband tones (CRSCSB and CLRCSB).
DB13 indicates a zero crossing of the 1020 Hz ident tone. IDENTN is a request by the Monitor to switch
in the 1020 Hz signal. IDENTN is synched by DB13 before a bank switch is initiated. Bank switching does
not occur until a positive zero crossing of the 1020 Hz occurs after an IDENTN state change. This minimizes
noise splatter in the audio spectrum.
Rev. C July, 2000 2-15

DB14 of the Audio RAM (U4-18) helps generate the signals from the EPLD named CRSBIPHZ and
CLRBIPHZ (U2-62,59). The bi-phase signals are TTL level and indicate a zero crossing of the 90/150 Hz
tone for the Course and Clearance sideband only tones. CRSBIPHZ and CLRBIPHZ are routed to
connectors P2-C7 and P2-C8 and are accessible via TP10 and TP11.
An internal wait state generator within the EPLD interfaces the phaser DACs (U5A/B) and RAM to the
Monitor. A single wait state is required to guarantee a write to U5 or the audio RAM. EXT_CLKOUT (U2-
89), EXT_ALE (U2-74), CRSPHZRN, and CLRPHZRN combine to create EXT_WAITN (U2-78).
EXT_WAITN is routed to the Monitor via connector P1-C16.
TCK (U2-64), TDO (U2-75), TMS (U2-17), and TDI (U2-6) are all routed via ISP connector J1. The EPLD
(U2) is an in-circuit programmable device. An external programmer can drive these signals for configuring
the EPLD, after the CCA is assembled, or possible in-the-field upgrades. RN3 and RN9 are 10 k ohm pull-up
resistor networks used to guarantee high levels on EPLD lines that are tri-stated during in-circuit
programming.
EXT_BHEN (U2-98), EXT_RDN (U2-1), and EXT_WRN (U2-93) are control signals from the monitor
used internally by the EPLD for system control. SYNTH_RESETN (U2-99) initializes the EPLD to a known
starting state. All of these signals are routed via connector P1.
EAD15 - EAD0 are the multiplexed address and data lines from the Monitor CPU. RN1 and RN2 10 k pull-
up resistor networks guarantee high levels during tri-state periods. The address/data lines connect to both
the EPLD (U2) and the phaser DACs (U5A/B) via connector P1.
The phaser DACs (U5A/B) set DC levels used by the SBO phasers within the power amplifier (PA). Refer
to section 2.3.2. The DACs are written directly by the monitor using CRSPHZRN and CLRPHZRN chip
selects (U5-1,2) and EXT_WRN (U5-13). A wait state is generated by the EPLD to insure a valid write to
either DAC. The DACs are powered by ±12 Vdc supplies (U5-6,7) and have a voltage output determined
by Vref (U5-3,10). A precision voltage regulator REF08 (U34) supplies the -10.240 Vdc reference,
permitting the DACs a 0 to +10.2375 Vdc output range. A 100 ohm resistor (R1, R2) and 0.1uF capacitor
(C18, C19) provide a low pass filter at the output of the DAC (U5-4,9).
The six DAC outputs (U5,6,7-4,9) are accessible at TP2 - TP7 and are routed to connector P2 and resistors
R164-R170. R164-R170 in conjunction with the TL062A op-amp (U8B) act as a summing amplifier for fault
isolation testing. When all DACs except the DUT are zeroed, the audio sum output (TP9 and P2-A7) will
directly reflect the output of the DUT.
TX_SELN (P1-B16) and DME_KEY (P1-B17) are monitor controls that operate the DME via DME_KEY+
(P1-B18) and DME_KEY- (P1-B19). TX_SELN must be a logic low to enable DME keying (DME_KEY).
While TX_SELN is high, transistor Q8 is on and current is shunted away from U23, disabling any effect of
DME_KEY.
2-16 Rev. C July, 2000

While TX_SELN and DME_KEY are low, transistor Q9 and photo-coupler U23 are off and the DME relay
is not energized. While TX_SELN is low and DME_KEY is high, transistor Q9 and photo-coupler U23 are
on and the DME relay will be energized.
2.3.2 Power Amplifier (030676) (1A22/1A23/1A24/1A25) Theory of Operation - The power amplifier
provides both amplification and modulation of the RF signal.
Functional operation of the power amplifiers is indicated by the block diagram Figures 2-8 and 2-9. Figure
2-8 depicts the CSB channel of the power amplifier and 2-9 shows the SBO channel. Refer to Figure 11-13.
RF carrier at a level of +10 dBm is input to the power amplifier at connector J2. This signal is routed through
a high pass filter to remove any low frequency components, amplified in MMIC amplifier C, and routed to
power splitters D and E. One output from splitter D provides the carrier for the SBO channel which is
described below. The other output goes to splitter E where one output provides a reference signal for the
CSB phase lock loop. The other output is routed to electronic phase shifter F, and after phase compensation
and modulation becomes the CSB output signal, which is routed to the Transfer Switch and antenna from
J4.
2.3.2.1 Operation of the CSB AM Modulator and Power Amplifier. - Refer to Figure 2-8 and Figure 11-13.
RF from the electronic phase shifter is routed through the MMIC amplifier G to the PIN Diode Modulator
H (CR20-CR23). This modulator consists of two diode attenuators in cascade which provide a dynamic range
of over 50 dB. Power output of the modulator is controlled by driver transistor S (Q10) which is in turn
controlled by loop amplifier R. The modulator provides AM modulation as well as control of the transmitter
carrier power output.
Following the modulator, the modulated signal is passed through a linear power amplifier I, J, K, L, and M.
This consists of MMIC amplifier U20, the FET driver amplifier Q12, and the output stages Q13 and Q14.
Following the driver amplifier, the RF power is split in power splitter K and drives the two output power
stages L in parallel. The outputs are recombined in power combiner M. After combining, a peak envelope
power of over 50 Watts is obtainable. The power stages are high power FET amplifiers which are biased into
class AB operation, and operate with an idle current of 200 Ma each. The amplifiers are all broad band
matched and have no RF tuning adjustments. Impedance matching is accomplished by multiple step L
networks and low Q, T Networks. Examples are C170, L57, C175, and L59 on the input of Q13, and the
T network L52, C153, and L53 on the output of Q12.
After the power combiner M, the signal is directed to a low pass filter which removes any harmonics created
in the RF power amplifier. This is an elliptic function, low pass design, which results in total attenuation of
harmonics to more than 65 dB below the carrier.
Rev. C July, 2000 2-17

The signal is then routed to the directional coupler O and then to the output at J4. The directional coupler
provides samples of both forward and reflected power which are routed to biased, temperature compensated,
AM detectors Q and P.
Reflected power is sensed by detector Q and routed to comparator V which is set to trip if the reflected
power exceeds approximately 5 Watts. This corresponds to a 3 to 1 VSWR at 20 Watts output power.
The comparator output fires a re-triggerable one-shot W which has two functions, reduction of the
transmitter output and sending an alarm to the monitor via the line driver X and J1-12.
2.3.2.2 Operation of the AM Modulation Feedback Loop. - The CSB section power amplifier incorporates
an AM feed back loop to control the modulation, power output, and to reduce modulation distortion
introduced by non-linearity in the PIN diode modulator, and the linear amplifier.
The AM loop error amplifier R is a differential amplifier which receives inputs from two sources; the audio
input originating at J1-17 and the AM detector P which is sampling the transmitter modulated output from
directional coupler O.
The audio input consists of the 90 and 150 Hz navigation tones, 1024 Hz morse identification tones, and a
DC level. The DC level determines the carrier output level. The total peak to peak AC level of the audio
tones determines the percent modulation of the transmitter. This peak level is approximately 7.2 volts relative
to ground when the transmitter is running at 20 Watts output.
The audio is routed from the input connector to the modulation level calibration pot T (R113) and then to
the “reduce power switch” U (U18) and finally to the loop amplifier R (U17B).
The differential inputs are connected at the loop error amplifier R, so an increased audio input results in
increased power output from the modulator, while increased input from the AM detector results in decreased
output. As a result, the amplifier acts to keep the waveform at the detector exactly identical to the input
waveform at its inputs. Since this amplifier has a very high gain, any error in the detected waveform relative
to the audio input, results in a change in the output of the amplifier to the PIN diode modulator in the correct
direction to correct the error. To maintain a constant modulation percentage with adjustment of the audio
drive level, an adjustment pot, R241 on sheet 3 of the schematic, provides an adjustable offset voltage at the
input of the loop amplifier U17B. This offset voltage nulls out the offset created in the biased AM detector
to maintain a constant modulation percentage with varying audio input levels.
2-18 Rev. C July, 2000

Figure 2-8. RF Power Amplifier - CSB Block Diagram
Rev. C July, 2000 2-19
The result is that the demodulated output from the biased AM detector P is an exact replica of the input
signal with very low distortion. The detected signal is buffered and routed to the Monitor via J1-14. It is also
available for test purposes on the PA test point TP4.
2.3.2.3 CSB Phase Feedback Loop Operation. - The CSB channel contains a phase lock loop which has
three purposes.
a. The first is to remove undesired phase modulation sidebands from the transmitter output. This
modulation occurs due to non-linearity in the PIN diode modulator and also to a lesser extent in the
linear RF power amplifier.
b. The second objective is to phase lock the CSB carrier output to the RF input to prevent de-phasing
of the system as the CSB power is adjusted.
c. A third function is to provide a carrier phase reference to a second phase lock loop which is used to
keep the SBO phase constant and provide for adjustment relative to the CSB carrier phase.
Refer to Figure 2-8. In addition to the forward power detector, the sample of the forward power output from
the directional coupler is routed the constant phase limiter Y. The constant phase limiter consists of 4
differential pair limiter amplifiers which can be compensated such that for a 30+ dB change in input level, the
output amplitude and phase do not change. Amplitude variations are held to less than 2 dB and the phase
change to less than 5 degrees.
This limiter removes the AM modulation and passes through any phase variations at its input while not
contributing any significant phase modulation of its own.
The limiter output is routed to power splitter Z which provides two outputs. One is the CSB phase reference
for the SBO phase lock loop. The other is routed via a mechanical phase adjuster AA to the CSB phase
detector AB. The mechanical phase adjuster is used to set the operating point of the CSB phase lock loop
(refer to 11-13), and consists of the components associated with C106 and C109.
The phase detector receives the phase feed back from the CSB amplifier as just described. In addition a
carrier phase reference is input from power splitter E. The phase detector is a balanced mixer type which
produces zero error voltage output when the inputs are at an approximate 90 degree phase difference. Fixed
phase shifters, not shown, in addition to the mechanical phase adjustments, provide compensation for circuit
and path length phase shifts to set up the desired 90 degree phase difference.
The input of the phase loop error amplifier AC is offset about 200 mV from ground so the effective zero
error voltage desired from the detector is approximately 200 mV when the loop is locked.
2-20 Rev. C July, 2000

Total phase control range of the electronic phase shifter is more than 100 degrees for control voltage inputs
of 0 to 12 volts with the center of the control range at 3 to 5 volts. The phase shifter is comprised of varactor
diode CR16, 90 degree hybrid T3, (refer to 11-13).
In operation, the mechanical phase shifter is adjusted to cause the loop to lock and to position the loop
control voltage output from the error amplifier AC (U10A on the schematic) in the 3 to 5 volt range.
The loop bandwidth is sufficiently wide so that undesired Phase Modulation occurring in the PIN modulator,
or the linear power amplifier, is processed and results in a compensating correction voltage producing an
immediate and opposite phase shift by the electronic phase shifter. Phase modulation components appearing
in the transmitter output spectrum are reduced to more than 30 db below the desired 90 and 150 Hz
sidebands.
2.3.2.4 Transmitter Enable/Disable Logic. - Control of the transmitter On/Off status is provided by the
transmitter Enable/Disable Logic AE which acts on both the CSB and SBO modulation circuits. The Tx-
Enable signal is input J1-25. This is a low=True logic level which must be Low to enable the transmitter. Also
input to the logic is a signal from the Thermal Switch AD.
This input will shut the transmitter down if the heat sink temperature exceeds a preset limit. In the event the
thermal shut down occurs, a high=True logic level is routed to the Monitor via J1-11.The output from the
control logic is routed to the PIN diode modulator driver input transistor base terminals (transistors Q10 CSB
and Q2 SBO) and essentially shunts the AM loop amplifier outputs to ground, which removes the RF drive
from the linear amplifiers in both the CSB and SBO channels.
2.3.2.5 SBO Modulator and Power Amplifier Operation - Operation of the SBO AM modulator, feedback
loop, and power amplifier is essentially the same as for the CSB channel, but there are some differences which
will be discussed in this section. Refer to the block diagram Figure 2-9 which depicts the SBO channel.
RF carrier power is input to the SBO channel from the power splitter D on the CSB block diagram. This
signal passes through an electronic phase shifter BB, a 0/180 degree Bi-Phase switch, and then to the PIN
diode modulator, power amplifier, low pass filter, and the output connector J3 via the directional coupler BH,
and the output pad BI.
The linear power amplifier BF consists of Q6 and Q7 on page 2 of the schematic. A single, lower power
output, device is used as only a few watts peak envelope power is required from the SBO amplifier. Again,
this is wide bandwidth amplifier so no RF tuning adjustments are needed.
Rev. C July, 2000 2-21

Figure 2-9. RF Power Amplifier - SBO Channel Block Diagram
2-22 Rev. C July, 2000
Operation of the AM feedback loop and modulator are identical to the CSB channel. There is one difference.
A detector bias offset adjustment BT is provided to enable the SBO detector offset to be compensated so
that 100 percent modulation of the SBO waveform can be obtained without clipping of the lower peaks at
the base of the SBO envelope. The unit to unit modulation sensitivity is set by input pot R54 on page 1 of
the schematic, and the detector offset bias control is R45.
The SBO power amplifier has a 6 dB attenuator at the output which may be selected by setting two jumpers.
This attenuator is used in installations requiring very low SBO power to meet the operational requirement
of the site. Provision of the attenuator enables the power stage, constant phase limiter, and detector to
operate at higher levels for optimal performance.
2.3.2.6 Operation of the SBO Channel Bi-Phase Switch. - The SBO carrier is suppressed by means of a
0/180 degrees bi-phase switch BC, which reverses the phase of the RF signal in synchronism with the polarity
reversals of the SBO modulation wave form.
The control signal for the switch is a 0-5 Volt logic level which is input to the power amplifier from the
synthesizer audio generator module. When the signal is High, the SBO phase is not reversed (relative to the
CSB carrier). When it is low, the phase is shifted 180 degrees.
The Bi-Phase switch drive is also applied to an error correction switch in the SBO phase lock loop which is
discussed in the next section.
2.3.2.7 Operation of the SBO Channel Phase Lock Loop. - The SBO phase lock loop is similar in operation
to the CSB phase lock loop; however the functions are not the same. This PLL has two main functions:
a. Maintain the phase of the SBO suppressed carrier relative to the CSB carrier as the SBO power is
adjusted and over the specified service conditions.
b. Provide a convenient means to electronically adjust the SBO phase relative to the CSB to phase of
the system.
The phase lock loop consists of the constant phase limiter BN, a mechanical phase adjuster BM, the phase
detector BP, the Bi-Phase Error Correction Switch BQ, and the loop amp and electronic phase shifter, BR
and BB.
The SBO output is shifted 0/180 degrees by the Bi-phase switch. This results in a continual reversal of the
error voltage from the phase detector which must be corrected before the error signal can be processed by
the loop amplifier. The Bi-Phase Correction Switch synchronously selects the phase detector output, or an
inverted replica of the output which is created by a unity gain inverter stage.
Rev. C July, 2000 2-23

This removes the effect of the bi-phase switch from the phase error signal and permits the PLL to operate
normally.
Unlike the CSB loop, the SBO loop is not a fast loop and no attempt is made to compensate for amplitude
induced phase distortion. Because of the low power required of the SBO linear amplifier, dynamic phase
corrections are not necessary.
It is required that the SBO suppressed carrier be nominally in phase with the CSB carrier, and that the phase
between the two be electronically adjustable. This is accomplished as follows.
The total phase shift through the CSB and SBO channels is well controlled such that if both electronic phase
adjusters (SBO and CSB) are driven with the same control voltage the phase difference between the two
channels is less than 30 degrees. The phase lock loops then act to maintain an exact phase relationship by
controlling the two phase shifters.
The CSB output phase is locked to the carrier input by the CSB loop. This phase may be adjusted under
closed loop conditions by adjusting the mechanical phase shifter AA in the CSB phase feed back loop. During
factory alignment the SBO phase shifter is fist set to the center of the SBO electronic control range by using
a fixed DC voltage. Then the CSB phase is adjusted to have the same output phase as the SBO.
The SBO loop is then closed, and the SBO mechanical adjustment BM is set to make the SBO carrier phase
identical to the CSB.
Because the phase reference for the SBO loop is obtained from the CSB limiter, the SBO and CSB track each
other and will remain in phase if the power of either output is adjusted or if the temperature changes.
Adjustment of the SBO phase is accomplished by a DC input which ranges from 0 to 10 volts. 5.0 volts is
defined as the SBO to CSB 0 degree phase difference point. Increasing voltage above 5 volts causes the SBO
phase to lead the CSB, and decreasing the control voltage causes it to lag the CSB. Setting of the mechanical
adjustment BM to align the SBO phase with the CSB as described above is accomplished with this phase
control input voltage set to 5.0 Volts. At least ± 20 degrees of adjustment range is provided.
The resistive summing junction at BS on Figure 2-9 (R25, R26, and R17 on sheet 1 of the schematic) sets
the phase control range. Resistor R25 sets the slope of the phase adjustment function which is approximately
linear.
2-24 Rev. C July, 2000

2.3.3 Monitor CCA (1A3/1A13) Theory of Operation. - The primary role of the Monitor CCA is to analyze
the detected integral audio waveforms from the recombiner network that is sampling the antenna RF feed
cables. A secondary role is to analyze detected audio from the standby transmitter and the Near Field
Monitor (NFM). Additional audio waveforms are sampled from test generator circuits located on the Remote
Maintenance Subsystem (RMS) to provide certification of the monitor. Analog signals from the synthesizer
and power amplifiers (PA’s) are also analyzed to provide fault isolation of those modules.
2.3.3.1 Monitor CCA (1A3/1A13) Block Diagram Theory. - Monitoring of the ILS signals is accomplished
using two microprocessors as shown in Figure 2-10. The MDSP software runs on a digital signal processor
that is responsible for collecting Analog to Digital Convertor (ADC) samples of the audio signals then
performing Fast Fourier Transforms (FFT) to calculate the ILS parameters. These parameters are passed
to the MCPU software for comparison against stored alarm limits. If parameters are out of tolerance beyond
the alarm delay times, the MCPU sends alarm signals to the local control unit (LCU).
Figure 2-10 Monitor CCA Block Diagram
Rev. C July, 2000 2-25

The monitor receives analog input signals from the monitor and standby transmitter recombiner assemblies.
These audio signals are conditioned by analog filters that are controlled by the MDSP. The outputs from the
filters, combined with the certification signals, are converted to digital data by the ADC.
Most of the digital circuitry on the monitor board is contained inside two Erasable Programmable Logic
Devices (EPLD). These devices provide all of the address decoding, microprocessor control logic, and ADC
control signals. Discrete logic buffers are used to read the backplane switch settings, read PA and synthesizer
faults, drive status LED’s, drive LCU alarm lines, and configure the synthesizer.
For localizer equipment, a Universal Asynchronous Receiver/Transmitter (UART) is used to receive RS-232
serial data from the Far Field Monitor (FFM). A UART is also used for bi-directional communication with
the RMS microprocessor.
2.3.3.2 Monitor CCA (1A3/1A13) Detailed Circuit Theory.
2.3.3.2.1 Audio Signal Conditioning. - This section describes the details of the monitor’s analog circuitry.
Throughout this section, refer to Figure 2-11 and schematic 11-3.
Integral Course Centerline Audio
Audio from the monitor recombiner can be applied to the monitor as baseband or can be amplitude modulated
on an 8 KHz intermediate frequency (IF). The output of the integral centerline course recombiner is received
and conditioned by U52. Op-amp U52A is a differential receiver with unity gain and a lowpass filter cutoff
frequency of 60 KHz. It has excellent common mode rejection due to the matched resistors in resistor
network RN31. Op-amp U52B is a lowpass inverting amplifier with a gain of 4dB and a cutoff of 60 KHz.
This output is applied to U56 pin 15 and can be inspected at TP13. U54 is a fourth order switched capacitor
filter configured as a four pole highpass filter with a cutoff frequency of 5.5 KHz and unity gain. The output
of the highpass filter is then applied to U52C which is a two pole Sallen and Key lowpass amplifier with 10
dB gain and a 20 KHz cutoff. U52C helps form an 8 KHz bandpass filter response and eliminates bleed
through of the 546 KHz digital clock on U54.
The bandpass filtered signal is applied to diode detector U52D. The input to the detector is AC coupled to
block any DC bias from U52A, U52B, and U52C plus U54. The diodes in the feedback path of the detector
insure only positive voltages will be applied to U56 pin two. The bandwidth of the detector is approximately
30 KHz; therefore, the baseband (90 Hz, 150 Hz, and 1020 Hz) signal will be accompanied with the original
8 KHz IF plus harmonics.
2-26 Rev. C July, 2000

Figure 2-11 Monitor Analog Front-End Block Diagram
Analog switches S1 and S2 of U56 form a multiplexer to select either band pass filtered, and detected, audio
signals when an 8 KHz IF carrier is used, or baseband audio signals, when used.. The normal input mode is
an 8 KHz IF. All integral and standby 8 KHz multiplexer select lines are driven by the Monitor Digital Signal
Processor (MDSP) based on the backplane switch settings of signal INTEG_8KHz_SEL. A high
(motherboard open circuit) on the select line sets the multiplexer for 8 KHz IF bandpass operation.
Switches S3 and S4 of U56 form an additional multiplexer that either passes through audio, or shorts the
input of U58 to ground. Before the MDSP takes any data, it pulls the lowpass filter zero line (/LPF_ZERO)
low to calibrate the DC bias in each MF6 filter through the (ADC), U30, by performing conversions on each
of the six channels fed by an MF6 band pass filter circuit.
Rev. C July, 2000 2-27

Resistor trim pot R202 is used to set the initial DC bias of the MF6 filter at U58 to a positive value that can
read by the ADC. Proper adjustment is accomplished by moving jumper J3 from its normal position (pin 1-2)
to the adjustment position (pin 2-4) then turning R202 until the DC voltage measured with a voltmeter at E4
is 200 ± 5 mV. Jumper J3 must be restored between pins 1-2 after the adjustment.
The baseband audio signal from the DC bias multiplexer is applied to an op-amp filter inside U58. The
inverting active filter provides an input filter for the sixth order lowpass switched capacitor filter inside U58.
A corner frequency of 3.4 KHz and a DC unity gain are used for the analog filter. A 100 KHz TTL clock
applied to U58 sets the lowpass corner frequency at 2 KHz, and the six poles in the filter assure that the 8
KHz IF and harmonics produced by the detector are attenuated below the ADC noise floor. U58B is a two
pole analog lowpass filter after the switched capacitor filter used to strip off the 100 KHz clock signal from
the audio output. An additional RC filter is used before the ADC input to limit the input current and filter
out any high frequency digital interference.
Equivalent Audio Interface Circuits
The circuit used for the Integral Course Centerline Audio is repeated exactly for the Integral Course Width,
and the Integral Clearance Centerline and Width channels. Audio from the Near Field Monitor is also
conditioned by the same circuit design. The NFM bandpass filter multiplexer select line is driven by the
MDSP based on the backplane setting of the signal NFM_8KHz_SEL.
Certification Audio Circuits
Integrity certification of the monitors is continuously being performed by the RMS processor. The two audio
output channels (centerline and width) from the RMS are conditioned and sampled by each monitor. Since
they are sourced as baseband signals, the only conditioning required is the differential receiver U59 with
additional ADC protection diodes CR78 through CR81. Test point TP16 can be used to inspect the
conditioned centerline audio and test point TP17 can be used for the width audio.
Critical Sampling Timing
Since response time of the monitor to alarm is critical, sampling of the four integral, one NFM, two
certification, and one extended multiplexed audio channels is performed simultaneously eight times per
second. Sampling is synchronized to the start of each key time of the identification morse code. This insures
that the samples will contain either a continuous ident tone or no ident tone during the 100 msec
data is collected.
Extended MUX Channels
Sampling of the standby transmitter is done at a much slower rate (every 4.5 seconds) using the final channel
of the analog to digital convertor U30. The input to U30 channel seven is multiplexed to select one of sixteen
possible sources using U34. The first four channels (0-3) are the standby transmitter course and clearance
2-28 Rev. C July, 2000

centerline and width channels after they have been differentially received using op-amp U60. These standby
signals can be inspected on TP32 through TP35. Channels four through seven are course and clearance CSB
and SBO audio from the power amplifier assemblies used for fault isolation and harmonic distortion
calculations. The same four audio channels are also analyzed at the output of the audio signal generator and
appear to the monitor as channels eight through eleven on U34. U34 channels twelve and thirteen are used
to sample the SBO phaser control voltage of the course and clearance transmitters respectively and the last
two channels are not used. Test points TP36 through TP39 are provided to sample the PA detected audio
on the monitor board.
A bandpass filter network consisting of U36, U38, U40 and U42 connects the output of U34 to ADC U30
channel seven. The network is identical to the ones used for the Integral and NFM Audio channels except
for the voltage follower buffer amplifier U36A, used to compensate for impedance variations through U34.
The bandpass filter multiplexer select line for this filter network is dynamically switched by the MDSP
according to which channel is currently being sampled. The bandpass filter is only used for standby
transmitter audio and will not be selected if the INTEG_8KHz_SEL line is low.
Ident Keyer Audio
Provision to select the identification audio for transmission to the internal system speaker or the RCSU via
a voice over data modem is accomplished using U61. Switches S1 and S2 are configured as a multiplexer
to select between the PA detected course and clearance CSB audio signals. This audio contains the 90, 150,
and 1020 Hz tones and is offset with DC voltage. U64A is used as a two-pole highpass filter. It has a gain
of 10 dB and a corner frequency of 900 Hz . When placed in series with U64B, the filter has four poles, a
gain of 20 dB, and a corner frequency of 800 Hz thus eliminating all of the DC and audio tones except for
the 1020 Hz identification. Switches S3 and S4 of U61 are used to enable the identification audio to the
backplane through R236. The control lines for the multiplexers are driven by the MDSP and are selected by
software commands to the monitor. Each monitor defaults on power-up to an open circuit ident audio
condition.
Frequency Separation Detectors
High speed comparators U62 and U63 are configured as zero crossing detectors which act as limiters to strip
off the modulation from the 8 KHz integral and standby IF audio. The TTL outputs at TP18 and TP19 are
8 KHz square waves representative of the course to clearance transmitter frequency separation. For single
frequency transmitters the waveforms at these test points are not used. The comparator outputs are
multiplexed together inside U27 then divided down to an 80 Hz signal and multiplexed with the course and
clearance bi-phase digital inputs. The resulting signal is presented to the Monitor Central Processor Unit
(MCPU), U6, for frequency counting.
Rev. C July, 2000 2-29

Power Supply/Grounding Test Points
Several test points are provided to verify power supply filters and regulators. Test points TP20, TP21, and
TP23 are located on the output of power supply conditioning filters. Test points TP27 and TP28 are used
to check the outputs of the linear regulators U65 and U66 that supply the analog switched capacitor filters
and multiplexers. Test points TP22, TP24, TP25, and TP26 are all connected to digital ground for
troubleshooting and aligning digital circuits, and test points TP29, TP30, and E6 are connected to analog
ground for analyzing analog circuits.
2.3.3.2.2 Digital Signal Processing. - This section describes the details of the monitor’s digital circuitry.
Throughout this section, refer to Figure 2-12 and schematic 11-3.
Main Crystal Clock
The main oscillator used by the monitor is selectable between an external clock, SYSCLK_B, or an internal
oscillator, Y1. The selection is accomplished by shorting J1-1 to J1-2 for the internal oscillator, or shorting
J1-2 to J1-4 for the external clock. In either case, the required frequency is 19.6608 MHz measured at J1-2.
The clock is then buffered by U2C, D, E, and F stages.
Monitor Control Processor Unit (MCPU)
The MCPU, U6, is an Intel 80C196KC microprocessor, which includes an internal eight input port, 12-bit
ADC, full duplex serial port, and 488 bytes of Static Random Access Memory (SRAM).
MCPU Analog to Digital Converter (ADC)
DC voltages are monitored through the built in ADC. +5V_RAW, +12V_RAW, -12V_RAW and
+28V_RAW are resistively divided down to a nominal 4.0 V, then buffered through op-amps U1A, B, C, and
D respectively, before being presented to U6 for sampling. Synthesizer clearance LO power (CLR_PWR)
and course LO power (CRS_PWR) signals are also buffered, amplified and presented to U6 for monitoring.
The reference voltage generator, U3, provides the reference voltage used by both U6 and U30. The reference
voltage is tuned to 5.000V ± 0.005V by trimpot R25, and can be measured at TP1. All of the ADC inputs
to U6 are protected against excessive current and over-voltage by the diode and resistor protection on the
output of each of the op-amps.
MCPU Halt LED
If the MCPU detects a fatal error, the processor will set the MCPU Halt LED, CR18, driven by Q1 and then
shutdown.
2-30 Rev. C July, 2000

Figure 2-12 Monitor Detailed Block Diagram
MCPU Serial Port
The MCPU provides a serial interface within the microprocessor reserved for software test and is not active
in operational units. Connection for this port is at J10. Similarly connectors J7 and J8 are provided for test,
integration and debug of the microprocessor.
Microprocessor Supervisor Chip
U5 is a microprocessor supervisor chip that controls the reset to the circuit card assembly (CCA), holding
the BD_RESET* signal true during power up to exceed the minimum reset time required by the
microprocessors. This timing is provided for either a power up condition, or if the Master Reset signal is
received from the backplane, through diode CR15. The reset out of the supervisor chip is protected by a
reverse biased diode since the MCPU can also drive this line directly. This reset also drives through two
isolation diodes, CR53 and CR55, to terminate the course and clearance power amplifier enable signals.
Rev. C July, 2000 2-31

Watch Dog Timer
A watchdog timer is part of the supervisor chip that must be accessed at a rate faster than once per second
to ensure that the watchdog does not drive the board reset through diode CR16. This is accomplished by
the microprocessor writing to the Alarm Fault Register at a rate faster than once per second. This ensures
that the Alarm Fault Register is updated and that the MCPU is operating normally.
Memory Write Protection
Also included in U5 is protection circuitry for the Non-Volatile Static Random Access Memory (NV-SRAM)
during power up/down cycles preventing erroneous writes to the device.
System Memory
Memory for the MCPU is provided by a 64K x 16 Programmable Read Only Memory (PROM), U10, two
32K x 8 SRAM’s, U8 and U9, and a 2K x 8 NV-SRAM, U11. The NV-SRAM is a standard SRAM backed
up by an Electrically Erasable Programmable Read Only Memory (EEPROM), that is written to with the
contents of the SRAM, when either a power-fail condition is detected or an EEPROM write is commanded
by the MCPU. Total time required to complete an EEPROM write cycle is approximately 10 msec.
Address/Data Bus Decode EPLD
Address/Data Bus decode, control, and chip select control for the various memory and I/O devices are
provided by the Address Controller Erasable Programmable Logic Device (EPLD), U7. Included in the
EPLD design is a 16-bit address latch, chip select decodes for all MCPU devices, Control Register #2, the
Error Register, Bus-width control, SRAM write control, and waitstate control. The EPLD is in-circuit
programmable accomplished through the Address Controller EPLD program port, J6.
To minimize capacitive loading on the MCPU address/data bus, the I/Os have been separated onto an isolated
data bus through a pair of buffers, U13, U14. In the event that no device is selected on either bus, a set of
pull-up resistor packs (RN2, RN3, RN4, and RN5) ensure that the buses go to a known state. Directional
control for the bus drivers is provided by the MCPU memory read command (MEMRD*). The enable
decode for the bus is provided by the Address Controller EPLD, U7.
Universal Synchronous/Asynchronous Receiver/Transmitter (USART)
Interface to/from the RMS and the Far Field Monitor (FFM) is provided through a dual Universal
Synchronous/Asynchronous Receiver/Transmitter (USART), U15, and RS-232 buffer/drivers, U12. Baud
rate generation is done inside the USART dividing down the input clock, 9.8304 MHz provided by the
MCPU as one-half of the system clock, 19.6608 MHz. The MCPU diagnostic serial port, J10 is driven by
part of U12.
2-32 Rev. C July, 2000

I/O Control Registers
Additional I/O registers include System Configuration Registers (SCON), U16, U17, RN7, RN8, Status
Register #2, U18, LED Register, U20, red LED’s CR50-CR47, green LED’s CR43-CR46, Alarm Fault
Register, U19 and External Signal Buffers, U21, U22.
Synthesizer Interface
Connection to the synthesizer is provided through the Synthesizer Interface buffer/drivers, U23, U24, U25,
U26. The bank select for the upper data bank is provided by the MCPU signal BSEL. If the monitor CCA
is installed as the slave unit (monitor slots 1A4 or 1A12), the Synthesizer Interface behaves the same with
the exception that any read accesses from the synthesizer port will return all “1's”.
Discrete Control EPLD, U27
Additional control circuits are included in the Discrete Control EPLD, U27. These include:
1) BCLEAR* Signal Generation - BCLEAR* is generated by “or”ing the board level reset
BD_RESET*, with the MCPU software generated reset, SW_RESET*. BCLEAR* is used to reset
all on board I/O’s, the MDSP, and the synthesizer.
2) ADC Sample Timing and Control Signals - Timing for the ADC (U30) clock and the serial clock
between the MDSP and the ADC is generated here along with the Start Conversion signal
(CONV_START*) and the Serial Synchronization signal (SYNC*). The main clock, 19.6608 Mhz
is divided by eight producing 2.44576 MHz which is used as the ADC Clock. This signal is then
counted out for 30 cycles. This produces a sample rate of 81.92 KHz. Both the SYNC* and
CONV_START* signals are decoded from the 30 cycle counter to transfer data between the ADC
and MDSP and to start the next conversion cycle. This produces enough samples to measure eight
different input signals to the ADC with 1024 samples in 0.1 seconds, allowing 10 Hz separation
between frequency measurements made by performing a Fast Fourier Transform (FFT) conversion
of the input data.
3) 8 Hz Time Generation. -An 8 Hz signal is generated by the MCPU locally for synchronization of the
MDSP’s in the whole system, to ensure that measurements are not made across the transition times
at the beginning and ending of Morse Code Identification generation. If both Master and TX_SEL*
signals are true, the local 8 Hz signal is multiplexed out to the MDSP and MCPU. If either Master
or TX_SEL* are not true, the signal multiplexed to the MDSP and MCPU is the 8 Hz signal
generated off board. This ensures that the MCPU that is currently transmitting is generating the 8
Hz synchronization signal.
4) MDSP/MCPU Interface Control. -The interface between the MDSP and MCPU is accomplished
through two flip-flops with this EPLD as shown in Figure 2-13.
Rev. C July, 2000 2-33

5) MF6/LTC1060 Clock Generation. - The clocks for the two switched capacitor filter networks are
generated by free running counters. The clock frequency used to clock the counters is the main clock
frequency of 19.6608 MHz. The MF6 clock is 100.31 KHz generated by dividing 19.6608 MHz by
196. The LTC1060 clock is 546.13 KHz generated by dividing 19.6608 MHz by 36.
6) MDSP IDMA bit 14 Address Control. - To facilitate the address interface between the MDSP and
the MCPU, address bit 14 needs to be driven high during the address portion of the bus cycle. The
address decode for the MCPU to access the dual-port memory within the DSP is from 0x1D00 to
0x1EFF. The physical location within the MDSP for data RAM is from 0x5D00 to 0x5EFF. While
the Address Latch Enable (ALE) signal is true, Modified Address bit 14 (MAD14) is driven high
latching in a high on every trailing edge of ALE. When ALE is false, MEMRD* selects direction for
the data to flow through with the output enable tied to the MDSP chip select (DSP_CS*).
7) MDSP Address Decode and Control. - Address decodes within the MDSP address space are limited
to the Filter Control Register. Since this is a write-only register, it is decoded with the MDSP I/O
segment select signal (DSP_IOMS*), the MDSP write command signal (DSP_WR*) and address bits
BADR8 and BADR9.
8) PA Enable Signals. - To allow control of the PA enable signals, a 3600 Hz pulse is received over the
TX_ON signal. While the pulse is present, a TX_ON flip-flop is set. If the synthesizer has been
configured and the CRS_PA_EN and CLR_PA_EN registers have been set by the MCPU, the course
and clearance PA’s will be commanded on. If the 3600 Hz signal is removed, the PA enable signal
will be removed within seven msec.
If both the MCPU and MDSP set their respective command signals, CTX_FORCE_ON and
DTX_FORCE_ON, the PA’s will be forced on regardless as to the condition of the other signals.
This state is only used for fault isolation and lasts less than five seconds while a complete set of PA
and synthesizer data is collected.
The output from the PA enable circuits within U27 are fed to a pair or inverters, U28C and B, which
drive two transistors, Q3 and Q4, to enable the course and clearance PA’s. If reset is applied to the
monitor CCA, the transistors immediately disable the PA’s.
9) Clearance and Course Bi-Phase and 8 KHz Divider/Multiplexer. - The 8 KHz outputs of U62 and
U63 respectively, are fed to a multiplexer then divided down to an 80 Hz signal which is further
multiplexed with the course and clearance bi-phase digital inputs. The resulting signal is presented
to the MCPU, U6, for internal frequency counting.
The EPLD employed is in-circuit programmable accomplished through the Discrete Control EPLD Program
Port, J5.
2-34 Rev. C July, 2000

Figure 2-13 MDSP to MCPU Interface. (Note: * indicates low-true logic)
Monitor Digital Signal Processor (MDSP)
The MDSP, U33, is an Analog Devices ADSP-2181KS-20 digital signal processor, which includes two high
speed serial ports, 16K x 24 program RAM, 16K x 16 data RAM, and an internal direct memory
access (IDMA) 16-bit interface. A DSP emulator port, J9, is provided for integration and test of the MDSP
software.
MDSP EPROM
An external 64K x 8 PROM, U31, is used to store the MDSP program which is downloaded into the internal
program RAM on power up.
MDSP Filter Control Register
An external DSP Filter Control Register, U29, is used to enable the different analog filters as described
above.
Rev. C July, 2000 2-35

MDSP ADC Interface
The ADC used in the design, U30, is an Analog Devices, AD7858, 12-bit, eight channel ADC capable of data
conversions up to a 200 KHz sampling rate.
MDSP Halt LED
If the MDSP detects a fatal error, the processor will set the MDSP Halt LED, CR65, driven by Q5 and then
shutdown.
Main Interface Connections for Monitor Module
Connection to the rest of the system is accomplished through two connectors located at the bottom of the
circuit card assembly, P1, P2. P1 is a 96 pin, three row connector. P2 is a 60 pin, three row connector with
spaces provided for four RF style connectors. No RF connectors were used in the monitor design and have
not been installed in the connector. Keying for the assembly is provided by a keyway attached to the outside
of both connectors that mates with a key-way on the backplane.
2.3.4 RMS CCA Theory of Operation. - The Remote Monitoring Subsystem (RMS) gathers data from
various sensors and internal monitoring points within the ILS station and controls various functions of the
ILS station. In order to accomplish this, the RMS communicates with up to four station monitors through
serial interfaces. It also communicates with the Cabinet Interface CCA (CI) through a parallel interface in
order to gather analog and status data directly from the various sensors.
The station status and various data is reported to the local status/control unit (LCU) and to the Remote
Control and Status Unit (RCSU) through a modem with simultaneous voice communication capabilities. This
modem permits identification tone monitoring along with RCSU to station voice intercommunication.
2.3.4.1 RMS CCA (012015)(1A8) Block Diagram Theory. - Refer to Figure 2-14. The RMS circuit card
consists of a microprocessor with RAM, PROM and EEPROM, EPLD, multiple serial interfaces, a modem,
a parallel interface, and a dual audio test generator.
2.3.4.1.1 Test Generator - A dual audio output test generator within the RMS produces precise ILS audio
signals in order to certify the accuracy of the monitors. Up to 16 different waveforms can be selected by the
microprocessor to be output for each of the two channels. Each point in the waveforms is calculated by the
RMS microprocessor and stored in a 32K x16 static RAM which is dedicated to use by the test generator.
An erasable, programmable, logic device (EPLD) provides the logic to control the operation of the audio
generator. A waveform is sent to each DAC as a repeating series of 2048 12 bit values at a rate of 61440
points per second. This produces a waveform that repeats every 1/30 sec. Because of the high sampling rate,
a very simple RC low-pass filter (R23, C7 and R24, C8) is needed to remove high frequency components
from the waveform. The EPLD also provides various other logic functions for the RMS CCA, such as
address decoding.
2-36 Rev. C July, 2000

Figure 2-14. RMS CCA Block Diagram.
Rev. C July, 2000 2-37
2.3.4.1.2 Microprocessor and Associated Circuitry - A 16 bit microprocessor, an Intel 80C186XL (U5), is
used to control the RMS card. It uses a 64K word (64K x16) PROM (U6) for program storage and two 32K
x8 static RAM ICs (U8 ,U9) for read/write memory. In order to prevent the loss of data in the event of a loss
of power, the RAM is backed up by a lithium battery (B1). Also, there is a 8K x8 EEPROM (U7) which is
used to store setup data. A power fail controller IC (U3) is used in order to provide a reliable transition to
and from a power-down state. A real-time clock (U4) is used to provide day/date/time information and a
timer interrupt signal to the microprocessor. It continues to count time during a power-down condition under
battery power.
2.3.4.1.3 Serial Interface - The serial interface provides the communications interface for the microprocessor
to communicate with other devices. The Zilog Z85230 enhanced serial communications controller (ESCC)
IC is used for each of five dual serial interface circuits used to provide the serial interface capabilities of the
RMS circuit card. One serial interface (U31B) is used for the simultaneous voice + data (SVD) modem on
the RMS card. The SVD modem allows a technician at the station to communicate with someone at the
RCSU without breaking the serial data connection.
The other serial interface lines are converted to/from RS232 levels and used to communicate with the
following external devices:
SCC0 (U22A) - PMDT SCC0 (U22B) - Spare

SCC1 (U23A) - Monitor #4 SCC1 (U23B) - Monitor #2
SCC2 (U26A) - Monitor #3 SCC2 (U26B) - Monitor #1
SCC3 (U27A) - DME #1 SCC3 (U27B) - DME #2
SCC4 (U31A) - External Modem or SCC4 (U31B) - SVD Modem
Dial-up Modem
In order to keep from excessively loading the microprocessor’s address/data bus, the bus signals to and from
the ESCCs are buffered.
2.3.4.1.4 Parallel Interface - The RMS communicates with the Local Control Unit (LCU) and the Cabinet
Interface Unit (CI) through an eight bit parallel interface.
2.3.4.1.5 Power Supply - Power is supplied to the RMS CCA by either of the two station 24 Vdc supplies.
The power is converted to +5 Vdc and ± 12 Vdc by a DC to DC converter (PS1) on the card.
2-38 Rev. C July, 2000

2.3.4.2 RMS CCA (012015)(1A8) Detailed Theory of Operation. - Refer to Figure 11-5.
2.3.4.2.1 Power Supply - The power for the RMS CCA comes from two separate sources of +24 Vdc
through Schottky rectifiers CR4 and CR5. The rectifiers isolate the two 24Vdc sources from each other and
allow either to supply power to the board. The 24 Vdc is converted to +5 Vdc, +12 Vdc and -12 Vdc by a
DC to DC converter PS1. The +5 Vdc supplies power for all the digital circuitry and the ±12 Vdc supplies
power for the analog and the RS232 interface circuitry. The supplies may be adjusted by potentiometer R50.
2.3.4.2.2 Microprocessor and Associated Circuitry - The microprocessor and its firmware are responsible
for monitoring and controlling the ILS system and directing communications with peripheral devices. The
microprocessor uses RAM, PROM, EEPROM, bus control, real time clock, and power monitor circuitry to
perform its functions. It processes the system status, directs communications with other devices, monitors
co-located DME systems, and communicates with the ILS monitors.
The microprocessor, U5 is an Intel 80C186XL. It accomplishes several major and minor functions in
accordance with its software programming. The clock input is driven by Y2, a 32 MHZ crystal controlled
oscillator. The 32 MHZ signal is divided by two within the microprocessor to produce a 16 MHZ internal
clock. The microprocessor uses a multiplexed bus to communicate both address and data information (AD0-
AD15). During a read or a write operation, the address is first placed on the bus, then the data is read from
or written to the bus. This makes it necessary to use latches to capture the address from the multiplexed
address/data bus when it is valid, store it during the remainder of the read or write operation, and place it on
the address bus (A0-A17). Two octal latches, U10 and U11, perform this function for address bits A0
through A15. The same function is performed for A16 and A17 within the EPLD U14. In this case however,
the input to the latches, AS16 and AS17, contains the address multiplexed with status information. The status
information on these lines is not used and the two address bits are latched in the same manner as for A0-A15.
The microprocessor U5 performs the major function of handling address/data control for the system. The
program for operating the RMS Processor CCA is stored in PROM U6 which is a 1024K bit (64 k by 16
bit) memory device. U6 is referred to as a “one time programmable” (OTP) PROM because it cannot be
erased and re-programmed. Chip select signal UCS* from U5 enables U6. The microprocessor also uses two
256K bit (32K by 8 bit) static RAM memory devices, U8 and U9, to store its stack and for the temporary
storage of data. The RAM is also used for the storage of operational parameters, test, and historical data
which is needed for a finite duration. U5 uses this data while performing calculations and data processing.
An EEPROM U7, a 64K bit (8K by 8 bit) device is used to store all local parameters such as alarm points,
station identifier, station morse code call letters, etc. for the ILS system. To prevent corruption of data,
parameters are stored in both the RAM (U8, U9) and the EEPROM (U7) with a checksum. Upon application
of power, the data in RAM (U8, U9) is checked for a valid file system structure. If the structure is not
correct, the file system structure will be remade. Then, data in EEPROM is checked against its checksum.
If incorrect, default values from the PROM (U6) are loaded to both RAM and EEPROM and used. If
correct, a check for the correct software revision level is made. If the revision level does not match, default
Rev. C July, 2000 2-39

values from the PROM (U6) are loaded to both RAM and EEPROM and used. If it does match, values from
EEPROM are loaded to RAM and used. If there is a change in the type (from localizer to glideslope, or vice-
versa) of the ILS since power was last applied, the correct (localizer or glideslope) default data values are
always loaded from the PROM (U6) to both RAM and EEPROM and used.
2.3.4.2.2.1 Address Decoding - The EPLD, U14 performs various logic functions. It performs all the
address decoding for the board. U14 also controls the test generator circuit. The 80C186XL microprocessor
has a 16 bit data bus, but is able to also perform 8 bit memory and I/O operations. As a result of this, an odd
addressed byte must be placed on the upper 8 bits of the data bus (AD8-AD15). Routing data from 8 bit
devices to the upper part of the data bus requires extra circuitry. Therefore communication with all 8 bit
devices is performed on even addresses so that data can be transferred on the lower 8 bits of the data bus
(AD0-AD7) only. For 16 bit devices such as the RAM and PROM, the 16 bits of the device are simply
connected to the 16 bits of the bus. Read operations from the RAM and ROM are simple. For word (16 bit)
reads on an even word boundary (A0=0), the microprocessor outputs the address and reads the 16 bits from
the device. For byte (8 bit) reads the microprocessor outputs the address and reads the 8 bit data either from
the low 8 data bits if the address is even, or the high 8 data bits if the address is odd. The same applies to
word reads from an odd address. This operation is split up into two separate byte read operations by the
microprocessor. The LCS and UCS lines from the microprocessor are used for the chip enable inputs of the
RAM and ROM respectively (as discussed above, the LCS for the RAM goes through U3), for protection.
Write operations to 16 bit devices such as RAM, are more complicated. For 8 bit write operations, the
address decoding logic must prevent a write to the unwanted byte or else an indeterminate value will be
written to it. This decoding is performed in U14 by providing separate logic for the WR inputs of the low
byte (U8) and the high byte (U9) of RAM. The write decoding logic for U8 uses A0=0 to ensure that data
is intended to be written to the low byte. The write decoding logic for U9 uses the BHE signal from the
microprocessor to ensure that data is intended to be written to the high byte.
The EEPROM, U7, is an 8 bit device. The data lines are connected only to the lower 8 bits of the data bus.
As a result, data can only be read or written to these devices on even addresses. A0 must be zero for even
addresses. Thus, these devices must use address lines starting at A1 to provide addressing within the device.
Other 8 bit devices that share this characteristic are the serial interface ICs, the parallel interface data and
control, and the station configuration read, as well as some functions within the EPLD that are used with the
test generator.
The test generator RAM (U15, U16) provide a special case. Although it is interfaced to all 16 bits of the data
bus, it must be accessed by the microprocessor with even word operations because the write control lines of
the upper and lower devices are connected together.
2-40 Rev. C July, 2000

2.3.4.2.2.2 Interrupts. - U5 has five interrupts; NMI, INT0, INT1, INT2, and INT3. NMI*, which comes
from test point TP1 and is inverted by U1A, is used only for testing purposes. INT0 is used for power fail
and real time clock functions. Interrupts 1, 2, and 3 are each inverted by U1F, U1B, and U1E. The input to
each of these inverters is pulled up to +5V (VCC) with a pull-up resistor. INT3 is not presently used, but is
connected to the backplane connector P2-B15. INT2 comes from the serial interface ICs U22 and U23 and
indicates that Monitor 4, Monitor 2, or the PMDT, is waiting to communicate with U5. INT1 comes from
U26, U27, and U31 and indicates that monitor 3, monitor 1, a modem, or a DME system, is waiting to
communicate with U5.
2.3.4.2.2.3 Power Fail, Reset, and Watchdog Functions (U3). - Microprocessor supervisor U3 is a
watchdog, battery changeover, and reset generator that works in conjunction with U5.
U3 has three power fail detection functions. One senses the lowering of the 24Vdc and provides a slight
advance warning to the microprocessor. Another senses the lowering of the +5V (VCC) supply to a threshold
voltage of 4.65V and immediately disables operation of the microprocessor and RAM (U8, U9). A third
power failure function in U3 provides a continuous source of power (VBB) for the RAM (U8, U9) and real
time clock (U4). When the VCC supply voltage is normal, the backup (VBB) voltage to the board is obtained
from the +5V (VCC) supply voltage applied to U3. When the +5V supply falls below the battery voltage,
U3 switches its VOUT (which is connected to the node VBB) from the +5V supply to a lithium battery which
is connected to its Vbatt input.
The 24 Vdc that the DC-DC converter uses to power the board is applied to a voltage divider network
consisting of resistors R2 and R6. The power fail sense line of U3 (PFI) samples the ratio of the supply
voltage. A normal supply voltage produces a reference voltage of approximately 2.75 Vdc at the power fail
input (PFI) of U2. This voltage is greater than the internal 2.27 Vdc power fail limit reference. When the
24V being supplied to the DC-DC converter (PS1) drops below about 19.7V, the PFO output of U3 goes
LOW. This signal is inverted by U1D. The resulting HIGH logic level then goes through OR gate U2D to
produce an INT0 at the microprocessor. The other input of U2D is the timer interrupt 0 signal from real time
clock U4. When either a real time clock interrupt or a power failure occurs, U5 will also receive an INT0
signal. To interpret the difference between a power fail condition and the normal operation of the real time
clock, U5 attempts to clear the INT0 flag within U4. If the flag clears, then the HIGH was generated by U4.
If the flag is again set, then the HIGH had to have been generated by a power fail condition, and U5 is forced
into a data protect condition by the software program.
A short time after the lowering of the 24V occurs, the VCC will lower. When U3 senses the lowering of the
5V VCC supply to below the reset threshold of 4.65V, it will assert RESET and R̄ĒS̄ĒT̄ signals which will
prevent any further operation of the microprocessor. Also the C̄Ē to the RAM U8 and U9 will be disabled,
which will prevent any further access to the RAM ICs as they enter data retention mode. When VCC reduces
further to below the voltage of the lithium battery B1, U3 instantly switches the source of the VBB output
voltage to the battery. Under the control of U3, the battery supplies 3.5 Vdc back-up power to real time
clock U4, OR gate U2, and static RAM U8 and U9. U3 also provides the BATT_ON output to indicate that
Rev. C July, 2000 2-41

the circuit board is on battery power. This signal is used with OR gates U2A, U2B, and U2C to disable the
RD, WR, and PCS0 (chip select) signals going to U4.
At power up, U3 asserts RESET and R̄ĒS̄ĒT̄ signal to U5 and other devices on the board. These lines inhibit
the microprocessor and other devices while the voltages and circuits are stabilizing from the application of
power. Once the supply voltage VCC input exceeds the internal reset threshold of 4.65V, a 200 millisecond
timer begins. After the 200 msec period has ended, U3 un-asserts the RESET and R̄ĒS̄ĒT̄ lines which allows
U5 to begin functioning according to the software program stored in U6. The timer insures that the voltage
has stabilized and is not cycling on and off.
U3 receives a watchdog signal from U5. The watchdog circuit monitors the activity of the microprocessor.
If U5 does not toggle the watchdog input (WDI) every 1.6 seconds, U3 will assert the RESET and R̄ĒS̄ĒT̄
lines forcing the microprocessor to attempt to re-initialize itself and the board. Also, U3 forces the watchdog
output (WDO) LOW. This turns on transistor Q2 which causes light-emitting diode (LED) CR3 to
illuminate. If a non-operational condition is not corrected by the reset, CR3 will provide a visual indication
that a CPU fault has occurred.
To prevent corrupted data from being written to the RAM, in the event of a power failure, the chip enable
to U8 and U9 is routed through the microprocessor supervisor IC U3. Upon sensing a power fail condition,
U3 immediately disconnects the CE to the RAM from its source and pulls the CE to an un-asserted (HIGH)
logic level.
2.3.4.2.2.4 Real Time Clock. - Real time clock U4 contains a day/date/time counter (0.01 seconds to years),
an oscillator clock, an interrupt control, an 8-bit data I/O, five address inputs, and several control inputs.
This device provides a true time and calendar output to the micro controller through the bi-directional 8-bit
data lines. When normal supply power is lost, 3.5 Vdc from lithium battery B1 is applied to the power bus
line by U3 to maintain the internal clock function and interrupt signal of U4.
U4 uses a 32.768 KHz clock frequency obtained from crystal Y1. Capacitor C4 is used to fine tune the clock
frequency to produce a precise timer interval (Ī N̄T̄) signal from U4. The adjustment of C4 is performed by
monitoring the signal at TP2. C4 is adjusted to produce a one second positive going gate at TP2. The INT
pulse is a short duration (less than 50 microseconds) pulse that is inverted by U1C. This signal is the
interrupt zero (INT0) pulse that is sent to U2D and U5.
U4 interfaces to the microprocessor through the lower eight bits of the data bus AD0-AD7, and uses A1-A5
for addressing. The microprocessor uses its internally decoded peripheral chip select PCS0 to select it. The
microprocessor programs the U4 for proper functionality by writing to its command register at PCS0+22H
and its interrupt mask register at PCS0+20H.
2-42 Rev. C July, 2000

2.3.4.2.3 ILS Test Generator - The ILS test generator consists of a dual 12 bit digital to analog converter,
U17, two 32K by 8 bit static RAM ICs, U15 and U16, and control logic within the EPLD (U14). Each of
the two outputs can reproduce any of 16 different waveforms which are stored in the RAM. The waveforms
are calculated by the microprocessor and written into the RAM. The microprocessor also selects which of
the 16 waveforms goes to each DAC. A waveform is sent to each DAC as a repeating series of 2048 12 bit
values at a rate of 61440 points per second. This produces a waveform that repeats every 1/30 sec.
The test generator has two modes of operation. One mode halts the output of the waveform and allows the
microprocessor to read and write to the test generator RAM. The other mode continuously outputs the
waveforms and does not allow the test generator RAM to be accessed. The microprocessor (U5) selects the
mode by writing a zero or a one to an I/O address of PCS2+6. A zero selects the mode which disables the
waveforms and allows the RAM to be accessed and a one selects the mode which enables the waveforms and
disallows RAM access. For purposes of discussion, these modes will be referred to as mode ZERO and mode
ONE, corresponding to the value written to PCS2+6.
When the mode ZERO is selected, a 15 bit multiplexer within the EPLD connects microprocessor address
lines A1-A15 to the address lines of the RAM ICs, U15 and U16. Address decoding is also enabled within
the EPLD. This provides an output enable and a write enable signal to the RAM ICs and an enable signal for
bus transceivers U12 and U13. These bus transceivers provide a data path from the data lines of the RAM
(U15, U16) to and from the microprocessor’s data bus (AD0-AD15). Also during this mode, logic in the
EPLD disables the enable lines to both sections of the dual DAC U17, so the voltage at both test generator
outputs remains constant.
The address decoding logic within the EPLD will allow only reads and writes to even addresses of the test
generator RAM, so word accesses to even addresses must be used. The microprocessor’s internally generated
MCS0 sets the base address of the test generator RAM. A contiguous block or “bank” of 2048 values in the
RAM specifies the voltage of the DAC output for a particular waveform. Since the test generator RAM
contains 32768 locations, there is sufficient capacity in the RAM for 16 different waveforms. The
microprocessor calculates the value of each point of the waveforms and writes them to the test generator
RAM. This occurs after a reset condition in the microprocessor. One or more of the waveforms can be
recalculated at any time under firmware control.
When mode ONE is selected, the EPLD sends a series of addresses to the RAMs that are generated by
sequencing logic within the EPLD along with a continuous output enable signal to make the RAM perform
a read operation on each address. The bus transceiver, U12 and U13, is disabled so that no connection with
the microprocessor’s data bus is possible. The series of addresses sent to the RAM makes it output the
correct series of data to the dual DAC U17. The series of data alternates between a data point for each of
the DACs. When the data point for a DAC within U17 is valid, the EPLD generates an enable signal
(DACEN0 or DACEN1) to latch the data into the appropriate DAC. In order to generate the proper series
of addresses with the proper timing, the EPLD takes a 1.8432 MHZ clock signal from crystal controlled
Rev. C July, 2000 2-43

oscillator Y3 and divides it by 15. The resulting 122.88 KHz is used to clock out the series of addresses
which alternate between the address of the data for the first DAC and the data for the second DAC. For each
two addresses (one to access the data for each DAC), the least significant 11 bits of the address are the same.
These 11 bits specify which of the 2048 points in the waveform are addressed. The most significant four bits
alternate between two values in order to select which of the 16 signals within the RAM are addressed for
each DAC. The four bit value for each DAC is stored in an eight bit latch within the EPLD. A four bit
multiplexer in the EPLD alternately selects between the two, four bit values and adds them to the 11 bit
address to create a 15 bit address for the RAM. A short time after an address is sent to the RAM, an enable
signal is sent to the appropriate DAC. This results in data being sent to each DAC at a rate of 61440 times
per second. After 1/30 of a second has elapsed, and 2048 data points have been sent to each DAC, the
waveform repeats.
The EPLD logic allows the microprocessor to write to the eight bit latch which stores the two sets of four
bits used to select one of the 16 waveforms to be sent to each of the two DACs. This is accomplished by
writing an eight bit value to the I/O address of PCS2+4. The lower 4 bits specifies which of the 16 waveforms
are used for the TGEN1 output. The upper 4 bits specifies which waveform is used for the TGEN2 output.
The selection of the waveforms by the microprocessor is allowed in either mode ZERO or ONE.
Because the test generator output is updated at such a high rate (61440 times per second), a simple R-C low
pass filter is all that is necessary to filter out undesirable high frequency components in the waveforms. The
R-C network consists of a series 100 Ohm resistor (R23, R24) followed by a shunt 0.1 uF capacitors (C7,
C8). The 100 Ohm resistor also serves to isolate the operational amplifiers within the DACs from capacitance
resulting from the connections between the RMS CCA and the monitors.
In order to perform fault isolation on the test generator, a window comparator circuit is used to compare the
voltages of the two outputs of the DAC U17. The window comparator circuit uses a dual comparator, U19.
The output of each comparator can be read by the microprocessor through logic in the EPLD U14. Each
comparator compares one of the DAC outputs with a slightly lowered version of the other DAC output. A
voltage divider to the -10.24V reference lowers the voltage of the negative input of each comparator. The
voltage divider uses a 100 Ohm resistor in series with the DAC output and a 100K Ohm resistor to the -
10.24V reference. The 100K resistor (R18, R20) sinks 100-200 uA of current which results in a voltage drop
of 10-20 mV across the 100 Ohm resistor (R19, R22). This results in the comparators both having HIGH
outputs when the two DACs have the same output voltage. If the DAC voltages are different by more than
10-20 mV, one of the comparator outputs will be LOW. When one of the comparator outputs goes LOW,
logic in the EPLD stores the LOW condition until the microprocessor clears it.
2-44 Rev. C July, 2000

2.3.4.2.4 Parallel Interface. - The RMS communicates with the Local Control Unit (LCU) and the Cabinet
Interface Unit (CI) through an eight bit parallel interface. In order to keep the design of the peripheral (LCU
or CI) simple, the RMS controls all the communication on the interface. The RMS reads and writes to the
peripheral circuitry with no handshaking. The interface consists of eight bi-directional address/data lines, an
address strobe, a write strobe, and a read enable. In order to achieve sufficient noise immunity, the logic
levels of the interface are 5V CMOS. The address strobe and the data write strobe are differential (RS422).
The parallel interface uses the following signals:
Address/Data I/O (8) -The eight bit bi-directional data lines with multiplexed address.
Address Strobe (differential) - A pulse from the RMS to latch address information into the peripheral.
Data Write Strobe (differential) - A pulse from the RMS to write data to the peripheral.
Data Read Enable - A pulse from the RMS to enable data from the peripheral to be placed on the data
lines.
The data output and control signals are sent through the data bus from the microprocessor to latches U39
and U40. These latches are edge triggered to avoid any time period in which indeterminate data is present
on their outputs. Their outputs will not change until after the data being sent to them is valid. In contrast, the
latches used to latch the address bus, U10 and U11, are “transparent”. When they are enabled, their outputs
will follow their inputs for a short time before the address becomes valid on the AD bus. The received data
is sent to the microprocessor by a tri-state gate U41. The address decoding for the latch strobes and the tri-
state enable is performed by the EPLD U14.
The microprocessor (U5) writes to the control latch (U39) at peripheral address PCS2+0. The
microprocessor writes to the data latch (U40) at address PCS2+2. The received data from the parallel
interface (U41) is read by the microprocessor at address PCS2.
2.3.4.2.5 Station Configuration Inputs - In order to reduce the amount of effort required to program various
modules within the ILS station for the proper configuration, there are logic signals that are sent from the
backplane to each module to specify the station configuration. The logic signals are produced by switches
on the backplane. The signals are read by the RMS CCA via tri-state gates U43 and U44 which places them
on the data bus when enabled by address decoding logic in the EPLD U14. This is the same manner in which
the data is read by the parallel interface discussed above. The microprocessor reads the configuration bits at
peripheral addresses PSC2+2 and PSC2+3. Isolation is provided in the event power is lost to the RMS CCA.
Diodes CR9 through CR22 and resistor networks RP6 and RP7 provide this isolation. The resistors in RP6
and RP7 pull the inputs to the U43 and U44 HIGH if the configuration inputs are HIGH. If a configuration
input is LOW, the diode is forward biased and input to U43 and U44 is pulled LOW.
Rev. C July, 2000 2-45

2.3.4.2.6 Serial Interface - The serial interface provides the communications interface for the microprocessor
to communicate with other devices. Primarily, it consists of five dual channel enhanced serial
communications controllers (ESCCs) which accomplish two-way communications with a PMDT, a remote
maintenance terminal (RMT) or modem, DME transponders 1 and/or 2 (if installed), and the four ILS
monitors.
Table 2-2 RMS CCA Serial Communication Channels

IC Select I/O Address Interrupt Baud Rate Communicates
Line with
U22A SCC0 PCS1+0 INT2 9600 PMDT
U22B SCC0 PCS1+04H INT2 N/A Spare
U23A SCC1 PCS1+10H INT2 19.2K Monitor #4
U23B SCC1 PCS1+14H INT2 19.2K Monitor #2
U26A SCC2 PCS1+20H INT1 19.2K Monitor #3
U26B SCC2 PCS1+24H INT1 19.2K Monitor #1
U27A SCC3 PCS1+30H INT1 1200 DME #1
U27B SCC3 PCS1+34H INT1 1200 DME #2
U31A SCC4 PCS1+40H INT1 9600 External Modem
U31B SCC4 PCS1+44H INT1 9600 SVD Modem
The circuits that handle communications between the microprocessor and the various devices within and
external to the ILS system are functionally the same. Five Zilog Z85230 enhanced serial communication
controller (ESCC) integrated circuits are used to provide the serial communication functionality. Each ESCC
is a dual communications device. Each half of the ESCC is capable of independent communications.
U20 is an octal bus transceiver to buffer the data bus going to and from the ESCCs. It is used to reduce the
amount of capacitance that must be driven by devices on the microprocessor’s bus. U20 is enabled by address
decoding circuitry within the EPLD. The direction of the data through U20 is determined by the logic level
of the direction signal (DT/R̄). When the direction signal is HIGH, data from the address/data bus is
transferred to the ESCC. When the direction signal is LOW, data from the ESCC is transferred to the
microprocessor’s address/data bus.
U21 is also an octal bus transceiver. It is permanently enabled in one direction in order to buffer various
control signals that are applied to the ESCC. These are addresses A1 and A2, R̄D̄, W̄R̄, and the 16 MHZ
clock signal from U5 (ECLK). The chip select signals for the ESCCs are decoded within the EPLD (U14).
2-46 Rev. C July, 2000

The decoding uses PCS1 and A4 through A6. PSC1 is also used to enable the bus transceiver U21. Because
the microprocessor has a 16 bit data bus and only the lower 8 bits are connected to the ESCCs, only even
addresses must be used to transfer data between the microprocessor and the ESCCs. A1 is used to select
between the data and control registers of the ESCC and A2 is used to select which of the two channels within
the device is addressed. This places the ESCC’s control registers at I/O addresses shown in Table 2-2. The
data registers addresses (A1=1) are the control register addresses +2. Because the ESCCs are extremely
versatile devices, they must be programmed by the microprocessor in order to perform their desired
functions. Programming entails setting baud rates, data encoding protocol and data modes This is
accomplished by writing to the 16 control registers within each channel of the ESCC. Because access to the
control registers is through a single address (A1=0), it must be accomplished by two write operations. The
first write accesses register WR0. The value sent to WR0 specifies which register is written to with the
second write operation. If the second operation is a read from the same location, one of the read registers
is accessed. The read registers return status information to the microprocessor. The actual data transferred
through the serial communication channel is written and read from the data register (A1=1). The parallel
information transferred through the data register is converted to and from serial information which is sent
and received from the remote device.
The serial input and output signals to and from the ESCCs are TTL levels. The logic levels of these signals
is converted to and from RS-232 levels by U24, U25, U28, U29, U30, and U32 in order to achieve higher
noise immunity and compliance with other RS-232 serial devices. Since the SVD modem circuit resides on
the RMS card, the serial interface signals for it are not converted to RS-232. All of the serial interface
channels communicate using RXD and TXD. The two modems each use two extra handshaking lines, DTR
and DCD.
When serial data is received, the ESCCs notify the microprocessor that data is ready to be read by sending
an interrupt signal, interrupt #1 (INT1) or interrupt #2 (INT2) depending on the channel the data was
received from, to the microprocessor. The microprocessor then checks the status registers of the ESCCs that
share the interrupt to see which one has the data. After the serial channel containing the data is determined,
it is read from the data register of the ESCC.
2.3.4.2.7 SVD Modem. - The RMS CCA communicates to the RSCU using a modem that has the ability
to transfer simultaneous voice and data information (SVD). The modem uses an integrated circuit U34, which
contains most of the functionality of the modem. The voice communication capability of the modem is
implemented as a speaker phone built in to the RMS CCA. A small microphone and speaker are mounted on
the front panel of the RMS CCA. The modem IC has various support circuitry in order to make it completely
functional. It contains a micro-controller which requires an external one-time-programmable PROM U35 to
contain its programming information. The programming information contained in the PROM is Rockwell
proprietary.
Rev. C July, 2000 2-47

A 52.416 MHZ crystal, Y4, is used by U34 to provide a clock for its internal functions. Because the crystal
is a third overtone type, a series resonant LC circuit consisting of L3 and C76 is used to dampen the
fundamental frequency of the crystal (17.47 MHZ) in order to prevent oscillation at this frequency. C78 and
C79 provide the proper loading for the crystal. The microphone input circuit consists of a dual operational
amplifier U33. U33A provides a bias voltage for the microphone. The +12V power supply is divided down
to approximately 5V by resistors R28 and R29. Capacitor C69 removes noise from the voltage. The
operational amplifier, U33A, serves as a unity gain buffer and presents the same voltage on its output at a
low impedance. U33:B serves as an amplifier for the microphone output. For the DC level at the microphone
output, U33B acts as a unity gain buffer. Capacitor C68 blocks DC current flow through R25, resulting in
no DC attenuation from the output of U33B to its negative input. The DC voltage at the microphone output
provides a good operating point for the amplifier. C68 provides a low impedance for speech signals. The
voltage divider consisting of R25 and R27 reduces the speech signal level from the output of U33B to its
negative input. This produces gain for the speech signal. The speech signal is then sent to U34 through DC
blocking capacitor C70. A portion of the ILS station’s ident signal is sent to U34 through R33 and C77 so
that the ident can be heard at the remote site. The level of the ident heard at the remote site is adjusted by
R33.
The modem circuit uses an LM4862 amplifier to amplify the speaker phone output of U34 to a level that will
drive the speaker. It is similar to an inverting operational amplifier. Its gain is determined by the ratio of R38
to R35+R36. It has two outputs driven to equal amplitude, but out of phase with each other. Each of the
outputs drives one side of the speaker. The resistors R41 and R42 limit the power to the speaker to keep
from damaging it. A portion of the ident signal also is mixed into the amplifier’s input through R43, C82, and
R36. The level of the ident heard through the local speaker is adjusted by R43. The voice level to the speaker
is adjusted by R34.
The circuitry to interface the modem U34 to the phone line consists of U37, FL1, FL2, CR8, C84, and C85.
Audio that is received through the phone line is received on the tip and ring of U37. The transmit audio
comes from U34 TXA2 to XMIT of U37. Separate outputs for the transmit and receive of the modem U34
are also provided so that a full duplex radio link can be used if a phone line is not available. The transmit
comes from U34 TXA2 through R39 to P2-A23. The receive comes from P2-A21 through R40 and C80 to
U34 RIN.
2-48 Rev. C July, 2000

2.3.4.2.8 BCPS Control and Monitoring. - The RMS is responsible for monitoring up to two Battery Charge
Power Supply (BCPS) cards. A BCPS has seven status lines that reflect the state of system power, battery
back-up, etc. The status lines are CNVRTRS_OK, FAIL_+5V, FAIL_+12V, FAIL_-12V, FAIL_+24V,
BAT_OK and FAIL_+12VM.
FAIL_+5V, FAIL_+12V, FAIL_-12V and FAIL_+12VM are active HIGH indicating a failure of the
individual supply. CNVRTRS_OK is a logical NOR of the individual supplies. If FAIL_+5V, FAIL_+12V,
FAIL_-12V and FAIL_+12VM are all low, CNVRTRS_OK will be HIGH. If any are high, CNVRTRS_OK
will be LOW.
The FAIL_+24V indicates when the 24 Vdc input supply has dropped below 23.5 Vdc. The BAT_OK line
is HIGH when a battery is connected and charged above 21 Vdc. The status lines are all open drain (similar
to open collector), pulled up with RP8 and RP9 and read via U45 and U46.
The RMS also has the ability to enable /disable charging of the battery by the BCPS. CHGINH1 and
CHGINH2 from U14 are translated by R44-R47, Q1, and Q2 to 1_CHG_ENABLE and 2_CHG_ENABLE
at P1-C3 and P1-C4. When CHG_ENABLE is LOW the BCPS is prevented from charging the battery.
2.3.5 AC Power Monitor CCA (012017) (1A17) Theory of Operation. - Refer to Figure 2-15 and Figure
11-7. The AC Power Monitor CCA provides a means for the ILS system to measure the AC current and
voltage levels of the obstruction lights and of the ILS system itself. A photo switch bypass is also
incorporated for the obstruction lights in the event manual operation is desired.
T1 is a current-sense transformer in series with the obstruction lights line supply from TB1-4 and TB1-5. AC
current through the primary of T1 induces a current in the secondary. The secondary is connected to J1-3
and J1-4. A resistor on the Cabinet Interface CCA converts this current to voltage for measurement.
T3 is a voltage step-down transformer connected in parallel to the obstruction lights supply at TB1-4 and
TB1-6. The transformer primary is strapped to accept a nominal 220 Vac. AC voltage on the primary is
stepped-down on the secondary, and current-limited by R1 and R2 in the unlikely event of an accidental
short-circuit. The secondary is center-tapped and is routed to J1-1, J1-2, and J1-13
Rev. C July, 2000 2-49

Figure 2-15. AC Power Monitor Block Diagram.
2-50 Rev. C July, 2000
T2 is a current-sense transformer in series with the ILS Transmitter’s line supply from TB1-10 and TB1-11.
AC current through the primary of T2 induces a current in the secondary. The secondary is connected to J1-7
and J1-8. A resistor on the Cabinet Interface CCA converts this current to voltage for measurement.
T4 is a voltage step-down transformer connected in parallel to the ILS Transmitter’s supply at TB1-9 and
TB1-10. The transformer primary is strapped to accept up to 220 Vac. AC voltage on the primary is stepped-
down on the secondary, and current-limited by R3 and R4 in the unlikely event of an accidental short-circuit.
The secondary is center-tapped and routed to J1-5, J1-6, and J1-14.
An external SPDT switch is connected at TB1-1, TB1-2, and TB1-3. This switch in the OFF position allows
an external photo switch to control the application of power to the obstruction lights. When in the ON
position the obstruction lights are turned ON continuously.
Earth ground is also connected to the AC Monitor CCA via the board’s mechanical mounting holes and TB1-
12.
2.3.6 Cabinet Interface CCA (012013) (1A18) Theory of Operation. - Refer to Figure 2-16, Figure 2-17,
Figure 2-18, Figure 2-19, and Figure 11-8. The Cabinet Interface CCA (CI) provides interconnection
between the RMS processor and the PMDT, RCSU, antenna distribution unit, and the environmental
sensors. The CI CCA provides signal processing (amplification, multiplexing, filtering, a-d conversion), data
communication, level translation, and transient voltage suppression for signals to the RMS processor.
Power supplies enter the CCA via connector J1. Transmitter 1 +24Vdc and Transmitter 2 +24Vdc are diode
ORed by CR2 and CR3 to create +24V. The CI CCA will operate when either of the two transmitters are
powered. Fuse F1 provides over-current protection while CR6 guards against over-voltage. C6, C7, C10,
and C13 filter noise and high-frequency bypass +24Vdc.
CR1 protects the +5V from transients. C1-C3 filter and high-frequency bypass the power supply.
CR4 protects the +12VI (voltage in) from transients. C5, L3, C9, and C12 form a pi-filter to reject high
frequency noise to power supply +12V.
CR5 protects the -12VI from transients. C4, L2, C8, and C11 form a pi-filter to reject high frequency noise
to power supply -12V.
Power to switching loads, U1 and U2 transceivers, is provided from +12VI and -12VI while +12V and -12V
supply the remaining sensitive analog components.
Inductor L1 provides a DC “short” and an AC “open” path between digital ground and chassis ground. All
transient voltage suppressors are connected to chassis ground. Chassis ground connects to the CCA via screw
lug E1. Digital and analog ground are connected directly together near connector J1 by R83.
Rev. C July, 2000 2-51

Figure 2-16. Cabinet Interface Associative Diagram
2-52 Rev. C July, 2000
NOTE
The character “*” is used to indicate an active low signal level.
The RMS CCA provides control signals via J1. PDATA0 to PDATA7 are a parallel bidirectional address/data
bus whose direction and function are controlled by PADDR_ST, PADDR_ST*, PWRITE_ST,
PWRITE_ST*, and PREAD_EN*. U4B and U5B convert the differential RS-485 levels of PADDR_ST/*
and PWRITE_ST/* to the HCMOS levels of ADD_STROBE and WRITE_STROBE.
The rising edge of ADD_STROBE latches address information through U7. U9C, U11B, and U14
completely decode eight chip selects of which six are utilized. Output latches U16, U17, and U18 as well as
U7 are guaranteed to be cleared upon power-up by voltage monitor U10. U10 and R12 will reset the latches
any time system power drops below 4.65 volts. A master reset, MRESET*, from J1-9 may also reset U10
and the latches through CR100 and R84.
Data is clocked through U16, U17, and U18 when the appropriate chip select line is low and
WRITE_STROBE transitions high. U9A, U15C, and U15D are logic gates that insure these conditions are
met before data appears at the outputs of the latches.
PREAD_EN* is an active low signal which enables data transfer through input buffers U8, U12, and U13
when the appropriate chip select line is also low. U9B, U9D, and U15B are logic gates that insure these
conditions are met before data appears at the outputs of the buffers.
U19A-D, U3E, and U11C form two programmable digital I/O ports whose inputs/outputs are routed to
terminal block TB5 (SPARE_DIGITAL_I/O_1 and SPARE_DIGITAL_I/O_2). The ports are programmed
as inputs upon power-up. R15 and R17 pull-up resistors ensure logic high levels at U12A (SPARE_I_1 and
SPARE_I_2) assuming there is no external pull-down at TB5. The ports may be programmed as outputs
using DIR_I*/O_1, DIR_I*/O_2, SPARE_O_1, and SPARE_O_2 from U16.
U20 and U21 are analog multiplexors controlled by U16 (IDENT_SEL and IDENT_EN). IDENT_SEL
routes either DET_ID_1 or DET_ID_2 through U20. DET_ID_1 and DET_ID_2 are both from TB4 and
transient protected by CR14 and CR15. IDENT_EN routes either the U20 output or an open line (NC) to
the U21 output called IDENT. IDENT connects to the backplane header J1-B.
U4A and U5A convert TTL level signals ANT_CLOCK and ANT_RESET from U16 to RS-485 level signals
ANT_CLOCK_POS, ANT_CLOCK_NEG, ANT_RESET_POS, and ANT_RESET_NEG. The RS-485
signals are transient voltage protected by CR21-CR24 and are available externally at TB2.
REM_ON_1, REM_ON_2, and REMOTE_OFF from U17 control power cycling to remote DME
equipment. U3D, U3F, U11A, and U11:D logic gates guarantee ON and OFF never occur at the same time.
Q1-Q3 provide open drain outputs REMOTE_ON_1*, REMOTE_ON_2*, and REMOTE_OFF* which are
transient protected by CR33-CR35 and route to TB4.
Rev. C July, 2000 2-53

Figure 2-17. Cabinet Interface Block Diagram (1 of 3).
2-54 Rev. C July, 2000
MODEM_RESET from U18 connects to the 9600 bps modem IC, U6. U6 supplies phone-line compatible
signals DIAL-UP_MODEM_TIP and DIAL-UP_MODEM_RING to TB2 after being transient protected by
CR11, CR12, R7, and R8. The RMM (RMS) may be sourced by either an optional external modem or the
dial-up modem. RMM/EXT* from J1A (conditioned by R9, U3A, and U3B) determines the source by
enabling either U1 or U2. U1 is a quad analog switch and U2 is an RS-232 to TTL transceiver. EXT_DTR,
EXT_RX, EXT_TX, and EXT_DCD connect to U1 and are available at J6. RMM_DTR, RMM_RX,
RMM_TX, and RMM_DCD join U1, U2 and J1.
FIRE_SENSOR_POS and INTRUSION_SENSOR_POS inputs (TB1) are from normally closed switch
contacts. The signals are pulled-up with resistors R18 and R19, transient protected by CR30 and CR31, and
connected to input buffer U12A. INTRUSION_SENSOR_BYPASS* from TB3-6 is a input to U13A that
may be used to bypass the intrusion sensor.
SW_POS*, DME1_BYPASS_LOGIC, and DME2_BYPASS_LOGIC inputs (TB4) are remote status lines
which are transient protected by CR28-CR30, diode isolated by CR25-CR27 and pulled-up by R13, R14, and
R16. The signal names are changed to ANT1/ANT2*, DME1_BYPASS, and DME2_BYPASS and are
connected to input buffer U12B. The name change is merely an attempt to more accurately express function.
The diode isolation prevents accidental power drain from the remote should the Cabinet Interface CCA be
powered down.
MUX_A0 through MUX_A3 from the Local Control Unit (via J1) select 1 of 12 signals from BNC
connectors J7, J8, J10-J16, and J18-J20 through analog multiplexor U23. The BNC connector signals are
terminated by RN1 and RN2 and transient protected by CR36-CR47. The selected BNC channel from analog
mux U23 is amplified by U24B after filtering by R57 and C77. The gain of U24B is set by R21, R22, and
R23. R20 acts as an impedance match between U24B and WATTMETER_OUT at the J17 BNC connector.
The BNC connectors are labeled as follows:
J7 - CRS_SBO_RFL J8 - CRS_CSB_RFL
J9 - IN-LINE_PHASING_TP J10 - CLR_CSB_FWD
J11 - CLR_SBO_FWD J12 - STDBY_TX_CRS_CSB
J13 - CLR_CSB_RFL J14 - CLR_SBO_RFL
J15 - STDBY_TX_CRS_SBO J16 - CRS_CSB_FWD
J17 - WATTMETER_OUT J18 - STDBY_TX_CLR_SBO
J19 - STDBY_TX_CLR_CSB J20- CRS_SBO_FWD
The IN-LINE_PHASING_TP connector, J9, is discussed elsewhere.
BNC connectors J7, J8, J10-J16, J18-J20 are also connected to analog mux U22. U22 channel selection is
performed by BNC_SEL_0 through BNC_SEL_3 from U18. The output of analog mux U22 is filtered by
R58 and C79, then amplified by U24C (whose gain is set by R25, R26, and R27).
Rev. C July, 2000 2-55

2-56 Rev. C July, 2000
The output of U24C is low pass filtered by R24 and C26 and passed on to an input of analog mux U27 as
BNC_TO_A-D.
U26 and U27 comprise a 14 channel differential analog multiplexor controlled by MMUX_SEL_0 through
MMUX_SEL_3 from U17. The 14 channels [SPARE_ANALOG_1 through SPARE_ANALOG_10 (all from
TB5), ANT_FAULT (from TB2), BNC_TO_A-D (mentioned previously), DME1_NORM/FAULT*, and
DME2_NORM/FAULT*. DME1_NORM/FAULT* and DME2_NORM/FAULT*] are buffered by U25B
and U25A to prevent accidental power drain in the event the Cabinet Interface CCA is powered down. R28-
R31 provide pull-downs and buffering in the event the DME1_MONITOR_LED and
DME2_MONITOR_LED signals from TB4 become disconnected. CR48 and CR49 provide transient
protection for these lines. ANT_FAULT is further surge protected by R5 and R6. CR50 through CR71
provide transient protection for the analog channels not protected elsewhere.
The outputs of analog multiplexors U26 and U27 connect to differential amplifier U24A. The gain of U24A
is set by R32-R35 while C27 filters noise. The output of diff amp U24A connects to a side of two channel
analog switch U29. MMUX_SEL_4 from U17 controls which of the channels is selected. The other channel
of U29 connects to the output of sixteen channel analog mux U28 (discussed elsewhere).
The output of mux U29 routes to input buffer U30. C28 and R36 provide filtering for U30 to allow “smooth”
voltage level transitioning when switching analog channels. The output of buffer U30 feeds the analog input
of A-D converter U31.
R37, R38, C29, and C30 program U31 to accept a bipolar analog input in the range of -10 volts to +10 volts.
A-D_CE from U3C and U14 enables the A-D. A-D_R/C* from U18 dictates either a read or a convert
action. A-D_A0 from U18 selects either the eight most significant or four least significant bits of the
conversion result (12 bits total) during a read. The 12-bit result is placed on the 8-bit bus (A-D_D0 through
A-D_D7) with two separate reads and routed to input buffer U8. A-D_STS connects to input buffer U12B
and indicates when a conversion is complete.
Analog multiplexor U28 is a sixteen channel mux controlled by MMUX_SEL_0 through MMUX_SEL_3
(from U17). Each of the sixteen input channels is discussed.
SYS_VAC_POS and SYS_VAC_NEG from J3 constitute an AC voltage full-wave rectified by CR86 and
CR87. The rectified signal is filtered and stored by bulk capacitor C48. C46 acts as a high frequency bypass.
CR90 is a transient voltage suppressor and R69 provides a level adjust. U33B buffers the final DC signal
SYS_VAC and connects to analog mux U28.
SYS_IAC_POS from J3 is converted from an AC current to an AC voltage by burden resistor R39 and
transient protected by CR72. The low level AC voltage is amplified by U24D and U32C (whose gains are
set by R41, R45, R46, R49, R51, and R55). CR74 and CR76 perform full-wave rectification of the signal.
R43 and R52 act to reduce the effects of input offset currents. C34 averages the rectified signal.
Rev. C July, 2000 2-57

2-58 Rev. C July, 2000
OB_LITE_VAC_POS and OB_LITE_VAC_NEG from J3 constitute an AC voltage full-wave rectified by

CR88 and CR89. The rectified signal is filtered and stored by bulk capacitor C49. C47 acts as a high
frequency bypass. CR91 is a transient voltage suppressor and R70 provides a level adjust. U33C buffers the
final DC signal OB_LITE_VAC and connects to analog mux U28.
OB_LITE_IAC_POS from J3 is converted from an AC current to an AC voltage by burden resistor R40 and
transient protected by CR73. The low level AC voltage is amplified by U32B and U32D (whose gains are
set by R42, R47, R48, R50, R53, and R56). CR75 and CR77 perform full-wave rectification of the signal.
R44 and R54 act to reduce the effects of input offset currents. C35 averages the rectified signal.
The +24V1 power supply voltage from J1-A is scaled down by voltage divider R71 and R73. C50 filters and
CR94 transient protects the final 24VPS_1_VOLT signal that connects to analog mux U28.
24VPS_1_CURR_POS and 24VPS_1_CURR_NEG from TB6 create a voltage across sense resistor R61.
Instrumentation amplifier U36 amplifies the sense voltage by the amount set with gain resistor R63. The
inputs of U36 are transient protected by CR82 and CR83. The output of amp U36 connects to analog mux
U28.
The +24V2 power supply voltage from J1-A is scaled down by voltage divider R72 and R74. C51 filters and
CR95 transient protects the final 28VPS_2_VOLT signal that connects to analog mux U28.
24VPS_2_CURR_POS and 24VPS_2_CURR_NEG from TB6 create a voltage across sense resistor R62.
Instrumentation amplifier U37 amplifies the sense voltage by the amount set with gain resistor R64. The
inputs of U37 are transient protected by CR84 and CR85. The output of amp U37 connects to analog mux
U28.
The BATT_1_VOLTAGE battery voltage from TB6A is scaled down by voltage divider R65 and R67. C44
filters and CR92 transient protects the final BATT_1_VOLT signal that connects to analog mux U28.
1_BAT_ISENS+ and 1_BAT_ISENS- from TB6 are a differential analog voltage representing the current
measured by the BCPS CCA. Amplifier U34 buffers and converts the differential voltage to a single-ended
voltage referenced to the CI analog ground. The inputs of U34 are transient protected by CR78 and CR79.
The output of amp U34 connects to analog mux U28.
The BATT_2_VOLTAGE battery voltage from TB6 is scaled down by voltage divider R66 and R68. C45
filters and CR93 transient protects the final BATT_2_VOLT signal that connects to analog mux U28.
2_BAT_ISENS+ and 2_BAT_ISENS- from TB6 are a differential analog voltage representing the current
measured by the BCPS CCA. Amplifier U35 buffers and converts the differential voltage to a single-ended
voltage referenced to the CI analog ground. The inputs of U35 are transient protected by CR80 and CR81.
The output of amp U35 connects to analog mux U28.
Rev. C July, 2000 2-59

Temperature sensor INTERIOR_TEMP_NEG from J5 is converted from DC current to voltage by sense

resistors R81 and R82. C55 filters and CR99 transient protects while U33:D buffers the signal
INTERIOR_TEMP to analog mux U28.
Temperature sensor EXTERIOR_TEMP_NEG from J4 is converted from DC current to voltage by sense

resistors R75 and R76. C52 filters and CR96 transient protects while U33:A buffers the signal
EXTERIOR_TEMP to analog mux U28.
The DME1_28VPS_VOLTAG power supply voltage from TB4 is scaled down by voltage divider R77 and
R79. C53 filters and CR97 transient protects the final DME1_28VPS_VOLT signal connected to analog
mux U28.
The DME2_28VPS_VOLTAG power supply voltage from TB4 is scaled down by voltage divider R78 and
R80. C54 filters and CR98 transient protects the final DME2_28VPS_VOLT signal connected to analog
mux U28.
PMDT_TX and PMDT_RX from TB2 are surge and transient protected by R3, R4, CR8, and CR10 before
being routed to TB3 and J1.
RCSU_TIP and RCSU_RING from TB2 are surge and transient protected by R1 and R2 before being routed
to J1.
DME1_TX, DME2_TX, DME1_RX, and DME2_RX from TB4 are transient protected by CR16-CR19 and
connected to J1.
DME_KEY+ and DME_KEY- from TB4 are transient protected by CR13 and CR106 and connected to J1.
The IN-LINE_PHASING_TP signal from BNC connector J9 is transient protected by CR20 and connected
to TB2.
WATTMETER_NEXTN and WATTMETER_CRS/CLRN route directly from J1-B to TB3.
1_FFM_RX and 2_FFM_RX route directly from J1-B to TB4.
2-60 Rev. C July, 2000

2.3.7 Local Control Unit (1A1) Simplified Theory of Operation. - Refer to Figure 2-20. The Local Control
Unit (LCU) controls the normal operation of the ILS. All operational functions are performed by the LCU
and are controlled by either the front panel keyboard when in the local mode or by the Remote Maintenance
Subsystem (RMS) through the parallel interface. The LCU is controlled by the Portable Maintenance Data
Terminal (PMDT), Remote Control Status Unit (RCSU) or Remote Status Unit (RSU) through the RMS
for all remote operator intervention, or by the RMS for automatic restart. The LCU receives the alarm
outputs from the installed Monitor Circuit cards and depending on the configuration of the system, uses the
results of these signals to determine alarm status. If an alarm is detected, the LCU shuts down the system
currently radiating and transfers to the standby system in accordance with the system configuration. The
LCU also provides the ability to disable monitors and bypass alarms as required by the operator.
Figure 2-20 Simplified Block Diagram
The LCU provides +24V to the two possible synthesizer VCO circuits, the +24V to activate the transfer
switch, and the transmit enable clock to the installed monitors.
Status is reported by LED’s visible to an operator standing in front of the ILS, or through the RMS to the
PMDT/RCSU/RSU. An alarm shutdown is reported to the RMS as well as indicated by an audible alarm.
Rev. C July, 2000 2-61

The LCU also accepts operator input to control the selection of the power reading displayed by the Power
Meter on the right side of the LCU control panel. The power meter displays the RF power readings in Watts,
from Bird Wattmeter bodies located at various points in the system.
2.3.7.1 Local Control Unit (1A1) Block Diagram Theory. - Refer to Figure 2-21.
2.3.7.1.1 DC to DC Converter - The LCU receives +24V from the two independent system power supplies
and diode ‘OR’s the two sources to provide input power to a DC to DC converter which supplies all required
voltages for the LCU.
2.3.7.1.2 Power Fail Detectors - Each of the two independent +24V sources is monitored by a voltage
comparator to monitor the health and availability of power from each of the sources. These signals are used
to determine voting logic for the alarm registers and is reported back to the RMS via the parallel interface.
2.3.7.1.3 Key Switch Registers - Front panel switches are de-bounced and held in the Key Switch Registers
pending processing by the LCU Transfer State machines. Commands received from the RMS via the parallel
interface also control the contents of the Key Switch Registers. The Registers will hold the last command
received until the LCU Transfer State machine processes the command.
2.3.7.1.4 Parallel Interface - The interface to the RMS is via a parallel data bus consisting of eight (8) data
bits, an Address Command line, a Write Command line, and a Read Command line. The sequence to access
internal registers within the LCU consist of the address being placed on the data bus followed by the strobing
of the Address Command line to latch the address into the internal address register. This is followed by the
Read Command line driven true to facilitate a read from the latched address. For a write command, the
address is followed by the data to be written to the LCU followed by strobing the Write Command line.
Alarm Configuration, Bypass Commands, Key Commands, and basic LCU configuration are some of the bits
controlled by the RMS via the parallel interface. State machine Status, Power-fail Status, System
Configuration bits (SCON), and Local/Remote status are some of the status bits that are readable by the RMS
via the parallel interface.
2.3.7.1.5 1.8432MHz Oscillator/Divider Chains - The LCU employs a 1.8432MHz crystal oscillator to
produce all frequencies required by the design. The frequency is divided by 512 to produce 3600Hz used
to produce the audible alarm tone and the Transmit On clocks driven back to the Monitors. The signal is
further divided by 8 to produce 450Hz used as the system clock within the design. This signal is divided by
45 to produce 10Hz used in the 20 Second delay counter and the Key De-bounce circuits.
2-62 Rev. C July, 2000

2.3.7.1.6 Positive Alarm Register - This register receives the positive (high True) alarms from the four
potential monitors within a system. Depending on the configuration of the alarm voting and bypass logic,
the Alarm Register will report an alarm to the Transfer State machines if reported by the enabled monitors.
2.3.7.1.7 Negative Alarm Register - This register receives the negative (low True) alarms from the four
potential monitors within a system. Depending on the configuration of the alarm voting and bypass logic,
the Alarm Register will report an alarm to the Transfer State machines if reported by the enabled monitors.
2.3.7.1.8 20 Second Delay Counter - The 20 Second Delay counter is activated whenever the system initially
powers up or a transmitter has been shut down without transferring to a standby system, to ensure that the
system will not radiate any signal for a period of 20 seconds following the shutdown.
2.3.7.1.9 LCU Transfer Control State machine #1 & #2 & Discrete Controls - The heart of the LCU are the
two redundant Transfer Control State machines. These are configured by the RMS, receive key commands
from the front panel or from the RMS, and process alarms reported by the Monitors after being filtered by
the Positive and Negative Alarm Registers. Once configured for on air, the State machines will drive out the
required signals to enable the transmit on clocks (1_TX_ON_CLK, 2_TX_ON_CLK), enable the +24V
power to the Synthesizer VCO’s (1_24VCO, 2_24VCO), and select the required system to be placed on the
antenna (1_+24ANT_SW, 2_+24ANT_SW).
With the redundant State machines, detection of an error assures that the system generating the error will be
removed from the air. The LCU transfers to the standby system (if configured to do so) either immediately
for a Hot Standby system or after a 20 second delay for a Cold Standby system. If further alarms are
detected, the LCU Transfer State machines will shut the standby transmitter down and block any further
transmission for a minimum of 20 seconds. Restarts are under the control of the RMS.
The LCU Transfer Control State machines report status back to the RMS indicating the state of the State
machines, and any shutdowns that have occurred. The Front Panel LED’s reflect the current state of the
State machines.
Rev. C July, 2000 2-63

Figure 2-21 LCU Detailed Block Diagram
2-64 Rev. C July, 2000
2.3.7.1.10 LED Control - Status is fed back to a local operator via the LED’s on the front panel of the LCU.
These reflect the state of the transmitters and the various alarms as reported by the monitors.
2.3.7.1.11 Audible Alarm - If an alarm as reported by the monitors is detected that is not bypassed, the
audible alarm is generated. The audible alarm can be reset by pressing the Alarm Silence button on the front
panel. In local mode, the audible alarm is disabled.
2.3.7.1.12 Wattmeter State machine - A power meter is provided on the front panel for viewing
measurements made by Bird Wattmeters within the system. Available measurements are selected via the
pushbutton switches on the front panel which indicates via LED’s which measurement is currently displayed.
2.3.7.2 Local Control Unit CCA (1A1A1) Detailed Theory of Operation - Refer to schematic 012008-9001
(Figure 11-6). The LCU controls the sequencing of the main and standby ILS transmitters according to alarm
signals from the monitors. It displays the status of the station and accepts control input from a local operator.
The LCU also provides status to and accepts control information from the PMDT or RCSU through the
RMS parallel interface. The LCU circuit card consists primarily of two Field Programmable Gate Arrays
(FPGA’s), discrete control logic and digital interface circuitry. It also contains light emitting diodes (LEDs)
and supporting driver circuitry.
2.3.7.2.1 Power Supply - The power for the LCU CCA comes from two separate sources of +24 Vdc
through Schottky rectifiers CR32 and CR33. The rectifiers isolate the two +24Vdc sources from each other
and allow either to supply power to the board. The +24 Vdc is converted to +5 Vdc by a DC to DC
converter, U11. The +5Vdc supplies power for all the circuitry in the LCU.
Each of the two +24 Vdc sources used to power the board are monitored by comparator U12. The two
comparator circuits are identical, so the following discussion will explain the monitoring of the 1_+24V
supply. The +24V supply voltage is reduced to approximately +3V by a voltage divider network consisting
of R42 and R47. This voltage is connected to the positive input of comparator U12A. The +5V VCC supply
is reduced to 2.5V by another voltage divider network, R40 and R39. This voltage is connected to the
negative input of U12A. When the +24V supply is at a normal voltage, the positive input to U12A is higher
than the negative input so the output of the comparator will be at a high logic level. Since the output of the
comparator is an open collector, R41 is necessary to pull it high. When the voltage of the +24V supply falls
below approximately +19.5V, the voltage at the positive input of U12A will fall below +2.5V and cause the
output of U12A to go to a low logic level.
Rev. C July, 2000 2-65

2.3.7.2.2 Pushbutton Switches and LED Display - The LCU accepts control input from the operator
through momentary contact pushbutton switches and presents status information for the ILS station through
a series of light emitting diodes (LEDs). The pushbutton switch circuitry is implemented by using a pull up
resistor to +5V to produce a high logic level, and using a pushbutton switch to momentarily ground it to
produce a low logic level. Switches that provide a toggling or sequencing function (where a multiple push
would give a different result from a single push) are de-bounced by logic within the EPLDs (U3 and U22).
For other switches, a repetitive contact or bounce will not have a noticeable affect.
The LEDs are driven from the logic with the help of 75468 Darlington Driver IC’s. For the purpose of
illustration, the circuit driving CR1 will be discussed. The MAINSEL signal from U3 is high true driven to
pin 1 of U6. The 75468 then sinks current from CR1 through R3 causing the LED to illuminate.
The board uses three different colors of LEDs: red, yellow, and green. Each of the three colors has a slightly
different forward bias voltage and efficiency. Because of this, each color of LEDs uses a different value of
series resistor in order to create the same degree of perceived brightness. A lamp test pushbutton is
implemented in the LCU in order to turn on all the LEDs to confirm their functionality. When the lamp test
switch, S19, is pushed, Pin 9 of U6 is driven low, causing the output of U6-16 to go low sinking current
through CR1 and R3, causing the LED to illuminate. This circuit is identical for all LED’s on the circuit card
assembly.\
2.3.7.2.3 Parallel Interface - The RMS communicates with the LCU and the Cabinet Interface Unit (CI)
through an eight bit parallel bus interface. In order to keep the design of the peripheral (LCU or CI) simple,
the RMS controls all the communication on the interface. The RMS reads and writes to the peripheral
circuitry with no handshaking. The interface consists of an eight bit bi-directional address/data bus, an
address strobe, a write strobe, and a read enable. In order to achieve sufficient noise immunity, the address
strobe and the data write strobe are driven differentially through an RS-422 interface IC, U5. The remainder
of the interface is driven to 5V CMOS logic levels.
The parallel interface uses the following signals:
Address/Data Bus - The eight bit bi-directional address/data buss with multiplexed address.
Address Strobe A differentially driven pulse from the RMS to latch address information into
the peripheral.
Data Write Strobe A differentially driven pulse from the RMS to write data to the peripheral.
Data Read Enable A pulse from the RMS to enable data from the peripheral to be placed on the
data bus.
The RMS has the ability to read the status and control the operation of the ILS station through a parallel
interface. Data transfer is accomplished by first placing an address on the bus and cycling the address strobe
(asserting, then de-asserting the address strobe signal). The LCU latches and decodes the address within the
EPLD’s U3 & U22.
2-66 Rev. C July, 2000

For a read operation, the read enable is then asserted which tells the LCU circuitry to place the appropriate
data on the data bus. For a write operation, the RMS places data on the data bus, then cycles the Data Write
Strobe (asserting and de-asserting the write strobe signal.) The address decoding circuitry within the EPLD’s
decodes eight addresses, starting at (hexadecimal) 80.
The decodes for those addresses and the bits assigned to each register are shown in the table below. To buffer
the EPLD’s, a bus transceiver U2 is used on the data bus to provide CMOS logic thresholds to/from the
parallel interface.
Addr = 80 Write Read

Bit 0 Monitor Enable 1 Monitor Enable 1
Bit 4 Monitor Logic (And/Or) Combined Monitor Logic (And/Or)
Bit 5 Maintenance Alert Shutdown/Log Error
Bit 6 Remote Fault Transfer In Process
Bit 7 Hot Standby Standby Shutdown/Enable Restart

Bit 0 Internal Monitor Bypass Internal Monitor Bypass
Bit 1 Standby Monitor Bypass Standby Monitor Bypass
Bit 2 Near Field Monitor Bypass Near Field Monitor Bypass
Bit 3 Far Field Monitor Bypass Far Field Monitor Bypass
Bit 4 Near Field Monitor Available VCO #1 +24V Sense
Bit 5 Far Field Monitor Available VCO #2 +24V Sense
Bit 6 Main 1 Selected Main 1 Selected
Bit 7 Alarm Silence Alarm

B0 Reserved Integral Monitor Alarm
B1 Reserved Integral Monitor Alarm Mismatch
B2 Reserved Standby Monitor Alarm
B3 Reserved Standby Monitor Alarm Mismatch
B4 Reserved Near Field Monitor Alarm
B5 Reserved Near Field Monitor Alarm Mismatch
B6 Reserved Far Field Monitor Alarm
B7 Reserved Far Field Monitor Alarm Mismatch
Rev. C July, 2000 2-67


Bit 0 Reserved Antenna 1 +24V Switch Sense
Bit 1 Reserved Antenna 2 +24V Switch Sense
Bit 2 Antenna 1 ON 1
Bit 3 Antenna 2 ON 2
Bit 4 Load 1 Power Fail 1
Bit 5 Load 2 Power Fail 2
Bit 6 Off 1 Antenna #1 Selected
Bit 7 Off 2 Local/Remote*

Bit 0 FFM_RUNNING_1 FFM_RUNNING_1
Bit 4 Reserved Reserved

Bit 0 Reserved Key Bit
Bit 1 Reserved Blink Enable Bit
Bit 2 Reserved Transfer (Bird)
Bit 3 Reserved Standby Shutdown/Enable Restart
Bit 4 Reserved Shutdown(Bird)/Log Error
Bit 5 Reserved ON 2 (Bird)
Bit 6 Reserved ON 1 (Bird)
Bit 7 Reserved Antenna Select 1 (Bird)
2-68 Rev. C July, 2000


Bit 0 Reserved Combined Monitor Logic (And/Or)
Bit 1 Reserved Transmit Blanking
Bit 2 Reserved Hot Standby
Bit 3 Reserved SCON0

Bit 0 Reserved Combined Monitor Logic (And/Or)
Bit 1 Reserved 0
Bit 2 Reserved FFM_RUNNING_Mismatch
Bit 3 Reserved FFM_RUNNING_ALARM
Bit 4 Reserved 0
Bit 5 Reserved 0
Bit 6 Reserved 0
Bit 7 Reserved 0
2.3.7.2.4 Monitor Alarm Interface Circuitry - In order to insure that a monitor alarm signal is communicated
to the control logic, redundancy is incorporated into the monitor alarm signals. Each alarm signal is sent as
two signals, one active high and the other active low. In the LCU, resistors are used to pull each of their
signals to their active (alarm) state. This insures that an alarm condition will be sensed if there is an open in
either alarm line. If an alarm line is shorted to its inactive (non-alarm) state, the other line will communicate
an alarm condition. If the 1_INT_ALARM+ signal is disconnected, a resistor in RN3 will pull the input high
resulting in an alarm condition being sent to the control logic in the EPLD U3. If the 1_INT_ALARM- signal
is disconnected, a resistor in RN15 will pull the input to a low logic level. The output of buffer U17 will send
a low level which will result in an alarm condition being sent to U22. HC logic devices are used to provide
CMOS (mid rail) thresholds for the alarm inputs.
Rev. C July, 2000 2-69

2.3.7.2.5 Station Control Logic - The station control logic is duplicated in both U3 and U22. The logic
responds to local operator control through the pushbutton switch inputs as well as remote control through
the parallel interface. The local operator can perform the following functions:
1.) Specify which ILS transmitter is to be designated as main.
2.) Turn either transmitter ON and connect it to the antenna.
3.) Turn either transmitter ON and connect it to the load.
4.) Turn either transmitter OFF.
5.) Toggle the bypass state of any of the four monitored signal sources (Integral, Standby, Near
Field, and Far Field).
6.) Silence the aural alarm (until the next event causes it to sound).
7.) Toggle the state of local control. When local control is set, input from the keypad is enabled.
The following functions can be performed by the RMS through the parallel interface:
1.) Functions 1-6 listed above.
2.) Enable or disable the alarm signals from any one of the four monitors. When a monitor’s
alarm signals are disabled, it is functionally equivalent to the monitor producing constant
alarms.
3.) Set the “AND/OR” state of the alarm logic when it combines the alarm signals from monitors
1 and 3 with the alarm signals from Monitors 2 and 4. When set to “AND”, all four monitors
must provide an alarm from the same source to cause the station to transfer. When set to
“OR”, Monitors 1 and 3 signaling an alarm or Monitors 2 and 4 signaling an alarm will cause
the station to transfer.
4.) Set the “Maintenance Alert” state. This lights the corresponding LED on the panel and
sounds the aural alarm.
5.) Set the “Remote Control Fault” state. This lights the corresponding LED on the panel and
sounds the aural alarm.
In the alarm logic circuitry, the alarms from monitors 1 and 3 are combined (AND’ed) to produce the
Monitor 1 alarm status that is displayed on the panel. Similarly, the alarms from monitors 2 and 4 are
combined to produce the Monitor 2 alarm status that is displayed on the panel. If a given monitors alarm
signals are disabled by the RMS, it is equivalent to all of that monitor’s alarm signals being asserted. This
allows the alarm signals from the other monitor in the pair (1 and 3 or 2 and 4) to control the Monitor 1 or
Monitor 2 alarm state. The state of the AND/OR setting determines whether both or either of the Monitor
1 or Monitor 2 signals are required to produce a transfer condition. If one of the two +24V power fail logic
2-70 Rev. C July, 2000

signals from U12 goes active, the alarm logic will force an alarm condition for the monitor pair that is
powered from the corresponding +24V supply. In order to avoid shutting the ILS station down, the alarm
logic is forced to the AND state. This allows the other monitor pair to monitor the system.
The alarm signals from the monitors have already been given the appropriate transfer delay times within the
monitors. This results in an immediate transfer when the combinatorial requirements of the alarm signals are
met. When a transfer condition occurs, the present transmitter that is connected to the antenna system is
taken off the air. The other transmitter is connected to the antenna, and turned on (if it is not already on).
If the transmitter, not designated as main is connected to the antenna when the transfer condition occurs, the
control logic will enter the shutdown state and both transmitters are turned off. Once the control logic enters
the shutdown state, no further transfer operations will take place until a local operator or the RMS turns one
of the transmitters on and specifies that it is connected to the antenna system. The Station Control Logic
controls which transmitter is connected to the antenna system by the status of the +24V ANT outputs. In
order to insure the state of the antenna transfer relay, a status signal is returned from it. This signal is
monitored by the RMS through the parallel interface at Bits 0 and 1 of address 83 (hex).
2.3.7.2.6 Aural Alarm - An aural alarm is turned on when the system control logic senses an alarm
condition as reported by the Monitors. The frequency for the alarm is obtained from Q9 output of U21. It
is the 1.832 MHZ divided by 512 which is 3600 Hz. The signal is inverted by U25B. The inverted and non-
inverted 3600 Hz signal are both gated by U20A and U20C. The two outputs of the or gates provide a
differential signal to drive piezoelectric alarm element LS1. The system control logic turns the alarm on by
asserting the active low ~ALARM signal. When the ~ALARM signal is at an inactive or high logic level, the
outputs of both U20A and U20C will be high which will result in no differential signal to drive the alarm.
When the ~ALARM signal is asserted to a logic low, the 3600 Hz will pass through U20A and U20C. The
level of the signal is adjusted by R68. R69 prevents the adjustment of R63 to result in a level which is too
low.
2.3.7.2.7 RF Wattmeter Selection Logic - The Wattmeter selection logic on the LCU CCA accepts operator
input, to control the selection of the Wattmeter reading, that is displayed by the meter movement and sent
to a BNC jack on the panel. The Wattmeter displays the RF power readings from Wattmeter bodies located
at various points in the system. The logic is controlled by the up, down, and Course/Clearance toggle buttons
on the panel. LEDs on the panel illuminate to show which RF power reading is being sent to the meter. The
logic sends a four bit address to the cabinet interface (CI) CCA to specify which Wattmeter reading to send.
An analog multiplexer in the CI selects the input from the appropriate Wattmeter body and sends the signal
to the meter movement and the BNC jack.
When an up or down button is pushed, the readings will sequence through all of the Course or Clearance
power measurements that are appropriate for the configuration of the ILS station. If the station is a dual
frequency station, the Course/Clearance toggle button will select between readings for the Course or
Clearance equipment. For a Glideslope station, the upper, middle, and lower antenna power readings will
Rev. C July, 2000 2-71

be included in the sequence regardless of whether the Course or Clearance is selected. If the station is a
single frequency station, the Course/Clearance toggle button will not be available. The Wattmeter selection
logic has no effect on the operation of the ILS station and is not controlled by anything else within the
system. External pushbutton inputs are provided for the UP and Course/Clearance toggle buttons. The two
inputs are pulled up by resistors R45 and R46 and inverted by U14A and U14B. The external button will
ground the input which will provide a logic low to the inverter. The outputs of the inverters are combined
with the local push button signals within U22.
2.3.7.2.8 System Configuration Inputs - In order to reduce the amount of effort required to program various
modules within the ILS station for the proper configuration, there are five logic signals that are sent from the
backplane to each module to specify the system configuration. The configuration signals are used by the
Wattmeter selection logic U22 in order to provide the proper sequence of measurement functions for a each
type of ILS station, and are readable by the RMS via hex address 86.
The logic signals are produced by switches on the backplane. Isolation is provided in the event power is lost
to the LCU. Diodes CR39 through CR43 and resistor network RN11 provide this isolation.
The resistors in RN11 pull the inputs to U22 to a high logic level if the configuration inputs are high. If a
configuration input is at a low logic level, the diode is forward biased and the input to U22 is pulled low.
If there is a power loss and the cathodes of the diodes are at a low voltage, the diodes will all be turned off
so the configuration inputs will not be affected.
2.3.7.2.9 Clock Oscillator and Divider - Clock signals are necessary for the operation of the sequential
circuitry within the two EPLDs U3 and U22. The output of a 1.8432 MHZ oscillator Y1, is sent to a
74HC4020 CMOS integrated circuit U21. U21 divides the oscillator frequency by 16384 to produce a 450
Hz clock signal. Within U22, the 450 Hz clock is divided by 45 to produce another 10 Hz clock. The 450
Hz clock and the 10 Hz clock are both used by U3 and U22. The divide by 512 (Q9) output of U29 is used
to provide 3600 Hz for the aural alarm for the LCU.
2.3.7.2.10 Reset and Watchdog Circuitry- -A reset circuit U13 is used to provide a reset signal to the LCU
logic circuitry when it is powered up, or in the event that the 5V power supply voltage falls below a
threshold. The LCU control logic uses the reset to set the system control logic to a safe operational state.
The alarm bypasses are turned off, the main transmitter is set to #1, and other settings within the logic are
set to a default state. As long as the reset is asserted, the transmitter off signals are asserted. When the reset
returns to its non-asserted state, the LCU waits to be configured before any transmitter is turned on and is
connected to the antenna. Immediately after reset, the RMS must update the control settings within the LCU
since the default settings such as monitor enables, Hot_Standby and the And/Or selection may not be desired.
A pushbutton switch S15 allows the operator to manually reset the system through the LCU. R51 pulls the
MR (pin 1) input to its inactive high state. When S15 is pushed, the Master Reset signal is asserted low
2-72 Rev. C July, 2000

causing U13 to generate a reset within the LCU at the same time the rest of the system is driven into a reset
condition.
A watchdog circuit within U13 monitors the internal 10Hz clock and de-asserts the transmitter enable signals
in the event that the clock oscillator or the clock dividing circuitry fails. The 10 Hz clock signal is connected
to the WDI input of U13. If the clock fails to toggle for 1.6 seconds, the ~WDO output will go active.
Logic within EPLD’s U3 and U22 will then assert the ~OFF1 and ~OFF2 signals to the monitor which will
then turn off both ILS transmitters.
2.3.8 Battery Charging Power Supply CCA (012014) (1A6/1A10) Theory of Operation. - Refer to Figure
2-22, Figure 2-23, Figure 2-24, and Figure 11-4. The Battery Charging Power Supply (BCPS) receives 24.5
Vdc from an external power converter and outputs +24 Vdc at 12 Amps., +5 Vdc at 3 Amps., +12 Vdc at
3 Amps. and -12 Vdc at 500 milliamps. In addition a battery charging output will charge an external lead
acid battery at up to 4.5 Amps.
Rev. C July, 2000 2-73

2.3.8.1 Battery Charging Power Supply CCA (012014) (1A6/1A10) Block Diagram Theory.-
The battery charging profile starts with a constant current fast charge which transitions to constant voltage,
and when the current decreases to 10% of the initial fast charge current, to a lower maintenance float voltage.
The battery charger also senses open and shorted battery conditions which causes a “Battery Fault” condition
to be output as well as illuminating a red BAT_FAULT indicator.
Figure 2-22. BCPS Block Diagram
Other indicators are illuminated by the absence of +24.5V Power Input (Red), On Batteries (Amber), Fast
Charging (Amber), Maintenance Charging (Green), and Converters OK (Green). The Fast Charging indicator
flashes during the pre-charge qualification period during which time the presence of a battery is sensed.
An adjustable threshold circuit senses loss of +24.5V Input Power and transfers to battery power before the
system performance is affected. A second adjustable low battery voltage sensor circuit disables the battery
input when the voltage falls below its threshold.
The low battery voltage sensor latches OFF until AC power is returned. This prevents the system from
cycling between OFF and ON as the batteries’ voltage recovers after being disconnected, and falls upon
reconnection. A Charger Reset push button switch is provided to reconnect the battery power should a
charged replacement battery be installed.
2-74 Rev. C July, 2000

Figure 2-23. BCPS Voltage Converter.
Rev. C July, 2000 2-75
Battery charging can be inhibited for test purposes by grounding the “Charge Inhibit” input available on the
module connector.
Battery charging is controlled by an internal current sensor and a remote battery voltage sensor. The remote
battery voltage sensor improves battery life by yielding more accurate float (maintenance) and fast charge
voltage control, while relaxing the battery cable size and length requirements.
The module current sensor is also used to output an accurate 4 Amp/Volt current analog for monitoring the
battery charge and discharge current. Positive voltage is indicative of a charging battery.
The battery charging voltage is temperature compensated within the module. External module strapping
provides for compensation between the higher module temperature and lower battery temperature in 5EC
steps from 0EC to 15EC.
Battery charging is inhibited above 45EC module temperature to shed load from the +24.5 Vdc Input Power
module. During this time the Maintenance, Fast Charge, and Battery Fault indicators will all be dark.
The unit has battery reversal protection. Diode CR32 protects the BCPS in the event the batteries are
connected improperly.
The +5V, +12V, +12VM, and -12V converter status are individually sensed and ORed together to illuminate
the CONVERTERS OK indicator. Each of these individual and combined status signals, in addition to a
+24.5V status signal, are output from open MOSFET drains with ON indicating the normal condition.
Remote indicators and/or monitoring are possible.
2.3.8.2 Battery Charging Power Supply CCA ( 012014) (1A6/1A10) Detailed Circuit Theory - Under
normal AC powered conditions power for the +5V, +12V and -12V converters as well as the +24V output
passes thru steering diode CR9.
+24.5V Input Power for charging the battery passes thru an EMI filter, C24, L1, and C27, to a 1.625:1
voltage step up converter, U10, Q1, Q2, T1, CR1, CR2, C38 & C39. This step up converter provides enough
voltage to the following buck down converter to charge the battery at up to 31 Vdc. The up converter
operates at a fixed virtually 100% duty cycle and is synchronized to half the 90 KHz buck down converter
frequency.
The buck down converter control is resident in the battery charger integrated circuit U2. Its pulse width
modulator (PWM) output is high-side coupled thru opto-coupler U1 to the series switching MOSFET
transistor Q3. Buck diode CR3, and output filter L2 & C12, complete the buck down converter. C10 and
C11 improve stability of the battery charging control loop. CR32 protects against battery reversal.
2-76 Rev. C July, 2000

Figure 2-24. BCPS Battery Charger Control Circuits.
Rev. C July, 2000 2-77
Voltage to power the buck converter opto-coupler U1 output is developed from a secondary winding on up
converter transformer T1 and rectifier-filter C14, CR8, CR7 & C13.
Jumpers J2-1 & J2-2 are used to adjust the battery charger integrated circuit U2 PWM operating frequency
to near 90 KHz.
Battery current is sensed in a 0.01 Ohm Kelvin connected sense resistor R75 and amplified to 4.00
Amps/Volt by instrument amplifier U7. Potentiometer R25 adjusts the amplifier gain to calibrate the 0.25
Volt/Amp module output.
Battery current feedback to the battery charger IC U2 is obtained by re-scaling the 0.25 Volt/Amp battery
current analog in resistor divider R27 & R28 to provide a 4.50 Amp fast charge current limit. The re-scaled
current analog is buffered in operational amplifier U8A before driving the SNS input to the battery charger
IC U2.
Battery charging voltage feedback to U2 is remotely sensed by two wires connected to the battery positive
and negative terminals. These are input as REM_VBAT+ and REM_VBAT-. Differential amplifier U8C
scales the battery voltage and references it to the SNS current input pin of battery charger IC U2.
Potentiometer R42 provides for calibration of the voltage feedback. R42 is adjusted for 27.5 Vdc
maintenance float charging voltage at 25EC module ambient temperature.
Buffer amplifier U8D applies the scaled battery voltage to voltage dividers that compensate for module-to-
battery temperature differential, and the difference between fast and maintenance charge voltage limits. These
voltage feedback dividers are controlled by an analog multiplexer IC U16. The inputs are the +5_DEG,
+10_DEG temperature differential module inputs and the “FLOAT” output from the battery charger IC U2.
Resistors R43 and R47 form the basic maintenance charge voltage divider.
Resistor R15 is applied across R47 to set the fast charge voltage, while resistors R46 and R45 adjust the
voltage feedback for a 5EC and 10EC temperature differential, respectively.
The +5_DEG and +10_DEG switches on the Backplane CCA provide for compensation between the higher
BCPS module temperature and lower battery temperature in 5EC steps from 0EC to 15EC. The switches
connect to CR29 and CR30 and control channel selection of multiplexor U16. The battery charging voltage
compensation is -3.9mV / cell / EC.
2-78 Rev. C July, 2000

+10_DEG +5_DEG Temperature Difference

Switch Switch
Open (Off) Open (Off) 0EC
Open (Off) Closed (On) 5EC
Closed (On) Open (Off) 10EC
Closed (On) Closed (On) 15EC
Capacitors C8 and C9 set the current and voltage feedback loop compensation of the battery charger IC U2.
The voltage step-up converter frequency is synchronized to the battery charger IC U2 PWM by triggering
one-shot multivibrator U11-A, from the PWM oscillator via capacitor C19. RC combination R55 & C20 set
the sync pulse width to 300 nanoseconds.
MAINTENANCE, FAST CHARGE and BATTERY FAULT charge status is output from U2 to LED’s
CR10 (green), CR12 (amber), and CR11 (red), respectively. The BATTERY FAULT output has an
undesirable blink during charge pending and over temperature conditions which is blanked by 300 millisecond
one-shot multi-vibrator U11B and NOR gate U13A.
Charging is inhibited at module temperatures over 45EC by solid state temperature sensor U9 and a
comparator constructed from operational amplifier U8B. The comparator circuit adds several degrees of
hysteresis to stabilize the temperature inhibit signal action.
Resistor R5 applies a small pre-charge current to the battery when the system is initialized. This allows the
battery charger IC U2 to sense the battery condition and initiate a fast charge or withhold charging if the
battery is shorted or not present.
Battery charging and discharging are controlled by voltage sensors U4 and U5. The +24.5V input power
status is scaled by the adjustable voltage divider R56, R62 & R58.
NPN Transistor Q7 buffers the input voltage divider output and applies it to the low voltage sensor U4. The
output of U4 is filtered by R61 and C22 and buffered by Schmitt trigger inverter U15C and inverter U13C.
The buffers drive the FAIL_+24V open drain output from Q12 as well as the AC_FAIL indicator CR27 via
Q18.
The Schmitt trigger inverter U15C also controls power to the battery charger IC U2 via PNP transistor Q19.
Thus U2 is reset by the loss of AC power and will initiate a battery charge cycle when AC power is returned.
NOR gate U6D combines the CHG_ENABLE input and the FAIL_24V to disable both the voltage step-up
converter and buck down converter whenever +24.5V input is lost or the CHG_ENABLE module input is
Rev. C July, 2000 2-79

grounded. The CHG_ENABLE input facilitates battery testing by disabling the battery charger and is
controlled by the RMS CCA.
The battery voltage is scaled by voltage divider R66, R67 & R69, buffered by NPN transistor Q8, and applied
to low voltage sensor U5. The output of U5 is buffered by Schmitt trigger inverter U15E and applied to a
flip-flop constructed from NOR gates U6A and U6B.
The flip-flop latches low battery voltage conditions to prevent cyclic behavior as the voltage recovers after
being disconnected. The +24.5V presence output from inverter U13C resets the flip-flop upon return of AC
power. The flip-flop can also be reset manually by push button switch S1. This allows for reactivation of the
system after battery replacement.
Battery discharge is activated when the output of NOR gate U6C goes high indicating the loss of +24.5V
input and adequate battery voltage. This turns MOSFET Q6 ON which illuminates the ON_BATTERIES
indicator and activates the solid state voltage generator U3. The voltage output from U3 turns on MOSFET
transistors Q4 and Q5 which connects the battery voltage to the +24V output and the DC-DC converters.
The sources of MOSFETS Q4 and Q5 are connected together to form an ON-OFF switch that functions
properly when the voltage differential across the combination has either polarity.
Voltage to power the most basic module functions, designated +5VREF, is developed in regulator U14 from
the +12V converter output via CR23 or should the +12V converter output be lost, from the 8.5 Vdc
regulated output from Q10 and CR22. The 8.5 Vdc regulator input is obtained from the step-up converter
output. This point has adequate voltage to power the 8.5 Vdc regulator whether the step-up converter is
functioning or not. When the step up converter is not functioning, battery power via L2 and the drain source
diode in Q3 is available and, otherwise, the +24.5V Input Power via L1, T1 and CR1 & CR2 is available.
+5V, +12V, +12VM and -12V power output is obtained from separate converter modules powered by the
+24V output. The output from these converters passes thru separate EMI filters consisting of (L3, C41 &
C44), (L4, C42 & C45), (L6, C57, & C58), and (L5, C43 & C50). Potentiometers R91 and R110 will adjust
the +12V and +5V, +12VM, -12V levels.
The +5V output status is sensed in low voltage sensor, U12, filtered for noise by R73 and C46, and buffered
by Schmitt trigger inverter U19F and inverter U19D. The output of inverter U19F is ORed with the +12V,
+12VM, and -12V converter low voltage sensors in diode, CR26. MOSFET Q13 buffers the open drain
1“FAIL_+5V” output which opens when the +5V converter (PS1) output is low.
The +12V output status is scaled by resistor voltage divider R78 & R79, buffered by NPN transistor Q20,
and input to low voltage sensor U17. Filter R84 and C48 removes noise and the output is then buffered by
Schmitt trigger inverter U15B and inverter U15D. The output of inverter U15D is ORed with the +5V,
+12VM, and -12V converter low voltage sensors in diode CR25. MOSFET Q14 buffers the open drain
“FAIL_+12V” output which opens when the +12V converter (PS2) output is low.
2-80 Rev. C July, 2000

The +12VM output status is scaled by resistor voltage divider R93 & R92, buffered by NPN transistor Q23,
and input to low voltage sensor U18. Filter R96 and C60 removes noise and the output is then buffered by
Schmitt trigger inverter U19A and inverter U19B. The output of inverter U19B is ORed with the +5V, +12V,
and -12V converter low voltage sensors in diode CR31. MOSFET Q24 buffers the open drain
“FAIL_+12VM” output which opens when the +12VM converter (PS1) output is low.
The -12V output status is scaled by resistor voltage divider R81 & R80, then sensed in the base-emitter
junction of NPN transistor Q21. R80 is referenced to the +5VREF bus to shift the voltage divider output
to a positive voltage. Filter R87 and C52 removes noise and the output is then buffered by Schmitt trigger
inverter U19E and inverter U19C. The output of inverter U19C is ORed with the +5V, +12VM, and +12V
converter low voltage sensors in diode CR24. MOSFET Q15 buffers the open drain “FAIL_-12V” output
which opens when the -12V converter (PS1) output is low.
2.3.9 Monitor Recombining Unit CCA (012027-0003) (1A15A1) Theory of Operation. - The MRU is
designed to operate with all localizer configurations, both Single Frequency and Capture-Effect. It contains
two identical sets of processing channels, one for Course CSB and SBO, and one for Clearance CSB and
SBO. In the Single Frequency Localizer configurations, the Clearance Channels of the MRU are
present, but are not used. For reasons of commonality, and completeness, the following discussion
contains references to capture-effect operation as well as to single frequency operation of the MRU.
2.3.9.1 Monitor Recombining Unit CCA (012027-0003) (1A15A1) Block Diagram Theory. - The Monitor
Recombining Unit, or MRU, receives samples of the radiated CSB and SBO signals from the RF Combining
unit in the localizer DU. The design of the -0003 MRU is such that it can support both capture-effect (two
frequency) and single frequency localizer systems. Adjustable gain controls permit the unit to be used with
20 and 14 element capture effect antenna systems and with 14 and 8 element single frequency systems. In
all types of systems there is a single CSB return line and a single SBO return line from the RF combining unit
to the MRU. The MRU operates on these signals and performs several functions:
a. It provides a means to adjust the phase of the SBO signal relative to the CSB signal so the two are
in phase.
b. It provides a centerline signal from the CSB input which is output to the monitor CCA for
measurement of RF Level, Ident modulation, SDM, and DDM.
c. It generates a “width” signal by combining the SBO signal with the CSB signal in an adjustable ratio
such that the monitor reads 0.155 DDM (150 Hz dominant) when the system is operating correctly.
Rev. C July, 2000 2-81

d. In capture-effect systems, the MRU provides a means to separate the course and clearance signals
and to convert both to an 8 KHz Intermediate Frequency (IF) which is further filtered and detected
on the monitor CCA. In single frequency systems, the IF down conversion process provides improved
interference rejection.
e. Connection of an external antenna mounted Near Field Monitor is supported.
A. Generation of the “Width” Monitor Signal.
Figure 2-25 depicts the traditional method by which a width signal can be created from the CSB, and SBO
signals returned from the RF Combiner. While the MRU does not work in exactly this way, the figure is
useful to explain how the width signal is generated.
Referring to Figure 2-25, the CSB signal from the RF Combiner is split into two paths. One output goes
directly to a course centerline (CL) detector which demodulates the carrier, 90 Hz and 150 Hz guidance
tones, and the ident tone which are then sent as DC (the carrier level) and audio to a monitor.
The other CSB output is routed to a summing network where it is combined with the SBO signal returned
from the RF Combiner. The SBO signal is passed through a phase shift network which is adjusted to put the
suppressed carrier of the SBO signal and the SBO sidebands into the same phase as the CSB signal. A
variable attenuator permits adjustment of the ratio of SBO power added to the CSB signal in the summing
network. This attenuator is set to produce a “width DDM” of 0.155 (150 Hz dominant) at the input to the
width detector. The detector demodulates the 90 Hz and 150 Hz tones which are sent to the monitor CCAs.
Figure 2-25. Generation of the Width Signal
2-82 Rev. C July, 2000

B. Down Conversion and Capture-Effect Course / Clearance Signal Separation
The above approach cannot be used in a capture-effect system because the CSB return line from the RF
Combiner contains both the Course and the Clearance CSB signals which are spaced only 8 KHz apart.
Similarly, the SBO return line contains both the Course and the Clearance SBO signals. Applying both to a
simple detector will produce a single output containing undesired products from both transmitters.
B.1. Capture-Effect Operation - Course / Clearance Separation
Refer to Figure 2-26 which shows the frequency spectrum of the CSB and SBO signals returned from the
RF Combiner for the Course and Clearance transmitters. The carrier, as well as the 90 and 150 Hz sidebands
are shown in relation to the ILS channel center frequency. The 1024 Hz ident sidebands are omitted for
clarity.
The MRU uses a mix down technique which exploits the 8 KHz Course to Clearance transmitter frequency
difference to separate the course and clearance signals. Refer again to Figure 2-26 where the course and
clearance output frequencies from the Frequency Synthesizer are shown. The clearance transmitter frequency
is set 4 KHz below the assigned channel frequency and the course transmitter frequency is set 4 KHz above
the channel center. By using the “clearance” frequency as a Local Oscillator, the Course CSB and SBO may
be mixed down to an intermediate frequency (IF) equal to the frequency difference or 8 KHz.
Figure 2-27 depicts the IF spectrum resulting from this process. The Clearance LO is subtracted from both
the Course and Clearance signals. The Clearance signal carrier is translated to 0 Hz or DC, and the Course
is translated to a carrier center frequency of 8 KHz with all sidebands intact and in the same amplitude and
phase relationships to the 8 KHz carrier. This 8 KHz Course IF signal is easily separated from the Clearance
tones at 90 and 150 Hz by high pass and band pass filters. It is then detected and processed by the Monitor
CCAs.
Separation of the Clearance signals is accomplished in an identical manner; except that the Course frequency
from the synthesizer is used as the local oscillator to translate the Clearance SBO and CSB to the 8 KHz IF
frequency.
Rev. C July, 2000 2-83

Figure 2-26. Course, Clearance, and LO Spectrum.
Figure 2-27. MRU Down Conversion IF Spectrum
2-84 Rev. C July, 2000

B.2. Single Frequency Localizer MRU Operation - Course CSB and SBO Down Conversion.
In Single Frequency Localizers, the MRU operates as described above, except that there is no Clearance RF
frequency returned from the DU/Combiner to the MRU. The Course frequency LO which is required to
down-convert the Clearance RF is terminated at the Synthesizer CCA and is not input to the MRU. Only
the Course Frequency CSB and SBO Channels of the MRU are active. Additionally, the Single Frequency
Localizer carrier frequency is centered on the assigned channel and is not offset by + 4 KHz. Consequently
the “Clearance” frequency LO output from the synthesizer is offset -8 KHz below the transmitted “Course”
frequency to produce an 8 KHz IF.
Figure 2-26A. Single Frequency Course & LO Spectrum
Figure 2-26A shows the frequency spectrum of the Course Transmitter input to the MRU. Figure 2-27A
shows the IF spectrum resulting when the Course Transmitter CSB and SBO are down converted to the 8
KHz IF.
Rev. C July, 2000 2-85

Figure 2-27A. Single Frequency MRU IF Spectrum
C. MRU Signal Processing Block Diagram.
Refer to Figure 2-28 which depicts the signal processing functions of the MRU as applied to either the
Course frequency or the Clearance frequency signals of a capture-effect system. The MRU contains two sets
of these circuits driven from power dividers on the SBO and CSB inputs; one set is for Course and one set
is for Clearance. In a single frequency Localizer, the Clearance circuits are not used.
The CSB and SBO input signals are processed in identical phase matched down conversion channels. After
the input power splitter (not shown) the CSB signal is routed to AT1 , a 10 dB pad, which attenuates the
signal and stabilizes the input impedance presented to the input power splitter. It is required to attenuate the
input signal level to place the signals in the linear dynamic range of the mixers. In the SBO channel AT3, a
6 dB pad, is used since the SBO power is less than the CSB power.
Following AT1 the CSB signal is routed to phase shifter P1 which is identical to P2 in the SBO channel. P1
is used for factory alignment to trim out the phase variations in the MRU such that the CSB and SBO signals
are down converted in phase when phase shifter P2 is centered. This removes all component phase tolerance
effects to maximize the available adjustment range of P2 at installation time.
2-86 Rev. C July, 2000

Figure 2-28. MRU Signal Processing Functions
Each phase shifter is followed by a 6 dB attenuator which stabilizes the load impedance presented to the
mixer by the phase shifter and the load impedance presented to the phase shifter by the mixer. Use of two
identical phase shifters mitigates their temperature drift to maintain the phase tracking of the CSB and SBO
channels over temperature to within 1 degree.
The output signals from AT1 and AT3 are routed to a phase matched dual down converter consisting of
mixers M1 and M2. LO is supplied in the same phase to each mixer by power splitter PS1 so the resulting
IF outputs from the mixers are also in phase.
Maintenance of phase tracking through the dual down converters is required to enable creation of the width
signal by summation of the CSB and SBO signals at the 8 KHz IF rather than at RF as depicted in Figure 2-
25. Summation at the 8 KHz IF enables a pot to be used to adjust the width level without interaction between
the width level and the SBO phase which otherwise occurs with variable RF attenuators.
Refer again to Figure 2-28. The output of each mixer is filtered by high pass filters with a 4 KHz cutoff
frequency to attenuate the undesired baseband 90, 150, and 1 KHz ident tones and to pass the desired 8 KHz
IF frequency and it’s associated sidebands.
After filtering, the CSB IF is routed to adjustable gain amplifier A1 which increases the level to 1.5 Volts
peak to peak for transmission to the monitor CCAs. A portion of this signal is also routed to summing
amplifier A2 where it is combined with the SBO IF from M2 and F2 to create the width signal. An adjustment
is provided to set the output of A2 to 1.5 Volts peak to peak for transmission to the monitor CCAs. A
separate width adjustment on the input of the summing network enables setting of the SBO to CSB IF signal
ratio to obtain 0.155 DDM.
Rev. C July, 2000 2-87

D. MRU Detailed Block Diagram.
Figure 2-29 is a detailed block diagram of the MRU which illustrates all functions of the MRU CCA.
The CSB and SBO signals from the RF combiner are input to the module and routed to power dividers. The
outputs of the power dividers drive a Clearance processing channel and a Course processing channel, each
of which consists of a CSB and an SBO down converter as described in the last paragraph.
This results in four 8 KHz IFs which are output to the monitor CCAs:
a. Clearance Centerline (CL) IF Signal - Not Present in Single Frequency Systems

b. Clearance Width (Width) IF Signal - Not Present in Single Frequency Systems
c. Course Centerline (CL) IF Signal
d. Course Width (Width) IF Signal
To support setup and test of the MRU a number of RF and IF test points are provided. These are arranged
either as matched 50 Ohm sample points or as high impedance sample points. SMB “push on” coax test point
connectors are used to enable a matched connection to be made.
Matched 50 Ohm sample outputs are provided on the two local oscillator input lines prior to the LO power
dividers and on each of the four RF input paths prior to each mixer. The coupling factor for these lines is -20
db and the test point impedance is matched to 50 Ohms enabling direct connection of a PIR, spectrum
analyzer, network analyzer, power meter, or other RF test equipment.
Additional test points are provided on each channel at the output of each 4 KHz high pass filter and at the
output of each adjustable gain amplifier at the point where the 8 KHz IF is routed to the Monitor CCAs. The
8 KHz IF test points are isolated by resistors and intended to drive high impedance devices such as
oscilloscopes, audio phase gain meters, and audio Voltmeters.
The MRU also contains an interface and output amplifier to support an optional Near Field Monitor (NFM).
Refer to Figure 2-29. The NFM interface performs the following functions using a single coaxial cable
connection from the MRU to the NFM:
a. Supplies power from a dedicated +18 Volt regulator to the NFM. Use of a current limited dedicated
regulator prevents accidental shorting of the NFM feed cable from damaging or preventing operation
of the MRU.
b. Supplies a Local Oscillator signal to a mixer located in the NFM.
c. Receives and amplifies an 8 KHz IF Course Centerline signal returned to the MRU from the NFM.
2-88 Rev. C July, 2000

Separation of these signals within the MRU is accomplished by means of filters in the NFM interface.
To facilitate measurements with a PIR using demodulated audio, the MRU is provided with a single channel
8 KHz detector and filter which may be used to demodulate any of the five 8 KHz IF outputs. The detector
is linear and provides the guidance tones as well as a DC level proportional to the IF carrier level. A five
position selector switch, shown in Figure 2-29 enables any of the five 8 KHz IF signals to be routed to the
detector.
The MRU operates from +24 Volts DC which is obtained by a diode OR from both transmitters in a two
transmitter system. Two regulators provide +18 Volts for internal use by the MRU and for power to the
optional NFM.
2.3.9.2 Monitor Recombining Unit (MRU) (1A15A1) Detailed Circuit Theory - Refer to Figure 11-9A,
Sheets 1 and 2; the schematic diagram of the -0003 MRU. As described above, the CSB and SBO inputs
enter the MRU at J3 and J2 where they are split into the Course and Clearance channels by PS1 and PS2.
The input attenuators are PI pads of which R1, R5 and R9 form a typical example. A 10 db input pad is used
in the CSB channels and a 6 dB pad is used in the SBO channels.
The phase shifters in all channels are identical and realized with low Q “T” networks consisting of two
inductors and a fixed and variable capacitor. L1, C1, C5, and L5 form a phase shifter identical to all phase
shifters in the MRU. These circuits provide an adjustment range of approximately ± 20 degrees. The fixed
capacitor C5, limits the adjustment range and makes the phase shift symmetric about the mechanical center
of the variable capacitor C1. For C1, C2, C3, and C4, multiple turn precision trimmers are used which allow
precise adjustment.
Test point TP-1 is a -20 db RF sample output. Voltage divider R25 and R28 attenuate the RF Voltage by
10X (i.e. -20dB) when a 50 ohm load is plugged into TP1. This type of test point provides minimal
disturbance of the impedance and insertion loss on the sampled line irrespective of the presence or absence
of a 50 Ohm load on TP-1. Accurate phase and amplitude measurements may be made at this type of test
point. The coupling accuracy is approximately 1 db.
Mixers MX-1 through MX-4 are high dynamic range mixers which operate at +10 dBm LO power, but will
work without change in conversion loss for LO inputs as low as + 4 dBm. LO power to the mixers is supplied
from the Frequency Synthesizer CCA via the transfer switches and input to the MRU on J4 and J1 at a level
of +14 dBm. Power splitters PS3 and PS4 route the LO signals to each mixer. 50 Ohm LO test points are
provided at T5 and TP6.
Rev. C July, 2000 2-89

Figure 2-29. MRU Detailed Block Diagram - Single Frequency Operation
2-90 Rev. C July, 2000
The LO at J4 is identified as (CLR FREQ) which indicates the frequency of the LO is that of the Clearance
transmitter. This is the signal required to down convert the COURSE signals to the 8 KHz IF. Similarly the
LO at J1 is identified as (CRS FREQ) indicating that this is the LO frequency required to convert the
CLEARANCE signals to the 8 KHz IF.
The IF mixer outputs are terminated at all frequencies in a 51 Ohm resistor to preserve the IF port match on
the mixer and the mixer balance.
Following the 51 Ohm resistor is a low pass filter of which L9 and C9 are typical. Used on all mixers, these
filters prevent the sum frequency output of the mixer and any LO present on the IF port of the mixers from
reaching the IF active filters.
Two pole active high pass filters are used to reject the baseband audio which results from conversion of the
undesired transmitter frequency to DC and audio as explained above. U1A and the associated components
form one of the filters. U2A, U3A, and U4A form the filters for the other three channels. All of the filters are
identical.
Each filter has a Voltage gain of 10, and has a response with the cutoff frequency placed at 4 KHz. The cutoff
frequency of 4 KHz is used to ensure the response in the 8 KHz IF pass band which extends from 7 to 9 KHz
(because of the 1 KHz ident tone) is flat and remains stable with component variations and temperature drift.
From the filters each IF signal is routed to the output amplifiers. As explained above, the centerline signals
are routed directly to the output amplifiers. U1B is the course centerline output amplifier and U3B is the
output amplifier for the clearance channel centerline. R65 and R67 adjust the gain of these amplifiers to set
the output level to the monitor CCAs to 1.5 Volts peak to peak.
To generate the width signal, the CSB IF from U1A and the SBO Signal from U2A are routed to the
summing amplifier U2B via resistors R55, R59, and R60. R55 is a variable resistor which is used to set the
ratio of SBO to CSB IF at the input of U2B to obtain the desired width DDM of 0.155. Resistor R66 is used
to set the amplitude of the width channel output level to the monitor CCAs to 1.5 Volts peak to peak.
The adjustable range of the gain controls and the width control are designed so the MRU will operate with
the 14 and 20 element capture-effect antenna systems and with the 8 and 14 element single frequency antenna
systems.
Operation of the Clearance Channel centerline and width circuits is identical to the Course channel as
described above.
Rev. C July, 2000 2-91

Power is input to the MRU on J6 and the signals to the monitors are output from the MRU on J6.
The near field monitor interface, voltage regulators, and power regulators are shown on sheet 2 of the
schematic diagram.
The NFM interface receives a sample of the clearance frequency LO from a resistive tap on the LO input
consisting of R33 and R34. The LO sample is coupled to the coaxial line connecting the NFM to the MRU
at J5 via capacitor C47. C47 is sized to pass the 108 to 112 MHZ LO signal and block lower frequencies.
DC operating Voltage is provided to the NFM via L13 and L14. L14 is chosen to block the LO signal from
the DC supply line.
The 8 KHz IF signal returned from the NFM is developed across the parallel combination of L13, C49, R90,
and the shunt capacitance of the coax cable to/from the NFM. These components form a very low Q resonant
circuit at 8 KHz having an equivalent impedance which is essentially determined by R90. The bandwidth of
this circuit extends from 4 to 20 KHz to ensure that shifts in the resonant frequency due to variations in the
length of the coax cable will have no effect.
The 8 KHz return signal developed across R90 is routed to U8A, which is a differential amplifier used to
cancel any hum or other noise present on the coax center conductor or the power supply. The returned 8
KHz level at R90 is approximately .5 to 1.5 Volts peak to peak. From U8A the signal is routed to U8B, an
adjustable gain amplifier used to set the 8 KHz IF level to the monitor CCAs to 1.5 Volts peak to peak.
U7A is a precision, low noise reference source, which provides a fixed DC reference level at ½ of the 18
Volt supply, to the amplifiers and filters which require a DC reference.
The remaining function of the MRU is the PIR test detector consisting of switch S1, and U5, U6, and U7B.
S1 is a tuning tool actuated switch which selects the signal to be detected. Any of the five 8 KHz IF signals
may be selected. U5A presents a high input impedance to the circuit selected by S1 to avoid loading
problems. It has a gain of 2 to increase the Voltage applied to the precision detector U5B. This improves the
detector linearity. U5B half-wave rectifies the 8 KHz IF, which is then filtered by low pass filter U6A and
U6B, to recover the DC component, the 90 Hz tone, and the 150 Hz tone.
The DC component at the output of U6B represents the 8 KHz carrier component but, is offset from ground
by 9 Volts due to the necessity to power the MRU from a single +18 Volt supply. Amplifier U7B is a level
shifter which restores the DC output of the detector to a ground reference.
The resistor network consisting of R102, R103, and R104 has several functions. It provides the input at ½
of the 18 Volt supply Voltage to reference amplifier U7A. The reference Voltage is used to bias the reference
inputs of all operational amplifiers in the MRU to approximately 9 Volts.
2-92 Rev. C July, 2000

This Voltage is developed at the wiper of R103 and is not critical except with respect to the operation of
U7B. Potentiometer R103 is used to trim the reference Voltage at the inverting input of U7A, such that it
is approximately ½ of the 18 Volt supply. This adjustment is used to trim out any DC offset created in the
detector amplifiers U5B, U6A and U6B, to ensure that when there is no 8 KHz present, the detector output
at TP16 is exactly 0 Volts DC.
Power conditioning circuits in the MRU consist of the diode OR, CR3 and CR4, and two 18 Volt regulators
U9 And U10. The diode OR enables powering of the monitor from either the main or the standby transmitter
supplies and ensures the MRU will operate if one or the other malfunctions.
U9 provides the +18 Volt source to power the MRU and U10 provides +18 Volts to power the NFM. This
signal is shown on the schematic as +18 NFM.
2.3.10 Transmitter Recombining Unit CCA (TRU) (012025) (1A15A3). Theory of Operation. - Located in
the Transfer / Recombiner Drawer, the TRU performs the frequency translation and width channel generation
required to monitor the standby transmitter. Like the MRU the TRU is designed to operate with either Single
Frequency or Capture-Effect Localizers. When used in a Single Frequency System, the Clearance RF
monitor signals are not present and there is no “Course Frequency” LO input to the TRU from the
Synthesizer. In the following discussion, references to processing of Clearance signals do not apply to
Single Frequency Systems.
The TRU receives an attenuated sample of the RF signal from each of the Course CSB, Course SBO,
Clearance CSB, and Clearance SBO outputs of the transfer switch. These signals are combined in amplitude
and phase to provide Course and Clearance path and width IF signals for the monitor. Also input to the TRU
are switched Course and Clearance Local Oscillators used for frequency translation of the RF signals to the
8 KHz IF.
Rev. C July, 2000 2-93

2.3.10.1 Transmitter Recombining Unit CCA (TRU) (012025) (1A15A3). Block Diagram Theory. -
Figure 2-30 is a block diagram illustrating operation of the Course Channel of the Transmitter Recombiner
Unit (TRU). Operation of the Clearance channel is identical.
Figure 2-30. TRU Course Channel Functional Block Diagram
The Course Centerline (CL) or “path” signal is created as follows. CSB from the output of the standby
Course PA is input to a power splitter within the TRU. One output of the power splitter goes directly to the
Course Centerline and is mixed with a LO signal from the Frequency Synthesizer at the Clearance Frequency.
The mixer translates the CSB signal directly to the 8 KHz IF, where after filtering and amplification, it is
routed to the monitor CCA’s as the CRS Centerline IF.
The Course Width signal is generated by summing the CSB, obtained from the other output of the CSB
power splitter, with the Course frequency SBO from the Course standby PA SBO output. The SBO signal
is passed through a variable attenuator and a mechanical phase shifter and then routed to a power splitter
connected as RF summing junction. The function of the phase shifter is to permit adjustment of the phase
between the CSB, and the SBO, at the summing network, such that the CSB carrier, and the suppressed SBO
carrier are in the same phase. Adjustment of the ratio of SBO Power to CSB power at the summing junction
is facilitated by the variable attenuator which is used to set the width DDM. This adjustment is made as part
of the system setup and installation.
As in the case of the centerline channel, the width channel is mixed down to the 8 KHz IF, and after
amplification and filtering, is output to the monitor CCAs.
The TRU contains a duplicate set of circuitry, identical to that just described, which provides Centerline, and
Width, outputs for monitoring a Standby Clearance Transmitter in a Capture-Effect System.
2-94 Rev. C July, 2000

2.3.10.2 Transmitter Recombining Unit (TRU) (1A15A3) Detailed Circuit Theory.- Refer to Figure 11-11.
Operation of the Course TRU channel is described in detail. Operation of the Clearance Channel is not
described because it is identical to the Course Channel.
The Course CSB signal enters the TRU at J2 where it is initially attenuated in a PI attenuator formed by R57,
R62, and R58. The signal is next routed to power splitter PS1 which divides the signal into two paths, one
for generation of the centerline signal, and the other for generation of the width signal. One output of PS1
is routed through a PI attenuator, to test jumper J7, and then to mixer MX1 for generation of the Clearance
centerline signal. At MX1 an 8 KHz IF is obtained by mixing the CSB RF Frequency with a Clearance
Frequency LO which enters the TRU on J1 and is routed to mixers MX1, and MX2, via the power splitter
PS1.
The 8 KHz IF output from MX1 is AC coupled by C13, and low pass filtered by L5 and C17, to remove the
RF components. After filtering, the centerline signal is amplified by U1A and U2B to a level of approximately
1 Volt peak to peak and is then routed to the monitor CCA’s via connector J11.
Operation of the Course Width channel is similar except the SBO is summed with the CSB to create the
Width signal. The Course SBO signal enters the TRU at connector J3. It is then routed through a fixed
attenuator (R60, R59, and R61) to variable attenuator AT2. From AT2, the SBO signal is passed through
the Course SBO phaser, which is adjusted by variable capacitor C7, to align the phase of the SBO suppressed
carrier with the CSB carrier. From the SBO phaser, the SBO signal is sent to power splitter PS3 which is
connected as a summing junction. Also input to this power splitter is the Course CSB signal from the output
of power splitter PS1. These two signals are summed to create the width signal. Attenuator AT2 enables
adjustment of the SBO power relative to the CSB power to set the width DDM to the correct value when
the system is installed.
The Course Width signal generated in PS3 is output on the “input port” which is Pin 6 and routed through
test jumper J10 to the width mixer, MX2, where it is down converted to the 8 KHz IF.
The 8 KHz IF output from MX2 is AC coupled by C14, and low pass filtered by L6 and C18, to remove the
RF components. After filtering, the Width IF signal is amplified by U1B andU2A to a level of approximately
1 Volt peak to peak. It is then routed to the monitor CCA’s via connector J11.
The operational amplifiers in the TRU, of which U1 is example, are operated as AC coupled 8 KHz IF
amplifiers. The amplifiers are connected in inverting mode, with the gain being established by feedback
networks consisting of R37, and R21. R21 is shunted by a temperature compensation network consisting of
fixed resistor R77, and thermistor R78. These components adjust the gain of the amplifier to compensate for
changes in conversion loss of the mixer which occur with temperature changes.
Rev. C July, 2000 2-95

The amplifiers operate from a single + 24 Volt supply voltage. For proper operation to non-inverting, input
of each amplifier is biased at approximately ½ of the supply voltage by resistor dividers of which R13 and
R14 are typical. Noise on the supply is removed by a filter capacitor, of which C21 is a typical example.
Power from the TRU is obtained by redundant 24 Volt inputs, one from Transmitter No. 1, and one from
Transmitter No. 2. The power inputs are summed by a diode OR network consisting of CR1, and CR2.
Test points are provided for the 8 KHz IF outputs at TP1, TP2, TP3, and TP4. RF test points which may be
used for measurement or for injection of test signals include the jumpers; J7, J10, J8, and J9.
2.3.11 Transfer Relay Driver Board (012044) (1A15A2). Theory of Operation. - Refer to Figure 11-10.
Electromagnetic transfer relays contained within the Transfer / Recombiner Drawer are used to transfer the
antenna and dummy load from one transmitter to the other. Transmitter number 1 or number 2 may be
connected to either the load or the antenna as determined by the system setup and action of the system
monitor and LCU.
Highly reliable magnetic latching transfer relays are used. The Transfer Relay Driver CCA has three primary
functions:
a. Receive and condition continuously asserted 24 volt logic signals from the LCU which indicate which
transmitter is to be connected to the antenna and to convert these signals into a single 200 millisecond
pulsed signal to drive the latching relays. The pulsed drive signals are applied to power FETs on the
driver board which drive the relays by asserting an open drain output to ground.
b. Provide drive to, and sense the condition of, the latching relay “indicator contacts” and to provide
three indications of the indicator contact status back to the LCU as negative true open collector logic
levels. The three status conditions reported are; position 1 selected, position 2 selected, or fault. Fault
is reported if one relay indicator or more is in position 2 when any other is in position 1. Fault is also
indicated if connection between the board and the relay indicator contacts is lost.
c. Power on reset. Upon power up, the relay logic board resets it’s internal timers to an idle or reset
condition. Additionally a pulse is generated which puts the relays in a known condition; at power up
transmitter 1 is always connected to the antenna and transmitter 2 is connected to the load. (If the
system is configured for transmitter 2 to be on the air, the system is subsequently put into this
condition under software control).
2-96 Rev. C July, 2000

2.3.11.1 Signal Interfaces. - The following tables describe the signal interfaces between the LCU, the 012044
board at J25, and the magnetic latching transfer relays which connect to the driver board via a harness at J1.
Table 2-3 shows the signal interface between the LCS and the Relay Driver board. Table 2-4 describes the
signal interfaces between the Relay Driver board and the magnetic latching transfer relays.
2.3.11.2 Relay Driver and Timing Logic. - Refer to figure 11-10 for operation of the major functions
described in the following sections.
The relay drive and timing logic is powered from two sources, Transmitter 1 or Transmitter 2, which are
connected to a +12 volt local regulator by means of a diode OR circuit. Either transmitter will power the
circuit in the event of failure of the other.
Selection of a particular transmitter to be connected to the antenna is initiated by the LCU. If transmitter 1
is to be connected to the antenna the LCU asserts +24 Volts on J25 Pin 5 and ground on J25 Pin 7. Both
must be asserted for a transfer to occur. Conversely if transmitter 2 is to be on the antenna, the opposite
condition is asserted by the LCU. Pin 5 is grounded and Pin 7 receives a +24 volt level
Table 2-3 LCU Interface - J25 Signal Inputs and Outputs
J25 PIN SIGNAL SIGNAL FUNCTION
1 AGND Analog Ground
2 2_TXSEL Output - Low True - Indicator status indicates #2 Tx on antenna
3 AGND Analog Ground
4 FAULT Output - Low True - Indicator contact position mismatch or

disconnect
5 1_+24ANT_SW Input - 0/24 V - Connect # 1 Tx to Antenna if 24 V, and Pin 7 low.
6 1 +24V Input - +24 V supply from Tx # 1
7 2_+24V_SW Input - 0/24 V - Connect # 2 Tx to Antenna if 24 V, and Pin 5 low.
8 2 +24V Input - 24 V supply from Tx #2
9 1_TXSEL Output - Low True - Indicator status indicates #1 Tx on antenna
10 NC
Rev. C July, 2000 2-97

Table 2-4 Transfer Relay Interface - J1 Signal Inputs and Outputs
J1 PIN SIGNAL SIGNAL FUNCTION
1 Pos 1 Ind Output to position 1 indicator contacts on all relays
2 Indicator Com. Input voltage from indicator moving contact (common) on all relays
3 Pos 2 Ind Output to position 2 indicator contacts on all relays
4,5,6 NC No Connection
7,8 SW POS 2 Output: Open drain drive to position 2 relay actuator coils. LOW = ON
9,10 SW POS 1 Output: Open drain drive to position 1 relay actuator coils. LOW = ON
11,12, +24 to Relays Output: +24 VDC supply to all relay coils
13,14
The Transfer Relay Driver CCA contains two identical circuits which drive the transfer switch coils.
Operation for one will be explained as they function identically, with the exception of the power on reset
function.
Assume TX-1 is to be connected to the antenna. The +24 volt logic signal from the LCU at J25-5 is routed
to a signal conditioner consisting of R2 and R4 which divides the voltage level to obtain 0/12 Volts which
is compatible with the CMOS logic used. This signal is routed directly to the three input AND gate U8A and
is one of 3 signals required to produce an output from U8.
At the same time J25-7 is asserted low by the LCU. This signal is inverted by U6B and also routed to U8A.
If this signal is not asserted low by the LCU, the action of U8 is to prevent a transfer from occurring because
the AND condition is not satisfied.
The input signal from J25-5 is also routed to a noise filter (R6 and C3) and a comparator circuit (U2A) with
hysteresis, which further eliminates false triggers prior to starting the relay pulse timer. R6 and R7 form a
voltage divider which converts the 0/24 volt input to a 0/12 volt level. This is routed to the comparator U2A
which is set to trip when the plus input exceeds a nominal 6 volt set point, plus approximately 1 volt of
hysteresis. When this occurs, the output of U6A goes high and is routed to the clock input of U3A; part of
the pulse timer.
The relay pulse timer uses a counter (U4), flip flop (U3A), and a clock (U6E and U6F), to obtain repeatable
long duration pulses without unreasonable component values.
2-98 Rev. C July, 2000

Counter U4 is held reset by the Qbar output of U3A. A rising edge from U2 clocks a HIGH to the Q output
of U3A. This clears Qbar and permits U4 to count. At the same time the HIGH output from Q is passed to
AND gate U8A and provides a third HIGH at the input. U8:A then outputs a HIGH which is the leading edge
of a 200 millisecond relay drive pulse. This is conducted via OR gate U7D to the FET driver U9ABC.
U9 drives the power FET Q1 into conduction via the coupling capacitor C7. This results in a low resistance
to ground at the output of Q1 which permits the +24 volt supply to pass through the relay coils to ground,
thus initiating a change in the relay position. The network consisting of R23, C7, and CR4 is a safety device.
This network has a time constant of approximately one second after which C7 will have charged to the point
where Q1 will turn off automatically. The purpose is to limit the maximum length of a relay drive pulse
should the timing logic or power on reset circuits experience a failure. This protects the relay coils from
burnout as they are not intended for continuous drive.
The relay drive pulse width is set to 200 milliseconds by the clock and counter U4. The clock frequency is
approximately 5120 Hz or a period of 195 microseconds. Once the reset on U4 has been cleared, the timing
interval starts. It continues until the Q11 output from U4 goes TRUE which occurs at 1024 counts of the
clock; that is, after 200 milliseconds. This output is routed via OR gate U7A to the RESET input of U3A.
This RESET signal clears the Q output of U3A which causes the output of the AND gate U8A to go LOW
and terminate the drive to Q1, thus ending the relay drive pulse.
Clearing U3A also returns the Qbar output of U3A HIGH asserting a RESET on U4 which clears it’s count
to zero and readies it for the next pulse.
2.3.11.3 Power On Reset. - The system software is designed for the relays to be set for transmitter 1 to be
on the antenna at the time power is applied. Since the logic in the relay driver timers can come up in any state,
a power on reset is used to ensure the timer flip flops are cleared immediately and that the relays are pulsed
at power up to connect TX-1 to the antenna.
Inverter U6D and an RC network consisting of R20 and C5 create a positive going pulse at the output of
U6D at power up. This pulse lasts approximately 0.3 seconds. It is routed to the RESET inputs of both U3
flip flops via the U7A and B OR gates. This clears the flip flops should they be set, terminates any ongoing
output pulses, and resets counters U4 and U5 to zero.
At the same time, this reset pulse is routed to the OR gate U7D . Here it is passed through the OR gate to
the driver for Q1 which is U9ABC. This pulse turns on Q1 briefly and causes all relays to be pulsed to the
TX-1 on antenna state as required.
Rev. C July, 2000 2-99

2.3.11.4 Indicator Status Circuit. - The indicator status circuit consists of the four comparators U10A, B,
C, and D, the associated resistors, and Q3.
External to the board, the fixed indicator contacts for position 1 are connected to R39 which is a 1K pull up
to 12 Volts. Similarly the fixed indicator contacts for position 2 are connected to R27 which is a 1K pull
down to ground potential.
The moving indicator contact is connected to the inputs of the 4 comparators, U10. The signal from this
contact will be at +12 if all relays are in position 1, ground if all are in position 2, and at 6 Volts if any one
contact is in a position different from the others. The 6 volt case occurs because the errant contact will
connect R27 and R39 forming a 2 to 1 voltage divider.
The voltage divider consisting of R31, R29 plus R30, and R32 set up three regions which are input to the
comparators. This is accomplished by input of a 4 Volt reference to U10C and U10D, and an 8 Volt reference
to U10A and U10B.
In operation, input voltages from the moving contact greater than 8 cause comparator U10A to output a low
TRUE signal indication of all relays being in position 1. Similarly an input from the moving contact of less
than 4 Volts results in a low TRUE output from comparator U10D indicating that all relays are in position
2.
If the input level is between 4 and 8 Volts, then a fault output is required. U10B and U10C provide the fault
indication through an open collector wired AND which drives Q3 ON when both U10B and U10C outputs
go high. This will only occur when the input to U10B is less than 8 Volts simultaneously with the input to
U10C being greater than 4 Volts.
In the absence of a connection to the indicator contacts; resistor R58 in conjunction with R29 and R30 bias
the input to the comparators to 6 Volts. This condition will thus initiate a fault output from Q3 if the indicator
contacts become disconnected.
2.3.12 Environmental Sensors. - Theory of Operation. - The Model 2100 ILS supports a number of
environmental sensor accessories. These include; the shelter inside temperature sensor, the shelter outside
temperature sensor, a fire/smoke detector, and intrusion sensor. Operation of each is discussed briefly in the
following paragraphs. The interface connections between the sensors and the 2100 ILS transmitter cabinet
are found on sheet 2 of Figure 11-1.
2-100 Rev. C July, 2000

2.3.12.1 Shelter Temperature Sensor Assembly Circuit Theory.- Refer to Figure 11-1. The Shelter
Temperature Sensor output is routed from the smoke detector junction box to the Cabinet Interface CCA
in the transmitter cabinet. The temperature sensor provides 1 microamp of current for each Celsius degree
change within the shelter. This current is converted to voltage on the Cabinet Interface CCA and measured
using the A/D converter. The shelter temperature sensor connects to J5, an RJ11 style receptacle.
2.3.12.2 Outside Temperature Sensor Assembly Circuit Theory.- Refer to Figure 11-1. The Shelter
Temperature Sensor output is routed from the smoke detector junction box to the Cabinet Interface CCA
in the transmitter cabinet. The temperature sensor provides 1 microamp of current for each Celsius degree
change within the shelter. This current is converted to voltage on the Cabinet Interface CCA and measured
using the A/D converter. The external temperature sensor connects to J4, an RJ11 style receptacle.
2.3.12.3 Fire/Smoke Detector Assembly Theory. - The Fire/Smoke detector operates on 28 Vdc supplied
by the Cabinet Interface CCA. A set of contacts monitored by the Cabinet Interface is normally closed and
opens when the smoke from a fire is detected. The contacts are monitored by the RMS processor through
the Cabinet Interface CCA. The Fire and Smoke Detector Assembly is connected to terminal strip TB1 on
the Cabinet Interface CCA.
2.3.12.4 Intrusion Sensor Assembly Theory.- The intrusion sensor is located on the upper opening of the
shelter door. The intrusion sensor requires no power to operate. When the shelter door is closed a magnet
on the door in close proximity to the sensor above the door holds a set of contacts in the closed position.
These contacts are monitored by the RMS processor through the Cabinet Interface CCA. The intrusion
detector is connected to terminal strip TB1 on the Cabinet Interface CCA.
Rev. C July, 2000 2-101

2-102 Rev. C July, 2000


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Operations & Maintenance Manual

Manual P/N 572100-0001

THIS DOCUMENT CONTAINS PROPRIETARY INFORMATION AND SUCH

Original Issue June, 1999

Copyright, Airport Systems International, Inc., 1999 - 2000

AIRPORT SYSTEMS INTERNATIONAL, INC.

LIST OF EFFECTIVE PAGES

Airport Systems International, Inc.

Rev. C July, 2000 Effective Pages 1

Effective Pages 2 Rev. C July, 2000

Rev. C July, 2000 Effective Pages 3

Effective Pages 4 Rev. C July, 2000

ELECTROSTATIC SENSITIVE DEVICES PRECAUTIONS

KEEP AWAY FROM LIVE CIRCUITS

DO NOT SERVICE OR ADJUST ALONE

MODEL 2100 SINGLE FREQUENCY LOCALIZER

HOW TO ORDER REPLACEMENT PARTS

2. Unit sub-assembly number (where applicable).

3. Item or reference symbol number from parts list or schematic.

4. Airport Systems International, Inc. part number and description.

5. Manufacturer's code, name and part number (where applicable).

6. Quantity of each replacement part required.

AIRPORT SYSTEMS INTERNATIONAL, INC.

AIRPORT SYSTEMS INTERNATIONAL, INC.

AIRPORT SYSTEMS INTERNATIONAL, INC.

I. THIS WARRANTY IS EXPRESSLY IN LIEU OF ALL OTHER WARRANTIES, EXPRESSED

J. CUSTOMER'S SOLE REMEDY FOR ANY BREACH OF THE WARRANTY SHALL BE

SECTION 1. GENERAL INFORMATION AND REQUIREMENTS

Paragraph Description Page

1.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

Rev. C July, 2000 i

SECTION 2. TECHNICAL DESCRIPTION

Paragraph Description Page

2.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

ii Rev. C July, 2000

SECTION 2. TECHNICAL DESCRIPTION

Paragraph Description Page

2.3.4.2.3 ILS Test Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-43

Rev. C July, 2000 iii

SECTION 2. TECHNICAL DESCRIPTION

Paragraph Description Page

2.3.8.2 Battery Charging Power Supply CCA ( 012014) (1A6/1A10)

iv Rev. C July, 2000

Paragraph Description Page

3.1 INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

Rev. C July, 2000 v

Paragraph Description Page

3.4.2.7.2 Station Configuration Screen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-28

vi Rev. C July, 2000

Paragraph Description Page

3.4.2.14 Transmitters Waveform Screens . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-63

SECTION 4. STANDARDS AND TOLERANCES

4.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1

SECTION 5. PERIODIC MAINTENANCE

5.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1

Rev. C July, 2000 vii

SECTION 6. MAINTENANCE PROCEDURES

Paragraph Description Page

6.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1

viii Rev. C July, 2000

SECTION 6. MAINTENANCE PROCEDURES

Paragraph Description Page

6.4.8 Setting Monitor RF level reference levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-31