University of Massachusetts Dartmouth

Spring 2007
CIS 273: Computer Organization & Design

Laboratory #6 – Tailoring the 32-bit ALU to MIPS

Objectives

• Verify a rule for detecting overflow when adding/subtracting two's-complement numbers.

• Add overflow detection to the 32-bit ALU and tailor the ALU to support the MIPS set on
less than instruction (slt).

Introduction

In this lab, you will extend the 32-bit ALU of the previous lab in two ways. First, you will add
overflow detection to the 32-bit ALU. Second, you will add support for the MIPS set on less than
instruction (slt).

Design

The n-bit ripple-carry adder in Figure 1 can be used to add 2's-complement numbers X and Y,
where the xn-1 and yn-1 bits are the sign bits. In this case, the carry-out bit, cn, is not part of the
answer.

Figure 1: An n-bit ripple-carry adder

Overflow can only occur when the signs of the two operands are the same. In this case,
overflow obviously occurs if the sign of the result is different. Therefore, the n-bit adder can be
augmented with a circuit to detect overflow by implementing the logic expression:

Overflow = (xn-1 AND yn-1 AND (NOT(Sn-1))) OR

(NOT(xn-1) AND (NOT(yn-1)) AND Sn-1)

It can also be shown that overflow occurs if and only if the carry bits cn and cn-1 are different.
Therefore, a simpler alternative method for detecting overflow can be obtained by implementing
the expression cn XOR cn-1 with an XOR gate.
Below is the 1-bit ALU which you used to create a 32-bit ALU in the last lab. Recall that this ALU
can perform addition, subtraction, AND, OR on the two data inputs according to an operation
code supplied to the ALU.

Operation Binvert CarryIn Result Function

00 0 X a AND b Logical AND
01 0 X a OR b Logical OR
10 0 0 a+b Addition
10 1 1 a-b Subtraction
11 1 1 Less Set on Less

Figure 2: A 1-bit ALU.

The input Less in the ALU above is used only for slt. Recall that we obtained a 32-bit adder by
connecting 32 instances of the ALU above and letting the carry ripple from one ALU to the next.
As discussed in class, the set-on-less than instruction can be performed using the 32-bit ALU by
subtracting b from a, setting the least significant bit of the Result to the sign bit of the result,
and setting all other bits to zero. Following that line of reasoning, we can connect 0 to the Less
input for the upper 31 bits of the ALU and connect the adder output of the ALU for the most
significant bit to the Less input for the least significant bit to implement set on less than. Thus,
we need a special 1-bit ALU for the most significant bit, with a new adder output line called Set,
and used only for slt. The 1-bit ALU for the most significant bit must also detect overflow. We
call that output Overflow. We already know that a simple circuit for detecting overflow can be
obtained by implementing the expression CarryIn XOR CarryOut with an XOR gate. Figure 3
shows the new 1-bit ALU for the most significant bit. It calculates overflow using several inputs
but we will use the alternative method of detecting overflow using CarryIn XOR CarryOut.
 Figure 3: A modified 1-bit ALU for the most significant bit

Finally, we can concatenate 31 copies of the 1-bit ALU in Figure 2 and one 1-bit ALU in Figure 3
to get the desired ALU. Figure 4 shows the 32-bit ALU.
 Figure 4: A 32-bit ALU

VHDL code

We start by specifying the entity declaration for the 1-bit ALU for the most significant bit:

library ieee;
use ieee.std_logic_1164.all;
entity ALU2 is
port (a, b, Less, CarryIn, Binvert: in std_logic;
Operation: in std_logic_vector (1 downto 0);
Result, CarryOut, Set, Overflow: out std_logic);
end ALU2;
Figure 5: Entity declaration for the 1-bit ALU for the most significant bit
This is similar to the declaration for the 1-bit ALU shown in Figure 2, except for the new output
ports Set and Overflow. The Set output will be the direct output from the adder for the set on
less than comparison test. The Overflow output will indicate whether overflow occurs or not.
Below is the VHDL code you used to create the 32-bit ALU in the previous lab. Of course, this
code is incomplete as it does not incorporate what must be done to accomplish the slt
instruction or detect overflow.

library ieee;
use ieee.std_logic_1164.all;
entity ALU32 is
port (a, b: in std_logic_vector (31 downto 0);
CarryIn, Binvert: in std_logic;
Operation: in std_logic_vector (1 downto 0);
Result: out std_logic_vector (31 downto 0);
CarryOut: out std_logic);
end ALU32;

architecture structural of ALU32 is

component ALU1 is
port (a, b, Less, CarryIn, Binvert: in std_logic;
Operation: in std_logic_vector (1 downto 0);
Result, CarryOut: out std_logic);
end component;

signal c: std_logic_vector (30 downto 0);

signal Less: std_logic;
begin
Less <= '0';
A1: ALU1 port map (a(0), b(0), Less, CarryIn, Binvert, Operation,
Result(0), c(0));
G1: for i in 1 to 30 generate
ALUs: ALU1 port map (a(i), b(i), Less, c(i - 1), Binvert,
Operation, Result(i), c(i));
end generate;
A32: ALU1 port map (a(31), b(31), Less, c(30), Binvert, Operation,
Result(31), CarryOut);
end structural;

Figure 6: Entity-architecture pair for the 32-bit ALU

 What you need to do

1. Show that the logic expression cn XOR cn-1 is a correct indicator of overflow in addition of
2's-complement integers, by completing the following table. To make it simpler to verify
this expression manually, let's limit the integers to 3 bits (n = 3). c2 is the carry into the
sign bit and c3 is the carry out of the sign bit.

a b a+b a b c2 c3 Overflow
(in decimal) (in decimal) (in decimal) (in 2’s complement) (in 2’s complement) (yes/no)
1 1 2
1 2 3
1 3 4
-1 -1 -2
-1 -2 -3
-1 -3 -4
-1 -4 -5
-2 -2 -4
-2 -3 -5
-2 -4 -6
-3 -3 -6
-3 -4 -7
-4 -4 -8

2. Create a new project by first creating a folder called newALU32 and make it the working
directory of the project. Set the Project name and the Top-level design entity to
newALU32. Choose StratixTM as the target device family.

3. Copy all the .vhd files you created in the ALU32 folder (except the ALU32.vhd) to the
newALU32 folder.

4. Create a new VHDL file. Type (or paste) the entity declaration for the 1-bit ALU entity
given in Figure 5 into the Text Editor. The architecture code for this entity will be similar
to the one for the 1-bit ALU created in the previous lab (file: ALU1.vhd), except for the
two extra outputs. Save the file with the name ALU2.vhd. Make sure to put a checkmark
in the box Add file to current project.

5. Create a new VHDL file. Create an entity named newALU32 by modifying the 32-bit ALU
entity-architecture pair in Figure 6 to handle slt and detect overflow. Save your code in
newALU32.vhd. Make sure to put a checkmark in the box Add file to current project.
 6. Perform functional simulation of the new 32-bit ALU circuit to verify the correctness of
the circuit for the following operations (all values are in decimal). For the signals a, b,
Operation and Result, choose the multibit representation when selecting the nodes for
the simulation. Calculate the decimal values of the most negative number and the most
positive number for 32-bit 2's-complement representation to determine whether the ALU
gives a correct indication of overflow.

(i) Add b = 323964240 to a = 1431586130.

(ii) Add b = 715897517 to a = 1431586131 .
(iii) Set on less than operation using the values a = 323964240 and b = 1431586130.
(iv) Set on less than operation using the values a = 1431586130 and b = 323964240.

Check off

To pass this lab you must demonstrate the correctness of the 32-bit ALU to a TA, and turn in a
hard copy of the following:

• Completed table above.

• The results of the simulation of the new 32-bit ALU (for the four test cases above).
• The complete VHDL source code (including architecture) for the 1-bit ALU for the most
significant bit
• The complete VHDL source code (including architecture) for the new 32-bit ALU.