EC381
Digital Systems I
University of Tripoli
Digital Systems 1
Binary Adder-Subtractor
Half adder
0 + 0 = 0 ; 0 + 1 = 1 ; 1 + 0 = 1 ; 1 + 1 = 10
Two input variables: x, y
Two output variables: C (carry), S (sum)
Truth table
Digital Systems 2
Full-Adder
Full-Adder
The arithmetic sum of three input
bits.
Three input bits
» x, y : two significant bits.
» z : the carry bit from the previous
lower significant bit.
Two output bits: C, S
Digital Systems 3
Binary Adder (Ripple Adder)Hierarchical
Design
Digital Systems 5
Carry propagation
When the correct outputs are available
The critical path counts (the worst case)
(A1, B1, C1) → C2 → C3 → C4 → (C5, S4)
When 4-bits full-adder → 8 gate levels (n-bits: 2n gate levels)
The total delay is 2n+1 (When S and Cout are ready).
Digital Systems 7
Overflow
Overflow
The storage is limited
Add two positive numbers and obtain a negative number
Add two negative numbers and obtain a positive number
V = 0, no overflow; V = 1, overflow
Example:
Digital Systems 8
Binary Subtractor
Digital Systems 10
BCD Adder (1/3)
Digital Systems 11
BCD Adder (2/3)
C = K +Z8Z4 + Z8Z2
Digital Systems 12
BCD Adder (3/3)
Block diagram
Design Approaches
The truth table of 2n-bit comparator
2n
» 2 entries - too cumbersome for large n
Use inherent regularity of the problem
» Reduce design efforts
» Reduce human errors
Digital Systems 14
Digital Systems 15
Four-bit magnitude comparator
Digital Systems 16