Registers

Lecture 21
 Princess Sumaya University 4241 – Digital Logic Design Computer Engineering Dept.

Registers

 Group of D Flip-Flops I0 D Q A0

 Synchronized (Single Clock) R

 Store Data I1 D Q A1

I2 D Q A2

I3 D Q A3
CLK
R
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Reset
 Princess Sumaya University 4241 – Digital Logic Design Computer Engineering Dept.

Registers
I0 D Q A0
CLK
I3 R
I2 I1 D Q A1
I1
R
I0
A3 I2 D Q A2
A2 R
A1
I3 D Q A3
A0
CLK
Note: New data has to go in R
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with every clock Reset
 Princess Sumaya University 4241 – Digital Logic Design Computer Engineering Dept.

Registers with Parallel Load

 Control Loading the Register with New Data

D7 Q7
R Q6
D6
E Q5
D5
G Q4 LD Q(t+1)
D4
I Q3 0 Q(t)
D3
S Q2 1 D
D2
T Q1
D1
E Q0
D0
R
LD

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 Princess Sumaya University 4241 – Digital Logic Design Computer Engineering Dept.

Registers with Parallel Load

 Should we block the “Clock” to keep the “Data”?

D7 Q7
R Q6 I0 D Q A0
D6
E Q5
D5
G Q4
D4 I1 D Q A
I Q3
D3 1
S Q2
D2
T Q1 I2 D Q A
D1
E Q0
D0 Delays 2
R the Clock
LD I3 D Q A
3
Load
CLK 5 / 28
 Princess Sumaya University 4241 – Digital Logic Design Computer Engineering Dept.

Gating Clock
skew problem!
In a synchronous circuit clock skew (TSkew) is the
difference in the arrival time between two
sequentially-adjacent registers or flip flops.

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 Princess Sumaya University 4241 – Digital Logic Design Computer Engineering Dept.

Alternative

 If load H (1), then D is

gated through
 Otherwise, Q is fed back
 Keep same value

 No clock gating

 We did this because D FF doesn’t have

“no change” behavior
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 Princess Sumaya University 4241 – Digital Logic Design Computer Engineering Dept.

1- Registers with Parallel Load

 Circulate the “old data”

I0
MUX
Y D Q A0
I0 I1 S

I0
MUX
Y D Q A
I1 I1 S 1

I0
MUX
Y D Q A
I2 I1 S 2

I0
MUX
Y D Q A
I3 I1 S 3
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Load CLK
 Princess Sumaya University 4241 – Digital Logic Design Computer Engineering Dept.

2- Shift Registers

 4-Bit Shift Register

Serial SI SO
D Q D Q D Q D Q
Input Serial
Output

CLK

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 Princess Sumaya University 4241 – Digital Logic Design Computer Engineering Dept.

2- Shift Registers
Q3 Q2 Q1 Q0
SI D Q D Q D Q D Q SO

CLK

CLK
SI
Q3
Q2
Q1
Q0 10 / 28
 Princess Sumaya University 4241 – Digital Logic Design Computer Engineering Dept.

Symbol

 Again, we could gate the clock

 But have to potentially deal with skew

Fall 2005 ENG241/Digital Design

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 Princess Sumaya University 4241 – Digital Logic Design Computer Engineering Dept.

Serial Transfer
 Example

Could shift
data in

What’s on wire at each clock?

Clocked 4 times
Fall 2005 ENG241/Digital Design
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 Princess Sumaya University 4241 – Digital Logic Design Computer Engineering Dept.

Table Showing Shift

 Example

Fall 2005 ENG241/Digital Design

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Another Example

14 EC 381 Digital Systems Fall 2013

 Princess Sumaya University 4241 – Digital Logic Design Computer Engineering Dept.

Serial Addition

Shift SI
Control Shift Register A
x
S
yFA
C
z
CLK Shift Register B

Q D

CLR
Clear

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 Serial Addition Then shift through
adder into A. Added
to 0 if A is empty.

Initially reset all

registers

Register A
accumulates

Adds one bit at a time

At same time, new

value going into B

Shift value in serially Stores carry one clock

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3- Bidirectional Shift Register
 Shift either way

17 ENG241/Digital Design Fall 2005

4- Universal Shift Registers
 4-bit register capable of multiple operations
 (use multiplexers instead of AND/OR gates at FF
inputs)

18 EC 381 Digital Systems Fall 2013

19 EC 381 Digital Systems Fall 2013
Hardware Comparison
 Serial vs. parallel adder
 One full adder vs. n adders
 Serial takes n units of time, parallel only one

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Parallel Load
 Can provide parallel outputs from flip-flops
 And also parallel inputs

21 ENG241/Digital Design Fall 2005

Shift Registers
 Capability to shift bits
 In one or both directions
 Why?
 Part of standard CPU instruction set
 Cheap multiplication
 Serial communications

22 ENG241/Digital Design Fall 2005