Introduction to

Phase Locked Loop

(PLL)
DIGITAVID, Inc.
Ahmed Abu-Hajar, Ph.D.
abuhajar@digitavid.net
Presentation Outline

What is Phase Locked Loop (PLL)

Basic PLL System

Problem of Lock Acquisition

Phase/Frequency Detector (PFD)

Charge Pump PLL

Application of PLL
What is Phase Locked Loop (PLL)

PLL is an Electronic Module (Circuit) that

locks the phase of the output to the input.

Vi(t) Phase Locked Vo(t)

Loop
Locked Vs. Unlocked Phase

Example of locked phase

Vi(t)

Vo(t)

Example of unlocked phase

Vo(t)

Vi(t)

Phase Error
( ∆φ)
Basic PLL System

PLL is a feedback system that detects the phase error ∆φ
and then adjusts the phase of the output.
Vi(t) Phase Locked Vo(t)
Loop

VI
Phase ∆φ Vo
VCO
Detector

The Phase Detector (PD), detects ∆φ between the output

and the input through feedback system

Voltage Control Oscillator (VCO) adjusts the phase
difference
Implementation of PD

Phase Detector is an XOR gate

VI
V1 Phase ∆φ Vo
∆φ VCO
Vo Detector

 1 VI ≠ Vo
∆ϕ = 
 0 VI = Vo
Vo(t)

Vi(t)

Phase Error
( ∆φ)
What is VCO ?

VCO is a circuit module that oscillates at a

controlled frequency ω.

The Oscillating Frequency is controlled using
Voltage VControl.
ω
– That is why the module is called

Voltage Control Oscillator ω0

VControl
VControl ω
VCO
ω = ωo + KVCO VControl

Vcontrol must be in the steady state for the VCO to
operate properly
Simple PLL

Structure
– Phase Detector ( XOR ) that detects the phase error ∆φ
– Low Pass Filter ( to smooth ∆φ )
– Voltage Control Oscillator (VCO)

Basic Idea
– If VI and Vout are out of phase (unlocked), then the PD module
detects the error and the LPF smoothes the error signal. The
control signal slows down or speeds up the VCO module; hence,
the phase is corrected (locked)
VI
Phase ∆φ VControl Vout
LPF VCO
Vout Detector
∆φ
Locked Condition

– Locked Condition
d
(ϕin − ϕout ) = 0
dt
– This implies that
ωin = ωout
VI
Phase ∆φ VControl Vout
LPF VCO
Vout Detector
∆φ
Example: In the UNLOCKED State

VI and Vout has ∆φ at the same Vi(t)

frequency ω1

The phase detector must Vo(t)
Phase Error
produce VI
( ∆φ)

Hence, VCO is dynamically
changing and PD is creating VControl
VControl to adjust for the phase
difference. ω VControl
ω1 V1

The PLL is in the Locked state
ω0
φ0
V1 VControl
In the UNLOCKED State

For Simplicity and by using Fourier Series

Let VI = VA cos (ω1t ) Vout = VB cos (ω1t + ϕo )

Due to ∆φ, PD creates Vcontrol

VCO will change

ωout = ω1 + KVCO VControl

The output voltage becomes
Vout = VB cos (ω1t + ϕo − ∆ϕ (t ) )
Dynamics of Simple PLL

PLL is a feedback system
– PD is a gain amplifier
– LPF be first order filter ( as an example)
– VCO is a unit step module

The transfer function of the feedback system is given as:

Φ out ωout ωn2 K PD KVCOωLPF

H ( s) = ( s) = ( s) = 2 H ( s) =
Φ in ωin s + 2ςωn s + ωn2 s 2 + ωLPF s + K PD KVCOωLPF

LPF
PD VCO
1
φin KVCO φout
KPD s
1+ s
ωLPF
Transient Response to PLL

The unit step response to second order system
– Overdamped
– Critically damped ωi
– Underdamped

Problems with this PLL
– Settling time Vs. ripple of Vcontor t
ωout
– Stability of the system
– Lacks performance in ICs
Φ out ωout ωn2
H ( s) = ( s) = ( s) = 2
Φ in ωin LPF s + 2ςωn s + ωn2
PD VCO
1 t
φin KVCO φout
KPD s
1+ s
ωLPF
Problem of Lock Acquisition

When PLL is turned on, the output frequency is far from
the input frequency

It is possible that the PLL would never lock

Modern PLL uses FREQUENCY DEDECTOR (FD) in
addition to the PD.

PD
LPF1

Vin Vout
ωin VCO
ωout
FD
LPF2
Phase/Frequency Detector (PFD)

One Module that detects both frequency and phase differences

This module senses the transition in A or B
A B QA QB
Initially 0 0 0 0 A PFD QA
A leads B 01 00 01 00
XX 01 10 00 B QB
A B QA QB
Initially 0 0 0 0
B leads A 00 0 1 00 0 1
0
1 XX 00 0 0

If A leads B, QA changes its state and QB remains unchanged

If B leads A, QB changes its state and QA remains unchanged

A A
B B
QB QB
QA QA
Hardware Implementation of PFD

Uses two Edge Triggering modules
using D-FF VDD

If A leads to “1” QA = “1” D QA

– When B becomes “1”, QB = “1” Q
momentarily A CK
– The AND gate RESETs Both to Qs “0”
VDD

D

If B leads to “1” QB = “1” Q
– When A becomes “1”, QA = “1” B CK QB
momentarily
– The AND gate RESETs Both to Qs “0”
Hardware Implementation of PFD
VDD

A
D QA
B
Q
QB A CK

QA VDD RES
RES
D
Q
A B QB
CK
B

QB
The Vout is the average of (QA – QB)
is used to detect the phase and the
QA frequency difference
RES
The Basic Block diagram

Structure VDD
– PFD
– LPF D
QA
– Differential Vin Q
Amplifier φin
CK
– VCO ωin

– Negative Feedback V
DD VCO

Disadvantage:
Sensitive to noise D
and offset voltages,
Q
ripple Vcontrol, .. Vout
CK QB

Use Charge Pump φout
PLL ωout
Charge Pump PLL

Structure VDD

– PFD
VDD
– Two switches
controlled by QA
and QB D
QA
– Capacitor Vin Q
φin
d VC ωin
CK
IC = C
dt
VDD VCO
d VC I
= C
dt C D
– VCO Q
– Negative Feedback Vout QB
CK
φout
– It charges or ωout
discharges the
capacitor
indefinitely
 Charge Pump PLL
VDD

The capacitor is replaced
with a LPF (Cp and Rp) to VDD
improve the phase margin
for stability

The transfer function of the D
QA
system is approximated as Vin Q
follows: φin
CK
ωin
I P KVCO
( RPCP s + 1) VDD VCO
2π CP CP
H (s) =
I I K D
s 2 + P KVCO RP s + P VCO KVCO Q RP
2π 2π CP Vout
CK QB
φout
ωout

Rp slows down the system
Application of PLL

Frequency Multiplications
– The feedback loop has frequency division
– Frequency division is implemented using a counter

VI
PFD ∆φ VControl Vout
LPF VCO
∆φ
Counter
(Frequency
Division)
Clock Skew Reduction
Buffers are used to distribute
the clock
Embed the buffer within the loop
Application of PLL

Clock Skew Reduction

– Buffers are used to distribute the clock
– Embed the buffer within the loop
VI
Buffer
PFD ∆φ VControl Vout
LPF VCO
Vout
∆φ

Jitter Reduction