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“Enabling Semiconductor Innovation and Growth”

EUV lithography drives Moore’s law well into the next decade

BAML 2018 APAC TMT Conference

Taipei, Taiwan
Craig De Young
Vice President IR - Asia IR
March 14, 2018
Public
Forward looking statements Public
Slide 2
January 17, 2018
This document contains statements relating to certain projections, business trends and other matters that are forward-looking, including statements with respect to
expected trends and outlook, including expected trends in the semiconductor market, expected annual operating profit, systems backlog, statements with respect to
expected revenue growth in the semiconductor market, including expected forecast growth by market, the expected relative semiconductor content in automotive
innovations by 2030, expected growth drivers in lithography demand in 2020, statements with respect to industry shrink roadmaps, EUV insertion plans and customer
roadmaps, statements with respect to the expected continuation of scaling and transistor density by 2030, expectations with respect to EUV, including expected benefits,
including lithography cost reduction and the expected benefits of High NA, target performance, EUV industrialization, including availability and throughput, shipments and
the expectation that the installed base of EUV systems will double in 2018, the expected innovation pipeline in the next 10 years and beyond, the expected increased
impact of new scalable memory types in the next 10 years and the expectation that such types will continue driving lithography, statements with respect to shrink being a
key driver supporting innovation and providing long-term industry growth, lithography enabling affordable shrink and delivering value to customers, and statements with
respect to the expected continuation of Moore's law and that EUV and scaling and shrinking will continue to support and enable Moore’s law and drive long term value for
ASML beyond the next decade. You can generally identify these statements by the use of words like "may", "will", "could", "should", "project", "believe", "anticipate",
"expect", "plan", "estimate", "forecast", "potential", "intend", "continue", "targets", "commits to secure" and variations of these words or comparable words.

These statements are not historical facts, but rather are based on current expectations, estimates, assumptions and projections about the business and our future financial
results and readers should not place undue reliance on them. Forward-looking statements do not guarantee future performance and involve risks and uncertainties. These
risks and uncertainties include, without limitation, economic conditions, product demand and semiconductor equipment industry capacity, worldwide demand and
manufacturing capacity utilization for semiconductors, including the impact of general economic conditions on consumer confidence and demand for our customers'
products, competitive products and pricing, the impact of any manufacturing efficiencies and capacity constraints, performance of our systems, the continuing success of
technology advances and the related pace of new product development and customer acceptance of new products including EUV, the number and timing of EUV systems
expected to be shipped and recognized in revenue, delays in EUV systems production and development and volume production by customers, including meeting
development requirements for volume production, demand for EUV systems being sufficient to result in utilization of EUV facilities in which ASML has made significant
investments, our ability to enforce patents and protect intellectual property rights, the outcome of intellectual property litigation, availability of raw materials, critical
manufacturing equipment and qualified employees, trade environment, changes in exchange rates, changes in tax rates, available cash and liquidity, our ability to refinance
our indebtedness, distributable reserves for dividend payments and share repurchases, results of the new share repurchase plan and other risks indicated in the risk factors
included in ASML's Annual Report on Form 20-F and other filings with the US Securities and Exchange Commission. These forward-looking statements are made only as of
the date of this document. We do not undertake to update or revise the forward-looking statements, whether as a result of new information, future events or otherwise.

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Semiconductor Scaling has changed how we…
Slide 3

LIVE WORK PLAY

Transistor density
Millions per mm2

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Insatiable need to transfer, store and analyse data
drives a continuous and growing demand for semiconductors Slide 4

Consumer
Electronics Smartphones

PC, laptop,
tablets

Factory
Automation

Autonomous driving

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 Scaling/Shrinking Supports Moore’s Law
Moore’s Law is underpinning a business model Slide 5

IC performance
1 improvement at
similar cost
Takeaways
Part of the profits are
reinvested in R&D,
equipment >$250+ billion of annual
operating profit is riding on
4 2
the industry’s ability to
Improved electronic keep this cycle going
devices and new
applications

>$250+ billion of
operating profit
per year
Consumers and businesses 3
upgrade or adopt new products
Public
ASML operates in a highly profitable value chain
with strong incentives to compete and drive innovation Slide 6

ASML
ASML Applied Materials LAM Research KLA-Tencor TEL
Peers
2 2 1 1 1 Semi Equipment
Semi
Semi Manufacturing
Non-Semi

NVIDIA
13 12 25 6 5 2 3 11 Semi Design

There remains a lot of

income generated

TE Connect

Canon
Murata
Total EBIT, B$

60 2 Hardware
13 5 8 2 2 4 ~290
~275 ~280
~250

Cognizant

NetEase
Yahoo
Baidu
eBay

ADP
®
2013 14 15 2016
/ Alphabet

24 20 13 12 6 7 4 2 2 2 2 22 Software & Services

Top technology companies in our ecosystem (EBIT CY2016, B$)

Source: Bloomberg (GICS 45 classification) Public
Leading edge Logic and Memory processes drive
growth in semiconductor markets Slide 7

Revenue growth is coming from those segments where roadmap Lately we’ve seen the following trends in
innovation continues: advanced logic, DRAM and NAND (non-
volatile memory) semiconductor markets:
WW Semiconductor revenue [B$] • Strong transition to 3D-NAND to
450 continue enabling large capacities at
lower cost
WW semiconductor Revenue [B$]

400 CAGR
3D NAND
5%
• Slowing DRAM roadmap leading to
350
2D NAND DRAM CAGR
lower bit growth resulting in price
300 14% increases, triggering capacity
250
investments
Logic ≤20 nm

200 • Increasing focus on new memory

CAGR
devices (i.e. x-Point)
150 Logic > 20 nm -2%
• Continuing strong drive for logic
100
shrink with process improvements
50 Legacy
coming on an annual cadence
0
2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021

Source: ASML analysis, Gartner Public

Semiconductors drive 80% of automotive innovations
Expected to represent 50% of the cost of goods in 2030 (per Audi) Slide 8

Relative Semiconductor
content in automotive [%COG]

100
90
80
70
60
50
40
30
20
10
0
1991 2015 2020 2030

Source: Berthold Hellenhtal, Audi, “Cross industry collaboration networks accelerate innovations”, ISS Europe, Munich, March 2017 Public
Disruptive trends also drive litho demand
Growth drivers: 2017 to 2020+ Slide 9

Storage Class Memory Growth and China Greenfield Emerging connected devices

CHINA
NAND

transition to 3D NAND Investments market (IoT)

IoT
Data volume
& complexity

Sensors &
Devices

Internet of Things will connect a growing number of

You Images &
are Media devices from 12 billion in 2012 to 50 billion in 2020
here

Text
IoT devices shipments, B units

Enterprise
Chinese government +65% p.a.
2010 2020 supports massive 0.4
0.3
Source: John Kelly III, IBM, December 2015 investment into domestic 0.2
0.2
semi industry 0
0.1

2015 16 17 18 19 2020

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Scaling will continue towards 1 billion transistors per mm2
We are ready to support the Semi industry’s ambition through the extension Slide 10

of Moore’s Law

High-NA
Transistor density

EUV
Millions per mm2

EUV
(+ pattern fidelity control)

Multi-patterning
(+ source-mask optimization, control loops)

Immersion
(+ optical proximity correction)

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EUV – A New Technology in Lithography Slide 11

• New technology transitions: customer perspective

• EUV progress & plans
• EUV infrastructure
• EUV extendibility

~4 m

~3 m ~8 m
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What is EUV? A litho technology that delivers 3x -> 5x
Resolution Enhancement Slide 12

l ArF immersion EUV

Resolution = k1 x
NA
k1 = 0.265 k1 = 0.32
k1 difficulty, limit = 0.25 strong OPC mask OPC mask

l Wavelength 193nm 13.5nm

NA 1.35 NA 0.33 NA > 0.5

NA Maximum Current Future
Numerical Aperture

Resolution 76nm 26nm < 16nm

Minimum pitch 38nm half pitch 13nm half pitch < 8nm half pitch Public
Dilemmas when adopting a game-changing technology
Early decision making Slide 13

It does not
It works
work

We have it
☺ 
We do not
have it ?? 

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How customers approach new technology insertions
Slide 14

• Visionary/champion
• R&D enthusiasm EUV Case
• First results Done

• Business manager “Shouldn’t we go for this?” To be addressed

• Manufacturing push back To be considered
• Tough criteria, entrance hurdles
• Dynamics: progress vs. milestones
• Product roadmap timing
• Business decision with up/down ticks
• Different risk appetite per customer and per segment

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Technology transitions: decisions based on early results
“You have to move to where the puck will be, not where it is” (Wayne Gretzky) Slide 15

Decision point

Desired performance
at the time of volume
ramp

Performance
Increasing complexity
introduces additional
risk - lengthening
leadtimes

Time
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General rule of New Technology adoption
Slide 16

Early adoption is
risky

Late adoption is
expensive
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EUV “rewards” at 7nm are clear: simpler process,
shorter cycle time enabling faster yield ramp and time to Public
Slide 17
Jan 2018

market
Typical # Litho Passes Modelled 7nm Cycle Time, weeks
90 0 1 2 3 4 5 6 7 8 9 10 11 12 13

85
-13% ArFi
80 -21% only
-19%
75
EUV
70 Low
65 -33%

60 EUV
High Dr. Gary Patton, Global Foundries
0 SEMI ISS 2017
14/16nm 10nm 7nm

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 EUV introduction delivers compelling benefits in layout
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flexibility and process simplification Slide 18

Jan 2018

2D EUV patterning EUV process simplification

• More layout flexibility for designers • Superior device performance
• Simpler process integration for engineers • Improved device variability

Esin Terzioglu, Qualcomm, International Symposium on EUV, October, 2014 Jeffrey Shearer et al, IBM, AVS, November 2014

Resulting in more effective shrink + higher yields

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 EUV alternatives are very costly and complex
Slide 19

Immersion Multiple Patterning EUV

Process Steps
CMP
60 Dry Etch
60 Metrology
# Process steps for 1 patterning step

Lithography
50 Track
Deposition
40 Clean
34 Hard mask
30 27
LE3 = 3x Litho-Etch, “Triple patterning”
20
LE4 = 4x Litho-Etch, “Quad patterning”
10
10 SAQP = Spacer Assisted Quad Patterning
Cut = Separate Litho-Etch step
0
LE3 LE4 SAQP Single
+ 3 cuts exposure Public
EUV enables continued Litho cost reduction
PAS 5500/60 Slide 20
PAS 2500/10

1
Res. 450nm XT:1400
Res. 900nm, 200mm 48wph
150mm 66wph
Relative Cost per Pixel

Resolution 65nm NXE:3400

0.1
300mm 145wph

AT:850

Res. 13nm
300mm 125wph
0.01 NXT:1950i
Res. 110nm
300mm 102wph

Res 38nm,
300mm 190wph
0.001
1984 1987 1990 1993 1996 1999 2002 2005 2008 2011 2014 2017 TBD
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 Slide 21

So where are we now?

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EUV industrialisation: from technology demonstration to
HVM System 2006 2017
Slide 22

Resolution : 40 nm 3x 13 nm
Overlay : 15 nm 10x 1.5 nm
Throughput : 0.05 WPH 2,500x 125 WPH
Public
 Significant progress in EUV industrialisation Slide 23

EUV Source & Throughput EUV Availability Cumulative EUV wafer exposures
Proven Power1 & Wafers/Hour2 Uptime % NXE:3xxx, Wafers

100% >2M
Source Power
Throughput, W/Hr ✓ 300W
250W3

1.1M

✓ 155W/Hr
125 W/Hr 0.6M

Uptime 0.3M
Planned upgrades

0%
2014 2015 2016 2017 2020 2016 2017 2018 2011 2012 2013 2014 2015 2016 2017
Target

1 Demonstrated on test rig, 2 Demonstrated at ASML or Customer, 3 Enables 145W/Hr on NXE:3400B Public
Evolution of EUV Infrastructure readiness
Slide 24

EUV Infrastructure 11/14 10/15 11/15 10/16 02/17

E-beam mask
inspection
AIMS Mask
Inspection
Actinic Blank
Inspection
From 2016 EUVL
EUV
Symposium

Pellicle
EUV Blank
Quality
Blank multi-layer
deposition tool
EUV Resist QC

Actinic Patterned
Mask Inspection

Source: Britt Turkot, Intel, International Workshop on EUV Lithography, California, June 2017.
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Industry shrink roadmap and EUV insertion plans
Slide 25
EUV in Production

HVM 2014 2015 2016 2017 2018 2019 2020 2021 2022
Logic

20 nm 16-14 nm 10 nm 7 nm 5 nm 3 nm Node name

Performance
Memory

DRAM

28-30 20-22 1X 1Y 1Z next Minimum half pitch

PC-RAM, ReRAM etc.

Memory
Storage

Minimum half pitch

Class

2X’/x2 1X”/x4 1Y”/x8 1Z”/x8 /x number of layers

Today’s status
Planar Floating Gate NAND Production1
Development1
22 17-18 14-15
Memory
Storage

Research1
Roadmap2
3D NAND
x24 x32 x48 x64 >x96 >x128 >x192 >x200 x number of layers

Source: 1) Customers - public statements,, IC Knowledge LLC; 2) ASML extrapolations Public

...which is supported by Customer shipments and orders
Installed Base of EUV systems expected to double in 2018 Slide 26

NXE:33x0 and NXE:3400

Shipments and Installed Base

R&D HVM ramp

Installed Base
Planned
Shipments 30+

22 22

12 End Q4 ‘17 order backlog: 28

9 10 systems from 6 Customers
7
3 4 3
2

’13 ’14 ’15 ’16 ’17 ’18 ’19 ’20

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And by recent customer statements on EUV insertion
Slide 27

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 Slide 28

What’s next?

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Customer roadmaps extend 10 years
Slide 29

1000

1 nm
2 nm
Transitor Density MTr / mm2

3 nm

100 5 nm
7 nm

10 nm

14/16 nm Density extrapolated,

20 nm
timing based on customer
28 nm reviews 2017
10 28/32 nm

45/40 nm

1
2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024 2025 2026 2027
HVM Wafer Start Date
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 High NA extends EUV with a larger resolution step than
immersion did for ArF Slide 31

1,000
Wavelength, nm
436, g-line
365, i-line
NXE:3400
248, KrF
193, ArF
45%
100 XT:1400
= k1 x Wavelength / NA
Resolution, nm

EUV 13.5 nm >10x

13nm, 0.33 NA

ArF 193nm NXT:1950i

65nm, 0.93 NA 67%
13.5, EUV
10 g-line ArF Timing TBD
i-line Immersion
ArFi 193nm High NA EUV
KrF EUV 38nm, 1.35 NA
Development systems
xx% Increase in NA
1 EUV, 13.5nm
<8nm, >0.5 NA
1985 1990 1995 2000 2005 2010 2015 2020 2025
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High NA EUV extends cost per pixel reduction
PAS 5500/60 Slide 31
PAS 2500/10

1.000
Res. 450nm XT:1400
Res. 900nm, 200mm 48wph
150mm 66wph
Relative Cost per Pixel

0.100 Resolution 65nm NXE:3400

300mm 145wph

AT:850 High NA EUV

Res. 13nm
0.010 300mm 125wph
NXT:1950i
Res. 110nm Res. <8nm
300mm 102wph 300mm 185wph

0.001 Res 38nm,

300mm 190wph

1984 1987 1990 1993 1996 1999 2002 2005 2008 2011 2014 2017 2020 TBD
2023
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EUV shrink + Holistic Litho (addressing k1) keeps Moore’s
Law affordable Slide 32

Exposure with
high order
optimisation

Optical
Computational
& e-beam
Lithography
Ensure measurement captures a Metrology
maximum of relevant information

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Our innovation pipeline will enable advanced imaging
and imaging process control the next 10 years and Slide 33

beyond

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EUV Summary
Slide 34

 Customers are targeting EUV introduction at 7nm to take advantage

7nm of process complexity, cycle time, IC shrink, yield, & performance
benefits

 Key EUV industrialisation & performance milestones have been

achieved in 2017, together with solid progress in EUV mask and
resist infrastructure

 EUV introduction enables a return to Litho enabled cost reduction

with the opportunity to extend multiple generations

 ASML is investing in a roadmap to enable continued Holistic

Lithography scaling for the coming decade
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What this means for ASML – As IC units grow and Litho
Intensity grows…….. ASML grows! Slide 35

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Summary - Our customers and their environment
Slide 36

• Strong incentives for the entire industry to continue IC

performance and cost improvements, now also driving system
innovations
• Our logic customers have roadmaps that extend to 2027 and
are not planning to slow down scaling
• Memory market is growing and performance improvements
continue, enabled by 3D stacking and new scalable memory
types. The latter will have an increasing impact the coming 10
years and continue to drive lithography

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Public