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# LAB MANUAL

2017-2018

INDEX

1 RTU SYLLABUS 5

## 3. INTRODUCTION THEORY OF LAB 11

4 MATLAB INTRODUCTION 12

5 LIST OF EXPERIMENTS

## PROG:- 1. OBJECTIVE: Plotting of various elementary signals 18

like impulse function, unit step function, ramp function,
quadratic function, general sinusoidal function.

## PROG:- 3. OBJECTIVE:Derive the Impulse response of a given 26

system..
PROG:- OBJECTIVE: Perform linear convolution of two given 29
4(a). sequences.

## PROG:- OBJECTIVE: Perform Circular convolution of two 31

4(b). given sequences.

## PROG:- 5. OBJECTIVE: . To study the design and 33

implementation of FIR filter to meet given specifications

## PROG:- 6. OBJECTIVE: To study the design and implementation 40

of IIR(LPF/HPF) filter to meet given specifications.

## PROG:- 7. OBJECTIVE: Realizing a given block diagram having 44

multiplier, adder/subtractor and system with given
Impulse response. Calculating output for given input.

for BPSK.

## PROG:- 9 OBJECTIVE:ToStudy the basic information of 54

architecture of TM3320C6XXD DSP kit using BLOOM
using DSP. Study architecture of TMS320C6XXD DSP
kit.
PROG:- OBJECTIVE: To perform linear convolution using DSP 76
10(a). processor.

## PROG:- OBJECTIVE: To implement circular convolution of 88

10(b). two sequences using DSP processor.

## PROG:- 1. OBJECTIVE: Plotting of various elementary signals 103

like impulse function, unit step function, ramp function,
quadratic function, and general sinusoidal function.

## PROG:- 3. OBJECTIVE:Derive the Impulse response of a given 107

system..
PROG:- OBJECTIVE: Perform linear convolution of two given 109
4(a). sequences.

## PROG:- OBJECTIVE: Perform Circular convolution of two

4(b). given sequences.

## PROG:- 5. OBJECTIVE: . To study the design and 111

implementation of FIR filter to meet given specifications

## PROG:- 6. OBJECTIVE: To study the design and implementation 112

of IIR(LPF/HPF) filter to meet given specifications.

## PROG:- 7. OBJECTIVE: Realizing a given block diagram having 114

multiplier, adder/subtractor and system with given
Impulse response. Calculating output for given input.

for BPSK.

## AIETM/CSE/FPGA LAB Page 3

PROG:- 9 OBJECTIVE: ToStudy the basic information of 119
architecture of TM3320C6XXD DSP kit using BLOOM
using DSP. Study architecture of TMS320C6XXD DSP
kit.
PROG:- OBJECTIVE: To perform linear convolution using DSP 121
10(a). processor.

## PROG:- OBJECTIVE: To implement circular convolution of

10(b). two sequences using DSP processor.

Syllabus

## Fundamental TheoryIntroduction to DSP architectures and programming.

Sampling Theory, Analog-to-Digital Converter (ADC), Digital-to-Analog
1. Converter (DAC), and Quantization; Decimation, Interpolation, Convolution,
Simple Moving Average;Periodic Signals and harmonics;Fourier Transform
(DFT/FFT), Spectral Analysis, and time/spectrumrepresentations; FIR and IIR
Filters;
Design (Simulation) using MATLAB/ SimulinkSimulate the lab exercises
2.

Implementation using pure DSP, pure FPGA and Hybrid DSP/FPGA platforms
Digital Communications: On-Off- Keying (OOK), BPSK modulation,and a
3. simple transceiver designWireless Communications: Channel coding/decoding,
Equalization,Simple Detection Algorithm, OFDM.Speech Classification and
Synthesis

## AIETM/CSE/FPGA LAB Page 5

PROGRAM EDUCATIONAL OBJECTIVES

## Sessional/Mid-term marks: 60 Practical Hrs : 3hrs/week

End-term Marks: 40
Total Marks: 100

1. PROGRAM OBJECTIVES:-
i. Preparation:- To prepare to pursue advanced graduate studies in computing or related
disciplines and provide students broad-based education in core areas of Computer Science,
including theoretical foundations, algorithms and data structures, and computer hardware,
with an appropriate blend of theory and practice and to specialize in a variety of areas of
Computer Science through a selection of elective courses.
ii. Core Competence:-To provide students with a solid foundation in computer engineering
field required to solve computing problems using various programming languages and
softwares, and students can solve problems through logical and analytical thinking.
iii. Breathe:-To train students with good computer and engineering breadth so as to
comprehend, analyze, design, and create novel products and solutions for the real life.
iv. Professionalism:-To inculcate in students professional and ethical attitude, effective
communication skills, teamwork skills, multidisciplinary approach, and an ability to relate
computer engineering issues to broader social context.
v. Learning Environment:-To provide students with an academic environment aware of
excellence leadership and lifelong learning needed for successful professional career
through independent studies, thesis, internships etc.

2. PROGRAM OUTCOMES:-
a) Graduates will demonstrate knowledge of mathematics, science & Computer Engineering
and will develop ability to apply fundamental principles of computing, mathematics and
sciences as appropriate to the discipline of computer science.
b) Graduates will demonstrate an ability to identify formulate and solve Computer Engineering
problems and analyze a problem and model it as a computing system using appropriate
methodologies.
c) Graduates will demonstrate an ability to design and conduct experiments, analyze and
interpret data.
d) Graduates will develop ability to design a system, component or process implement and test
a computer application and to evaluate and compare the efficiencies of alternative solutions
as per the needs and specifications.
e) Graduates will develop an ability to visualize and work on laboratory and multidisciplinary
class.

## AIETM/CSE/FPGA LAB Page 6

f) Graduates will demonstrate skills to use modern engineering tools software’s and
equipment’s to analyze problems.
g) Graduates will demonstrate knowledge of professional and ethical responsibilities.
h) Graduates will able to communicate effectively in both verbal and written form.
i) Graduate will show the understanding of impact of Computer engineering solutions on the
society and also be aware of contemporary issues.
j) Graduate will develop confidence for self-education and ability for lifelong learning.
k) Graduate can participate and succeed in competitive examinations like GATE etc.

## 3) Course Educational Objective:-

After studying FPGA LABpracticalin their graduation plan student will be able to:
i. Apply the knowledge to manage and to handle various signal based applications like
extraction/modification of information in a signal, to solve the real world problems.
ii. Gain a repudiated designation as good signal processing manager and administrator
ethically by applying signal processing software technologies.
iii. Be successfully accepted in future’s development scenario as an engineering graduate
pursuit of lifelong learning.
iv. Exhibit team spirit management & effective signal processing dealings.
v. Can give better emerging computer based techniques and ideas to analyze design
implement industry based on FPGA module development.
vi. The FPGA experiments attempts to provide practical knowledge of applications in digital
signal processing using FPGA and DSP platforms used in real world for extracting
information from signals.
vii. It provides the convenient environment for the development of chips/modules used to
process signals in various electronic systems according to our requirements.

## 4) Course Outcomes (student learning outcomes):

Each student learning outcome (SLO) maps to one of the program education objective
(PEO) as indicates in parentheses following the outcomes.

## 1. Implementation and understanding of DSP and FPGA circuits/modules.

2. They are able to understand the difference among various DSP applications.
3. Implement proficiency in using and developing various DSP application softwares
according to market demand.
4. Can show their ability to apply conceptual skills in signal processing.

## AIETM/CSE/FPGA LAB Page 7

5. Graduates will show interest towards the development of different modern and efficient
tool (MATLAB and CCStudio 3.)
6. Graduates will able to know about the programming as well as block diagram
implementation of a DSP system using MATLAB and SIMULINK of a DSP system.
7. Implement different types of DSP applications and use of them.
8. By understanding it, graduate will be able to design and implement existing, as well as
innovative system designs in DSP.
9. They will introduce the concepts of using DSP processor kit and interfacing it with
computer software.
10. Student can developed competitive approach in the emerzing market of DSP Processors.

## 5) COURSE OBJECTIVES CONTRIBUTION TO PROGRAM OUTCOMES:-

Students who have successfully completed this course will have full understanding of following
concepts:-

## COURSE OBJECTIVE PROGRAM OUTCOME

i. Apply the knowledge to
manage and to handle various 1. Graduates will demonstrate an ability to identify
signal based applications like formulate and solve Computer Engineering
extraction/ modification of problems and analyze a problem and model it as
information in a signal, to a computing system using appropriate
solve the real world problems. methodologies.
2. Graduates will demonstrate an ability to design
and conduct experiments, analyze and interpret
ii. Gain a repudiated designation data.
as good signal processing 3. Graduates will develop ability to design a
manager and administrator system, component or process implement and
ethically by applying signal test a computer application and to evaluate and
processing software compare the efficiencies of alternative solutions
technologies. as per the needs and specifications.
iii. Be successfully accepted in 4. Graduate will show the understanding of impact
future’s development scenario of Computer engineering solutions on the
as an engineering graduate society and also be aware of contemporary
pursuit of lifelong learning. issues.
5. Graduate will develop confidence for self
education and ability for lifelong learning.
iv. Exhibit team spirit
management & effective

## AIETM/CSE/FPGA LAB Page 8

signal processing dealings.
v. Can give better emerging
computer based techniques
and ideas to analyze design
implement industry based on
FPGA module development
vi. The FPGA experiments
attempts to provide practical
knowledge of applications in
6. Graduates will demonstrate skills to use modern
digital signal processing using
engineering tools software and equipments to
FPGA and DSP platforms
analyze problems.
used in real world for
extracting information from
signals.

6. BOOKS:-
Text books:

## Digital signal processing by By S Salivahanan

Reference Books :

## Introduction to Simulink with Engineering Applications-Steven T. Karris

7. INSTRUCTIONAL METHODS:-

## I.Black board presentation

II.PowerPoint presentation
III.Multimedia like video lectures

## AIETM/CSE/FPGA LAB Page 9

7.2. Interactive Instruction:

II. Quiz

## 7.3 Indirect Instructions:

I. Problem solving

7.4Independent Instructions:

Assignments

8) LEARNING MATERIALS:-

## 1. Text/lecturer notes/ lecturer PPT

2 .Multimedia material (videos, text with animations)
3. Web Resources:-
 www.mathworks.com
 www.matlab.com
 www.dsplaboratory.com
 www.matrixlab.com

9) ASSESSMENT OF OUTCOMES:-
1. Sessional tests (two in each semester and assessment is done on the basis of average of
marks.
2. End term exam (Conducted by RTU, KOTA)
3. Surprise Quiz/ Tests.
4. Presentation by students.
5. Daily class room interaction.
6. Assignments.
7. Online Exam(Two exams in each semester)
10). OUTCOMES WILL BE ACHIEVED THROUGH FOLLOWING:-

## 1. Class room teaching (through chalk and board /PPT).

2. Discussion on case- studies.
3. Video lectures through NPTEL, MATHWORKS.

## AIETM/CSE/FPGA LAB Page 10

INTRODUCTION THEORY OF LAB

## 1. Always prefer M-files to write the programs in MAT-LAB.

2. Save the M-files with .m extension.
3. Do not save the file with the name which resembles to any predefined function in the
MATLAB.
4. Always refer to the MATLAB help while using any new function or in case of confusion.
5. Clear the command window while running any new program by giving the clear
command, because it generates confusion.
6. To see the diagrammatic result refer to the figure window of MATLAB.
7. In case of slow processing, don’t press the ‘run button’ or any other button again and
again. Give it some time to recover.
8. Save the programs on each turn and simultaneously prepare the file, it will save your time.
9. Never use numbers while saving the programs.

## AIETM/CSE/FPGA LAB Page 11

INTRODUCION TO MATLAB

MATLAB

## MATLAB stands for ‘MATRIX-LABORATORY’.

MATLAB is a high-level language and interactive environment that enables you to perform
computationally intensive tasks faster than with traditional programming languages such as C,
C++, and FORTRAN. MATLAB allows easy matrix manipulation, plotting of functions and
data, implementation of algorithms, creation of user interfaces and interfacing with programs in
other languages. MAT-LAB contains matrix which does not require any dimensions so it is very
easy to implement any program or any algorithmmin a few dozen of lines with a great accuracy
and with a great efficiency.

HISTORY OF MATLAB

MAT-LAB was invented in late 1970’s by ‘Cleve Moler’.he was the chair person of computer
science department at the university of New Mexico. He invented it to give the direct access to
linpak and eispak without learning fortranto his students. Very soon it becomes very popular in
other universities and in other communities. Jack Little an engineer exposed to it when Cleve
Moler made a visit to the Stanford University. Later on realizing his potential he joined with
Cleve Moler and Steve Bangertto rewroye the MAT-LAB in ‘C’which is known as ‘math works’
in 1984. These rewritten libraries are known as ‘jack-pack’.it was firstly used by control design
engineers. This is a high-level matrix/array language with control flow statements, functions,
data structures, input/output, and object-oriented programming features. It allows both
"programming in the small" to rapidly create quick and dirty throw-away programs, and
"programming in the large" to create large and complex programs. MATLAB has extensive
facilities for displaying vectors and matrices as graphs, as well as annotating and printing these
graphs. It includes high-level functions for two-dimensional and three-dimensional data
visualization, image processing, animation, and presentation graphics. It also includes low-level
functions that allow you to fully customize the appearance of graphics as well as to build
complete graphical user interfaces on your MATLAB applications. MATLAB has evolved over
a period of years with input from many users. In university environments, it is the standard
instructional tool for introductory and advanced courses in mathematics, engineering, and
science. In industry, MATLAB is the tool of choice for high-productivity research, development,
and analysis In MATLAB, a matrix is a rectangular array of numbers. Special meaning is
sometimes attached to 1-by-1 matrices, which are scalars, and to matrices with only one row or
column, which are vectors. MATLAB has other ways of storing both numeric and nonnumeric
data, but in the beginning, it is usually best to think of everything as a matrix. The operations in
MATLAB are designed to be as natural as possible. Where other programming languages work
with numbers one at a time, MATLAB allows you to work with entire matrices quickly and
AIETM/CSE/FPGA LAB Page 12
easily. A good example matrix, used throughout this book, appears in the Renaissance engraving
Melencolia I by the German artist and amateur mathematician Albrecht Dürer.

## How to get started

When the computer has started go through the following steps in the different menus
 Look for the Network Applications folder and double click on that
 Within this you will see a little icon for Matlab – double click on that
Within about 30 seconds Matlab will open.

Starting MATLAB

After logging into your account, you can enter MATLAB by double-clicking on the MATLAB
shortcut icon on your Windows desktop. When you start MATLAB, a special window called the
MATLAB desktop appears. The desktop is a window that contains other windows. The major
tools within or accessible from the desktop are:
 The Command Window
 The Command History
 The Workspace
 The Current Directory
 The Help Browser
 The Start button

Figure-1

## MAT-LAB has six members in its product family.

1. Technical computing –it includes the mathematical computation, data analysis, algorithm
development and vizualisation.
2. Control designing -it is a very good fascility provided in MAT-LAB.by using this fascility
we can design open loop and closed loop control systems, we can analyse these
systems by connecting different input signals to the input port of the system.
3. Signal processing -it is also related with model designing. It includes the analysis of different
signals, which are applied to the input ports of different systems.

## AIETM/CSE/FPGA LAB Page 14

4. Image processing -it includes the processing of images and videos, analysis, algorithm
development and system design.the tools for image processing in MAT-LAB
gives a great help to scientists, researchers, astronauts in the different disciplines
such as medical imaging, aerospace, material science.
5. Test and measurements - Test & Measurement solution provides a complete set of tools for
test, data analysis and modeling, and presentation-quality reports, all in a single
environment.
6. Modeling and simulation -this is a very good facsility provided in MAT-LAB.before
implementing any system in real time world, we can simulate it and can see its
response to the different inputs. According to its output we can decide its merits
and demerits. so before implementing the system in real world , we can improve
it with the help of simulation.

Simulink is software for modeling, simulating, and analyzing Dynamic systems. It supports
linear and nonlinear systems, modeled in continuous time, sampled time, or a hybrid of the two.
Systems can also be multirate, i.e., have different parts that are sampled or updated at different
rates. Simulink is a software package that enables you to model, simulate and analyze systems
whose output changes over time. Such systems are often referred to as dynamic systems.
Simulink helps you to explore the behavior of a wide range of real world dynamic systems
including electrical circuits, shock absorbers braking systems and many other electrical,
mechanical and thermodynamic systems. Simulating a dynamic system is a two step process.
First the user creates a block diagram using a simulink model editor that graphically depicts time
dependent mathematical relationship among the system’s input states and outputs. The user then
commands simulink to simulate the system represented by the model from a specified start time
to a specified stop time. Simulink enables you to pose a question about a system, model it, and
see what happens. With Simulink, you can easily build models from scratch, or take an existing
model and add to it. Thousands of engineers around the world use Simulink to model and solve
real problems in a variety of industries. Simulink turns your computer into a lab for modeling
and analyzing systems that simply wouldn't be possible or practical otherwise, whether the
behavior of an automotive clutch system, the flutter of an airplane wing, the dynamics of a
predator-prey model, or the effect of the monetary supply on the economy. Simulink provides
numerous demos that model a wide variety of such real-world phenomena.

Block-sets

Block-sets are specialized collection of simulink blocks built for solving particular problems. It
gives the block presentation of the various control systems. Signal processing block-sets is a tool
for digital signal processing algorithm simulation and code generation. All the blocks support
double and single floating point data types. Most blocks also support fixed point and integer data

## AIETM/CSE/FPGA LAB Page 15

types when you have simulink fixed point. You can interconnect signal processing block-sets
block to create sophisticated models capable of simulating operations such as speech and audio
processing, wireless digital communications, radar/sonar and medical electronics.

Simulink libraries are used to design the models. It contains the elements required to construct a
model of a system. It includes sources, sinks, mathematical operations, transfer function blocks,
feedback loops, various types of output devices and input signals.

## Figure 3 -Simulink Library Browser

Here in the above figure you can see the sources which are generally connected to the input port
of the system. The second element is sink which are connected to the output port of the system to
plot the response of the system. The various transfer functions can be written by using the
continuous and discrete facility. The math operation provides the mathematical expressions like
product and addition. To make a model in MAT-LAB first of all we have to open the simulink
AIETM/CSE/FPGA LAB Page 16
library browser. It gives the list of all the essential elements required to construct a model. When
we further open the listed elements they will give us the detailed members of the respected
families.

For example:-

 Sinks  scope

Bode plotter

## Figure-4- Simple block

In the above figure the input section contains the sine wave generator which is given to the
quantizer. The quantizer converts the continuous wave into the discrete levels. The output can be
seen in the scope.

TOOL-BOX

Control System Toolbox builds on the foundations of MATLAB to provide functions designed
for control engineering. Control System Toolbox is a collection of algorithms, written mostly as
M-files, that implements common control system design, analysis, and modeling techniques.
These are specialized collection of M-files built specifically for solving particular classes of
problems. For example:-

1. Filter design
2. Signal processing
3. Image processing
By using these M-files we can solve the problems related to the transfer function of the control
systems.

## AIETM/CSE/FPGA LAB Page 17

Program No-1
OBJECTIVE: Plotting of various elementary signals like impulse function, unit step function,
ramp function, quadratic function, sine wave,and a general sinusoidal function.
Software Required:- MATLAB Software.
Theory:

Here we attempt to plot some elementary functions using MATLAB commonly used in various
applications in DSP . these functions are discussed below-

Impulse function:

The Dirac delta can be loosely thought of as a function on the real line which is zero everywhere
except at the origin, where it is infinite-

## Unit Step Function:

Unit Step function u(t) is one for all positive values, and zero for negative values of input.

## u(t) useful for representing the opening or closing of switches

Figure-step function

Ramp function:

## AIETM/CSE/FPGA LAB Page 18

In Ramp function, input is equal to output for positive values, and zero elsewhere.

Figure-Ramp function

y  t2

Sine wave:

y  sin(t )

## AIETM/CSE/FPGA LAB Page 19

Figure-Sine function

Sinusoidal function:

## It is a sinusoidal function having two or more frequencies.

y  sin(t1)  sin(t 2)

## Figure-1.a.6 – Sinusoidal function

PROGRAM:

clear all;

close all;

clc;

t = (0:pi:100);

y = sin(2*pi*100*t);

y1 = sin(2*pi*10*t) + 2*sin(2*pi*50*t);

## imp= [1; zeros(99,1)];

unit_step = ones(100,1);

ramp_sig= t;

subplot(3,2,1),stem(imp);

## AIETM/CSE/FPGA LAB Page 20

title('Impulse Function');

xlabel('time');

ylabel('Amplitude');

axis([-10 10 0 1])

subplot(3,2,2),stem(unit_step);

## title('Unit step Function');

xlabel('time');

ylabel('Amplitude');

axis([-10 10 0 1]);

subplot(3,2,3),plot(t,ramp_sig);

title('Ramp Function');

xlabel('time');

ylabel('Amplitude');

xlabel('time');

ylabel('Amplitude');

subplot(3,2,5),plot(t,y);

title('Sinusoidal function');

xlabel('time');

ylabel('Amplitude');

subplot(3,2,6),plot(t,y1);

title('y1');

xlabel('time');

## AIETM/CSE/FPGA LAB Page 21

ylabel('Amplitude');

Output:

Program No-2
AIETM/CSE/FPGA LAB Page 22
OBJECTIVE: Verification of sampling theorem.
Software Required:- MATLAB Software.
Theory-

Sampling: Is the process of converting a continuous time signal into a discrete time signal. It is
the first step in conversion from analog signal to digital signal.

Sampling Theorem (Nyquist Theorem ): Sampling theorem states that “Exact reconstruction
of a continuous time base-band signal from its samples is possible, if the signal is band-limited
and the sampling frequency is greater than twice the signal bandwidth”. i.e. fs > 2fm, where fm
is the highest frequency present in that signal.

Nyquist Rate Sampling: The Nyquist rate is the minimum sampling rate required to avoid
aliasing, equal to the highest modulating frequency(fm) contained within the signal. In other
words, Nyquist rate is equal to two sided bandwidth of the signal (Upper and lower sidebands).
To avoid aliasing, the sampling rate must exceed the Nyquist rate. i.e. fs > fm.

Aliasing: Aliasing is a phenomenon where the high frequency components of the sampled signal
interfere with each other, because of inadequate sampling fs < 2fm.
Aliasing leads to distortion in recovered signal. This process is called Undersampling. This is
the reason why sampling frequency should be at least twice the bandwidth of the signal. In
practice signal are oversampled, where fs is significantly higher than Nyquist rate to avoid
aliasing. . This process is called Oversampling.
Frequency spectrum of a signal which has undergone aliasing is shown below.

Program-

clear all;

close all;

clc;

tf=0.05;

t=0:0.00005:tf;

## f=input('Enter the analog frequency,f = ');

xt=cos(2*pi*f*t);

fs1=1.3*f;

n1=0:1/fs1:tf;

xn=cos(2*pi*f*n1);

subplot(3,1,1),plot(t,xt,'b',n1,xn,'r*-');

title('Undersampling plot');

xlabel('time');

ylabel('Amplitude');

fs2=2*f;

n2=0:1/fs2:tf;

xn=cos(2*pi*f*n2);

subplot(3,1,2),plot(t,xt,'b',n2,xn,'r*-');

title('Nyquist plot');

xlabel('time');

ylabel('Amplitude');

fs3=20*f;

n3=0:1/fs3:tf;

xn=cos(2*pi*f*n3);

## AIETM/CSE/FPGA LAB Page 24

subplot(313),plot(t,xt,'b',n3,xn,'r*-');

title('Oversampling plot');

xlabel('time');

ylabel('Amplitude');

Output:

Program No-3

## OBJECTIVE: Derive the Impulse response of a given system.

Software Required:- MATLAB Software.
Theory-
A discrete time system performs an operation on an input signal based on predefined criteria to
produce a modified output signal. The input signal x(n) is the system excitation, and y(n) is the
system response. The transform operation is shown as,

## Figure-1.c.1 – Transform Operation

If the input to the system is unit impulse i.e. x(n) = δ(n) then the output of the system is
known as impulse response denoted by h(n) where,

h(n) = T[δ(n)]

Any arbitrary sequence x(n) can be represented as a weighted sum of discrete impulses. Now the
system response for a linear system is given by-

## y(n) = Σx(k) T[δ(n-k)]

for k = -  to  .
The response to the shifted impulse sequence can be denoted by-

h(n- k) = T[δ(n-k)]
that implies that,
y(n) = Σx(k) h(n-k)
for k= -  to  .

That implies that for a linear time-invariant system if the input sequence is x(n) and impulse
response h(n) is given, we can fine output y(n) by using above equation, which is known as
convolution sum(discussed later) and can be represented by y(n) = x(n) * h(n).

## AIETM/CSE/FPGA LAB Page 26

Program-

clear all;
close all;
clc;
disp('Difference Equation of a digital system');
N=input('Desired Impulse response length = ');
b=input('Coefficients of x[n] terms = ');
a=input('Coefficients of y[n] terms = ');
h=impz(b,a,N);
disp('Impulse response of the system is h = ');
disp(h);
n=0:1:N-1;
figure(1);
stem(n,h);
xlabel('time index');
ylabel('h[n]');
title('Impulse response');

OUTPUT:

## [Given y(n)-y(n-1)+0.9y(n-2)= x(n)]

Difference Equation of a digital system
Desired Impulse response length = 100
Coefficients of x[n] terms = 1
Coefficients of y[n] terms = [1 -1 0.9]

## AIETM/CSE/FPGA LAB Page 27

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Program No-4(a)

## Software Required:- MATLAB Software.

Theory: Convolution is an integral concatenation of two signals. It has many applications in
numerous areas of signal processing. The most popular application is the determination of the
output signal of a linear time-invariant system by convolving the input signal with the impulse
response of the system. Note that convolving two signals is equivalent to multiplying the Fourier
Transform of the two signals.
Mathematic Formula:
The linear convolution of two continuous time signals x(t) and h(t) is defined by-

## For discrete time signals x(n) and h(n), is defined by

Where x(n) is the input signal and h(n) is the impulse response of the system.
In linear convolution length of output sequence is,
length(y(n)) = length(x(n)) + length(h(n)) – 1;

Graphical Interpretation:
 Reflection of h(k) resulting in h(-k)
 Shifting of h(-k) resulting in h(n-k)
 Element wise multiplication of the sequences x(k) and h(n-k)
 Summation of the product sequence x(k) h(n-k) resulting in the convolution
value for y(n).

## AIETM/CSE/FPGA LAB Page 29

Program:

clc;
x1 = input('Enter the 1st seq:');
x2 = input('Enter the 2nd seq:');
y = conv(x1, x2);
disp('The linear convolution of two sequences:');
disp(y);
n = 0:length(y)-1;
stem(n, y);
xlabel('Time');
ylabel('Magnitude');
title('Linear convolution');

Output:
Enter the 1st seq:[1 2 3 1]
Enter the 2nd seq:[1 1 1]
The linear convolution of two sequences:
136641

Program No 4(b)

## OBJECTIVE: Perform Circular convolution of two given sequences.

Software Required:- MATLAB Software.
Theory:

Let x1(n) and x2(n) are finite duration sequences both of length N with DFT’s X1(k)
and X2(k). Convolution of two given sequences x1(n) and x2(n) is given by the
equation,
x3(n) = IDFT[X3(k)]
X3(k) = X1(k). X2(k)

Then,

## where N stands for modulo operation.

Program:

clc;
x1 = input('Enter 1st seq:');
x2 = input('Enter 2nd seq:');
n = max(length(x1),length(x2));
x1 = fft(x1,n);
x2 = fft(x2,n);
y = x1.*x2;
yc = ifft(y,n);
disp('circular convolution:');
disp(yc);
N=0:1:n-1;
subplot(1,1,1);
stem(N,yc);
xlabel('Time');
ylabel('Magnitude');
title('Circular convolution');

## AIETM/CSE/FPGA LAB Page 31

axis([-1 5 0 15]);

OUTPUT:
Enter 1st seq:[1 1 2 1]
Enter 2nd seq:[1 2 3 4]
Circular convolution:
13 14 11 12

## AIETM/CSE/FPGA LAB Page 32

Program No-5

OBJECTIVE: To study the design and implementation of FIR filter to meet given
specifications.
Software Required:- MATLAB Software.
Theory:

Filters are the frequency selective circuit that passes a specified band of frequencies and blocks
or attenuates signals of frequencies outside this band.

## 3. Audio frequency filters (A.F) or Radio frequency filters (RF)

Analog filter are designed to process analog signals, while digital filters process analog signals
using digital techniques.

Depending on the type of element used in their construction, filters may be classified as passive
or active. Elements used in passive filters are resistors, capacitors and inductors. Active filters,
on the other hand, employ transistors or op-amps in addition to the resistors and capacitors.
Depending on the frequency used the filters are classified as AF and RF.

## 1. low pass filter

2. high pass filter
3. band pass filter
4. band reject filter
5. all pass filter

## A Finite Impulse Response (FIR) filter is a discrete linear time-invariant system

Whose output is based on the weighted summation of a finite number of past inputs.
An FIR transversal filter structure can be obtained directly from the equation for
Discrete-time convolution.

In this equation, x (k) and y (n) represent the input to and output from the filter at time
n. h(n-k) is the transversal filter coefficients at time n. These coefficients are

## AIETM/CSE/FPGA LAB Page 33

Generated by using FDS (Filter Design Software or Digital filter design package).
FIR – filter is a finite impulse response filter. Order of the filter should be specified.
Infinite response is truncated to get finite impulse response. Placing a window of
finite length does this. Types of windows available are Rectangular, Barlett,
Hamming, Hanning, Blackmann window etc. This FIR filter is an all zero filter.

Finite Impulse Response (FIR) Filter: The FIR filters are of non-recursive type,
whereby the present output sample is depending on the present input sample and previous input
samples. The transfer function of a FIR causal filter is given by-

## Where h(n) is the impulse response of the filter.

The Fourier transform of h(n) is-
N 1
H (e j )   h(n)e  j n
n 0

In the design of FIR filters most commonly used approach is using windows. The desired
frequency response H d (e j ) of a filter is periodic in frequency and can be expanded in Fourier
series. The resultant series is given by,

And known as Fourier coefficients having infinite length. One possible way of obtaining FIR
filter is to truncate the infinite Fourier series at n = [( N  1) / 2]

## Where N is the length of the desired sequence.

The Fourier coefficients of the filter are modified by multiplying the infinite impulse
response with a finite weighing sequence w(n) called a window.

## Where w(n) = w(-n) for n  [( N  1) / 2]

=0 for n  [( N  1) / 2]

After multiplying w(n) with hd(n), we get a finite duration sequence h(n) that satisfies the
desired magnitude response,

## AIETM/CSE/FPGA LAB Page 34

h(n) = hd(n).w(n) for n  [( N  1) / 2]

=0 for n  [( N  1) / 2]

## The frequency response H (e j ) of the filter can be obtained by convolution of H d (e j ) and

W (e j ) is given by,

H (e j )  (1/ 2 )  H d (e j )W ((e j (  ) )).d


H (e j )  H d (e j ) *W (e j )

Program:

clear all;
close all;
clc;
rp=input('enter passband ripple');
rs=input('enter the stopband ripple');
fp=input('enter passband freq');
fs=input('enter stopband freq');
f=input('enter sampling freq ');
wp=2*fp/f;
ws=2*fs/f;
num=-20*log10(sqrt(rp*rs))-13;
dem=14.6*(fs-fp)/f;
n=ceil(num/dem);
n1=n+1;
if(rem(n,2)~=0)
n1=n;
n=n-1;
end
c=input('enter your choice of window function 1. rectangular 2. triangular 3.kaiser: \n ');

if(c==1)
y=rectwin(n1);
disp('Rectangular window filter response');
end

## AIETM/CSE/FPGA LAB Page 35

if (c==2)
y=triang(n1);
disp('Triangular window filter response');
end

if(c==3)
y=kaiser(n1);
disp('kaiser window filter response');
end

%LPF
b=fir1(n,wp,y);
[h,o]=freqz(b,1,256);
m=20*log10(abs(h));
subplot(2,2,1);plot(o/pi,m);
title('LPF');
ylabel('Gain in dB-->');
xlabel('(a) Normalized frequency-->');

%HPF
b=fir1(n,wp,'high',y);
[h,o]=freqz(b,1,256);
m=20*log10(abs(h));
subplot(2,2,2);
plot(o/pi,m);
title('HPF');
ylabel('Gain in dB-->');
xlabel('(b) Normalized frequency-->');

%BPF
wn=[wp ws];
b=fir1(n,wn,y);
[h,o]=freqz(b,1,256);
m=20*log10(abs(h));
subplot(2,2,3);plot(o/pi,m);
title('BPF');
ylabel('Gain in dB-->');
xlabel('(c) Normalized frequency-->');

## AIETM/CSE/FPGA LAB Page 36

%BSF
b=fir1(n,wn,'stop',y);
[h,o]=freqz(b,1,256);
m=20*log10(abs(h));
subplot(2,2,4);plot(o/pi,m);
title('BSF');
ylabel ('Gain in dB-->');
xlabel ('(d) Normalized frequency-->');

## Output: enter passband ripple0.02

enter the stopband ripple0.01
enter passband freq1000
enter stopband freq1500
enter sampling freq 10000
enter your choice of window function 1. rectangular 2. triangular 3.kaiser:

## 1Rectangular window filter response

2.
enter passband ripple0.02
enter the stopband ripple0.01
enter passband freq1000

## AIETM/CSE/FPGA LAB Page 37

enter stopband freq1500
enter sampling freq 10000
enter your choice of window function
1. rectangular 2. triangular 3.kaiser:

2
Triangular window filter response

## 3. enter passband ripple0.02

enter the stopband ripple0.01
enter passband freq1000
enter stopband freq1500
enter sampling freq 10000

## enter your choice of window function

1. rectangular 2. triangular 3.kaiser:

3
kaiser window filter response-

## AIETM/CSE/FPGA LAB Page 38

AIETM/CSE/FPGA LAB Page 39
Program No -6

OBJECTIVE : To study the design and implementation of IIR(LPF/HPF) filter to meet given
specifications.
Software Required:- MATLAB Software.
Theory:
The IIR filter can realize both the poles and zeroes of a system because it has a
rational transfer function, described by polynomials in z in both the numerator and the
denominator:

𝒎 𝒏

## 𝒚(𝒏) = ∑ 𝒃𝒌 𝒙(𝒏 − 𝒌) + ∑ 𝒂𝒌 𝒚(𝒏 − 𝒌)

𝒌=𝟎 𝒌=𝟏
M and N are order of the two polynomials
bk and ak are the filter coefficients. These filter coefficients are generated using FDS(Filter
Design software or Digital Filter design package).
IIR filters can be expanded as infinite impulse response filters. In designing IIR
filters, cutoff frequencies of the filters should be mentioned. The order of the filter
can be estimated using butter worth polynomial. That’s why the filters are named as butter worth
filters. Filter coefficients can be found and the response can be plotted.

Program:

clc;
clear all;
close all;
disp('enter the IIR filter design specifications');
rp=input('enter the passband ripple');
rs=input('enter the stopband ripple');
wp=input('enter the passband freq');
ws=input('enter the stopband freq');
AIETM/CSE/FPGA LAB Page 40
fs=input('enter the sampling freq');
w1=2*wp/fs;w2=2*ws/fs;
[n,wn]=buttord(w1,w2,rp,rs,'s');
c=input('enter choice of filter 1. LPF 2. HPF \n ');
if(c==1)
disp('Frequency response of IIR LPF is:');
[b,a]=butter(n,wn,'low','s');
end
if(c==2)
disp('Frequency response of IIR HPF is:');
[b,a]=butter(n,wn,'high','s');
end
w=0:.01:pi;
[h,om]=freqs(b,a,w);
m=20*log10(abs(h));
an=angle(h);
figure,subplot(2,1,1);plot(om/pi,m);
title('magnitude response of IIR filter is:');
xlabel('(a) Normalized freq. -->');
ylabel('Gain in dB-->');
subplot(2,1,2);plot(om/pi,an);
title('phase response of IIR filter is:');
xlabel('(b) Normalized freq. -->');

Output:

## enter the IIR filter design specifications

enter the passband ripple0.15
enter the stopband ripple60
enter the passband freq1500
enter the stopband freq3000
enter the sampling freq7000

## AIETM/CSE/FPGA LAB Page 41

1
Frequency response of IIR LPF is:

## enter the IIR filter design specifications

enter the passband ripple0.15
enter the stopband ripple60
enter the passband freq1500
enter the stopband freq3000
enter the sampling freq7000

## enter choice of filter 1. LPF 2. HPF

2
Frequency response of IIR HPF is:

## AIETM/CSE/FPGA LAB Page 42

AIETM/CSE/FPGA LAB Page 43

EXPERIMENT 7

OBJECTIVE: Realizing a given block diagram having multiplier, adder/subtractor and system
with given Impulse response. Calculating output for given input.
Software Required:- MATLAB Software
THEORY-

## AIETM/CSE/FPGA LAB Page 44

AIETM/CSE/FPGA LAB Page 45
Example-Given difference equation-y[n]= .75 y[n-1]- 0.125y[n-2]+ x[n]+2x[n-1]+x[n-2]

## AIETM/CSE/FPGA LAB Page 46

Direct form 1 block diagram

## AIETM/CSE/FPGA LAB Page 47

Procedure for make block diagram-

1. Start matlab.

## 2. Open model option in new option.

3. A new window is open and in this new window open Simulink library browser.

## 6. Start the simulation.

7. Output can see in scope block that is same in case of direct form1 and direct form2.

We implement here, two Direct form 2, systems, with given transfer functions-

## AIETM/CSE/FPGA LAB Page 48

OUTPUT:

If we give a square wave of amplitude 1, and frequency of 0.005 Hz, Input and output
waveforms for the model will be-

## Its block diagram is-

AIETM/CSE/FPGA LAB Page 49
A demo model using fixed−point Simulink blocks can be displayed by typing-

fxpdemo_direct_form2

## in MATLAB’s Command Window. This demo is an implementation of the third−order transfer

function. Input and Output waveforms will be like-

Program No 8

## OBJECTIVE: To simulate the transmitter and receiver for BPSK.

Software Required:- MATLAB Software.
THEORY-
BPSK-binary phase shift keying.
In BPSK modulation, the phase of the RF carrier is shifted 180 degrees in accordance with a
digital bit stream. The digital coding scheme used is called NRZ-M. A "one" causes a phase
transition, and a "zero" does not produce a transition. That way you don't have to worry about the
polarity of the signal. The receiver performs a differentially coherent detection process, in which
the phase of each bit is compared to the phase of the preceding bit. Better performance can be
obtained with fully coherent PSK, but that requires an absolute phase reference at each end, and
no phase variations in the propagation path. Pretty hard to achieve, even on LF. Because the
output of the receiver's coherent detector swings from +V to -V when there's a phase transition,
rather than from +V to zero in the case of on-off keying, BPSK offers a 6-dB advantage in
signal-to-noise ratio over on-off keying for a given carrier level.

BPSK TRANSMITTER-

## AIETM/CSE/FPGA LAB Page 52

Outputs of bpsk receiver-

## AIETM/CSE/FPGA LAB Page 53

DSP Lab using TMS320C6XXX DSP Kits

Program No 9

OBJECTIVE : Study the basic information of architecture of TM3320C6XXD DSP kit using
BLOOM using DSP. Study architecture of TMS320C6XXD DSP kit.

## INTRODUCTION TO DSP PROCESSORS

A signal can be defined as a function that conveys information, generally about the state
or behavior of a physical system. There are two basic types of signals viz Analog (continuous
time signals which are defined along a continuum of times) and Digital (discrete-time).

## Remarkably, under reasonable constraints, a continuous time signal can be adequately

represented by samples, obtaining discrete time signals. Thus digital signal processing is an ideal
choice for anyone who needs the performance advantage of digital manipulation along with
today’s analog reality. digital processing must offer some clear advantages that include:

Programmability: A single piece of digital DSP hardware can perform many functions. For
example, a multimedia PC can play music and also function as a word processor if it is loaded
with suitable programs. This ability to use the same hardware for many functions provides
important flexibility.

Stability: The stability of analog circuits depends upon several factors. Analog circuits are
affected by temperature and aging, and tolerence. Also, two analog systems using the same
design and components may differ in performance.

Repeatability: A properly designed digital circuit will produce the same result every time, in
addition to being identicalfrom unit to unit. If the same multiplication is performed on 500
computers, all 500 computers shouldproduce the same result. Component tolerances, aging, and
temperature drifts also do not affect digital circuits nearly as much.

Temperature: Digital circuits do not gradually change their characteristics over time,
temperature, or humidity. Theyeither work or they don’t work. In other words, digital circuits are
repeatable as long as they are designed with enough tolerance to operate properly over the range
of expected conditions.

## AIETM/CSE/FPGA LAB Page 54

Aging: The effects of component aging can be detrimental to analog circuits as characteristics
and performancechange. These effects can sometimes be anticipated, or their effect may not be
critical. Analog designersmust be aware of these effects.
Some practical applications of DSP systems are: Toys, Videophones, Modems, Phone
Systems, 3D Graphics, Image Processing.

## Components of a Typical DSP System

Typical DSP systems consist of a DSP chip, memory, possibly an analog-to-digital converter
(ADC), digital-to-analog converter (DAC), and communication channels.

DSP Chip

A DSP chip can contain many hardware elements; some of the more common ones are listed
below.

## Central Arithmetic Unit

This part of the DSP performs major arithmetic functions such as multiplication and addition. It
is the part that makes the DSP so fast in comparison with traditional processors.

## Auxiliary Arithmetic Unit

DSPs frequently have an auxiliary arithmetic unit that performs pointer arithmetic, mathematical
calculations, or logical operations in parallel with the main arithmetic unit.

Serial Ports
DSPs normally have internal serial ports for high-speed communication with other DSPs and
data converters. These serial ports are directly connected to the internal buses to improve
performance, to reduce external address decoding problems, and to reduce cost.

Memory
Memory holds information, data, and instructions for DSPs and is an essential part of any DSP
system. Although DSPs are intelligent machines, they still need to be told what to do. Memory
devices hold a series of instructions that tell the DSP which operations to perform on the data
(i.e., information).

## A/D and D/A Converters

Analog-to-digital converters (ADCs) accept analog input and turn it into digital data that consist
of only 0s and 1s. Digital-to-analog converters (DACs) perform the reverse process; they accept
digital data and convert it to a continuous analog signal.

## AIETM/CSE/FPGA LAB Page 55

Ports
Communication ports are necessary for a DSP system. Raw information is received and
processed; then that information is transmitted to the outside world through these ports. For
example, a DSP system could output information to a printer through a port. The most common
ports are serial and parallel ports. A serial port accepts a serial (single) stream of data and
converts it to the processor format. When the processor wishes to output serial data, the port
accepts processor data and converts it to a serial stream (e.g., modem connectionson PCs). A
parallel port does the same job, except the output and input are in parallel (simultaneous) format.
The most common example of a parallel port is a printer port on a PC.

## Hence a processor which is designed to perform the special operations (digital

manipulations) on the digital signal within very less time can be called as a Digital signal
processor. The difference between a DSP processor, conventional microprocessor and a
microcontroller are listed below.
Microprocessor or General Purpose Processor such as Intel xx86 or Motorola 680xx family

-No RAM
-No ROM
-No I/O ports
-No Timer

## Microcontroller such as 8051 family

Contains - CPU
- RAM
- ROM
-I/O ports
- Timer &
- Interrupt circuitry

Some Micro Controllers also contain A/D, D/A and Flash Memory
DSP Processors such as Texas instruments and Analog Devices
Contains - CPU
- RAM
-ROM
- I/O ports
- Timer
Optimized for – fast arithmetic
AIETM/CSE/FPGA LAB Page 56
- Extended precision
- Dual operand fetch
- Zero overhead loop
- Circular buffering

Feature Use

## Fast-Multiply accumulate Most DSP algorithms, including filtering,

transforms, etc. are multiplication- intensive

## Multiple – access memory architecture Many data-intensive DSP operations require

reading a program instruction and multiple data
items during each instruction cycle for best
performance

Specialized addressing modes Efficient handling of data arrays and first-in, first-
out buffers in memory

Specialized program control Efficient control of loops for many iterative DSP
algorithms. Fast interrupt handling for frequent
I/O operations.

On-chip peripherals and I/O interfaces On-chip peripherals like A/D converters allow for
small low cost system designs. Similarly I/O
interfaces tailored for common peripherals allow
clean interfaces to off-chip I/O devices.

## AIETM/CSE/FPGA LAB Page 57

OBJECTIVE: To study the architecture of TMS320C6XXX DSP kit.

Theory:
Computers need instructions to operate. At every clock cycle, they must be told what to do. If the
instructions are stored, the computer just has to fetch and execute them. Such computers are
called stored Program machines. Our computer typically fetches an instruction and then data,
operates on the data, and returns the resulting data to the store. Stored program machines use two
well-known and widely used computer architectures: von Neuman and Harvard.. The following
diagram shows the structure of the two architectures.
Von Neuman Architecture
The von Neuman machines store programming and data in the same memory area. In this type of
machine, an instruction contains the operation command and the address of the data on which the
operation is performed. There are two basic operation units within these machines: the arithmetic
logic unit (ALU) and the input/output unit. The ALU performs the core operations: multiply,
add, subtract, and many more. It is on these very simple core operations that complex software,
such as word processing software, can be built. The input/output unit manages the flow of
external data for the machine.

Harvard Architecture
The primary difference between Harvard architecture and von Neuman architecture is that with
Harvard, program and data memories are physically separated transmission paths. This enables
the machine to transfer instructions and data simultaneously. Such a structure can greatly
enhance performance, because instructions and data can be fetched simultaneously. Harvard
machines also have ALUs and input/output units.
The drawback to using a true Harvard architecture is that since it uses separate program and
data memories, it needs twice as many address and data pins on the chip and twice as much
external memory. Unfortunately, as the number of pins or chips increases, so does the price.
Electronic designers, who have had to tackle problems like these before, have come up with
an elegant solution: a single data and address bus is used externally, while two (or more) separate
buses for program and data are used internally. Timing (multiplexing) handles the separation of
program and data information. In one clock cycle, the program information flows on the pins,
and in the second cycle, data follows on the same pins. Program and data information is then
routed onto separate internal program and data buses. Such machines are called modified
Harvard architecture processors because the internal architecture is Harvard while the external
architecture is von Neuman.

## AIETM/CSE/FPGA LAB Page 58

Figure 3.b.1-Harward and von Neuman architecture.

## This chapter provides an overview of the architectural structure of the TMS320C67xxDSP,

which comprises the central processing unit (CPU), memory, and on-chip peripherals. The
C67xE DSPs use an advanced modified Harvard architecture that maximizes processing power
with eight buses. Separate program and data spaces allow simultaneous access to program
instructions and data, providing a high degree of parallelism. For example, three reads and one
write can be performed in a single cycle. Instructions with parallel store and application-specific
instructions fully utilize this architecture. In addition, data can be transferred between data and
program spaces. Such Parallelism supports a powerful set of arithmetic, logic, and bit-
manipulation operations that can all be performed in a single machine cycle. Also, the C67xx
DSP includes the control mechanisms to manage interrupts, repeated operations, and function.

## AIETM/CSE/FPGA LAB Page 59

Figure 3.d.2- BLOCK DIAGRAM OF TMS 320VC 6713

Bus Structure

The C67xx DSP architecture is built around eight major 16-bit buses (four program/data buses
and four address buses):
_ the program bus (PB) carries the instruction code and immediate operands from Program
memory.

_ Three data buses interconnect to various elements, such as the CPU, data address generation
logic, program address generation logic, on-chip peripherals, and data memory.

## AIETM/CSE/FPGA LAB Page 60

_ The CB and DB carry the operands that are read from data memory.
_ The EB carries the data to be written to memory.
_ Four address buses (PAB, CAB, DAB, and EAB) carry the addresses needed for Instruction
execution.

The C67xx DSP can generate up to two data-memory addresses per cycle using the two auxiliary
register arithmetic units (ARAU0 and ARAU1). The PB can carry data operands stored in
program space (for instance, a coefficient table) to the multiplier and adder for
multiply/accumulate operations or to a destination in data space for data move instructions
(MVPD and READA). This capability, in conjunction with the feature of dual-operand read,
supports the execution of single-cycle, 3-operand instructions such as the FIRS instruction. The
C67xx DSP also has an on-chip bidirectional bus for accessing on-chip peripherals. This bus is
connected to DB and EB through the bus exchanger in the CPU interface. Accesses that use this
bus can require two or more cycles for reads and writes, depending on the peripheral’s structure.

## Central Processing Unit (CPU)

The CPU is common to all C67xE devices. The C67x CPU contains:

## _ 40-bit arithmetic logic unit (ALU)

_ Two 40-bit accumulators
_ Barrel shifter
_ 17 × 17-bit multiplier
_ Compare, select, and store unit (CSSU)
_ Data address generation unit
_ Program address generation unit

## Arithmetic Logic Unit (ALU)

The C67x DSP performs 2s-complement arithmetic with a 40-bit arithmetic logic unit (ALU)
and two 40-bit accumulators (accumulators A and B). The ALU can also perform Boolean
operations. The ALU uses these inputs:

_16-bitimmediate value
_ 16-bit word from data memory
_ 16-bit value in the temporary register, T
_ Two 16-bit words from data memory

## _ 32-bit word from data memory

_ 40-bit word from either accumulator
AIETM/CSE/FPGA LAB Page 61
The ALU can also function as two 16-bit ALUs and perform two 16-bit operations
Simultaneously.

## Figure 2.d.3 – ALU UNIT

Accumulators

Accumulators A and B store the output from the ALU or the multiplier/adder block. They can
also provide a second input to the ALU; accumulator A can be an input to the Multiplier/adder.
Each accumulator is divided into three parts:
_ Guard bits (bits 39–32)
_ High-order word (bits 31–16)
_ Low-order word (bits 15–0)
Instructions are provided for storing the guard bits, for storing the high- and the loworder
accumulator words in data memory, and for transferring 32-bit accumulator words in or out of
data memory. Also, either of the accumulators can be used as temporary storage for the other.

Barrel Shifter

## AIETM/CSE/FPGA LAB Page 62

The C67x DSP barrel shifter has a 40-bit input connected to the accumulators or to data memory
(using CB or DB), and a 40-bit output connected to the ALU or to data memory (using EB). The
barrel shifter can produce a left shift of 0 to 31 bits and a right shift of 0 to 16 bits on the input
data. The shift requirements are defined in the shift count field of the instruction, the shift count
field (ASM) of status register ST1, or in temporary register T (when it is designated as a shift
count register).The barrel shifter and the exponent encoder normalize the values in an
accumulator in a single cycle. The LSBs of the output are filled with 0s, and the MSBs can be
either zero filled or sign extended, depending on the state of the sign-extension mode bit (SXM)
in ST1. Additional shift capabilities enable the processor to perform numerical scaling, bit
extraction, extended arithmetic, and overflow prevention operations.

The multiplier/adder unit performs 17 _ 17-bit 2s-complement multiplications with a 40- bit
addition in a single instruction cycle. The multiplier/adder block consists of several elements: a
multiplier, an adder, signed/unsigned input control logic, fractional control logic, a zero detector,
a rounder (2s complement), overflow/saturation logic, and a 16-bit temporary storage register
(T). The multiplier has two inputs: one input is selected from T, a data-memory operand, or
accumulator A; the other is selected from program memory, data memory, accumulator A, or an
immediate value. In addition, the multiplier and ALU together execute multiply/accumulate
(MAC) computations and ALU operations in parallel in a single instruction cycle. This function
is used in determining the Euclidian distance and in implementing symmetrical and LMS filters,
which are required for complex DSP algorithms. See section 4.5, Multiplier/Adder Unit, on page
4-19, for more details about the multiplier/adder unit.

## AIETM/CSE/FPGA LAB Page 63

Figure 2.d.4 - MULTIPLIER/ADDER UNIT

These are the some of the important parts of the processor and you are instructed to gothrough
the detailed architecture once which helps you in developing the optimized codefor the required
application.

## PROCEDURE FOR 6713 DSK

Step: I
1. First connect the dsk 6713 kit by USB cable and power on.
2. Now some LEDs glowing on
3. Open the 6713 DSK diagnostic (driver) icon.
4. Reset the kit
5. Give start in driver, now it start to checks all .
6. Finally it displays PASS.
7. Then click close the window.
Step: II
1. Open the CCS setup and select Family-c67xx, platform-DSK, endianneslittle.
2. Select C67xx DSK board and add then save & quit.
3. Now CCS will open.

## AIETM/CSE/FPGA LAB Page 64

4. Go Debug connect
5. Project New project give project name Finish.
6. File NewSource file. (now editor window will open).
7. Type your C code in editor window.
8. File Save give name.C Save.
9. Project Add files to project select your C program and open it.
10. Project Save project.
11. Project Build. (now your c code converted into .out format)
12. File Load program Select your .out file Open. (.out file present in
the path where you are stored .C file)
13. Now your program is loading and disassembly will open.
14. If your program wants inputs go View Memory.
15. Give data memory location Ok (now new window will open)
16. Double click on data side new window will open give data increment the address.
17. Open your output memory location also.
18. Debug Run debug Halt.
19. Now you will see the output in your output memory location

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Program No 10(a)

## Procedure to create new Project:

1. To create project, Go to Project and Select New.

## AIETM/CSE/FPGA LAB Page 76

Mathematical Formula:

The linear convolution of two continuous time signals x(t) and h(t) is defined by:

## AIETM/CSE/FPGA LAB Page 77

Where x(n) is the input signal and h(n) is the impulse response of the system.
In linear convolution length of output sequence is,
Length (y(n)) = length(x(n)) + length(h(n)) – 1.

Program:
#include<stdio.h>
main()
{
int m=4; /*Lenght of i/p samples sequence*/
int n=4; /*Lenght of impulse response Co-efficients */
int i=0,j;
int x={1,2,3,4,0,0,0,0}; /*Input Signal Samples*/
int h={1,2,3,4,0,0,0,0}; /*Impulse Response Co-efficients*/
/*At the end of input sequences pad 'M' and 'N' no. of zero's*/
int *y;
y=(int *)0x0000100;
for(i=0;i<m+n-1;i++)
{
y[i]=0;
for(j=0;j<=i;j++)
y[i]+=x[j]*h[i-j];
}
for(i=0;i<m+n-1;i++)
printf("%d\n",y[i]);
}
Output:
1, 4, 10, 20, 25, 24, 16.
Or

#include<stdio.h>
int x,h,y;
main ()
{
int i,j,m,n;
printf("\n enter value for m");
scanf("%d",&m);
printf("\n enter value for n");
scanf("%d",&n);
printf("Enter values for i/p x(n):\n");

## AIETM/CSE/FPGA LAB Page 78

for(i=0;i<m;i++)
scanf("%d",&x[i]);
printf("Enter Values for i/p h(n) \n");
for(i=0;i<n; i++)
scanf("%d",&h[i]);
// padding of zeros
for(i=m;i<=m+n-1;i++)
x[i]=0;
for(i=n;i<=m+n-1;i++)
h[i]=0;
/* convolution operation */
for(i=0;i<m+n-1;i++)
{
y[i]=0;
for(j=0;j<=i;j++)
{
y[i]=y[i]+(x[j]*h[i-j]);
}}
//displaying the o/p
for(i=0;i<m+n-1;i++)
printf("\n The Value of output y[%d]=%d",i,y[i]);
}

Result:
enter value for m4
enter value for n4
Enter values for i/p
1234
Enter Values for n
1234
The Value of output y=1
The Value of output y=4
The Value of output y=10
The Value of output y=20
The Value of output y=25
The Value of output y=24
The Value of output y=16

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Program No 10(b)

## OBJECTIVE : To implement circular convolution of two sequences.

Theory:
Circular Convolution:
Let x1(n) and x2(n) are finite duration sequences both of length N with DFT’s X1(k) and
X2(k). Convolution of two given sequences x1(n) and x2(n) is given by the equation,
x3(n) = IDFT[X3(k)]
X3(k) = X1(k) X2(k)

Program:
#include<stdio.h>
int m,n,x,h,y,i,j,temp,k,x2,a;
void main()
{
int *y;
y=(int *)0x0000100;
printf(" enter the length of the first sequence\n");
scanf("%d",&m);
printf(" enter the length of the second sequence\n");
scanf("%d",&n);
printf(" enter the first sequence\n");
for(i=0;i<m;i++)
scanf("%d",&x[i]);
printf(" enter the second sequence\n");
for(j=0;j<n;j++)
scanf("%d",&h[j]);
if(m-n!=0) /*If length of both sequences are not equal*/

## AIETM/CSE/FPGA LAB Page 88

{
if(m>n) /* Pad the smaller sequence with zero*/
{
for(i=n;i<m;i++)
h[i]=0;
n=m;
}
for(i=m;i<n;i++)
x[i]=0;
m=n;
}
y=0;

a=h;
for(j=1;j<n;j++) /*folding h(n) to h(-n)*/
a[j]=h[n-j];
/*Circular convolution*/
for(i=0;i<n;i++)
y+=x[i]*a[i];
for(k=1;k<n;k++)
{
y[k]=0;
/*circular shift*/
for(j=1;j<n;j++)
x2[j]=a[j-1];
x2=a[n-1];
for(i=0;i<n;i++)
{
a[i]=x2[i];
y[k]+=x[i]*x2[i];

## AIETM/CSE/FPGA LAB Page 89

}
}
/*displaying the result*/
printf(" the circular convolution is\n");
for(i=0;i<n;i++)
printf("%d ",y[i]);
}

Or

## /* program to implement circular convolution */

#include<stdio.h>
int m,n,x,h,y,i,j, k,x2,a;
void main()
{
printf(" Enter the length of the first sequence\n");
scanf("%d",&m);
printf(" Enter the length of the second sequence\n");
scanf("%d",&n);
printf(" Enter the first sequence\n");
for(i=0;i<m;i++)
scanf("%d",&x[i]);
printf(" Enter the second sequence\n");
for(j=0;j<n;j++)
scanf("%d",&h[j]);
if(m-n!=0) /*If length of both sequences are not equal*/
{
if(m>n) /* Pad the smaller sequence with zero*/
{
for(i=n;i<m;i++)

## AIETM/CSE/FPGA LAB Page 90

h[i]=0;
n=m;
}
for(i=m;i<n;i++)
x[i]=0;
m=n;
}
y=0;
a=h;
for(j=1;j<n;j++) /*folding h(n) to h(-n)*/
a[j]=h[n-j];
/*Circular convolution*/
for(i=0;i<n;i++)
y+=x[i]*a[i];
for(k=1;k<n;k++)
{
y[k]=0;
/*circular shift*/
for(j=1;j<n;j++)
x2[j]=a[j-1];
x2=a[n-1];
for(i=0;i<n;i++)
{
a[i]=x2[i];
y[k]+=x[i]*x2[i];
}
}
/*displaying the result*/
printf(" The circular convolution is\n");
for(i=0;i<n;i++)

## AIETM/CSE/FPGA LAB Page 91

printf("%d \t",y[i]);
}

Output:
enter the length of the first sequence4
enter the length of the second sequence4
enter the first sequence4 3 2 1
enter the second sequence1 1 1 1
the circular convolution is10 10 10 10

## Procedure to create new Project:

1. To create project, go to Project and Select New.

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Program 1
Object: Plotting of various elementary signals like impulse function, unit step
function, ramp function quadratic function, and general sinusoidal function.
S.NO Questions

1 What is MATLAB?

## Ans MATLAB stands for ‘MATRIX-LABORATORY’.MATLAB is a high-level

language and interactive environment that enables you to perform computationally
intensive tasks faster than with traditional programming languages
2 Give some application of matlab software?

## Ans 1. Signal processing

2. Image processing
3. Signal interpolation ,etc.
3 Give the extensions for variable file in the matlab?

Ans Example.m

4 Define signals?

Ans Is a function that conveys information about the behavior or attributes of some
phenomenon
5 What are the differences between analog and discrete signal?

## Ans Analog Digital

Analog signal is a continuous Digital signals are discrete time
Signal signal which represents physical signals generated by digital
measurements. modulation.
Waves Denoted by sine waves Denoted by square waves
Uses continuous range of values to Uses discrete or discontinuous
Representation
represent information values to represent information
Human voice in air, analog Computers, CDs, DVDs, and
Example
electronic devices. other digital electronic devices.
6 Give the differences between digital and discrete signal?

## Ans A discrete signal or discrete-time signal is a time series consisting of a sequence of

quantities. In other words, it is a time series that is a function over a domain of
AIETM/CSE/FPGA LAB Page 103
integers.

## A digital signal is a physical signal that is a representation of a sequence of discrete

values, for example of an arbitrary bit stream, or of a digitized analog signal.
7 Give the differences between analog and digital signal?

## Ans A digital signal is a physical signal that is a representation of a sequence of discrete

values, for example of an arbitrary bit stream, or of a digitized analog signal.

An analog or analogue signal is any continuous signal for which the time varying
feature (variable) of the signal is a representation of some other time varying
quantity, i.e., analogous to another time varying signal.
8 Explain the unit step function?

Ans The Heaviside step function, or the unit step function, is a discontinuous function
whose value is zero for negative argument and one for positive argument.
9 Define impulse signal?

Ans An ideal impulse function is a function that is zero everywhere but at the origin,
where it is infinitely high. However, the area of the impulse is finite.
10 Define ramp function?

Ans The ramp function may be defined analytically in several ways. Possible definitions
are:

## 11 Explain how sine wave is plotted in matlab?

Ans Y=sin(2*pi*f*t)

## AIETM/CSE/FPGA LAB Page 104

Ans Unit step signal is produced

15 What is the basic difference between plot command and stem command?

Ans Plot command is used for drawing graphs with continuous time axis
Stem command is used for drawing graphs with discrete time axis
PROGRAM 2
Object: Verification of SAMPLING THEOREM.
S.NO Questions

## 1 Explain the sampling theorem?

Ans Sampling is the process of converting a signal (for example, a function of continuous
time or space) into a numeric sequence (a function of discrete time or space)
2 Why sampling is necessary?

Ans It helps to convert continuous signals in discrete and then digital signal is formed so
that the signal have less chances of error
3 How a sampled signal is recovered at receiver?

Received signal is multiplied with impulse train and then the signal is passed through
the low pass filter
4 What do you mean by aliasing effect on a signal?

Ans Aliasing refers to an effect that causes different signals to become indistinguishable
(or aliases of one another) when sampled.
5 What is the condition to avoid aliasing for sampling?

Ans FS>=2FM
FS=>sampling frequency
FM=>message frequency
6 What do you mean by nyquist criteria?

Ans The sampling frequency should be at least twice the highest frequency contained in
the signal.
7 What is under sampling?

## Ans Bandpass sampling is a technique where one samples a bandpass-filtered signal at a

sample rate below its Nyquist rate (twice the upper cut-off frequency), but is still
able to reconstruct the signal.
8 How can be aliasing be avoided?

## AIETM/CSE/FPGA LAB Page 105

Ans By keeping sampling frequency greater than twice the message frequency.

## Ans Ideal Low Pass Filter.

10 Why we have used plot and stem command both in the program?

## Ans Plot command is used for plotting the message signal

Stem command is used for plotting the sampled signal
11 Why subplot command is used in the program?

Ans Subplot command is used for plotting various graphs on the same window

## 12 Explain the use of hold on signal used in the program?

Ans Hold command is used to hold the value of the signal for instant of time.

Ans

Sampled signal

## AIETM/CSE/FPGA LAB Page 106

14 Which command is used for closing all the opened plots?

## Ans T=initial limit:interval:final limit

Program 3
Object:Derive the IMPULSE RESPONSE of given system.

S.NO Questions

## 1 What do you mean by impulse response of a system?

Ans The impulse response, or impulse response function (IRF), of a dynamic system is
its output when presented with a brief input signal, called an impulse.
2 Why impulse response of a system is necessary to be calculated?

Ans To calculate the transfer function of the system and its response to any signal can be
determined.
3 What is a LTI system?

Ans The system that is almost having a constant behavior throughout the time

4 Give the difference between time invariant and time variant system?

Ans A time-invariant (TIV) system is one whose output does not depend explicitly on
time.
A time-variant system is a system that is not time invariant (TIV). Roughly speaking,
characteristics its output depend explicitly upon time.
5 Give the use of ZEROS command in matlab?

## 6 How a zero matrix is different from one matrix?

Ans All the elements of the matrix are one rather than zero

7 Can we change the value of a zero matrix element by our choice? If yes specify the
command?

## AIETM/CSE/FPGA LAB Page 107

Ans Matrix(element location)=value

## Ans Using label command

9 Is there any command to plot the whole function IMPULSE in a statement? Specify
the command

## Ans To see the values of the variable defined

12 Can we change the time axis interval for a graph? What is the particular syntax?

Ans T= -1:.01:1
The value can be changed during codding only
13 What is the function of command window in matlab?

## AIETM/CSE/FPGA LAB Page 108

Program 4
Object: Perform convolution on two signals

S.NO Questions

## 1 What is mean by linear convolution?

Ans Linear convolution takes two functions of an independent variable, which I will call
time, and convolves them using the convolution sum formula

## Ans Used for the convolution function

3 Define convolution

## Ans convolution is a mathematical operation on two functions f and g, producing a

third function that is typically viewed as a modified version of one of the original
functions

Ans cconv

## AIETM/CSE/FPGA LAB Page 109

Ans Stem plots the discrete graphs

## 8 What is the total output length of linear convolution sum?

Ans X[n] and y[m] is input then output sequence length is n+m-1

## 9 What is circular convolution?

Ans If a input is multiplied with time shifted version of LTI system then result is circular
convolution

10 What is DFT?

Ans DFT stands for discrete Fourier trAnsform and computes Z-trAnsform for evenly
spaced points around a unit circle

## 12 What is the frequency response of a system?

Ans It is a function that describe the magnitude and phase shift of a filter over a range of
frequencies

## Ans DSP stands for digital signal processing system

14 What is correlation?

## AIETM/CSE/FPGA LAB Page 110

Program 5
Object: Study the design and implementation of FIR filter to meet given
specifications.
S.NO Questions
1 What are filters?
Ans Circuits that passes certain signals and stops the rest
2 Define high pass and low pass filter?
Ans High pass filter= It passes high order frequencies
Low pass filter= It passes low order frequencies
3 What are band pass and band reject filters?
Ans Band pass filter= It passes a band of frequencies
Band reject filter= it stops a certain band of frequencies only
4 What are FIR filters?
Ans Finite Impulse response = it can process impulse response of finite duration
5 What do you mean by impulse response of a filter?
Ans How a filter responds to impulse signal
6 Give the difference between IIR and FIR filter?
Ans IIR filter process signal of Infinite length and FIR filter process signal of finite length
7 Why filters are necessary in a communication circuit?
Ans It is necessary to remove the effect of noise
8 What is the response of Butterworth FIR filter?
Ans flat a frequency response
9 What is the response of Chebyshev FIR filter?
Ans Passband ripple is observed
10 What is attenuation in a filter?
Ans It reduces the output power of a signal

## AIETM/CSE/FPGA LAB Page 111

11 What do you mean by Passband of a filter?
Ans The frequency band which is passed by the filter
12 What do you mean by stopband of a filter?
Ans The frequency band which is stopped by the filter
13 What is fdesign method in matlab?
Ans It is used for Filter specification object
14 What do you mean by Exploring the Process Flow Diagram.?
Ans How a process is completed in FPGA modelling
15 What do you mean by algorithm?
Ans It is just a flow method how a codding of program can be done

Program 6
Object: Study the design and implementation of IIR filter to meet given
specifications
S.No Questions
1 What are FIR and IIR LTI systems
Ans FIR LTI SYSTEM= How a LTI system behaves to finite impulse signal
IIR LTI SYSTEM= How a LTI system behaves to infinite impulse signal
2 Differentiate between recursive and non-recursive LTI systems
Ans Recursive system= system response depend on past output
Non-Recursive system= system response do not depend on past output

3 Which have a low error rate recursive and non-recursive LTI systems
Ans Recursive LTI system
4 Define window function.
Ans It give output as dft sequence
5 What is Multirate Digital Signal Processing
Ans The system which works on different frequencies
6 Why DSP system have advantage over analog system
Ans Because the modern work on digital signal is gaining importance than analog system
7 Differentiate between up-sampling and down-sampling
Ans Up sampling= sampling at high frequency than nyquist rate
Down sampling= sampling at lower frequency than nyquist rate
8 Define decimation
AIETM/CSE/FPGA LAB Page 112
Ans Sampling the sampled signal at lower rate
9 Define interpolation
Ans Reconstruction of sampled signal
10 Main difference between Analog filters and Digital filters.
Ans The difference lies in the input signal
11 Main difference between Passive filters or Active filters.
Ans The devices used in construction of filter give main the diffrence
12 What is the use of disp command?
Ans Display text or array
13 How a condition can be implied in matlab program

## 14 How a for loop is designed in matlab

Ans for index = values
program statements
end
15 Why clear all command is used in the program
Ans To erase the variable content in memory

## AIETM/CSE/FPGA LAB Page 113

Program 7
Object: Realizing a given block diagram having multiplier, adder, subtractor
and system with given impulse response. Calculate output of given input.
S. NO. Question

## 2 What is mean by LTI system?

Ans Linear time invariant system that is remaining constant throughout its operational time

## AIETM/CSE/FPGA LAB Page 114

5 How Simulink window is opened using command window

## 6 Name commonly used blocks

Ans Demux,Mux,Buses,Sum

## 12 What is clear command?

Ans Clear removes all variables from the workspace, releasing them from system memory.

## 13 What is the format of title command?

Ans Title(‘name ’)

14 From where we get all these blocks to realize a given block diagram?

## AIETM/CSE/FPGA LAB Page 115

Program 8
Object: Simulate transmitter & receiver of BPSK
S. NO. Questions

Ans

## AIETM/CSE/FPGA LAB Page 116

3 Draw the theoretical diagram of BPSK transmitter and receiver?

Ans

reciver

transmitter

## 6 Why modulation is necessary?

Ans It is useful for long distance transmission and less power is needed to be
transmitted

## AIETM/CSE/FPGA LAB Page 117

Ans Coherent modulation=> use of same carrier at each transmitter and receiver

## 8 What do you mean by on-off keying?

Ans In this technique the signal is switched between the 2 levels know as on and off
level

## 9 What is difference between ASK and PSK?

Ans ASK=> Amplitude shift keying. Amplitude of signal is switched between 2 levels

Ans

## 13 Why Simulink is used in matlab

Ans It is done to save the time for codding each block. For each function we have a
predefined block that can perform each function

## 14 How the properties of block can be changed

Ans By use of properties of the block and then editing the same for the block

## AIETM/CSE/FPGA LAB Page 118

Ans CYCLIC REDUNDANCY CHECK

Program 9
Object: Study the basic information of architecture of TM3320C6XXD DSP
kit using BLOOM using DSP. Study architecture of TM3320C6XXD DSP kit.
S.NO Questions

## 1 What is mean by digital signal processor?

Ans A device which is designed for processing the digital signals only is known as digital signal
processor

## 2 What are basic features of digital signal processor?

Ans For filtering the signals, data manipulation, digital signal processing etc.

Ans TM3320C6XXD

## AIETM/CSE/FPGA LAB Page 119

4 What are main parts of DSP processor architecture?

## 5 What is the role of bus structure in DSP architecture?

Ans It is used for transferring the data from memory and to memory of DSP

6 What are the names of different address buses use in DSP architecture?

## 10 Where adaptive processing of a signal is used

Ans Adaptive processing of signal is used where speed of signal are of different speeds

11 Name some commands which are used for pulse shaping of the signal in matlab

## 12 Which function is used for comments in MATLAB?

Ans There is no function but a % sign is used for denoting the comments

## Ans It plot the X and Y axis grids

14 Can we rotate the graphs in 3d view? If yes then name the command

## AIETM/CSE/FPGA LAB Page 120

Ans YES by rotate3d on and rotate3d off command

## Ans It is used to open the file of different format in windows application.

Program 10
Object: Perform convolution using DSP kit
S.NO Questions

Ans VI VSK6713

Ans C language

## 5 Which step is used for convolution in c language

Ans multiplication

Ans .lib

Ans .out

Ans .c

## AIETM/CSE/FPGA LAB Page 122

Ans It is same as CRO