Experiment No.

1A
Roll No. : 226
Aim : Study of Basic Logic Gates.

Objective Designing of Basic Logic Gates Using a Data Flow Modeling.

:

Program : AND Gate : library ieee; Truth Table :

use ieee.std_logic_1164.all;
entity and_gate is
INPUT OUTPUT
port(a,b:in std_logic;
y:out std_logic); A B C
end and_gate; 0 0 0
architecture DF of and_gate is 0 1 0
begin 1 0 0
y<= a and b; 1 1 1

end DF; Output Equation :

C=A.B

OR Gate : library ieee; Truth Table :

use ieee.std_logic_1164.all;
entity or_gate is INPUT OUTPUT
port(A,B:in std_logic;
Y:out std_logic); A B C
end or_gate; 0 0 0
architecture DF of or_gate is 0 1 1
1 0 1
begin
1 1 1
Y<= A OR B;
end DF;
Output Equation :

C=A+B

NOT Gate : library ieee; Truth Table :

use ieee.std_logic_1164.all;
entity not_gate is INPUT OUTPUT
port(A:in std_logic;
Y:out std_logic); A B
0 1
end not_gate;
1 0
architecture DF of not_gate is
begin
Y<= NOT A; Output Equation :
end DF;
B = Ā

Department of Electronics and Telecommunication Engineering, YCCE, Nagpur

3/28/2019 6:44:05 AM Page 1 of 6
 Simulation AND Gate :
Result
:

OR Gate :

NOT Gate :

RTL View AND Gate :

:
Y
A
Y
B

Department of Electronics and Telecommunication Engineering, YCCE, Nagpur

3/28/2019 6:44:05 AM Page 2 of 6
 OR Gate :

Y
A
Y
B

NOT Gate :

A Y

Result / Thus we have successfully designed basic gates using data flow modeling method.
Conclusion
:

Roll No. : 226

Marks out of 10 Signature :
Sem/Br : VI ET
Dr.D.B.Bhoyar(Course Teacher)

Experiment No. 1B
Roll No. : 226
Aim : Study of Universal Gates.

Objective Designing of Universal Gates Using a Data Flow Modeling.

:

Program : NAND Gate : library ieee; Truth Table :

use ieee.std_logic_1164.all;
entity nand_gate is
INPUT OUTPUT
port(a,b:in std_logic;
y:out std_logic); A B C
end nand_gate; 0 0 0
architecture DF of nand_gate is 0 1 0
begin 1 0 0
y<= Not(a and b); 1 1 1

end DF; Output Equation :

C =not (A . B)

Department of Electronics and Telecommunication Engineering, YCCE, Nagpur

3/28/2019 6:44:05 AM Page 3 of 6
 NOR Gate : library ieee; Truth Table :
use ieee.std_logic_1164.all;
entity nor_gate is INPUT OUTPUT
port(A,B:in std_logic;
Y:out std_logic); A B C
end nor_gate; 0 0 0
architecture DF of nor_gate is 0 1 1
1 0 1
begin
1 1 1
Y<= not(A OR B);
end DF;
Output Equation :

C = not(A + B)

Simulation NAND Gate :

Result
:

NOR Gate :

Department of Electronics and Telecommunication Engineering, YCCE, Nagpur

3/28/2019 6:44:05 AM Page 4 of 6
 RTL View NAND Gate :
:

NOR Gate :

Result / Thus we have successfully designed universal gates using data flow modeling method.
Conclusion
:

Roll No. : 226

Marks out of 10 Signature :
Sem/Br : VI ET
Dr.D.B.Bhoyar(Course Teacher)
Department of Electronics and Telecommunication Engineering, YCCE, Nagpur
3/28/2019 6:44:05 AM Page 5 of 6
 Department of Electronics and Telecommunication Engineering, YCCE, Nagpur
3/28/2019 6:44:05 AM Page 6 of 6